JP6246956B1 - Etching method, semiconductor chip manufacturing method, and article manufacturing method - Google Patents

Abstract

An etching method in which needle-like residual portions are unlikely to occur is provided. An etching method according to an embodiment is a catalyst layer containing a noble metal on a surface containing a semiconductor, the first part covering at least partly the surface and having a discontinuity, Non-etched located on the first part and remaining at a position corresponding to the discontinuous part as the catalyst layer moves according to the progress of etching without disturbing the supply of the etching agent to the first part. Forming a catalyst layer including a second portion in contact with the portion, and then supplying the etching agent to the catalyst layer to etch the surface under the action of the catalyst layer as a catalyst. Including. [Selection] Figure 3

Description

  Embodiments described herein relate generally to an etching method, a semiconductor chip manufacturing method, and an article manufacturing method.

  The Mac Etch (Metal-Assisted Chemical Etching) method is a method of etching a semiconductor surface using a noble metal as a catalyst. According to the MacEch method, for example, a high aspect ratio hole can be formed in a semiconductor substrate.

Special table 2013-527103 gazette JP 2011-101209 A

  The problem to be solved by the present invention is to provide an etching method in which needle-like residual portions are unlikely to occur.

  According to the first aspect, a catalyst layer containing a noble metal on a surface containing a semiconductor, the first part covering at least partly the surface and having a discontinuous part, and the first part Located above, does not interfere with the supply of the etching agent to the first part, and contacts the unetched part remaining at the position corresponding to the discontinuous part as the catalyst layer moves according to the progress of etching. Forming a catalyst layer including a second portion, and then supplying the etchant to the catalyst layer to etch the surface under the action of the catalyst layer as a catalyst. An etching method is provided.

  According to a second aspect, there is provided a method for manufacturing a semiconductor chip, comprising etching a semiconductor wafer into individual semiconductor chips by etching using an etching method according to the first aspect, wherein the surface is the surface of the semiconductor wafer. Is done.

  According to the third aspect, there is provided a method for manufacturing an article including etching the surface by the etching method according to the first aspect.

Sectional drawing which shows schematically the structure etched in the etching method which concerns on embodiment. Sectional drawing which shows schematically the catalyst layer formation process in the etching method which concerns on embodiment. Sectional drawing which shows schematically the etching process start state in the etching method which concerns on embodiment. Sectional drawing which shows schematically the state after progress for a fixed time from the state shown in FIG. Sectional drawing which shows schematically the etching process in a comparative example. The top view which shows roughly the semiconductor wafer used in the semiconductor chip manufacturing method concerning embodiment. Sectional drawing along the VII-VII line of the semiconductor wafer shown in FIG. The top view which shows roughly the catalyst layer formation process in the semiconductor chip manufacturing method which concerns on embodiment. Sectional drawing along the IX-IX line of the semiconductor wafer shown in FIG. FIG. 10 is a plan view schematically showing an example of a structure obtained by the method shown in FIGS. 6 to 9. Sectional drawing along the XI-XI line of the semiconductor wafer shown in FIG. The microscope picture which shows the cross section of the structure which formed the dendritic crystal. The photomicrograph which shows the upper surface of the structure which formed the dendritic crystal. The microscope picture which shows the cross section of the structure obtained by etching the structure which formed the dendritic crystal. The microscope picture which shows the cross section of the structure which formed the dendritic crystal. The photomicrograph which shows the upper surface of the structure which formed the dendritic crystal. The microscope picture which shows the cross section of the structure obtained by etching the structure which formed the dendritic crystal. The photomicrograph which shows the section of the structure in which a catalyst layer consists of noble metal particles. The microscope picture which shows the cross section of the structure obtained by etching the structure in which a catalyst layer consists of noble metal particles. The photomicrograph which shows the section of the structure in which a catalyst layer consists of noble metal particles. The microscope picture which shows the cross section of the structure obtained by etching the structure in which a catalyst layer consists of noble metal particles.

  Hereinafter, embodiments will be described in detail with reference to the drawings. In addition, the same reference number is attached | subjected to the component which exhibits the same or similar function through all the drawings, and the overlapping description is abbreviate | omitted.

  First, the etching method according to the embodiment will be described with reference to FIGS. 1 to 4.

In this method, first, a structure 1 shown in FIG. 1 is prepared.
At least a part of the surface of the structure 1 is made of a semiconductor. The semiconductor is selected from, for example, Si; Ge; a semiconductor made of a compound of a group III element such as GaAs and GaN and a group V element; and SiC. The term “group” used here is “group” in the short-period periodic table.

  The structure 1 is, for example, a semiconductor wafer. The semiconductor wafer may be doped with impurities, and semiconductor elements such as transistors and diodes may be formed. The main surface of the semiconductor wafer may be parallel to any crystal plane of the semiconductor.

Next, the mask layer 2 is formed on the surface of the structure 1 made of a semiconductor.
The mask layer 2 is a layer for forming a noble metal pattern as a catalyst layer on the surface of the structure 1. The mask layer 2 has an opening. The width of the opening is preferably in the range of 0.1 μm to 15 μm, and more preferably in the range of 5 μm to 10 μm. When forming a dendritic crystal to be described later, if the width of the opening is too wide, it is difficult to sufficiently cover the surface made of the semiconductor with the catalyst layer at the position of the opening. This is because if the width of the opening is too narrow, it becomes difficult for the etching agent to reach the surface made of the semiconductor.

  As the material of the mask layer 2, any material can be used as long as it can suppress adhesion of a noble metal to be described later to a region covered with the mask layer 2 on the surface of the structure 1. Examples of such a material include organic materials such as polyimide, fluorine resin, phenol resin, acrylic resin, and novolac resin, and inorganic materials such as silicon oxide and silicon nitride.

  The mask layer 2 can be formed by, for example, an existing semiconductor process. The mask layer 2 made of an organic material can be formed by, for example, photolithography. The mask layer 2 made of an inorganic material can be formed by, for example, forming an inorganic material layer by vapor deposition, forming a mask by photolithography, and patterning the inorganic material layer by etching. Alternatively, the mask layer 2 made of an inorganic material can be formed by oxidizing or nitriding the surface region of the structure 1, forming a mask by photolithography, and patterning the oxide or nitride layer by etching. The mask layer 2 can be omitted.

  Next, as shown in FIG. 2, the catalyst layer 6 is formed on the surface of the structure 1 made of a semiconductor. The catalyst layer 6 is made of a noble metal. The noble metal is, for example, one or more metals selected from the group consisting of Au, Ag, Pt, and Rh.

The catalyst layer 6 includes a first portion 4 and a second portion 5.
The first portion 4 at least partially covers the semiconductor surface of the structure 1. The first portion 4 is, for example, a layer having a concavo-convex structure on the surface. The first portion may have a discontinuous portion. The first portion 4 serves as a catalyst for the oxidation reaction of the semiconductor surface in contact therewith.

The first portion 4 has a larger apparent density and is thinner than the second portion 5. The thickness d ₁ of the first portion 4 is preferably in the range of 1 nm to 1000 nm, and more preferably in the range of 10 nm to 500 nm. If the first portion 4 is extremely thin, an excessive amount of discontinuities may occur in the first portion 4. When the first portion 4 is thick, the etching agent may not be sufficiently supplied to the semiconductor surface.

  The second part 5 is located on the first part 4. The second portion 5 includes, for example, dendritic crystals made of a noble metal. Similar to the first portion 4, the second portion 5 acts as a catalyst for the oxidation reaction.

The second portion 5 has a smaller apparent density and is thicker than the first portion 4. The thickness d ₂ of the second portion 5 is preferably 0.1 μm or more, and more preferably 1 μm or more. When the second portion 5 is thin, there is a possibility that the second portion 5 cannot contact the portion that could not be etched without acting as the catalyst of the first portion 4, that is, the unetched portion. The thicker the second portion 5, the higher the possibility that the unetched portion can be removed. Although the upper limit of the thickness of the 2nd part 5 is not specifically limited, Usually, it is 5 micrometers or less. The thickness of the first portion 4 _{d 1} and the ratio _d 1 / _{d 2} of the thickness _{d 2} of the second portion 5 is preferably in the range of 0.01 to 10, 0.01 to 0 More preferably within the range of .5. The unetched portion will be described later in detail.

Next, the apparent density will be described. In explaining the apparent density, the following areas are defined.
First, a two-dimensional region corresponding to the sum of the first portion 4 and its discontinuous portion on the semiconductor surface is defined as an A region. Next, the part located in the 2nd part 5 just above A area | region is made into B part. A portion from the upper surface of the first portion 4 to the maximum height of the B portion in the three-dimensional region located immediately above the A region is defined as a C portion.

  The apparent density of the first portion 4 is a value obtained by dividing the mass of the first portion 4 by the total volume of the first portion 4 and its discontinuous portion. The apparent density of the second portion 5 is a value obtained by dividing the mass of the B portion by the volume of the C portion. The apparent density can be confirmed by observing the cross section of the catalyst layer 6.

Such a catalyst layer 6 is obtained by the following method, for example.
The catalyst layer 6 can be formed by, for example, electrolytic plating, reduction plating, or displacement plating. The first portion 4 may be formed by applying a dispersion containing noble metal particles, or using a vapor deposition method such as vapor deposition and sputtering. Hereinafter, the formation of the catalyst layer 6 by displacement plating will be described as an example.

  For precipitation of the noble metal by displacement plating, for example, an aqueous solution of potassium tetrachloroaurate (III), an aqueous solution of gold sulfite or an aqueous solution of potassium gold (I) cyanide can be used. Hereinafter, description will be made assuming that the noble metal is gold.

  The displacement plating solution is, for example, a mixed solution of a potassium tetrachloroaurate (III) aqueous solution and hydrofluoric acid. Hydrofluoric acid has a function of removing a natural oxide film on the surface of the structure 1.

  The displacement plating solution may further contain at least one of a complexing agent and a pH buffer. The complexing agent has an action of stabilizing noble metal ions contained in the displacement plating solution. The pH buffer has an effect of stabilizing the reaction rate of plating. Examples of these additives include glycine, citric acid, carboxylate ion, cyanide ion, pyrophosphate ion, ethylenediaminetetraacetic acid, ammonia, aminocarboxylate ion, acetic acid, lactic acid, phosphate, boric acid, or two of them. Combinations of the above can be used. As these additives, glycine and citric acid are preferably used.

  When the structure 1 is immersed in the displacement plating solution, the natural oxide film on the surface of the structure 1 is removed, and a portion of the surface of the structure 1 that is not covered by the mask layer 2 is precious metal, Here, gold is deposited. Thereby, the 1st part 4 is obtained.

  When displacement plating is performed under specific conditions, the catalyst layer 6 including the first portion 4 and the second portion 5 and the second portion 5 including dendrites is obtained by a single treatment. The displacement plating solution used in such displacement plating includes, for example, an aqueous solution of potassium tetrachloroaurate (III), hydrofluoric acid, glycine and citric acid.

  The concentration of potassium tetrachloroaurate (III) in the displacement plating solution is preferably in the range of 10 μmol / L to 1000 mmol / L, and more preferably in the range of 1 mmol / L to 100 mmol / L. . When this concentration is low, it is difficult to generate dendrites. When this concentration is high, the layers are formed at a high density, so that it may be difficult to form layers having different densities and thicknesses.

  The hydrogen fluoride concentration in the displacement plating solution is preferably in the range of 0.01 mol / L to 5 mol / L, and more preferably in the range of 0.5 mol / L to 2 mol / L. When the hydrogen fluoride concentration is low, it is difficult to form dendrites. When the concentration of hydrogen fluoride is high, dissolution of the semiconductor surface proceeds, which may adversely affect etching.

  The glycine concentration in the displacement plating solution is preferably in the range of 0.1 g / L to 20 g / L, and more preferably in the range of 1 g / L to 10 g / L. When the glycine concentration is low, it is difficult to generate dendrites.

  The citric acid concentration in the displacement plating solution is preferably in the range of 0.1 g / L to 20 g / L, and more preferably in the range of 1 g / L to 10 g / L. When the citric acid concentration is low, it is difficult to generate dendrites.

  Moreover, you may use what has the function similar to these instead of glycine and a citric acid. Instead of glycine, for example, carboxylate ion, cyanide ion, pyrophosphate ion, ethylenediaminetetraacetic acid, ammonia, or aminocarboxylate ion may be used. Instead of citric acid, for example, carboxylate ion, acetic acid, lactic acid, phosphate, or boric acid may be used.

  When the structure 1 in which the mask layer 2 is formed is immersed in a displacement plating solution, a dense thin layer made of gold is formed in a region of the semiconductor surface that is not covered by the mask layer 2. , Dendrites made of gold grow. Thereby, the catalyst layer 6 in which the second portion 5 includes dendrites can be obtained by a single treatment.

Next, as shown in FIG. 3, an etching agent 7 is supplied to the catalyst layer 6.
Specifically, for example, the structure 1 in which the mask layer 2 and the catalyst layer 6 are formed is immersed in the etching agent 7. Etching agent 7 contains hydrofluoric acid and an oxidizing agent.

  When the etching agent 7 contacts the semiconductor surface, the oxidizing agent oxidizes the portion of the surface where the first portion 4 is close, and hydrofluoric acid dissolves and removes the oxide. Therefore, as shown in FIG. 4, the etching agent 7 etches the semiconductor surface in the vertical direction at the position of the opening under the action of the catalyst layer 6 as a catalyst.

  The concentration of hydrogen fluoride in the etching agent 7 is preferably in the range of 1.0 mol / L to 20 mol / L, more preferably in the range of 5 mol / L to 10 mol / L, and 3 mol / L to 7 mol. More preferably, it is in the range of / L. When the hydrogen fluoride concentration is low, it is difficult to achieve a high etching rate. When the hydrogen fluoride concentration is high, excessive side etching may occur.

The oxidizing agent in the etching agent 7 is, for example, hydrogen peroxide, nitric acid, AgNO ₃ , KAuCl ₄ , HAuCl ₄ , K ₂ PtCl ₆ , H ₂ PtCl ₆ , Fe (NO ₃ ) ₃ , Ni (NO ₃ ) ₂ , Mg It can be selected from (NO ₃ ) ₂ , Na ₂ S ₂ O ₈ , K ₂ S ₂ O ₈ , KMnO ₄ and K ₂ Cr ₂ O ₇ . Hydrogen peroxide is preferred as the oxidizing agent because no harmful by-products are generated and the semiconductor element is not contaminated.

The concentration of the oxidizing agent such as hydrogen peroxide in the etching agent 7 is preferably in the range of 0.2 mol / L to 8 mol / L, and is in the range of 2.0 mol / L to 4.0 mol / L. Is more preferable, and it is still more preferable to exist in the range of 3.0 mol / L to 4.0 mol / L.
In the method shown in FIGS. 1 to 4, the surface of the structure 1 made of a semiconductor is etched as described above.

  By the way, as shown in FIG. 5, when the structure 1 which consists of the aggregate | assembly of the noble metal particle 3 and has the catalyst layer 6 with the wide clearance gap between the noble metal particles 3 is immersed in the etching agent 7, an etching agent 7 can easily reach the semiconductor surface through the gaps between the noble metal particles 3. Accordingly, the etching agent 7 etches a region of the semiconductor surface that is close to the noble metal particles 3. However, since the region corresponding to the gap between the noble metal particles 3 in the semiconductor surface is difficult to be oxidized, the etching is difficult to proceed. Therefore, the semiconductor remains in a needle shape in the region corresponding to the gap. The needle-like residual portion 8 can cause dust.

  Further, when the gap between the noble metal particles 3 is narrow, the etching agent 7 cannot easily reach the semiconductor surface. Therefore, the etching hardly proceeds.

  The method described with reference to FIGS. 1 to 4 hardly causes a needle-like residual portion even though etching is sufficiently advanced. The present inventors believe that this is due to the following reason.

  Since the 1st part 4 is thin as mentioned above, possibility that it has a discontinuous part is high. Therefore, the etching agent 7 can reach the semiconductor surface through the discontinuity. Since the apparent density of the second portion 5 is smaller than that of the first portion 4, supply of the etching agent 7 to the first portion 4 is not hindered. Therefore, the semiconductor can be etched as shown in FIGS.

  The catalyst layer 6 moves downward as etching progresses. However, the etching does not proceed in the discontinuous portion, and an unetched portion remains at a position corresponding to the discontinuous portion as the catalyst layer 6 moves. Since the second portion 5 is located on the first portion 4 and is thicker than the first portion 4, there is a possibility that the second portion 5 comes into contact with the unetched portion and is oxidized in the process of moving downward. high. The etching agent 7 etches the oxidized unetched part. Therefore, it is considered that a needle-like residual portion is unlikely to occur.

The catalyst layer 6 can be variously modified.
For example, the first portion 4 may be a granular layer made of noble metal particles and having a gap through which the etching agent 7 can flow between the particles. Alternatively, the first portion 4 may be a porous film in which a plurality of through holes are provided in a continuous film made of a noble metal.

  Further, the second portion 5 may have a form other than the dendritic crystal. For example, the second portion 5 may be a porous layer having liquid permeability.

  The catalyst layer 6 may further include one or more other portions in addition to the first portion 4 and the second portion 5. For example, the catalyst layer 6 may have a multilayer structure of three or more layers.

  The second portion 5 does not need to be integrated from the start to the end of etching. That is, the second portion 5 may be decomposed into a plurality of pieces when the catalyst layer 6 moves downward as the etching progresses. These fragments may change their orientation as the catalyst layer 6 moves. Therefore, when the second part 5 produces a non-spherical fragment, for example, when the second part 5 containing dendrites has decomposed into a plurality of fragments, the second part 5 remains integral. In comparison, the probability that the second portion 5 is in contact with the unetched portion is increased.

  The etching method described above can be used for manufacturing various articles. The etching method described above can also be used for forming a recess or a through hole or dividing a structure such as a semiconductor wafer. For example, the above-described etching method can be used for manufacturing a semiconductor device.

  A method for manufacturing a semiconductor chip including etching a semiconductor wafer into a plurality of semiconductor chips will be described with reference to FIGS.

  First, the structure shown in FIGS. 6 and 7 is prepared. This structure includes a semiconductor wafer 9, a mask layer 2, and a dicing sheet 11. A semiconductor element region 10 is formed on the surface of the semiconductor wafer 9. The mask layer 2 covers an element region 10 that is a region where semiconductor elements are formed on the surface of the semiconductor wafer 9 and plays a role of protecting the semiconductor elements from damage. The dicing sheet 11 is affixed to the back surface of the surface on which the mask layer 2 of the semiconductor wafer 9 is provided.

Next, as shown in FIGS. 8 and 9, a catalyst layer 6 made of a noble metal is formed on the surface of the semiconductor wafer 9 by the method described with reference to FIG.
Next, the structure shown in FIGS. 8 and 9 is etched by the method described with reference to FIGS. Etching is performed until the bottom surface of the recess formed thereby reaches the surface of the dicing sheet 11.

  As described above, according to the above-described method, the semiconductor chip 12 including the semiconductor element region 10 can be obtained as shown in FIGS.

  In this method, for example, the mask layer 2 can be used as a protective layer for protecting the semiconductor chip. Since the mask layer 2 covers the entire surface of the semiconductor chip, this method can achieve a higher strength than when general dicing using a blade is performed.

  In this method, the shape of the upper surface of the semiconductor chip is not limited to a square or a rectangle. For example, the shape of the upper surface of the semiconductor chip may be circular or hexagonal. In this method, semiconductor chips having different top shapes can be formed simultaneously.

Hereinafter, test examples will be described.
<Test Example 1>
A mask layer and a catalyst layer including first and second portions were formed on the structure by the following method, and this was etched. Then, the influence of the structure of the catalyst layer on the etching was examined.

  First, a mask layer was formed on the surface of a structure made of a semiconductor. The mask layer was formed by photolithography using a photoresist. The width of the opening of the mask layer was 5 μm.

Next, a plating solution A was prepared by mixing an aqueous potassium tetrachloroaurate (III) solution, hydrofluoric acid, glycine and citric acid. The plating solution A had a potassium tetrachloroaurate (III) concentration of 5 mmol / L, a hydrogen fluoride concentration of 1 mol / L, a glycine concentration of 10 g / L, and a citric acid concentration of 10 g / L. It was.
Next, the structure on which the mask layer was formed was immersed in the plating solution A at 23 ° C. for 3 minutes to form a catalyst layer. FIG. 12 and FIG. 13 show the results of observing the structure in which the catalyst layer and the mask layer are formed with a scanning electron microscope.

  FIG. 12 is a scanning electron micrograph showing a cross section of the catalyst layer formed using the plating solution A. FIG. 13 is a scanning electron micrograph showing the upper surface of the catalyst layer formed using the plating solution A. As shown in FIGS. 12 and 13, the catalyst layer has a dendrite in the second part, the second part is thicker than the first part, and the apparent density of the second part is apparent in the first part. It was confirmed that the density was smaller than the density.

Next, an etching agent was prepared by mixing hydrofluoric acid and hydrogen peroxide. This etching agent had a hydrogen fluoride concentration of 10 mol / L and a hydrogen peroxide concentration of 0.5 mol / L.
The structure in which the mask layer and the catalyst layer were formed was immersed in this etchant, and this was etched. FIG. 14 shows the result of observation of the etched structure with a scanning electron microscope.

  FIG. 14 is a scanning electron micrograph showing a cross section of the structure after etching. As shown in FIG. 14, the occurrence of acicular residual portions was suppressed.

<Test Example 2>
A mask layer and a catalyst layer were formed on the structure by the same method as described in Test Example 1 except that the width of the opening was set to 10 μm, and this was etched.

  FIG. 15 is a scanning electron micrograph showing a cross section of the catalyst layer formed using the plating solution A. FIG. 16 is a scanning electron micrograph showing the upper surface of the catalyst layer formed using the plating solution A. As shown in FIG. 15 and FIG. 16, the catalyst layer has a dendrite in the second part, the second part is thicker than the first part, and the apparent density of the second part is apparent in the first part. It was confirmed that the density was smaller than the density.

  FIG. 17 is a scanning electron micrograph showing a cross section of the structure after etching. As shown in FIG. 17, generation | occurrence | production of the acicular residual part was suppressed.

<Test Example 3>
A mask layer and a catalyst layer composed of aggregates of noble metal particles were formed on the structure by the following method, and this was etched. Then, the influence of the structure of the catalyst layer on the etching was examined.

  First, a mask layer was formed on the surface of a structure made of semiconductor by the same method as in Test Example 1. The width of the opening of the mask layer was 10 μm.

  Next, a plating solution B was prepared by mixing an aqueous potassium tetrachloroaurate (III) solution, hydrofluoric acid, ammonium hydrogen fluoride, glycine and citric acid. The plating solution B has a potassium tetrachloroaurate (III) concentration of 1 mmol / L, a hydrogen fluoride concentration of 0.25 mol / L, an ammonium fluoride concentration of 4.75 mol / L, and a glycine concentration of The citric acid concentration was 10 g / L.

  Next, the structure was immersed in the plating solution B for 1 minute at room temperature to form a catalyst layer. FIG. 18 shows the result of observation of the structure formed with the catalyst layer and the mask layer with a scanning electron microscope.

  FIG. 18 is a scanning electron micrograph showing a cross section of the catalyst layer formed using the plating solution B. As shown in FIG. 18, it was confirmed that the catalyst layer was composed of aggregates of noble metal particles.

  Next, as in Test Example 1, an etchant was prepared and this structure was etched. FIG. 19 shows the result of observation of the etched structure with a scanning electron microscope.

  FIG. 19 is a scanning electron micrograph showing a cross section of the structure after etching. As shown in FIG. 19, a needle-like residual portion was generated.

<Test Example 4>
A mask layer and a catalyst layer were formed on the structure by the same method as described in Test Example 3 except that the immersion time in the plating solution B was 3 minutes, and this was etched.

  FIG. 20 is a scanning electron micrograph showing a cross section of the structure of the catalyst layer formed using the plating solution B. As shown in FIG. 20, it was confirmed that the catalyst layer was composed of aggregates of noble metal particles.

  FIG. 21 is a scanning electron micrograph showing a cross section of the structure after etching. As shown in FIG. 21, the etching did not proceed.

Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.
The invention described in the scope of the original claims of the original application is added below.
[1]
On the surface made of semiconductor,
A catalyst layer made of a noble metal, the first part at least partially covering the surface, and located on the first part, the apparent density is smaller than the first part Forming a catalyst layer comprising a thicker second portion;
An etching method comprising: supplying an etching agent to the catalyst layer and etching the surface under the action of the catalyst layer as a catalyst.
[2]
Item 2. The etching method according to Item 1, wherein the noble metal is one or more metals selected from the group consisting of Au, Ag, Pt, and Rh.
[3]
Item 3. The etching method according to Item 1 or 2, wherein the semiconductor contains Si.
[4]
Item 4. The etching method according to any one of Items 1 to 3, wherein the etching agent contains H ₂ O ₂ .
[5]
Item 5. The etching according to any one of Items 1 to 4, further comprising forming a mask layer including an opening having a width in a range of 0.1 μm to 15 μm on the surface, and etching at the position of the opening. Method.
[6]
Item 6. The etching method according to any one of Items 1 to 5, wherein the second portion includes dendritic crystals made of the noble metal.
[7]
A method for manufacturing a semiconductor chip, comprising: etching a semiconductor wafer into individual semiconductor chips by etching using the etching method according to any one of Items 1 to 6, wherein the surface is the surface of the semiconductor wafer.
[8]
Item 8. A method for manufacturing an article, comprising etching the surface by the etching method according to any one of Items 1 to 7.

  DESCRIPTION OF SYMBOLS 1 ... Structure, 2 ... Mask layer, 3 ... Noble metal particle, 4 ... 1st part, 5 ... 2nd part, 6 ... Catalyst layer, 7 ... Etching agent, 8 ... Needle-like residual part, 9 ... Semiconductor wafer, 10 ... Semiconductor element region, 11 ... Dicing sheet, 12 ... Semiconductor chip.

Claims (8)

On the surface containing the semiconductor,
A catalyst layer comprising a noble metal, the first part covering at least part of the surface and having a discontinuity; and an etchant located on the first part, the etching agent being applied to the first part Forming a catalyst layer including a second portion that contacts an unetched portion remaining in a position corresponding to the discontinuous portion as the catalyst layer moves according to the progress of etching without disturbing the supply;
Then, supplying the etching agent to the catalyst layer, and etching the surface under the action of the catalyst layer as a catalyst.   The etching method according to claim 1, wherein the noble metal is one or more metals selected from the group consisting of Au, Ag, Pt, and Rh.   The etching method according to claim 1, wherein the semiconductor contains Si. The etching method according to claim 1, wherein the etchant contains H ₂ O ₂ .   5. The method according to claim 1, further comprising forming a mask layer including an opening having a width in a range of 0.1 μm to 15 μm on the surface, and etching at the position of the opening. Etching method.   The etching method according to claim 1, wherein the second portion includes dendritic crystals made of the noble metal.   A method of manufacturing a semiconductor chip, comprising: etching a semiconductor wafer by the etching method according to claim 1 into individual chips, wherein the surface is a surface of the semiconductor wafer.   A method for manufacturing an article, comprising etching the surface by the etching method according to claim 1.