JP6970263B2 - Etching method, semiconductor chip manufacturing method and article manufacturing method - Google Patents

Description

Embodiments of the present invention relate to an etching method, a method for manufacturing a semiconductor chip, and a method for manufacturing an article.

Etching is known as a method for forming holes and grooves in a semiconductor wafer.
As an etching method, for example, a method of forming a mask layer on a semiconductor wafer, patterning the mask layer by laser scribing, and using the patterned mask layer as an etching mask to perform plasma etching of the semiconductor wafer is known.

Further, as etching, a MacEtch (Metal-Assisted Chemical Etching) method is known. The MacEtch method is a method of etching a semiconductor substrate containing silicon by using, for example, a noble metal as a catalyst.

Japanese Unexamined Patent Publication No. 2015-57840 Special Table 2015-509283 Gazette

An object to be solved by the present invention is to prevent the portion remaining after etching from becoming porous.

According to the first aspect, an uneven structure including a convex portion is formed on the surface of the semiconductor substrate, and a catalyst layer containing a noble metal is selectively formed on the upper surface of the convex portion among the surfaces. This includes supplying an etching solution to the catalyst layer and etching the semiconductor substrate under the action of the noble metal as a catalyst, and the formation of the uneven structure includes an opening on the surface. An etching method including forming a first mask layer to have, etching the surface using the first mask layer as an etching mask, and removing the first mask layer is provided. ..
According to the second aspect, the concave-convex structure including the convex portion is formed on the surface of the semiconductor substrate, and the catalyst layer containing the noble metal is selectively formed on the upper surface of the convex portion in the surface. This includes supplying an etching solution to the catalyst layer and etching the semiconductor substrate under the action of the noble metal as a catalyst, and the formation of the uneven structure includes an opening on the surface. An etching method including forming a second mask layer having a semiconductor layer and forming a semiconductor layer on the surface at the position of the opening is provided.
According to the third aspect, the concave-convex structure including the convex portion is formed on the surface of the semiconductor substrate, and the catalyst layer containing the noble metal is selectively formed on the upper surface of the convex portion in the surface. A semiconductor wafer is etched into a semiconductor chip by an etching method including supplying an etching solution to the catalyst layer and etching the semiconductor substrate under the action of the noble metal as a catalyst. Provided is a method for manufacturing a semiconductor chip, the surface of which is the surface of the semiconductor wafer, which includes dissociation.
According to the fourth aspect, the etching method according to the first aspect provides a method for manufacturing an article including etching the surface.

FIG. 5 is a cross-sectional view schematically showing a first mask layer forming step in the etching method according to the embodiment. FIG. 5 is a cross-sectional view schematically showing a step of etching the surface of a semiconductor substrate by using the first mask layer as an etching mask in the etching method according to the embodiment. FIG. 5 is a cross-sectional view schematically showing a step of removing the first mask layer in the etching method according to the embodiment. FIG. 3 is a cross-sectional view schematically showing a third mask layer forming step in the etching method according to the embodiment. The cross-sectional view schematically which shows the catalyst layer formation process in the etching method which concerns on embodiment. The cross-sectional view schematically which shows the etching process start state in the etching method which concerns on embodiment. FIG. 6 is a cross-sectional view schematically showing a state after a lapse of a certain period of time from the state shown in FIG. FIG. 5 is a cross-sectional view schematically showing a semiconductor substrate to be etched in a comparative example. The cross-sectional view schematically which shows the catalyst layer formation process in a comparative example. The cross-sectional view schematically which shows the etching process in the comparative example. FIG. 3 is a cross-sectional view schematically showing a semiconductor substrate to be etched in the etching method according to the embodiment. The cross-sectional view schematically which shows the catalyst layer formation method in the etching method which concerns on embodiment. FIG. 5 is a cross-sectional view schematically showing an etching process in the etching method according to the embodiment. FIG. 2 is a cross-sectional view schematically showing a second mask layer forming step in the etching method according to another embodiment. FIG. 5 is a cross-sectional view schematically showing a semiconductor layer forming step in the etching method according to another embodiment. FIG. 3 is a cross-sectional view schematically showing a third mask layer forming step in the etching method according to another embodiment. The plan view which shows schematic the semiconductor wafer used in the semiconductor chip manufacturing method which concerns on embodiment. FIG. 17 is a cross-sectional view taken along the line XVIII-XVIII of the semiconductor wafer shown in FIG. The plan view which shows schematic the semiconductor layer formation process in the semiconductor chip manufacturing method which concerns on embodiment. FIG. 19 is a cross-sectional view taken along the line XX-XX of the semiconductor wafer shown in FIG. FIG. 3 is a plan view schematically showing a third mask layer forming step in the semiconductor chip manufacturing method according to the embodiment. FIG. 21 is a cross-sectional view taken along the line XXII-XXII of the semiconductor wafer shown in FIG. The plan view which shows schematic the catalyst layer formation process in the semiconductor chip manufacturing method which concerns on embodiment. FIG. 23 is a cross-sectional view taken along the line XXIV-XXIV of the semiconductor wafer shown in FIG. 23. FIG. 6 is a plan view schematically showing an example of the structure obtained by the method shown in FIGS. 17 to 24. FIG. 25 is a cross-sectional view taken along the line XXVI-XXVI of the semiconductor wafer shown in FIG. 25. A photomicrograph showing a cross section of a semiconductor wafer in which a convex portion and a third mask layer are formed. A photomicrograph showing a cross section of a structure obtained by forming a catalyst layer on the structure shown in FIG. 27. A photomicrograph showing a cross section of a structure obtained by etching the structure shown in FIG. 28. A photomicrograph showing a cross section of a structure obtained by etching a semiconductor wafer having no uneven structure including a convex portion.

Hereinafter, embodiments will be described in detail with reference to the drawings. Components that exhibit similar or similar functions are designated by the same reference numerals throughout the drawings, and duplicate description will be omitted. Further, in the present specification, the "micrograph" is a scanning electron micrograph.

First, the etching method according to the embodiment will be described with reference to FIGS. 1 to 7.

In this method, first, the semiconductor substrate 1 shown in FIG. 1 is prepared.
At least a part of the surface of the semiconductor substrate 1 is made of a semiconductor. The semiconductor is, for example, from silicon (Si); germanium (Ge); a semiconductor composed of a compound of a group III element such as gallium arsenide (GaAs) and gallium nitride (GaN) and a group V element; and silicon carbide (SiC). Be selected. According to one example, the semiconductor substrate 1 contains silicon. The term "group" used here is "group" in the short-period periodic table.

The semiconductor substrate 1 is, for example, a semiconductor wafer. Impurities may be doped in the semiconductor wafer, and semiconductor elements such as transistors and diodes may be formed on the semiconductor wafer. Further, the main surface of the semiconductor wafer may be parallel to any crystal plane of the semiconductor.

Next, as shown in FIG. 1, the first mask layer 2 is formed on the surface of the semiconductor substrate 1.
The first mask layer 2 is a layer for forming a convex portion described later on the surface of the semiconductor substrate 1. The first mask layer 2 has one or more openings.

As the material of the first mask layer 2, any material can be used as long as it protects the region of the surface of the semiconductor substrate 1 covered by the first mask layer 2 from etching. Examples of such a material include organic materials such as polyimide, fluororesin, phenol resin, acrylic resin, and novolak resin.

The first mask layer 2 can be formed by, for example, an existing semiconductor process. The first mask layer 2 made of an organic material can be formed by, for example, photolithography.

Next, as shown in FIG. 2, the semiconductor substrate 1 is etched using the first mask layer 2 as an etching mask.
When the semiconductor substrate 1 is etched, the convex portion 3 is formed on the surface of the semiconductor substrate 1.

Etching is, for example, dry etching. Examples of the dry etching include plasma etching using a gas such as _{SF 6} , CF ₄ , C ₂ F ₆ , C ₃ F ₈ , CCl _{F 2 , CCl 4} , _{PCl 3} , or CBr F _3.

_{The height h 1} of the convex portion 3 is preferably in the range of 0.001 μm to 1 μm, and more preferably in the range of 0.15 μm to 0.5 μm. If the height h ₁ is too small, the noble metal element diffuses into the region of the semiconductor substrate 1 directly below the third mask layer 4 described later when the catalyst layer 6 described later is formed. Etching in the direction intersecting with the thickness direction is likely to proceed. The upper limit of the height h ₁ is not particularly limited, but is usually 10 μm or less.

Here, "height h ₁ " is a value obtained by the following method. First, a cross section of the semiconductor substrate 1 including the convex portion 3 is photographed with a scanning electron microscope (SEM). The magnification shall be in the range of 10,000 times to 100,000 times. Next, the height of the convex portion 3 in the image is measured. Specifically, the height of the side wall on the left side of the convex portion 3 and the height of the side wall on the right side of the convex portion 3 are measured. When the heights of the left and right side walls of the convex portion 3 are the same, the height of either side wall is defined as "height h ₁ ". When the heights of the left and right side walls of the convex portion 3 are different, the height of the lower side wall is defined as "height h ₁ ".

Next, as shown in FIG. 3, the first mask layer 2 is removed. Next, as shown in FIG. 4, the third mask layer 4 is formed on the surface of the semiconductor substrate 1.
The third mask layer 4 has an opening at the position of the convex portion 3. For example, the size and shape of the opening is equal to the size and shape of the upper surface of the convex portion 3. The third mask layer 4 has an upper surface having a height equal to or higher than the upper surface of the convex portion 3.

The third mask layer 4 has etching resistance to an etching solution for etching the semiconductor substrate 1.
Any material can be used as the material of the third mask layer 4. Examples of this material include organic materials such as polyimide, fluororesin, phenol resin, acrylic resin, and novolak resin, and inorganic materials such as silicon oxide and silicon nitride.

The third mask layer 4 can be formed by, for example, an existing semiconductor process. The third mask layer 4 made of an organic material can be formed by, for example, photolithography. The third mask layer 4 made of an inorganic material can be formed, for example, by forming an inorganic material layer by a vapor phase deposition method, forming a mask by photolithography, and patterning the inorganic material layer by etching. Alternatively, the third mask layer 4 made of an inorganic material can be formed by oxidation or nitriding of the surface region of the semiconductor substrate 1, mask formation by photolithography, and patterning of the oxide or nitride layer by etching.

_{The thickness t 3} of the third mask layer 4 is preferably in the range of 0.001 μm to 10 μm, and more preferably in the range of 0.1 μm to 1 μm.

Here, "thickness t ₃ " is a value obtained by the following method. That is, the thickness t ₃ of the third mask layer 4 is from the upper surface of the third mask layer 4 to the lower surface of the third mask layer 4 in the image obtained by observing the cross section parallel to the thickness direction with a microscope. The distance.

The ratio t ₃ / h _{1 of the thickness t 3} of the third mask layer 4 to the height h ₁ of the convex portion 3 is preferably 1 or more, and more preferably 1.5 or more. When the ratio t ₃ / h ₁ is less than 1, when the catalyst layer described later is formed on the upper surface of the convex portion 3, the catalyst layer is formed not only on the upper surface of the convex portion 3 but also on the side wall of the convex portion 3. .. The portion of the catalyst layer located on the side wall of the convex portion 3 may hinder the movement of the catalyst layer in the thickness direction of the semiconductor substrate 1 in the process of etching the semiconductor substrate 1, making it difficult for the etching to proceed. be. When the ratio t ₃ / h ₁ is 1 or more, the third mask layer 4 can suppress the adhesion of the catalyst layer to the side wall of the convex portion 3. The upper limit of the ratio t ₃ / h ₁ of the semiconductor substrate 1 is not particularly limited, but is usually 5 or less.

The width of the opening portion (that is, the width of the convex portion 3) of the third mask layer 4 is preferably in the range of 0.3 μm to 80 μm, and preferably in the range of 1 μm to 20 μm. If the width of the convex portion 3 is too wide, the number of semiconductor chips that can be manufactured from one semiconductor substrate 1 may be reduced when this etching method is used for individualizing from a semiconductor substrate to a semiconductor chip. high. If the width of the opening is too narrow, it is difficult for the etching solution described later to reach the surface of the semiconductor substrate 1.

Next, as shown in FIG. 5, the catalyst layer 6 containing the noble metal is formed on the upper surface of the convex portion 3. The catalyst layer 6 contains, for example, precious metal particles 5. The noble metal is, for example, one or more metals selected from the group consisting of Au, Ag, Pt, Pd, Ru and Rh.

The thickness of the catalyst layer 6 is preferably in the range of 0.01 μm to 0.3 μm, and more preferably in the range of 0.05 μm to 0.2 μm. If the catalyst layer 6 is too thick, the etching solution 7 described later does not easily reach the semiconductor substrate 1, so that etching does not proceed easily. If the catalyst layer 6 is too thin, the ratio of the total surface area of the noble metal particles 5 to the area to be etched is too small, so that etching does not proceed easily.
The thickness of the catalyst layer 6 is the distance from the upper surface of the catalyst layer 6 to the upper surface of the convex portion 3 in the image obtained by observing the cross section parallel to the thickness direction with a microscope.

The catalyst layer 6 covers the upper surface of the convex portion 3 at least partially. The catalyst layer 6 may have a discontinuous portion.

The shape of the precious metal particles 5 is preferably spherical. The shape of the noble metal particles 5 may be another shape such as a rod shape or a plate shape. The noble metal particles 5 act as a catalyst for an oxidation reaction on the surface of the semiconductor in contact with the noble metal particles 5.

The particle size d ₁ of the noble metal particles 5 is preferably in the range of 0.001 μm to 1 μm, and more preferably in the range of 0.01 μm to 0.5 μm.

Here, "particle size d ₁ " is a value obtained by the following method. First, the main surface of the catalyst layer 6 is photographed with a scanning electron microscope (SEM). The magnification shall be in the range of 10,000 times to 100,000 times. Next, the area of each of the precious metal particles 5 is obtained from the image. Next, assuming that each noble metal particle 5 is spherical, the diameter of the noble metal particle 5 is obtained from the above area. This diameter is defined as the "particle size d ₁ " of the precious metal particles 5.

The catalyst layer 6 can be formed by, for example, electrolytic plating, reduction plating, or replacement plating. The catalyst layer 6 may be formed by applying a dispersion liquid containing the noble metal particles 5 or by using a vapor phase deposition method such as a vapor deposition method and a sputtering method. Among these methods, substitution plating is particularly preferable because the noble metal can be deposited directly and uniformly on the convex portion 3. Hereinafter, as an example, the formation of the catalyst layer 6 by substitution plating will be described.

For the precipitation of the noble metal by the replacement plating, for example, an aqueous solution of tetrachloroauric acid (III) or a silver nitrate solution can be used. An example of this process will be described below.

The replacement plating solution is, for example, a mixed solution of an aqueous solution of tetrachloroauric acid (III) acid tetrahydrate and hydrofluoric acid. Hydrofluoric acid has the effect of removing the natural oxide film on the surface of the semiconductor substrate 1.

When the semiconductor substrate 1 is immersed in the replacement plating solution, the natural oxide film on the surface of the semiconductor substrate 1 is removed, and precious metal, here gold, is deposited on the upper surface of the convex portion 3. As a result, the catalyst layer 6 is obtained.

The concentration of tetrachloroauric acid (III) acid tetrahydrate in the replacement plating solution is preferably in the range of 0.0001 mol / L to 0.01 mol / L. The hydrogen fluoride concentration in the replacement plating solution is preferably in the range of 0.1 mol / L to 6.5 mol / L.

The substitution plating solution may further contain a sulfur-based complexing agent. Alternatively, the replacement plating solution may further contain glycine and citric acid.

Next, as shown in FIG. 6, the etching solution 7 is supplied to the catalyst layer 6. For example, the semiconductor substrate 1 in which the convex portion 3, the third mask layer 4, and the catalyst layer 6 are formed is immersed in the etching solution 7. The etching solution 7 contains, for example, a corrosive agent and an oxidizing agent. The etching solution 7 may further contain ammonium fluoride.

When the etching solution 7 comes into contact with the surface of the semiconductor substrate 1, the oxidizing agent oxidizes the portion of the surface where the noble metal particles 5 are close to, and the corrosive agent dissolves and removes the oxide. Therefore, as shown in FIG. 7, the etching solution 7 etches the surface of the semiconductor substrate 1 in the vertical direction (that is, the above-mentioned thickness direction) under the action of the catalyst layer 6 as a catalyst.

The corrosive agent dissolves the above oxides. This oxide is, for example, SiO ₂ . The corrosive agent is, for example, hydrofluoric acid.

The hydrogen fluoride concentration in the etching solution 7 is preferably in the range of 0.4 mol / L to 20 mol / L, more preferably in the range of 0.8 mol / L to 16 mol / L, and 2 mol / L. It is more preferably in the range of 10 mol / L. If the hydrogen fluoride concentration is too low, it is difficult to achieve a high etching rate. If the hydrogen fluoride concentration is too high, the controllability of etching in the processing direction (for example, the thickness direction of the semiconductor substrate 1) may decrease.

The oxidizing agents in the etching solution 7 are, for example, hydrogen peroxide, nitric acid, AgNO ₃ , KAuCl ₄ , HAuCl ₄ , K ₂ PtCl ₆ , H ₂ PtCl ₆ , Fe (NO ₃ ) ₃ , Ni (NO ₃ ) ₂ , Mg. (NO ₃ ) ₂ , Na ₂ S ₂ O ₈ , K ₂ S ₂ O ₈ , KMn _{O 4} and K ₂ Cr ₂ O ₇ can be selected. Hydrogen peroxide is preferable as the oxidizing agent because it does not generate harmful by-products and does not contaminate the semiconductor device.

The concentration of the oxidizing agent such as hydrogen peroxide in the etching solution 7 is preferably in the range of 0.2 mol / L to 8 mol / L, and more preferably in the range of 0.5 mol / L to 5 mol / L. It is more preferably in the range of 0.5 mol / L to 4 mol / L. If the concentration of oxidant is too low, it will be difficult to achieve a high etching rate. Excessive concentration of oxidant can result in excessive side etching.

According to the etching method described above, a needle-shaped residual portion 8 may be formed on the semiconductor substrate 1.

The needle-shaped residue 8 may be removed by using at least one of wet etching and dry etching, for example. The etching solution in wet etching can be selected from, for example, a mixed solution of hydrofluoric acid, nitric acid and acetic acid, tetramethylammonium hydroxide (TMAH), KOH and the like. Examples of the dry etching include plasma etching using a gas such as _{SF 6} , CF ₄ , C ₂ F ₆ , C ₃ F ₈ , CCl _{F 2 , CCl 4} , _{PCl 3} , or CBr F _3.

The etching solution 7 may be supplied to the catalyst layer 6 after the third mask layer 4 is removed.

In the method shown in FIGS. 1 to 7, the semiconductor substrate 1 is etched as described above.

By the way, when a semiconductor substrate having no uneven structure including the above-mentioned convex portions is etched, the portion remaining after etching tends to become porous. This will be described below.

In the etching method according to the comparative example, first, as shown in FIG. 8, a structure including the semiconductor substrate 1 having no convex portion 3 and the third mask layer 4 is prepared.

Next, as shown in FIG. 9, the catalyst layer 6 is formed on the surface of the semiconductor substrate 1 by subjecting the structure shown in FIG. 8 to the above-mentioned substitution plating. The catalyst layer 6 contains precious metal particles 5. The noble metal particles 5 include noble metal nanoparticles 5a and noble metal particles 5b. When the catalyst layer 6 is formed on the surface of the semiconductor substrate 1, the noble metal element diffuses inside the semiconductor substrate 1. The portion of the semiconductor substrate 1 containing the diffused noble metal element is referred to as the noble metal diffusing portion 9. The precious metal diffusion portion 9 is formed not only in the portion corresponding to the opening of the third mask layer 4 but also in the portion directly below the third mask layer 4 in the surface region of the semiconductor substrate 1. A part of the precious metal particles 5 is also present in the portion directly below the third mask layer 4.

Next, as shown in FIG. 10, the structure shown in FIG. 9 is etched. As the etching progresses, the noble metal particles 5 and the noble metal diffusion portion 9a corresponding to the opening of the third mask layer 4 of the noble metal diffusion portions 9 move in the thickness direction of the semiconductor substrate 1. On the other hand, of the precious metal diffusing portions 9, the noble metal diffusing portion 9b directly below the third mask layer 4 moves in a direction intersecting the thickness direction as the etching progresses. As a result, a plurality of holes extending in the direction intersecting the thickness direction are formed in the portion of the surface region of the semiconductor substrate 1 directly below the third mask layer 4.

As described above, when a semiconductor substrate having no uneven structure including convex portions is etched, the portion remaining after etching tends to become porous.

On the other hand, according to the etching method described with reference to FIGS. 1 to 7, the portion remaining after etching is unlikely to become porous. The present inventors believe that this is due to the following reasons.

First, the structure shown in FIG. 11 is obtained by the method described with reference to FIGS. 1 to 4. FIG. 11 shows a semiconductor substrate 1 in which the convex portion 3 and the third mask layer 4 are formed.

Next, the structure shown in FIG. 12 is obtained by the method described with reference to FIG. FIG. 12 shows a semiconductor substrate 1 in which a convex portion 3, a third mask layer 4, and a catalyst layer 6 are formed. The catalyst layer 6 contains the noble metal particles 5, and the noble metal particles 5 include the noble metal nanoparticles 5a and the noble metal particles 5b. Further, the semiconductor substrate 1 includes the above-mentioned precious metal diffusion unit 9.

The precious metal diffusion portion 9 is formed in a portion of the surface region of the semiconductor substrate 1 corresponding to the opening of the third mask layer 4, but is difficult to be formed in a portion directly below the third mask layer 4. This is because the upper surface of the convex portion 3 and the lower surface of the third mask layer 4 are sufficiently separated from each other.

Next, when the structure shown in FIG. 12 is etched by the method described with reference to FIGS. 6 and 7, the structure shown in FIG. 13 is obtained. As the etching progresses, the catalyst layer 6 progresses in the thickness direction of the semiconductor substrate 1. Since the noble metal diffusion portion 9 is hardly present in the portion of the semiconductor substrate 1 directly below the third mask layer 4, etching does not easily proceed in this portion.

Therefore, in the etching method described with reference to FIGS. 1 to 7, a plurality of holes extending in a direction intersecting the thickness direction thereof are formed on the semiconductor substrate 1 as compared with the etching method according to the comparative example. Hateful.

Therefore, according to the etching method according to the embodiment, the portion remaining after etching is unlikely to become porous.

Hereinafter, another example of a method of forming an uneven structure including the convex portion 3 on the surface of the semiconductor substrate 1 will be described.

First, as shown in FIG. 14, the semiconductor substrate 1 is prepared, and the second mask layer 10 is formed on the surface of the semiconductor substrate 1. The second mask layer 10 is a layer for forming the semiconductor layer 11 described later on the surface of the semiconductor substrate 1. The second mask layer 10 has one or more openings.

As the material of the second mask layer 10, any material can be used as long as it has sufficient resistance to the film forming process of the semiconductor layer 11 described later.

The material of the second mask layer 10 is, for example, SiN, SiO ₂ or Al. The material of the second mask layer 10 may be the same material as the material of the third mask layer 4 described above.

Next, as shown in FIG. 15, the semiconductor layer 11 is formed in a region of the surface of the semiconductor substrate 1 corresponding to the opening of the second mask layer 10. The semiconductor layer 11 is formed, for example, over the entire area of the opening of the second mask layer 10. The semiconductor layer 11 corresponds to the above-mentioned convex portion 3.

The semiconductor layer 11 is made of, for example, a semiconductor. The semiconductor may be the semiconductor described with reference to FIG. The material of the semiconductor layer 11 may be the same as the material of the semiconductor substrate 1, and may be different from the material of the semiconductor substrate 1 as long as it can be etched under the etching conditions for etching the semiconductor substrate 1. ..

The semiconductor layer 11 can be formed by, for example, epitaxial growth. According to one example, the semiconductor layer 11 can be formed by epitaxially growing silicon.

Next, as shown in FIG. 16, the second mask layer 10 is removed to form the third mask layer 4. The second mask layer 10 may be used as the third mask layer 4 without removing the second mask layer 10.

The other example of the method of forming the concavo-convex structure including the convex portion 3 on the surface of the semiconductor substrate 1 has been described above.

The etching method described above can be used for manufacturing various articles. Further, the etching method described above can also be used for forming recesses or through holes, or for dividing a structure such as a semiconductor wafer. For example, the etching method described above can be used for manufacturing a semiconductor device.

With reference to FIGS. 17 to 26, an example of a method for manufacturing a semiconductor chip, which includes etching a semiconductor wafer and separating it into a plurality of semiconductor chips, will be described.

First, the structures shown in FIGS. 17 and 18 are prepared. This structure includes a semiconductor wafer 12, a second mask layer 10, and a dicing sheet 14. The semiconductor element region 13 is formed on the surface of the semiconductor wafer 12. The second mask layer 10 covers the semiconductor element region 13 which is a region on which the semiconductor element is formed on the surface of the semiconductor wafer 12, and plays a role of protecting the semiconductor element from damage. The dicing sheet 14 is attached to the back side of the surface of the semiconductor wafer 12 provided with the second mask layer 10.

Next, as shown in FIGS. 19 and 20, the semiconductor layer 11 is formed on the surface of the semiconductor wafer 12 by the method described with reference to FIG.
Next, as shown in FIGS. 21 and 22, the second mask layer 10 is removed to form the third mask layer 4 by the method described with reference to FIG.
Next, as shown in FIGS. 23 and 24, the catalyst layer 6 containing a noble metal is formed on the surface of the semiconductor wafer 12 by the method described with reference to FIG.
Next, the structures shown in FIGS. 23 and 24 are etched by the method described with reference to FIGS. 6 and 7 to obtain the structures shown in FIGS. 25 and 26. Etching is performed until the bottom surface of the recess formed thereby reaches the surface of the dicing sheet 14.

As described above, according to the above-mentioned method, as shown in FIGS. 25 and 26, a semiconductor chip 15 each including a semiconductor element region 13 can be obtained.

Further, in this method, the shape of the upper surface of the semiconductor chip is not limited to a square or a rectangle. For example, the shape of the upper surface of the semiconductor chip may be circular or hexagonal. Further, in this method, semiconductor chips having different top surface shapes can be formed at the same time.

Hereinafter, Examples and Comparative Examples will be described.
<Example>
A convex portion, a third mask layer, and a catalyst layer were formed on the semiconductor wafer by the following method, and these were etched. Then, it was investigated whether the portion remaining after etching became porous.

In this method, a semiconductor wafer was fragmented to obtain a semiconductor chip. This individualization was performed so that the volume removed when the semiconductor wafer was individualized was 5% of the volume of the entire semiconductor wafer.

Specifically, first, a first mask layer was formed on the surface of the semiconductor wafer. The first mask layer was formed by photolithography using a photoresist. The first mask layer has openings formed in a grid pattern. The width of the opening was 1 μm.

Next, a convex portion was formed on the semiconductor wafer by dry etching using the first mask layer as an etching mask. The height of the convex portion was 0.2 μm.

Next, the first mask layer was removed, and a third mask layer having an opening at the position of the convex portion was formed on the semiconductor wafer. The size and shape of the opening were formed to be equal to the size and shape of the upper surface of the convex portion. Further, the third mask layer was formed so that the height of the upper surface thereof was equal to the height of the upper surface of the convex portion. FIG. 27 shows the results of observation with a scanning electron microscope of the semiconductor wafer on which the convex portion and the third mask layer are formed.

FIG. 27 is a photomicrograph showing a cross section of a semiconductor substrate on which a convex portion and a third mask layer are formed. As shown in FIG. 27, the height of the upper surface of the third mask layer is equal to the height of the upper surface of the convex portion.

Next, a 50 mL plating solution A containing an aqueous solution of tetrachloroauric acid (III) acid tetrahydrate and hydrofluoric acid was prepared.

Next, the semiconductor wafer on which the convex portion and the third mask layer were formed was immersed in the plating solution A at room temperature for 60 seconds to form a catalyst layer on the upper surface of the convex portion. The immersion was performed without rotating the semiconductor wafer. FIG. 28 shows the results observed with a scanning electron microscope of the semiconductor wafer on which the catalyst layer was formed. FIG. 28 is a photomicrograph showing a cross section of a structure obtained by forming a catalyst layer on the structure shown in FIG. 27.

Next, 27.5 mL of hydrofluoric acid, 8.6 mL of hydrogen peroxide and 63.9 mL of water were mixed to prepare 100 ml of an etching solution. A semiconductor wafer having a convex portion, a third mask layer, and a catalyst layer was immersed in this etching solution at 25 ° C. for 30 minutes, and this was etched. FIG. 29 shows the results of observing the etched semiconductor wafer with a scanning electron microscope.

FIG. 29 is a photomicrograph showing a cross section of the structure obtained by etching the structure shown in FIG. 28. As shown in FIG. 29, according to the etching method according to the example, the portion remaining after etching did not become porous.

<Comparison example>
The third mask layer and the catalyst layer were formed on the semiconductor substrate by the same method as the etching method described in the examples except that the convex portions were not formed on the semiconductor wafer, and the third mask layer and the catalyst layer were etched.

FIG. 30 is a photomicrograph showing a cross section of a structure obtained by etching a semiconductor wafer having no uneven structure including a convex portion. As shown in FIG. 30, the portion of the semiconductor wafer region remaining after etching was porous.

The present invention is not limited to the above embodiment as it is, and at the implementation stage, the components can be modified and embodied within a range that does not deviate from the gist thereof. In addition, various inventions can be formed by an appropriate combination of the plurality of components disclosed in the above-described embodiment. For example, some components may be removed from all the components shown in the embodiments. Further, components over different embodiments may be combined as appropriate.
The inventions described in the original claims are described below.
[1]
Forming a concavo-convex structure including convex parts on the surface of the semiconductor substrate,
To selectively form a catalyst layer containing a noble metal with respect to the upper surface of the convex portion of the surface.
An etching method comprising supplying an etching solution to the catalyst layer and etching the semiconductor substrate under the action of the noble metal as a catalyst.
[2]
The formation of the uneven structure is
To form a first mask layer having an opening on the surface,
Using the first mask layer as an etching mask to etch the surface,
Item 2. The etching method according to Item 1, which comprises removing the first mask layer.
[3]
The formation of the uneven structure is
To form a second mask layer having an opening on the surface,
Item 2. The etching method according to Item 1, which comprises forming a semiconductor layer on the surface at the position of the opening.
[4]
Item 3. The etching method according to Item 3, wherein the semiconductor layer is formed by an epitaxial growth method.
[5]
The formation of the catalyst layer is performed in the presence of a third mask layer which is open at the position of the convex portion and has an upper surface having a height equal to or higher than the upper surface of the convex portion. The etching method according to any one of 4.
[6]
Item 5. The etching method according to Item 5, wherein the etching solution is supplied to the catalyst layer while leaving the third mask layer.
[7]
Item 6. The etching method according to Item 6, wherein the third mask layer has higher etching resistance to the etching solution as compared with the convex portion.
[8]
Item 6. The etching method according to any one of Items 1 to 7, wherein the etching solution contains a corrosive agent and an oxidizing agent.
[9]
The corrosive agent contains hydrofluoric acid and
The oxidizing agents are hydrogen peroxide, nitric acid, AgNO ₃ , KAuCl ₄ , HAuCl ₄ , K ₂ PtCl ₆ , H ₂ PtCl ₆ , Fe (NO ₃ ) ₃ , Ni (NO ₃ ) ₂ , Mg (NO ₃ ) _2. Item 8. The etching method according to Item 8, which comprises at least one of Na ₂ S ₂ O ₈ , K ₂ S ₂ O ₈ , KMn _{O 4} , and K ₂ Cr ₂ O _7.
[10]
Item 6. The etching method according to any one of Items 1 to 9, wherein the height of the convex portion is in the range of 0.15 μm to 0.5 μm.
[11]
Item 6. The etching method according to any one of Items 1 to 10, wherein the precious metal is Au.
[12]
A method for manufacturing a semiconductor chip, which comprises etching a semiconductor wafer by the etching method according to any one of Items 1 to 11 and fragmenting the semiconductor wafer into semiconductor chips, the surface of which is the surface of the semiconductor wafer.
[13]
A method for producing an article, which comprises etching the surface by the etching method according to any one of Items 1 to 12.

1 ... semiconductor substrate, 2 ... first mask layer, 3 ... convex part, 4 ... third mask layer, 5 ... noble metal particles, 5a ... noble metal nanoparticles, 5b ... noble metal particles, 6 ... catalyst layer, 7 ... etching solution, 8 ... Needle-shaped residual portion, 9 ... Noble metal diffusion portion, 9a ... Noble metal diffusion portion, 9b ... Noble metal diffusion portion, 10 ... Second mask layer, 11 ... Semiconductor layer, 12 ... Semiconductor wafer, 13 ... Semiconductor element region, 14 ... Dicing sheet, 15 ... Semiconductor chip.

Claims (13)

Forming a concavo-convex structure including convex parts on the surface of the semiconductor substrate,
To selectively form a catalyst layer containing a noble metal with respect to the upper surface of the convex portion of the surface.
It includes supplying an etching solution to the catalyst layer and etching the semiconductor substrate under the action of the noble metal as a catalyst.
The formation of the uneven structure is
To form a first mask layer having an opening on the surface,
Using the first mask layer as an etching mask to etch the surface,
An etching method including removing the first mask layer. Forming a concavo-convex structure including convex parts on the surface of the semiconductor substrate,
To selectively form a catalyst layer containing a noble metal with respect to the upper surface of the convex portion of the surface.
It includes supplying an etching solution to the catalyst layer and etching the semiconductor substrate under the action of the noble metal as a catalyst.
The formation of the uneven structure is
To form a second mask layer having an opening on the surface,
An etching method including forming a semiconductor layer on the surface at the position of the opening. The etching method according to claim 2, wherein the semiconductor layer is formed by an epitaxial growth method. The formation of the catalyst layer is performed in the presence of a third mask layer which is open at the position of the convex portion and has an upper surface having a height equal to or higher than the upper surface of the convex portion. The etching method according to any one of 3 to 3. It further comprises forming a third mask layer opened at the position of the convex portion after forming the uneven structure and before forming the catalyst layer, wherein the catalyst layer is the upper surface of the convex portion. The etching method according to any one of claims 1 to 3, wherein the third mask layer is selectively formed on the upper surface of the convex portion. The etching method according to claim 4 or 5, wherein the etching solution is supplied to the catalyst layer while leaving the third mask layer. The etching method according to claim 6, wherein the third mask layer has higher etching resistance to the etching solution as compared with the convex portion. The etching method according to any one of claims 1 to 7, wherein the etching solution contains a corrosive agent and an oxidizing agent. The corrosive agent contains hydrofluoric acid and
The oxidizing agents are hydrogen peroxide, nitric acid, AgNO ₃ , KAuCl ₄ , HAuCl ₄ , K ₂ PtCl ₆ , H ₂ PtCl ₆ , Fe (NO ₃ ) ₃ , Ni (NO ₃ ) ₂ , Mg (NO ₃ ) _2. , Na ₂ S ₂ O ₈ , K ₂ S ₂ O ₈ , KMnO ₄ , and K ₂ Cr ₂ O _{7 according} to claim 8. The etching method according to any one of claims 1 to 9, wherein the height of the convex portion is in the range of 0.15 μm to 0.5 μm. The etching method according to any one of claims 1 to 10, wherein the precious metal is Au. Forming a concavo-convex structure including convex parts on the surface of the semiconductor substrate,
To selectively form a catalyst layer containing a noble metal with respect to the upper surface of the convex portion of the surface.
A semiconductor wafer is etched into a semiconductor chip by an etching method including supplying an etching solution to the catalyst layer and etching the semiconductor substrate under the action of the noble metal as a catalyst. A method for manufacturing a semiconductor chip whose surface is the surface of the semiconductor wafer. A method for manufacturing an article, which comprises etching the surface by the etching method according to any one of claims 1 to 11.

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