JP6237156B2 - Scheduling device, cell processing device, and traffic shaping method - Google Patents

Description

  The present invention relates to a scheduling device, a cell processing device, and a traffic shaping method, and can be applied to traffic shaping of an ATM (Asynchronous Transfer Mode) cell processing device applied to an exchange device or a transmission device, for example.

  As a traffic shaping method for ATM cells, for example, there is a method described in Patent Document 1. The technology described in Patent Document 1 stores an arrival cell in a corresponding queue among a plurality of queues, and uses a content addressable memory (hereinafter referred to as CAM) to read a read time for the storage cell of the queue. The scheduling is performed by instructing cell output to the corresponding queue at the set read time.

JP 2002-368785 A

  The technique described in Patent Document 1 has the following problems.

<Problem 1>
As shown in FIG. 9, between ATM cell processing devices 1 and 1 facing each other, ATM cells of a plurality (4 in FIG. 9) of ATM ports P1 to P4 are multiplexed and transmitted, and each ATM cell processing device 1 Multiplexed ATM cells arriving from the opposing ATM cell processing device are demultiplexed for each ATM port P1 to P4 and distributed to the respective ATM ports P1 to P4. When each ATM cell processing device 1 performs ATM cell traffic shaping for each ATM port P1 to P4 of the demultiplexed ATM cell, the scheduling device 2 to which the traffic shaping method described in Patent Document 1 is applied. Must be provided by the number of ATM ports (= 4), and the hardware scale of the ATM cell processing apparatus 1 is increased or the processing amount of software processing is increased.

<Problem 2>
In the technique described in Patent Document 1, the actual time and the next read time are compared in each process at the time of cell input or output to the CAM. In a general implementation, a time counter that counts the actual time uses a finite counter value, so that the counter value periodically returns to zero. When the round cycle of the count value is simply determined according to the number of ports or the like, the magnitude comparison at both times is simply a magnitude comparison. Therefore, when the counter value is reset only for one of the cases, the comparison determination result may be reversed from the original result. In view of such a point, the technique described in Patent Document 1 proposes a process of periodically updating the reading time from the CAM by applying a time counter having a period three times the theoretically determined period. Yes. However, when a time counter with a long round cycle is applied, there is a concern that the processing may be complicated and the configuration may be complicated.

  Therefore, a scheduling device, a cell processing device, and a traffic shaping method that can reduce the hardware scale, simplify processing, and simplify the configuration are desired.

According to the first aspect of the present invention, an input cell is stored in a corresponding queue among a plurality of queues prepared for each connection number based on the connection number included in the header of the input cell. In the scheduling device for setting the next output time for the storage cell and forming the output instruction of the storage cell that matches the next output time for which the current time is set, (1) storing the next output time for each connection number; An associative memory means for executing a search every time a search for a next output time that matches the input current time is instructed at a predetermined period; (2) a current time clock means for counting up the current time; and (3) a current time clock means. Master clock means for measuring a master time having the same basic update cycle as the time, and (4) when there are a plurality of next output times that match the current time when searching the associative memory means. Otherwise, the current time by the current time clock means is counted up, and if there are a plurality of next output times that match the current time, the current time count by the current time clock means is stopped, the amount that the current time is later than the master time, when there is no next output time matching the current time, possess a current time clock control means for eliminating expediting the count-up period of the current time clock means, (5 The port number is included in the header of the input cell. The associative memory means, the current time clock means, the master clock means, and the current time clock control means are provided for each port number, and each associative memory means The search timing is shifted .

  According to the second aspect of the present invention, cell storage means having a plurality of queues for each connection number and the input cells are stored in the corresponding queues among the plurality of queues based on the connection numbers included in the headers of the input cells. A scheduling unit configured to set a next output time for the storage cell for each of the queues and form an output instruction for the storage cell that matches the next output time for which the current time is set. As a device, the scheduling device according to the first aspect of the present invention is applied.

According to a third aspect of the present invention, an input cell is stored in a corresponding queue among a plurality of queues prepared for each connection number based on the connection number included in the header of the input cell. In the traffic shaping method in the scheduling device for setting the next output time for the storage cell and forming an output instruction for the storage cell that matches the next output time for which the current time is set, (1) the associative memory means includes a connection number Each time the next output time is stored, the search is executed every time a search for the next output time that matches the input current time is instructed in a predetermined cycle. (2) The current time clock means counts up the current time (3) The master clock means measures the master time having the same basic update cycle as the current time, and (4) the current time clock control means is the above associative memory. When there is a plurality of next output times that match the current time at the stage search, the current time by the current time clock means is counted up, and when there are a plurality of next output times that match the current time, Stop counting the current time by the current time clock means, and count up the current time clock means when there is no next output time that matches the current time because the current time is delayed from the master time by this stop. (5) The port number is included in the header of the input cell, and the associative memory means, the current time clock means, the master clock means, and the current time clock control means are provided for each port number. Provided, and the search timing of each of the associative memory means is shifted .

  According to the present invention, it is possible to realize a scheduling device, a cell processing device, and a traffic shaping method that can reduce the hardware scale, simplify processing, and simplify the configuration.

It is a block diagram which shows the structure of the ATM cell processing apparatus of embodiment and the scheduling apparatus of embodiment. It is explanatory drawing which shows an example of the address map of the buffer management information storage part in the ATM cell processing apparatus of embodiment. It is explanatory drawing which shows an example of the address map of CAM in the scheduler in the ATM cell processing apparatus of embodiment. It is each part timing chart in the ATM cell processing apparatus of embodiment. It is a flowchart which shows the operation | movement when the ATM cell in the ATM cell processing apparatus of embodiment is input. It is a flowchart (1) which shows the operation | movement at the time of reading the ATM cell in the ATM cell processing apparatus of embodiment. It is a flowchart (2) which shows the operation | movement at the time of reading the ATM cell in the ATM cell processing apparatus of embodiment. It is a timing chart which shows the change of the port time when multiple coincidence occurs in a certain scheduler in the ATM cell processing device of the embodiment. It is explanatory drawing of the conventional subject.

(A) Main Embodiment Hereinafter, an embodiment of a scheduling device, a cell processing device, and a traffic shaping method according to the present invention will be described with reference to the drawings. The cell processing apparatus according to the embodiment is an ATM cell processing apparatus such as an exchange apparatus or a transmission apparatus that handles ATM cells.

(A-1) Configuration of Embodiment FIG. 1 is a block diagram illustrating configurations of an ATM cell processing device of the embodiment and a scheduling device of the embodiment. 1, the detailed configuration of the scheduler is illustrated only for the scheduler 14-1 of the port P1, but the schedulers 14-2 to 14-M of the ports P2 to PM (M is an integer of 2 or more) are also included in the scheduler 14. It has the same detailed configuration as -1.

  In FIG. 1, an ATM cell processing apparatus 10 according to an embodiment includes a cell input processing unit 11, a cell storage unit 12, an output cycle storage unit 13, schedulers 14-1 to 14-M, a port selector 15, a timing counter 16, and a master clock. 17, a next output time calculation unit 18, a buffer control unit 19, and a buffer management information storage unit 20. The components excluding the cell storage unit 12 are also components of the scheduling apparatus according to the embodiment.

  Each scheduler 14-m (m is 1 to M) includes a CAM 41-m, a CAM search control unit 42-m, a port clock 43-m, a port clock control unit 44-m, and a master clock phase shift unit 45-m. Have.

  The function of each part will be described below, but the details of the function will also be clarified in the description of the operation.

  The cell input processing unit 11 extracts header information S101 such as a port number and an in-device connection number from the input ATM cell (input cell) S100, and uses the extracted header information S101 as the buffer control unit 19 and all schedulers 14. Output to CAM 41-1 to 41-M in -1 to 14-M. Further, the cell input processing unit 11 outputs the input cell S100 to the cell storage unit 12 as it is.

  Here, the port number to be extracted is an identifier indicating an ATM port (hereinafter, abbreviated as a port as appropriate) as an ATM cell output destination. The in-device connection number is an identifier indicating the ATM line (connection) to which the ATM cell belongs. The port number and the in-device connection number are stored in the header of the ATM cell S100 input to the ATM cell processing device 10.

  The cell storage unit 12 is an aggregate of queue buffers Q1 to QN for each in-device connection. The cell storage unit 12 is provided with an input cell S100 from the cell input processing unit 11, and is also provided with a cell write instruction S104 and a cell read instruction S103 from the buffer control unit 19, and the cell storage unit 12 receives the input cell S100. Then, the data is written to the queue buffer Qw (w is 1 to N) defined by the cell write instruction S104, and the ATM cell S200 is read from the queue buffer Qr (r is 1 to N) defined by the cell read instruction S103. The ATM cell S200 read from the cell storage unit 12 has been scheduled and is given to the subsequent circuit.

  The buffer control unit 19 fetches buffer status information S111 including a write pointer, a read pointer, a time setting flag, etc. from the buffer management information storage unit 20, and responds to a change in the status of the cell stored in the cell storage unit 12. The updated buffer status information S112 is output to the buffer management information storage unit 20. Here, the write pointer is a cell write start address in the queue buffer Qw for writing the ATM cell, and the read pointer is a cell read start address in the queue buffer Qr for reading the ATM cell. The time setting flag indicates whether or not the next output time is set for the CAM 41-m corresponding to the port number of the current input cell, and “1” is set when the next output time is set. Set to the time setting flag.

  The buffer control unit 19 inputs the in-device connection number of the input cell S100 from the cell input processing unit 11, and sends to the cell storage unit 12 a buffer write instruction S104 for instructing writing to the queue buffer related to the in-device connection number. Output.

  The selected CAM search match information S106 is input from the port selector 15 to the buffer control unit 19, and the buffer control unit 19 instructs reading from the queue buffer related to the in-device connection number in the CAM search match information S106. Cell read instruction S103 is output to cell storage unit 12. Further, the buffer control unit 19 outputs a next output time calculation instruction S109 to the next output time calculation unit 18.

  The buffer control unit 19 outputs a CAM registration instruction S110 to the CAMs 41-1 to 41-M of the schedulers 14-1 to 14-M and registers the next output time.

  The buffer management information storage unit 20 stores a write pointer, a read pointer, and a time setting flag for each address corresponding to the in-device connection number. FIG. 2 shows an example of an address map of the buffer management information storage unit 20. In FIG. 2, a 19-bit memory area is allocated for each in-device connection number (CONID = 0, 1, 2,..., 255 (= N)), and a read pointer RP [ 8: 0] is assigned, the write pointer WP [8: 0] is assigned to the higher 9 bits, and the time setting flag F is assigned to the most significant bit. The read pointer RP [8: 0] and the write pointer WP [8: 0] are reset (that is, updated cyclically) at a timing exceeding the maximum value represented by 9 bits. Accordingly, when the queue buffer related to a certain in-device connection number is full, the read pointer RP [8: 0] is larger than the write pointer WP [8: 0] by 1 and the queue buffer is empty. Is equal to the read pointer RP [8: 0] and the write pointer WP [8: 0].

  The output cycle storage unit 13 stores a basic cell interval (in other words, a set bandwidth) for each connection. The cell interval S102 stored in the output cycle storage unit 13 is read by the next output time calculation unit 18.

  The next output time calculation unit 18 receives the next output time calculation instruction S 109 from the buffer control unit 19, the port time S 107 selected from the port selector 15, and the cell interval S 102 from the output cycle storage unit 13. The next output time calculation unit 18 calculates the next output time S108 of the ATM cell connection (connection number in the apparatus) input to the cell storage unit 12 based on the input information, and all the schedulers 14-1 To 14-M CAMs 41-1 to 41-M.

  The timing counter 16 is a counter that counts up by 1 every cell time. The timing counter 16 is a counter whose period is a period obtained by multiplying one cell time by the number of schedulers (= number of ports) (hereinafter also referred to as port time). The timing counter 16 outputs cell timing information S601 that is a counter value to the port selector 15, the CAM search control units 42-1 to 42-M, and the port clocks 43-1 to 43-M.

  The master clock 17 supplies reference time information to all the schedulers 14-1 to 14-M. The master clock 17 is a counter that counts up by 1 every port time. That is, since the number of ATM ports is M, the master clock 17 counts up every M cell time. The master clock 17 outputs the master time S701 that is the counter value to the master clock phase shift units 45-1 to 45-M.

  The scheduler 14-m for the port Pm determines (schedules) the output time (read time from the cell storage unit 12) of the ATM cell addressed to the port number Pm stored in the cell storage unit 12.

  The CAM 41-m in the scheduler 14-m is composed of an associative memory as described in Patent Document 1, and the next output time of each queue and the CAM registration valid / invalid bit are set for each address corresponding to the in-device connection number. It is something to remember. FIG. 3 shows an example of the address map of the CAM 41-m. In FIG. 3, a 13-bit memory area is allocated for each in-device connection number (CONID = 0, 1, 2,..., 255), and the next output time [11: 0] is assigned to the lower 12 bits in the memory area. Is assigned, and the CAM registration valid / invalid bit V is assigned to the most significant bit. The CAM registration valid / invalid bit is information indicating whether the next output time stored in the CAM 41-m is valid or invalid, and takes “1” when valid and “0” when invalid.

  The CAM 41-m receives the next output time setting instruction S105 from the buffer control unit 19, receives the header information S101 from the cell input processing unit 11, receives the CAM registration instruction S110 from the buffer control unit 19, and receives the next output time. The next output time S108 is input from the calculation unit 18, the CAM search execution instruction S402-m is input from the CAM search control unit 42-m, and the port time S401-m is input from the port clock 43-m.

  The CAM 41-m performs storage content update processing based on input information such as the next output time setting instruction S105, header information S101, CAM registration instruction S110, and next output time S108.

  The CAM 41-m searches for an address (connection number in the apparatus) that matches the port time S401-m when a valid CAM search execution instruction S402-m is input, and controls the port selector 15 and the port clock. CAM search match information S406-m, which is a CAM search result including a match flag and a match address (intra-device connection number), is output to the unit 44-m, and a CAM search multiple match flag S403 is output to the port clock control unit 44-m. -M is output. In the search of the CAM 41-m, a plurality of match addresses may be searched (multiple match). At this time, the CAM search multiple match flag S403-m becomes “1”. Even in such a case, the CAM search match information S406-m includes only one match address (for example, the address of the youngest number).

  The CAM search control unit 42-m performs a CAM search. Cell timing information S601 is input from the timing counter 16 to the CAM search control unit 42-m, and port time S401-m is input from the port clock 43-m. The CAM search control unit 42-m The CAM search execution instruction S402-m is formed at the timing determined for the own port Pm based on, and output to the CAM 41-m.

  The port clock 43-m generates time information (port time) S401-m used by the scheduler 14-m to actually determine the output time of the next cell.

  The port clock 43-m counts up the port time S401-m of the port Pm, and the port time S401-m is incremented by 1 every timing of 1 cell time × number of ports. The cell clock information S601 is input from the timing counter 16 to the port clock 43-m, and the port clock control signal S404-m is input from the port clock controller 44-m. The port clock 43-m is based on these. The appropriately updated port time S401-m is output to the CAM 41-m, the CAM search control unit 42-m, and the port selector 15. Increment timings of the port clocks 43-1 to 43-M of the schedulers 14-1 to 14-M are shifted by one cell time by the cell timing information S601.

  The timing chart of FIG. 4 also includes timing charts of port times S401-1 to S401-M in the respective schedulers 14-1 to 14-M. FIG. 4 shows a case where the number of ports M is four. The cell timing information S601 output from the timing counter 16 circulates in accordance with the number of ports M (= 4). In the example of FIG. 4, the values “0” to “3” are cyclically changed. . The port time S401-m in each scheduler 14-m is incremented by 1 when the cell timing information S601 takes the value “m−1”, whereby the port times S401-1 to S401-M are incremented by the increment timing. Are shifted by one cell time. In FIG. 4, the period described as “another port cell output time” is a time during which a port other than the port Pm related to the port time S401-m outputs a cell. And the “other port cell output time”, the operation of the scheduler 14-m is different.

  As described above, the port clock 43-m has a function of counting the cell output time at the corresponding port Pm. The port clock 43-m has a function of stopping the count or speeding up the count according to the port clock control signal S404-m from the port clock control unit 44-m. The reason why the count is stopped or fast-turned will be clarified in the operation section.

  The port clock control unit 44-m implements stop / fast-forward control of the count of the port clock 43-m. The port clock control unit 44-m receives the CAM search multiple match flag S403-m and the CAM search match information S406-m from the CAM 41-m, and receives the port time S401-m from the port clock 43-m. Master time S405-m of corresponding port Pm is input from master clock phase shift unit 45-m, and port clock control unit 44-m uses port clock control signal S404-m generated based on these inputs as port clock 43-m. output to m.

  Master clock phase shift unit 45-m receives master time S701 from master clock 17 and cell timing information S601 from timing counter 16, and master clock phase shift unit 45-m is based on these inputs. Thus, a master time S405-m in which the phase of the master time S701 is shifted by a predetermined amount for the corresponding port Pm is generated and output to the port clock controller 44-m.

  The timing chart of FIG. 4 also includes timing charts of the master times S405-1 to S405-M corresponding to the ports in the schedulers 14-1 to 14-M. The master clock phase shift unit 45-m shifts the phase of the master time S701 so that the master time S405-m of the corresponding port Pm is updated when the cell timing information S601 takes the value “m−1”. Thereby, the phases (change timings) of the master times S405-1 to S405-M corresponding to the ports P1 to PM are shifted by one cell time.

  Cell timing information S601 is input from the timing counter 16 to the port selector 15, port times S401-1 to S401-M are input from the port clocks 43-1 to 43-M, and CAMs 41-1 to 41-M to CAM. The search match information S406-1 to S406-M is input, and the port selector 15 selects the cell timing information S601 from the port times S401-1 to S401-M and the CAM search match information S406-1 to S406-M. The port time determined by the value at that time and the CAM search match information are selected, the selected port time S107 is output to the next output time calculation unit 18, and the selected CAM search match information S106 is output to the buffer control unit 19. .

(A-2) Operation of Embodiment Next, the operation of the ATM cell processing apparatus 10 of the embodiment having the above-described configuration will be described in order by dividing the operation at the time of cell input and the operation at the time of cell output.

<Operation during cell input>
FIG. 5 is a flowchart showing the operation of the ATM cell processing apparatus 10 when an ATM cell is input.

  When an ATM cell is input, the cell input processing unit 11 extracts the header information S101 of the input cell (step ST100), and based on the in-device connection number in the extracted header information S101, the buffer control unit 19 Then, the buffer management information storage unit 20 reads the buffer status information S111 (see FIG. 2) including the write pointer, the read pointer, and the time setting flag (step ST101).

  Then, based on the buffer status information S111, the buffer control unit 19 determines whether or not the queue buffer Qn corresponding to the in-device connection number of the input cell is full (step ST102). For example, when the read pointer is write pointer + 1, it is determined that the queue buffer Qn is full.

  If the queue buffer Qn is full, the buffer control unit 19 does not issue the buffer write instruction S103 (does not perform buffer write), and discards the input ATM cell (step ST103).

  If the queue buffer Qn is not full, the buffer control unit 19 determines whether or not the queue buffer Qn corresponding to the in-device connection number of the input cell is empty and the time setting flag is “0” (invalid). It discriminate | determines (step ST104). For example, it is determined that the queue buffer Qn is empty when the read pointer matches the write pointer.

  When the queue buffer Qn corresponding to the in-device connection number of the input cell is empty and the time setting flag is “0”, the buffer control unit 19 sets the next output time to the CAM, the queue buffer of the input cell Control is performed to execute writing to the disk and updating the write pointer (steps ST105 to ST107). The order of control for executing these three operations is not limited to the order shown in FIG.

  When the queue buffer Qn is not full and the queue buffer Qn is not empty or the time setting flag is “1”, the buffer control unit 19 writes the input cell to the queue buffer and updates the write pointer. Control is performed (steps ST108 and ST109). The order of control for executing these two operations is not limited to the order shown in FIG. In FIG. 5, step ST106 and step ST108 are separately described as the step of writing the input cell into the queue buffer. However, these steps may be executed by the same processing routine. Similarly, the write pointer update step ST107 and step ST109 may be executed by the same processing routine.

  In step ST105 for setting the next output time to the CAM, the buffer control unit 19 issues a next output time setting instruction S105 to all (port) schedulers 14-1 to 14-M. The CAM 41-m of each scheduler 14-m (m is 1 to M) is a CAM that sets the next output time based on the port number in the header information S101 input from the cell input processing unit 11. (In other words, whether or not the port related to the scheduler is a port to be set). The CAM 41-m that sets the next output time sets the current port time +1 as the next cell output time to the address corresponding to the in-device connection number in the header information S101 of the input cell, and sets the CAM registration valid / invalid bit. Set to “1” (valid) (see FIG. 3).

  In writing steps ST106 and ST108 of input cells to the queue buffer, the buffer control unit 19 issues a buffer write instruction S103 to the cell storage unit 12, and writes the input cell S100 to the corresponding queue buffer Qn.

  In the write pointer update steps ST107 and ST109, the buffer control unit 19 increases the write pointer fetched from the buffer management information storage unit 20 by 1 (however, if the value before update is the maximum value, it is updated to the minimum value). ) The buffer state information S112 including the updated write pointer is output to the buffer management information storage unit 20 and overwritten.

  As described above, if the time setting flag = 0 of the connection at the time of cell input (cell reception), the next cell time is registered as the output time, so the cell interval from the previous output cell is If the cell interval is greater than the previous output cell time while ensuring, cell output can be immediately performed after cell input. The cell output of the in-device connection number whose cell output is delayed by the operation at the time of multiple coincidence described later can be advanced, and the average cell interval can be made closer to the predetermined cell interval.

<At cell output>
FIGS. 6 and 7 are flowcharts showing the operation of the ATM cell processing apparatus 10 when reading an ATM cell. FIG. 6 shows the cell time during which the port selector 15 selects CAM search match information from the scheduler of its own port. 7 mainly shows the operation of the scheduler, and FIG. 7 mainly shows the operation of the scheduler in the cell time when the port selector 15 selects the CAM search match information from the scheduler of the other port.

  In FIG. 4 described above, the own port cell output time and the other port cell output time are shown in time series.

  In each scheduler 14-1 to 14-M, for each cell time, port times S401-1 to S401-M represented by the port clocks 43-1 to 43-M in the scheduler and the CAM registration valid / invalid bit “ 1 ”(valid) is used as a search key, and the search for CAMs 41-1 to 41-M is activated by the CAM search execution instructions S402-1 to S402-M from the CAM search control units 42-1 to 42-M. . Each of the CAMs 41-1 to 41-M executes a search, passes the CAM search match information S406-1 to S406-M, which is a CAM search result, to the port selector 15, and sets the CAM search multiple match flags S403-1 to S403-M. Are transmitted to the port clock control units 44-1 to 44-M, and the port selector 15 outputs the ATM time determined for each port based on the cell timing information S601 (for example, in the case of the port P1). For example, when the cell timing information S601 is “3” (see FIG. 4), the CAM search match information S406-m related to the port is selected and given to the buffer control unit 19 as the selected CAM search match information S106. Also (step ST200). Note that, as described above, the CAM search match information S406-1 to S406-M includes information on the match flag and the match address (internal connection number).

  The schedulers 14-1,..., 14-M of each port operate by shifting by one cell time so that the output cell timings of the schedulers of the respective ports do not compete with each other, and input from the timing counter 16 as shown in FIG. The cell output time of the own port is uniquely identified from the value of the cell timing information S601, and the cell output is controlled in cooperation.

  For example, when viewed from the scheduler 14-1 of the port P 1, the cell time that the own port outputs the cell is when the cell timing information S 601 is “3”, and the cell time that the other ports P 2 to P 4 output the cell is This is when the cell timing information S601 is “0”, “1”, and “2”. Further, for example, when viewed from the scheduler 14-2 of the port P2, the cell time that the own port outputs the cell is when the cell timing information S601 is “0”, and the cells that the other ports P1, P3, and P4 output the cell. The time is when the cell timing information S601 is “1” to “3”. The cell times are similarly determined for the schedulers 14-3 and 14-4 of the ports P3 and P4.

  The buffer control unit 19 uses the CAM match address to read the write pointer and the read pointer from the buffer management information storage unit 20 to identify the buffer state, and according to the result, cell output processing, port time control processing, CAM Performs clear processing (writes “0” to the CAM registration valid / invalid bit of CAM), and after output of the ATM cell, outputs a new cell output time (cell time + set band (output cycle)) to the CAM of its own port. Further, the time setting flag is set to “1” (steps ST201 to ST215, ST250 to ST254). The port clock controller 44-m also executes a control operation according to the CAM search match information S406-m.

  The operation according to the selected CAM search match information S106 will be described below by dividing into the cell output time of the own port (see FIG. 6) and the cell output time of other ports (see FIG. 7).

  Based on the match flag, the buffer control unit 19 determines whether there is a match in the search of the CAM 41-m related to the scheduler 14-m of the own port (step ST201).

  If there is no match in the search of the CAM 41-m, the buffer control unit 19 does not execute the cell output process, and also sets the time setting flag of the buffer management information storage unit 20 and the CAM registration information of the CAM 41-m. The valid / invalid bit is not manipulated. In this case, only the operation of incrementing the port time by 1 by the port clock control unit 44-m is executed (step ST202).

  If there is a match in the search of the CAM 41-m, the buffer control unit 19 determines whether the queue buffer in the cell storage unit 12 defined by the match address (device connection number) is empty (there is a CAM search match and the queue It is determined whether or not the buffer is empty. Whether or not the queue buffer is empty is recognized based on whether or not the read pointer and the write pointer obtained from the buffer management information storage unit 20 match as described above.

  If there is a match in the search of the CAM 41-m and the queue buffer specified by the match address (in-device connection number) is not empty, the buffer control unit 19 specifies the match address (in-device connection number). The ATM cell at the position indicated by the read pointer of the queue buffer in the cell storage unit 12 is output (step ST204), and the current port time indicated by the port time S107 is designated as the new (next) output time (read time). The time obtained by adding the output periods related to the coincidence address (in-device connection number) from the output period storage unit 13 is obtained and registered in the CAM 41-m, and the CAM registration valid / invalid bit is set to “1” (step ST205). ) In addition, “1” is set in the time setting flag related to the coincidence address (internal connection number). In addition, the read pointer fetched from the buffer management information storage unit 20 is incremented by 1 (however, if the pre-update is the maximum value, the read pointer is updated to the minimum value), and the post-update read pointer is updated. The included buffer status information S112 is output to the buffer management information storage unit 20 and overwritten (step ST207). In the above processing, without confirming whether or not the queue buffer is empty at the time of cell output, it is assumed that there are still ATM cells remaining, and various parameters are updated, and are empty at the next output timing. It is supposed to be confirmed.

  Even when there is a match in the search of the CAM 41-m and the queue buffer specified by the match address (intra-device connection number) is not empty, the port clock control unit 44-m is related to the search for the CAM 41-m. As information, CAM search match information S406-m and CAM search multiple match flag S403-m are given. Here, the control operation by the port clock control unit 44-m is executed independently of the control operation by the buffer control unit 19, and the port clock control unit 44-m has a match address in the CAM search match information S406-m. Recognize something independently. The port clock control unit 44-m determines whether or not the CAM search multiple match flag S403-m is set (step ST208). In other words, it is determined whether or not there are a plurality of in-device connection numbers in which the current port time is set as the cell output time. If the CAM search multiple match flag S403-m is not set, the port clock control unit 44-m increments the port time by 1 (step ST209), and the CAM search multiple match flag S403-m is set. The port time is not updated (the count is stopped; step ST210).

  The buffer control unit 19 updates the CAM registration valid / invalid bit to “0” if there is a match in the search of the CAM 41-m and the queue buffer defined by the match address (in-device connection number) is empty. Then, “0” is set to the time setting flag related to the coincidence address (connection number in apparatus) (step ST212).

  When there is a match in the search of the CAM 41-m and the queue buffer specified by the match address (device connection number) is empty, the control operation by the port clock control unit 44-m is the port when the queue buffer is not empty. Since it is the same as the control operation by the timepiece control unit 44-m, detailed description thereof is omitted (steps ST213 to ST215).

  FIG. 7 shows the own port (the other port when viewed from the port represented by the cell timing information S601) when the value of the cell timing information S601 input from the timing counter 16 represents the cell output time of the other port other than the own port. ) Shows a control operation by the port clock control unit 44-m in the scheduler 14-e (e is 1 to M). The buffer control unit 19 executes control processing related to the port indicated by the value of the cell timing information S601 (see FIG. 6), but does not execute control processing related to ports other than the port indicated by the value of the cell timing information S601. is there.

  The port clock control unit 44-e determines whether there is a match based on the CAM search match information S406-e, although it is the cell time of the other port (step ST250). If there is a match, the port clock control unit 44-m continues the current port time (step ST251). If there is no match, the port clock control unit 44-m determines whether the master time S405-e of the port Pe matches the port time S401-e (step ST252). If the two times coincide, the port clock control unit 44-m continues the current port time (step ST253). On the other hand, if both times do not match, the port clock control unit 44-m increases the current port time by 1 and approaches the master time (step ST254).

  The following is a list of the above operations, organized by case. As long as various parameters can be updated and the operation can be controlled as described below, the operation is not limited to the procedure shown in FIGS.

(A) Operation at time of own port cell output (A-1) When CAM search does not match-Cell output processing: No cell output-Port time control: Port time = Port time + 1
-Time setting flag setting: No processing-CAM registration valid / invalid bit: No processing (A-2) CAM search match and buffer not empty-Cell output processing: Cell output-Port time control:
-When there is no multiple match: port time = port time + 1
-When there is multiple match: port time = port time (count stop)
• Time setting flag setting: 1 set • CAM registration valid / invalid bit: 1 set (a-3) CAM search match and buffer empty • Cell output processing: No cell output • Port time control:
-When there is no multiple match: port time = port time + 1
-When there is multiple match: port time = port time (count stop)
-Time setting flag setting: 0 is set-CAM registration valid / invalid bit: 0 is set (a) Operation at the time of other port cell output (i-1) No CAM search match-Cell output processing: No cell output-Port time control :
-When master time = port time: Port time = port time-When master time ≠ port time: Port time = port time + 1 (count forward)
-Time setting flag setting: No processing-CAM registration valid / invalid bit: No processing (b-2) CAM search match-Cell output processing: No cell output-Port time control: Port time = Port time-Time setting flag setting: No processing-CAM registration valid / invalid bit: No processing Even if there is a plurality of in-device connection numbers using the current port time as the cell output time in a certain scheduler, an ATM cell output corresponding to one of the in-device connection numbers is output. Is executed. In such a case, when the port time is updated, in the next search, the connection number in the apparatus that has been searched last time but the ATM cell output is not executed is not searched, and the ATM cell output is not executed. Therefore, the port time continuation process (counter (port clock) stop control) in steps ST210 and ST215, and the port time 1 increment process (counter fast-forward control) in the cell output time of other ports in step ST254 are executed. It was decided.

  FIG. 8 is a timing chart showing such changes in port time when multiple matches occur. FIG. 8 shows changes in the port time of the scheduler 14-1 related to the port P1.

  The port clock 43-1 of the scheduler 14-1 searches for the CAM 41-1 when the cell timing information S601 is “3”. Basically (when it cannot be searched and when only one is searched), the port clock 43-1 The time S401-1 is incremented by one.

  In FIG. 8, since multiple coincidence occurred in the CAM search performed when the master time S405-1 in the scheduler 14-1 is “1” and the cell timing information S601 is “3”, the port ST is described in step ST210 described above. “1” at time S401-1 is continued.

  In the other port cell output time in which the master time S405-1 in the scheduler 14-1 is “2” and the cell timing information S601 is “0”, “1” or “2”, the port time S401- “1” of 1 is continued. Since multiple matches occurred in the CAM search performed when the master time S405-1 in the scheduler 14-1 is “2” and the cell timing information S601 is “3”, the above-described step ST210 causes the port time S401-1 to be changed. “1” is continued.

  In the other port cell output time in which the master time S405-1 in the scheduler 14-1 is “3” and the cell timing information S601 is “0”, “1” or “2”, the port time S401- “1” of 1 is continued. In the CAM search performed when the master time S405-1 in the scheduler 14-1 is “3” and the cell timing information S601 is “3”, one match has occurred, so that the port time S401-1 is determined by the above-described step ST209. Is updated to “2”.

  In the other port cell output time in which the master time S405-1 in the scheduler 14-1 is “4” and the cell timing information S601 is “0”, the port time S401-1 is updated to “3” by the above-described step ST254. The In the other port cell output time in which the master time S405-1 in the scheduler 14-1 is “4” and the cell timing information S601 is “1”, the port time S401-1 is updated to “4” by the above-described step ST254. The In the other port cell output time in which the master time S405-1 in the scheduler 14-1 is “4” and the cell timing information S601 is “2”, “4” of the port time S401-1 is continued by the above-described step ST253. The

By controlling the port time as described above, even when multiple matches occur in the CAM search, it is possible to output ATM cells of all the connection numbers within the apparatus having the port time as the next output time, and all outputs are output. When finished, the port time can be returned to the normal state.
(A-3) Effect of Embodiment According to the above-described embodiment, the cell clock is sequentially transmitted even when multiple matches occur, by stopping the count of the port clock according to the CAM match result or by rotating the count fast. This eliminates the need for an output time storage unit and its control unit for transmitting a cell when multiple matches occur, and can reduce the hardware scale.

  In addition, according to the above-described embodiment, it is not necessary to compare the time at the time of cell input or cell output, and the counter with the triple period required in the prior art described in Patent Document 1 or the periodic output time Processing such as update processing becomes unnecessary, and processing can be simplified.

  According to the above embodiment, the scheduler is provided for each port. However, since the cell storage unit is common to all ports, the scale can be reduced as compared with the prior art described in Patent Document 1.

  According to the above-described embodiment, when the time setting flag of the corresponding connection is “0” at the time of cell input (cell reception), the next cell time is registered as the output time. When the cell interval is secured and the cell interval is longer than the previous output cell time, the cell can be output immediately after cell input.

(B) Other Embodiments In the above embodiment, an ATM cell processing device having a plurality of ATM ports is shown. However, the technical idea of the present invention can be applied to an ATM cell processing device having one ATM port. it can. For example, “0” to “2” of the cell timing information S601 shown in FIG. 4 is not used as the other port period, but is used as a period for fast forwarding, so that the ATM port can be used for one ATM cell processing apparatus. However, the technical idea of the present invention can be applied.

  The cell handled by the cell processing apparatus is not limited to the ATM cell, and the technical idea of the present invention can be applied to a cell processing apparatus handling other fixed-length packets (cells).

  DESCRIPTION OF SYMBOLS 10 ... ATM cell processing apparatus, 11 ... Cell input process part, 12 ... Cell memory | storage part, 13 ... Output period memory | storage part, 14-1-14-M ... Scheduler, 15 ... Port selector, 16 ... Timing counter, 17 ... Master Clock 18 Next output time calculation unit 19 Buffer control unit 20 Buffer management information storage unit 41-1 to 41-M CAM 42-1 to 42-M CAM search control unit 43-1 ˜43-M... Port clock, 44-1 to 44-M... Port clock controller, 45-1 to 45-M... Master clock phase shift unit.

Claims (3)

Based on the connection number included in the header of the input cell, the input cell is stored in a corresponding queue among a plurality of queues prepared for each connection number, and for each of the queues, the next output time for the storage cell In the scheduling device that forms the output instruction of the storage cell that matches the next output time for which the current time is set,
An associative memory means for storing a next output time for each connection number and executing a search each time a search for a next output time matching the input current time is instructed at a predetermined period;
Current time clock means for counting up the current time;
Master clock means for measuring the master time having the same basic update cycle as the current time;
When searching the associative memory means, when there are a plurality of next output times that match the current time, the current time by the current time clock means is counted up, and there are a plurality of next output times that match the current time. The current time clock means stops when the current time count by the current time clock means is stopped, and when there is no next output time that matches the current time, the current time is delayed from the master time by this stop. have a and the current time clock control means be eliminated to speed up the count-up period of,
The port number is included in the header of the input cell,
The associative memory means, the current time clock means, the master clock means, and the current time clock control means are provided for each port number, and the timing for searching for each associative memory means is shifted. . Based on the cell storage means having a plurality of queues for each connection number, and the connection number included in the header of the input cell, the input cells are stored in the corresponding queues among the plurality of queues. In a cell processing device having a scheduling device for setting a next output time for a storage cell and forming an output instruction for the storage cell that matches the next output time for which the current time is set,
2. A cell processing apparatus according to claim 1, wherein the scheduling apparatus is one according to claim 1 . Based on the connection number included in the header of the input cell, the input cell is stored in a corresponding queue among a plurality of queues prepared for each connection number, and for each of the queues, the next output time for the storage cell In the traffic shaping method in the scheduling device for forming the output instruction of the storage cell that matches the next output time set to the current time,
The associative memory means stores the next output time for each connection number, and executes a search every time a search for the next output time that matches the input current time is instructed in a predetermined cycle,
The current time clock means counts up the current time,
The master clock means keeps the master time having the same basic update cycle as the current time,
The current time clock control means counts up the current time by the current time clock means to match the current time except when there are a plurality of next output times that match the current time when searching the associative memory means. When there are multiple output times, stop counting the current time by the current time clock means, and when there is no next output time that matches the current time, the current time is delayed from the master time. To cancel the count-up cycle of the current time clock means ,
The port number is included in the header of the input cell,
The traffic shaping, wherein the associative memory means, the current time clock means, the master clock means, and the current time clock control means are provided for each port number, and the search timing of each associative memory means is shifted. Method.

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