JP6231608B2 - Mounting method of optoelectronic integrated circuit - Google Patents

Description

  The present invention relates to an optical trigger type optoelectronic integrated circuit that operates in response to an optical trigger pulse, and more particularly to a method for mounting an optoelectronic integrated circuit having a distributed constant circuit configuration on a substrate.

  In recent years, with the rise of packet-based networks centered on the Internet, there has been a demand for an increase in optical communication capacity and improvement in flexibility and expandability. In addition to a global IP network, a network within a data center is also required to realize a packet switch network with low power consumption and a large capacity. Therefore, it is necessary to realize a network (optical packet switch network) using optical packets that is excellent in terms of bandwidth utilization efficiency, flexibility, and expandability.

  In order to realize such an optical packet switch network, generation of an asynchronous arbitrary length burst optical packet signal is indispensable. For this purpose, a low-speed (<1 Gbps) parallel signal output from a random access memory (RAM) in an optical packet router that is a node of the optical packet switch network is converted into a high-speed (> 10 Gbps) serial signal used in an optical fiber. The operation of converting must be performed on the burst signal. In a general parallel-serial conversion circuit, it is difficult to cope with such a burst signal for clock recovery used internally, and in many cases, the parallel-serial conversion circuit itself is large-scale. There is a problem that large power consumption is required.

  In order to solve these problems, an optical trigger sampling circuit using a charge / discharge MSM-PD (Metal-Semiconductor-Metal Photo Detector) (see, for example, Non-Patent Document 1) has been proposed (for example, Patent Document 1). 1, refer to Non-Patent Document 2). Furthermore, based on OCTA (Optically Clocked Transistor Array) technology that applies this optical trigger type sampling, which has developed this optical trigger type sampling circuit and realized the tolerance of optical power fluctuation using differential trigger. A parallel-serial conversion circuit (see, for example, Patent Document 2 and Non-Patent Document 3) has also been proposed. A circuit diagram of this differential trigger type parallel-serial conversion circuit is shown in FIG.

  In the differential trigger parallel / serial conversion circuit shown in FIG. 4, MSM-PDs 401-1, 402-1 are used as photoelectric converters, and HEMTs (High Electron Mobility Transistors) 401-3, 401-4, 402 are used as transistors. -3, 402-4 is used.

  As a basic principle, in the first channel block 401, the parallel signal input from the first channel signal input terminal 401-5 is obtained by using the steep rise of the pulse generated by the MSM-PD 401-1. Cut out into a rectangle, generate a 1-bit serial signal, and output the serial signal to the signal output line 411, thereby realizing parallel-serial conversion for the first channel.

  Such an operation is shifted by one unit interval (however, the unit interval of serial signal output. Hereinafter, the expression “unit interval” is all based on the data rate of serial signal output). Continuous parallel-serial conversion is performed in a loop operation in which the same operation is performed up to the third channel block 403, the same operation is performed up to the N-th channel block 40N, and the operation is finally continued to the first channel block 401 again. Operation is realized.

Hereinafter, a more specific process of parallel-serial conversion will be described focusing on the first channel block 401. First, in the differential trigger type parallel-serial conversion circuit, the potentials V _NH and V _MSM are positively biased and the potential V _NL is negatively biased. Therefore, a positive potential is applied to one electrode A of the MSM-PD 401-1 through the resistor 401-8, and the resistor 401-9 is applied to the other electrode B of the MSM-PD 401-1 and the gate of the HEMT 401-3. 401-10 and a negative potential is applied to the gate of the HEMT 401-4 by a resistor 402-7. Therefore, the HEMT 401-3 is turned off in the absence of an optical trigger pulse, and the HEMT 401-4 Is on.

  Here, when the optical trigger pulse 401-6 is irradiated to the MSM-PD 401-1, a negative pulse is generated in one electrode A of the MSM-PD 401-1 and a positive pulse is applied to the other electrode B. Occur. Although the HEMT 401-3 is in an off state, the HEMT 401-3 is turned on by a positive pulse generated at the electrode B of the MSM-PD 401-1. The HEMT 401-4 remains on. Accordingly, since both the HEMT 401-3 and the HEMT 401-4 are turned on, the signal of the first channel signal input terminal 401-5 starts to flow through the signal output line 411.

  After one unit interval of the optical trigger pulse 401-6, the optical trigger pulse 402-6 is irradiated to the MSM-PD 402-1 of the second channel block 402. As a result, like MSM-PD 401-1, a negative pulse is generated at one electrode A of MSM-PD 402-1 and a positive pulse is generated at the other electrode B. The negative pulse generated from the electrode A of the MSM-PD 402-1 is level-converted through the capacitor 402-2 and turns off the HEMT 401-4. As a result of the irradiation of the optical trigger pulse 402-6 shifted by one unit interval in this way, the first channel signal input is performed only for one unit interval from the irradiation of the optical trigger pulse 401-6 to the irradiation of the optical trigger pulse 402-6. The signal of the terminal 401-5 can be cut out and output to the signal output line 411.

  This light trigger pulse irradiation occurs in the same manner in the next third channel block 403 with a time offset of one unit interval, and the signal at the second channel signal input terminal 402-5 is sent to the signal output line 411 only for one unit interval. Is output. Such an operation is repeated, and the signal of each channel signal input terminal is cut out at every unit interval to realize parallel-serial conversion.

  FIG. 5 shows a configuration in which the differential trigger type parallel-serial conversion circuit shown in FIG. 4 is a differential input type. The first channel block 501 includes an MSM-PD 501-1, a capacitor 501-2, HEMTs 501-3, 501-4, and 501-11, resistors 501-7 to 501-10, and 501-12 to 501-14. It has. The second channel block 502 includes an MSM-PD 502-1, a capacitor 502-2, HEMTs 502-3, 502-4, 502-11, resistors 502-7 to 502-10, 502-12 to 502-14. It has. The same applies to other channel blocks.

  In the configuration shown in FIG. 5, the circuit composed of the HEMT 501-11 and the resistors 501-12 to 501-14 converts the signal input to the first channel differential signal input terminal 501-5 into a single-phase signal to convert the HEMT 501. -4. Similarly, a circuit including the HEMT 502-11 and the resistors 502-12 to 502-14 converts a signal input to the second channel differential signal input terminal 502-5 into a single-phase signal and inputs the signal to the HEMT 502-4. . The operation of the other configuration is the same as that of the differential trigger type parallel-serial conversion circuit shown in FIG.

  In the differential trigger parallel / serial conversion circuit shown in FIG. 4 and FIG. 5, irradiation of the optical trigger pulse shifted by one unit interval as described above is performed in the first channel block, the second channel block, the third channel block,. .. The operation of a loop in which the Nth channel block is performed in order, the optical trigger pulse is given to the Nth channel block, and then the optical trigger pulse is given again to the first channel block after one unit interval. Done.

  An OEIC (Opto-Electronic Integrated Circuit) in which a differential trigger type parallel-serial conversion circuit as shown in FIGS. 4 and 5 is integrated on one chip includes a plurality of MSM-PDs and a plurality of optical axes. An optical connection with the optical system is essential. For example, in the example of FIG. 6, the optical trigger pulse 301 propagating through the multi-core ribbon fiber 302 is irradiated from the optical head 303 toward the OEIC 306. The electrical connection between the OEIC 306 and the outside is realized by a wire 304 that connects a wiring 308 on the ceramic substrate 305 and an electrode pad (not shown) on the OEIC 306.

  The OEIC 306 inevitably is designed as a distributed constant circuit because it requires a chip size for receiving a plurality of optical trigger pulses at the same time it handles a signal of 10 Gbps or higher. Therefore, in most cases, the OEIC 306 needs to have a transmission line on the chip, and it is difficult to integrate and miniaturize it.

  In particular, in the OEIC 306 in which the differential trigger parallel / serial conversion circuits as shown in FIGS. 4 and 5 are integrated on one chip, between the first channel block and the second channel block, and between the second channel block and the third channel block. There is high-speed electrical signal delivery, and similarly, there is also high-speed electrical signal delivery between the first channel block and the N-th channel block, so the channel blocks with signal delivery must be close enough to be handled in a lumped manner. In order to realize such a close arrangement, it is necessary to arrange each channel block in a loop shape so that the first channel block and the Nth channel block can be brought close to each other.

  Therefore, on the optical head 303 side, it is necessary to arrange the emission end of the optical trigger pulse to each channel block on the OEIC 306 in a loop shape. For example, in the case of 16 channels (N = 16), a small and inexpensive 1 × 16 optical heads could not be used, and a 2 × 8 relatively large and expensive optical head was required.

JP 2004-88660 A JP 2012-004617 A

Kiyoto Takahata and 4 others, “3 ps electrical pulse generation from a discharge-” based metal-semiconductor-metal according to "Electronics Letters", I Triple E (IEEE), January 2005, Vol. 41, No. 1, pp. 38-40 R. Urata and four others, "An Optically Clocked Transistor Array for High Speed Asynchronous Label Swapping Forty Gigabit Perconcons and Beyond (An Optically Clocked Transistor Array for High-Speed Asynchronous Label Swapping: 40 Gb / s and Beyond ”, Journal of Lightwave Technology (JOURNAL OF LIGHTWAVE TECHNOLOGY), i-Triple (IEEE), March 2008, Volume 26 , No. 6, pp. 692-703 Yuji Ishikawa and five others, “A novel optically clocked transistor array using differential operation, for A differential optical clocked transistor array using differential operation for parallel to serial conversion parallel-to-serial conversion) ”, ECOC 2010

  As shown in FIG. 6, in the method of mounting an OEIC formed with an optical trigger transistor circuit (channel block) on a ceramic substrate, mechanical connection for mounting the OEIC on the substrate and an optical head on the OEIC are arranged. Therefore, there is a problem in that mounting man-hours, component costs, and size increase because it is necessary to separately perform optical connection and electrical connection for connecting the wiring of the OEIC and the ceramic substrate through wires.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide an OEIC mounting method capable of realizing a reduction in the number of components, a reduction in mounting man-hours, and a reduction in size.

The method for mounting an optoelectronic integrated circuit according to the present invention includes a step of flip-chip mounting an optoelectronic integrated circuit in which a plurality of phototrigger type transistor circuits operating in response to an optical trigger pulse are arranged on a planar lightwave circuit, The lightwave circuit includes a plurality of optical waveguides coupled to an output end of a multi-core ribbon fiber through which the optical trigger pulse propagates, and an optical trigger transistor that propagates the optical trigger pulse through the optical waveguide, corresponding to the optoelectronic integrated circuit. comprising a light emitting portion for emitting in the direction of the light receiving elements of the circuit, and electrically connected to the wiring through the respective optical trigger type transistor circuit and the bump of the optoelectronic integrated circuit, the wiring of the planar lightwave circuit comprises comprises a transmission line for propagating the output signal of the plurality of light trigger type transistor circuits of the optoelectronic integrated circuit, the plurality of light triggered the optoelectronic integrated circuit Transistor circuit is disposed in plan view two-dimensionally, and is characterized in configuring the distributed constant circuit is connected in parallel with the transmission line through the formed the bumps on the transmission line .

Further, in one configuration example of the optoelectronic integrated circuit mounting method of the present invention, the plurality of phototrigger transistor circuits of the optoelectronic integrated circuit are irradiated to each light receiving element with a predetermined unit interval shifted in time. A parallel-serial conversion circuit that operates in response to an optical trigger pulse, converts a parallel signal input from the planar lightwave circuit into a serial signal, and outputs the serial signal to the planar lightwave circuit is configured.
In one configuration example of the optoelectronic integrated circuit mounting method of the present invention, each light receiving element of the plurality of phototrigger type transistor circuits of the optoelectronic integrated circuit is an MSM-PD.
In one configuration example of the mounting method of the optoelectronic integrated circuit according to the present invention, the light emitting portion of the planar lightwave circuit is formed of a plurality of phototrigger type transistor circuits arranged in a two-dimensional plan view on the optoelectronic integrated circuit. Correspondingly, it consists of a plurality of total reflection mirrors or a plurality of Bragg couplers arranged two-dimensionally in plan view on the planar lightwave circuit.

  According to the present invention, mechanical connection, optical connection, and electrical connection between a planar lightwave circuit and an optoelectronic integrated circuit can be realized simultaneously by flip-chip mounting the optoelectronic integrated circuit on the planar lightwave circuit. As a result, according to the present invention, it is possible to realize a reduction in the number of components, a reduction in mounting man-hours, and a reduction in the size of the module on which the optoelectronic integrated circuit is mounted.

  In the present invention, the size of the optoelectronic integrated circuit chip can be reduced by eliminating the transmission line from the optoelectronic integrated circuit which is a distributed constant circuit and forming the transmission line in the planar lightwave circuit.

  Further, in the present invention, by using the MSM-PD as the light receiving element of each of the plurality of photo-trigger type transistor circuits of the optoelectronic integrated circuit, the light receiving element having a smaller parasitic capacitance per unit area than a normal pin-PD or the like. Therefore, it is possible to increase the size of the light receiving element, and to increase the manufacturing tolerance at the time of flip chip mounting.

It is sectional drawing explaining the mounting method of the optoelectronic integrated circuit which concerns on embodiment of this invention. It is a disassembled perspective view explaining the mounting method of the optoelectronic integrated circuit which concerns on embodiment of this invention. It is sectional drawing which shows one example of a structure of the light emission part of the quartz type plane light wave circuit which concerns on embodiment of this invention. It is a circuit diagram which shows the structure of the conventional differential trigger system parallel serial conversion circuit. It is a circuit diagram which shows the structure of the conventional differential input type | mold differential trigger system parallel serial conversion circuit. It is a figure explaining the optical connection of the conventional optoelectronic integrated circuit and an optical system.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view illustrating an OEIC mounting method according to an embodiment of the present invention, and FIG. 2 is an exploded perspective view illustrating an OEIC mounting method. The mounting method of the present embodiment is characterized in that the OEIC 108 is flip-chip mounted on the quartz-based planar lightwave circuit 103 via bumps 107.

  In this embodiment, an element having a 16-channel photo-trigger transistor circuit is used as the OEIC 108 that is a photo-trigger distributed constant circuit based on the OCTA technology. Examples of the optical trigger transistor circuit include the channel blocks 401 to 40N and 501 to 50N described in FIGS. 4 and 5 (N = 16 in this embodiment). The channel blocks 401 to 40N (or 501 to 50N) that operate according to the optical trigger pulse 101 are arranged on the OEIC 108 in a two-dimensional shape in plan view. These channel blocks constitute a differential trigger parallel / serial conversion circuit as a whole.

  Inside the quartz-based planar lightwave circuit 103, there are a plurality (16) of optical waveguides 104 coupled to the output end of the multi-core ribbon fiber 102 (16 cores in the present embodiment), and these optical waveguides 104. A light emitting section 105 is formed for emitting the propagating light trigger pulse 101 in the direction of the light receiving element of the corresponding channel block of the OEIC 108.

  FIG. 3 is a cross-sectional view illustrating an example of the configuration of the light emitting unit 105. The light emitting unit 105 corresponds to a plurality of channel blocks arranged in a two-dimensional plan view on the OEIC 108, and a plurality of (16 pieces) arranged in a two-dimensional plan view on the quartz-based planar lightwave circuit 103. It consists of a total reflection mirror 1050. Each total reflection mirror 1050 has a reflection surface that is inclined at a certain angle with respect to the light emitting direction from the optical waveguide 104 (the left-right direction in FIG. 3). A reflective film made of Au or the like is formed on the reflective surface. However, the formation of the reflective film is not an essential constituent requirement.

  As described with reference to FIGS. 4 and 5, it is necessary to irradiate each channel block 401 to 40N (or 501 to 50N) mounted on the OEIC 108 with the optical trigger pulse 101 shifted by one unit interval in time, Each channel block needs to be irradiated with the optical trigger pulse 101 at a period of 16 unit intervals. Therefore, the optical trigger pulse 101 is irradiated to the MSM-PD of the first channel block one unit interval after the optical trigger pulse 101 is irradiated to the MSM-PD of the sixteenth channel block.

  In this way, in order to irradiate the optical trigger pulse 101 while shifting the time sequentially from the first channel block to the 16th channel block, 16 optical delay lines having optical delay amounts that sequentially increase by one unit interval ( (Not shown) may be provided. If these optical delay lines are connected one by one to the input ends of the corresponding optical fiber core lines of the multi-core ribbon fiber 102, the optical trigger pulse applied to the second channel block is applied to the optical trigger applied to the first channel block. There is a delay of 1 unit interval with respect to the pulse, and the optical trigger pulse irradiated to the third channel block has a delay of 2 unit interval with respect to the optical trigger pulse irradiated to the first channel block. The optical trigger pulse irradiated to each channel block has a delay of 15 unit intervals with respect to the optical trigger pulse irradiated to the first channel block. it can.

  On the other hand, a polymer layer 112 is formed on the surface of the quartz-based planar lightwave circuit 103 by spin coating or the like, and a metal wiring 106 is formed on the polymer layer 112. A part of the metal wiring constitutes the transmission line 111 described above.

  When the OEIC 108 is mounted on the quartz-based planar lightwave circuit 103, the surface of the quartz-based planar lightwave circuit 103 (the surface on which the metal wiring 106 and the transmission line 111 are formed and the emission surface of the optical trigger pulse 101) The OEIC 108 may be flip-chip mounted on the quartz-based planar lightwave circuit 103 with bumps 107 made of Au, for example, so that the light receiving surface of the OEIC 108 faces each other.

  Each of the optical trigger pulses 101 incident on the 16 optical waveguides 104 through the multi-core ribbon fiber 102 propagates through the optical waveguides 104 and reaches the total reflection mirror 1050 formed at the output end of the optical waveguides 104. The light trigger pulse 101 that has reached the total reflection mirror 1050 has its traveling direction changed by 90 degrees, and is emitted to the light receiving portion of the corresponding channel block of the OEIC 108 as emitted light 109. The optical trigger pulse is shifted by one unit interval for MSM-PD 401-1, 402-1 (or 501-1, 502-1) which is the light receiving element of each channel block 401-40N (or 501-50N). The irradiation with 101 is as described above.

  In the present embodiment, the transmission line 111 formed on the quartz-based planar lightwave circuit 103 constitutes the signal output line 411 (or 511) of FIGS. By flip-chip mounting the OEIC 108 on the quartz-based planar lightwave circuit 103, the outputs of the channel blocks 401 to 40N (or 501 to 50N), that is, the HEMT 401-3, 402-3 (or HEMT 501-3, 502-3). These drains are connected to the transmission line 111 via bumps 107.

The signal input terminals 401-5 and 402-5 (or 501-5 and 502-5) of each channel block 401 to 40 N (or 501 to 50 N) are on the quartz-based planar lightwave circuit 103 via the bumps 107. Connected to the metal wiring 106. Similarly, the potentials V _NH , V _MSM , V _NL and the ground potential are also supplied from the metal wiring 106 on the quartz-based planar lightwave circuit 103 via the bumps 107.

  As described above, in the present embodiment, the mechanical connection, the optical connection, and the electrical connection between the quartz-based planar lightwave circuit and the OEIC are simultaneously realized by flip-chip mounting the OEIC on the quartz-based planar lightwave circuit. can do. As a result, in the present embodiment, the mechanical connection for mounting the OEIC on the substrate, the optical connection for disposing the optical head on the OEIC, and the wiring of the OEIC and the substrate are connected via wires as in the prior art. Since it is not necessary to perform electrical connection separately, it is possible to realize a reduction in the number of components, a reduction in mounting man-hours, and a reduction in the size of the module on which the OEIC is mounted.

In this embodiment, the example in which the optical trigger type transistor circuit formed in the OEIC 108 has 16 channels (16) is described. However, the same effects as those in this embodiment can be obtained even in configurations with other numbers of channels. Needless to say.
In this embodiment, an example in which a plurality of total reflection mirrors are used as the light emitting unit 105 has been described. However, the same effect as in this embodiment can be obtained even when a Bragg coupler is used instead of the total reflection mirror. Can do.

  The present invention can be applied to an optoelectronic integrated circuit which is an optical trigger type distributed constant circuit.

  DESCRIPTION OF SYMBOLS 101 ... Optical trigger pulse, 102 ... Multi-core ribbon fiber, 103 ... Quartz system plane light wave circuit, 104 ... Optical waveguide, 105 ... Light-emitting part, 106 ... Metal wiring, 107 ... Bump, 108 ... Optoelectronic integrated circuit, 109 ... Output Illumination, 111 ... transmission line, 112 ... polymer layer, 401 to 40N, 501 to 50N ... channel block, 401-1, 402-1, 501-1, 502-1 ... MSM-PD, 1050 ... total reflection mirror.

Claims (4)

Including flip-chip mounting an optoelectronic integrated circuit in which a plurality of phototrigger type transistor circuits operating in response to a phototrigger pulse are disposed on a planar lightwave circuit,
The planar lightwave circuit is:
A plurality of optical waveguides coupled to an output end of a multi-core ribbon fiber through which the optical trigger pulse propagates;
A light emitting section for emitting a light trigger pulse propagating through each optical waveguide in a direction of a light receiving element of a corresponding light trigger type transistor circuit of the optoelectronic integrated circuit;
Each optical trigger type transistor circuit of the optoelectronic integrated circuit and wiring electrically connected through bumps ,
The wiring of the planar lightwave circuit includes a transmission line for propagating output signals of a plurality of light trigger transistor circuits of the optoelectronic integrated circuit,
The plurality of photo-trigger transistor circuits of the optoelectronic integrated circuit are arranged in a two-dimensional plan view and are connected in parallel to the transmission line via the bumps formed on the transmission line. A method of mounting an optoelectronic integrated circuit, comprising: In the mounting method of the optoelectronic integrated circuit of Claim 1 ,
The plurality of photo-trigger type transistor circuits of the optoelectronic integrated circuit operate in response to the photo-trigger pulse irradiated to each light receiving element by a predetermined unit interval and input from the planar lightwave circuit. An optoelectronic integrated circuit mounting method comprising: a parallel-serial conversion circuit configured to convert a parallel signal into a serial signal and output the parallel signal to the planar lightwave circuit. In the mounting method of the optoelectronic integrated circuit of Claim 1 or 2 ,
The method of mounting an optoelectronic integrated circuit, wherein each light receiving element of the plurality of phototrigger type transistor circuits of the optoelectronic integrated circuit is an MSM-PD. In the mounting method of the optoelectronic integrated circuit according to any one of claims 1 to 3 ,
The light emitting part of the planar lightwave circuit is arranged in a two-dimensional plan view on the planar lightwave circuit corresponding to a plurality of light trigger transistor circuits arranged in a two-dimensional plan view on the optoelectronic integrated circuit. A method for mounting an optoelectronic integrated circuit, comprising: a plurality of total reflection mirrors or a plurality of Bragg couplers.