JP6225863B2 - Clock adjustment mechanism - Google Patents

Description

  The present invention relates to a clock adjustment mechanism for performing clock correction of a processing unit.

  An image forming apparatus such as a multifunction peripheral is provided with a plurality of CPUs (processing units) including a main CPU and a sub CPU. For example, the main CPU executes processing for controlling the entire apparatus. The sub CPU receives an instruction from the main CPU and executes specific processing such as communication control and power control (see, for example, Patent Document 1).

  Each CPU includes a clock generation unit that generates an operation clock, and executes processing based on the operation clock generated by the clock generation unit. For example, each CPU measures time using the operation clock generated by the clock generation unit, and measures the timing of processing to be executed.

JP 2012-244606 A

  In an image forming apparatus provided with a CPU that measures time by measuring time, if the CPU is not timed accurately (that is, if the frequency accuracy of the clock generated by the clock generator is low), the CPU The timing of the processing to be executed is deviated from the desired timing (the processing is performed at a point outside the time zone for processing). Therefore, the timing by the CPU needs to be accurately performed.

  Here, for example, a CPU with a built-in or external clock generation unit using a crystal as a vibrator can accurately measure time. For this reason, in order to reduce a shift in timing of processing executed by the CPU, a high-accuracy clock generation unit that can accurately measure time may be built in or externally attached to the CPU.

  However, a high-accuracy clock generator that can accurately measure time is generally expensive. For this reason, in an image forming apparatus provided with a plurality of CPUs, there is a problem in cost if all the clock generation units of the plurality of CPUs are accurate and highly accurate. For this reason, the clock generation unit of the sub CPU uses an inexpensive oscillation circuit (for example, a CR oscillation circuit) in order to avoid an increase in cost. As a result, there arises a disadvantage that the timing accuracy of the sub CPU is lowered. That is, the timing of processing executed by the sub CPU is shifted.

  The present invention has been made to solve the above-described problem, and an object of the present invention is to provide a clock adjustment mechanism capable of improving the timing accuracy of a processing unit that measures time by measuring time. .

  In order to achieve the above object, the clock adjustment mechanism of the present invention includes a first processing unit and a second processing unit. The first processing unit generates a first clock, and a first clock that generates and outputs a reference signal having a period corresponding to a predetermined first count using the first clock. An output unit, a first clock measurement unit that measures a cycle of a signal input to the first processing unit using the first clock, and a correction unit that corrects the cycle of the first clock are included. The second processing unit includes a second clock generation unit that generates a second clock, a second clock measurement unit that measures the period of a reference signal output from the first processing unit using the second clock, and a reference signal A comparison unit that compares the actual count number of the second clock measurement unit when the period of the second clock is measured with a second count number predetermined as the count number of the second clock corresponding to the period of the reference signal; When the actual count number of the clock measurement unit is greater than the second count number, a correction signal having a shorter cycle than the reference signal is output to the first processing unit, and when the actual count number of the second clock measurement unit is smaller than the second count number And a second clock output unit that outputs a correction signal having a longer cycle than the reference signal to the first processing unit. When the correction signal is output from the second processing unit to the first processing unit, the first clock measurement unit measures the period of the correction signal using the first clock, and the correction unit performs the period of the correction signal. The first clock cycle is corrected so that the count number of the first clock counted during the period becomes the first count number, and the first clock output unit uses the corrected first clock to A reference signal having a period corresponding to the count number is generated and output. Then, when the actual count number of the second clock measurement unit matches the second count number, the second processing unit instructs the first processing unit to end the correction of the cycle of the first clock.

  In the configuration of the present invention, a reference signal having a period corresponding to the first count number is transmitted from the first processing unit to the second processing unit, and the measurement of the period of the reference signal is performed by the second processing unit. Here, if the frequency accuracy of the first clock is low, a deviation occurs between the actual count number and the second count number of the second clock measurement unit. Specifically, if the period of the first clock is longer than the ideal value, the period of the reference signal is longer, so the actual count number of the second clock measurement unit is larger than the second count number. On the other hand, if the cycle of the first clock is shorter than the ideal value, the cycle of the reference signal is shortened, so that the actual count number of the second clock measurement unit is smaller than the second count number. Therefore, the second clock output unit outputs a correction signal having a shorter cycle than the reference signal to the first processing unit when the actual count number of the second clock measurement unit is larger than the second count number, and the second clock measurement unit When the actual count number is less than the second count number, a correction signal having a longer period than the reference signal is output to the first processing unit. When such a correction signal is output to the first processing unit, the first clock measurement unit measures the period of the correction signal using the first clock. The correction unit corrects the cycle of the first clock so that the count number of the first clock counted during the cycle of the correction signal becomes the first count number. The first clock output unit generates and outputs a reference signal having a period corresponding to the first count number, using the corrected first clock. Then, when the actual count number of the second clock measurement unit matches the second count number, the second processing unit instructs the first processing unit to end the correction of the cycle of the first clock. That is, the correction unit finishes correcting the cycle of the first clock. As a result, the frequency accuracy of the first clock is increased, and the timing accuracy of the first processing unit is improved.

  As described above, with the configuration of the present invention, it is possible to improve the timing accuracy of the processing unit.

Schematic showing an example of a multifunction machine according to an embodiment of the present invention. 1 is a block diagram showing an example of a hardware configuration of a multifunction machine according to an embodiment of the present invention. The figure for demonstrating the electric power supply system of the multifunctional device by one Embodiment of this invention The figure for demonstrating the clock correction of the power supply CPU of the multifunctional device by one Embodiment of this invention. The figure for demonstrating the flow (The flow of the process which jig | tool CPU performs) of the power supply CPU of the multifunctional device by one Embodiment of this invention The figure for demonstrating the flow (clocking of the process which power supply CPU performs) of the power supply CPU of the multifunctional device by one Embodiment of this invention

  Hereinafter, an embodiment of the present invention will be described by taking a multifunction peripheral as an example.

<Overall configuration of MFP>
As shown in FIG. 1, the multifunction peripheral 100 (corresponding to the “image forming apparatus” of the present invention) includes an image reading unit 1 and a printing unit 2. The image reading unit 1 reads a document and generates image data. The printing unit 2 transports the paper P along the paper transport path 21 and forms a toner image based on the image data. Then, the printing unit 2 prints the toner image on the paper P being conveyed, and discharges the printed paper P to the discharge tray 22.

  The printing unit 2 includes a paper feeding unit 3, a paper transport unit 4, an image forming unit 5, and a fixing unit 6. The paper feed unit 3 includes a pickup roller 31 and a paper feed roller pair 32, and supplies the paper P stored in the paper cassette 33 to the paper transport path 21. The paper transport unit 4 includes a plurality of transport roller pairs 41 and transports the paper P along the paper transport path 21.

  The image forming unit 5 includes a photosensitive drum 51, a charging device 52, an exposure device 53, a developing device 54, a transfer roller 55, and a cleaning device 56. Then, the image forming unit 5 forms a toner image based on the image data, and transfers the toner image onto the paper P. The fixing unit 6 includes a heating roller 61 and a pressure roller 62, and fixes the toner image transferred onto the paper P by heating and pressing.

  The multifunction device 100 also includes an operation panel 7. The operation panel 7 includes a liquid crystal display panel 71 with a touch panel. The liquid crystal display panel 71 displays soft keys and messages for accepting various settings. Further, the operation panel 7 is also provided with hard keys 72 such as a numeric keypad and a start key.

<Hardware configuration of MFP>
As shown in FIG. 2, the multifunction machine 100 includes a main control unit 110. The main control unit 110 includes a main CPU 111, an image processing unit 112, and a storage unit 113. The image processing unit 112 includes an ASIC dedicated to image processing, and performs image processing (enlargement / reduction, density conversion, data format conversion, etc.) on the image data. The storage unit 113 includes a ROM and a RAM, and stores a control program and data.

  The main CPU 111 performs overall control of the multifunction peripheral 100 based on the control program and data stored in the storage unit 113. Specifically, the main CPU 111 controls the reading operation of the image reading unit 1 and the printing operation of the printing unit 2. Further, the main CPU 111 controls the display operation of the operation panel 7 or detects an operation performed on the operation panel 7.

  The multifunction device 100 includes a power supply unit 120 and a power supply control unit 130. The power supply unit 120 is connected to a commercial power supply and generates a voltage necessary for operating the plurality of power supplied units 10 (parts that operate by receiving power supply). The power supply control unit 130 includes a power supply CPU 131 and a power supply storage unit 132, and controls power supply to the plurality of power supplied units 10. The power supply CPU 131 corresponds to the “first processing unit” of the present invention.

  Here, the parts corresponding to the power supply unit 10 in the multifunction peripheral 100 are the image reading unit 1, the printing unit 2 (the paper feeding unit 3, the paper transporting unit 4, the image forming unit 5 and the fixing unit 6), and the operation panel 7. And a main control unit 110. Specifically, a motor for driving a rotating body constituting each part of the image reading unit 1 and the printing unit 2 corresponds to the power supply unit 10. In the operation panel 7, the liquid crystal display panel 71 (touch panel) corresponds to the power receiving unit 10. Further, in the main control unit 110, the main CPU 111, the image processing unit 112, and the storage unit 113 correspond to the power supplied unit 10.

<Power supply to the power receiver>
As shown in FIG. 3, a plurality of switch units SW respectively corresponding to the plurality of power receiving units 10 are connected to the power supply control unit 130. When the switch unit SW is on, power is supplied to the corresponding power-supplied supply unit 10, and when the switch unit SW is off, power supply to the corresponding power-supplied supply unit 10 is stopped. . The power supply CPU 131 controls the supply and stop of power supply to the power-supplied supply unit 10 by switching the switch unit SW on and off.

  Specifically, the power supply CPU 131 starts power supply to the plurality of power supplied units 10 in a predetermined order when the multifunction device 100 is turned on. That is, the power supply CPU 131 switches the plurality of switch units SW from off to on in a predetermined order. For example, the power supply CPU 131 first starts supplying power to the main CPU 111 and then sequentially starts supplying power to the other power-supplied supply units 10.

  The power supply CPU 131 also starts supplying power to the elements constituting the main CPU 111 in a predetermined order when supplying power to the main CPU 111. For example, the power supply CPU 131 first starts power supply to the CPU core that performs management and calculation of the entire CPU, and then sequentially starts power supply to components other than the CPU core.

<CPU clock correction>
As shown in FIG. 4, the power supply CPU 131 includes a core unit 133, a bus interface unit 134, a cache memory 135, and a first clock generation unit 136. The core unit 133 performs overall management of the CPU and various processes. The bus interface unit 134 transmits and receives signals to and from other CPUs, reads data to be processed, and outputs processed data. The cache memory 135 stores data. The first clock generation unit 136 generates an operation clock (corresponding to the “first clock” of the present invention) of the power supply CPU 131. The first clock generation unit 136 is composed of an inexpensive oscillation circuit (for example, a CR oscillation circuit) with low frequency accuracy in order to avoid an increase in cost. Hereinafter, the operation clock of the power supply CPU 131 generated by the first clock generation unit 136 is referred to as a first clock.

  When the power supply CPU 131 sequentially starts power supply to the plurality of power supplied units 10, the power supply CPU 131 measures time using the first clock, and sets the power supply start timing (timing for switching on / off the switch unit SW). measure. However, if the frequency accuracy of the first clock is low, there is a possibility that the on / off switching timing of the switch unit SW deviates from the ideal timing.

  Therefore, the power supply CPU 131 transmits / receives a signal to / from the correction jig 200 separate from the multifunction peripheral 100, and corrects the cycle of the first clock based on the correction signal transmitted from the correction jig 200. Perform (clock correction). For example, the correction jig 200 can be attached to and detached from a control board on which the power supply CPU 131 is mounted. Then, by attaching the control board to the correction jig 200, the terminal of the control board (terminal connected to the bus interface unit 134 of the power supply CPU 131) can be connected to the correction jig 200 so as to be communicable. When the clock correction is performed using such a correction jig 200, the control board on which the power supply CPU 131 is mounted needs to be mounted on the correction jig 200, so that the clock correction is performed at the time of adjustment before shipping the apparatus.

  The power supply CPU 131 is provided with a first clock output unit 137, a first clock measurement unit 138, and a correction unit 139 in order to perform clock correction. The first clock output unit 137 generates a clock signal using the first clock and outputs it to the outside of the power supply CPU 131. The first clock measurement unit 138 measures the period of the clock signal input to the power supply CPU 131 using the first clock. The correction unit 139 corrects the cycle of the first clock.

  The correction jig 200 includes, for example, a jig CPU 210, a jig storage unit 220, and a jig operation unit 230. The jig CPU 210 performs processing necessary for clock correction. The jig storage unit 220 stores programs and data for operating the jig CPU 210. The jig operation unit 230 receives various operations for performing clock correction.

  The jig CPU 210 includes a core unit 211 that performs overall CPU management and various processes, a bus interface unit 212 that transmits and receives signals to and from other CPUs, a cache memory 213 that stores data, and an operation clock of the jig CPU 210. (Corresponding to the “second clock” of the present invention) is included. Hereinafter, the operation clock of the jig CPU 210 generated by the second clock generation unit 214 is referred to as a second clock.

  The second clock generation unit 214 is configured using, for example, a crystal oscillation circuit using a crystal resonator as an oscillation source. For this reason, the second clock generated by the second clock generation unit 214 has higher frequency accuracy than the first clock generated by the first clock generation unit 136. The second clock has a higher frequency than the first clock, and the correction CPU 210 operates at a higher speed than the power supply CPU 131.

  The jig CPU 210 is provided with a second clock output unit 215, a second clock measurement unit 216, and a comparison unit 217 in order to perform clock correction. The second clock output unit 215 generates a clock signal using the second clock and outputs it to the outside of the jig CPU 210. The second clock measurement unit 216 measures the period of the clock signal input to the jig CPU 210 using the second clock. The comparison unit 217 compares the magnitude relationships of the periods of the two clock signals.

  In the clock correction, first, a clock correction start instruction is issued from the jig CPU 210 to the power supply CPU 131. For example, the jig CPU 210 instructs the power supply CPU 131 to start clock correction when an operation for starting clock correction is performed on the jig operation unit 230. When the power supply CPU 131 receives a clock correction start instruction, the first clock output unit 137 generates a reference signal having a period corresponding to a predetermined first count using the first clock, and sends the reference signal to the jig CPU 210. Output. The data indicating the first count number is stored in advance in the power storage unit 132, for example, and is read from the power storage unit 132 to the cache memory 135 at the time of clock correction.

  When the reference signal is input to the jig CPU 210, the second clock measuring unit 216 measures the period of the reference signal using the second clock. Then, the comparison unit 217 measures the actual count number of the second clock measurement unit 216 when measuring the cycle of the reference signal, and a second count number that is predetermined as the count number of the second clock corresponding to the cycle of the reference signal. And compare. The data indicating the second count number is stored in advance in the jig storage unit 220, for example, and is read from the jig storage unit 220 to the cache memory 213 at the time of clock correction.

  Here, when the period of the first clock is deviated from the theoretical value, the actual count number of the second clock measurement unit 216 does not match the second count number. Specifically, if the period of the first clock is longer than the ideal value, the time required to count the first clock until reaching the first count number becomes longer, and the period of the first clock is ideal. If the value is shorter than the value, the time required for counting the first clock until the first count is reached is shortened. Therefore, the period of the reference signal input to the jig CPU 210 (the period measured by the second clock measuring unit 216) is longer when the period of the first clock is longer, and the period of the first clock is longer. If it is shorter, it will be shorter. Thereby, when the cycle of the first clock is longer than the ideal value, the actual count number of the second clock measurement unit 216 is larger than the second count number, and the cycle of the first clock becomes the ideal value. On the other hand, when it is shorter, the actual count number of the second clock measurement unit 216 is smaller than the second count number.

  As a result of the comparison by the comparison unit 217, if the actual count number of the second clock measurement unit 216 and the second count number do not match, the second clock output unit 215 corrects the cycle of the first clock. Signal is generated. At this time, the correction signal generated by the second clock output unit 215 is set based on the period of the reference signal (reference signal output from the power supply CPU 131) input to the jig CPU 210. Specifically, if the actual count number of the second clock measurement unit 216 is larger than the second count number, a correction signal having a period shorter by a predetermined value than the period of the reference signal measured by the second clock measurement unit 216 is generated. If the actual count number of the second clock measuring unit 216 is less than the second count number, a correction signal having a period longer than the period of the reference signal measured by the second clock measuring unit 216 by a predetermined value is generated. The predetermined value is determined in advance and corresponds to the length of one cycle of the first clock, for example. Then, the second clock output unit 215 outputs a correction signal to the power supply CPU 131.

  When the correction signal is output from the jig CPU 210 to the power supply CPU 131, the first clock measurement unit 138 measures the period of the correction signal using the first clock. If the period of the correction signal is set shorter than the period of the first clock, the period of the correction signal cannot be measured. Therefore, the cycle of the correction signal is set longer than the cycle of the first clock.

  When the cycle of the correction signal is measured by the first clock measurement unit 138, the correction unit 139 sets the count number of the first clock counted during the cycle of the correction signal to be the first count number ( The period of the first clock is corrected so that the time required to count the first clock until it reaches the first count number is the period of the correction signal. In order to perform such correction, the cycle of the first clock generated by the first clock generator 136 is variable. The first clock output unit 137 uses the corrected first clock to generate and output a reference signal having a period corresponding to the first count number.

  After the corrected reference signal based on the first clock is output from the power supply CPU 131 to the jig CPU 210, the second clock measurement unit 216 continuously measures the period of the reference signal using the second clock, and the comparison unit 217. Compares the actual count number of the second clock measurement unit 216 with the second count number. Then, the second clock output unit 215 increases or decreases the correction signal by a predetermined value and outputs it to the power supply CPU 131 until the actual count number of the second clock measurement unit 216 matches the second count number (clock correction is performed). to continue). When the difference between the actual count number of the second clock measurement unit 216 and the second count number falls within a predetermined allowable range, the actual count number of the second clock measurement unit 216 matches the second count number. You may assume that

  When the actual count number of the second clock measurement unit 216 matches the second count number by such clock correction, the jig CPU 210 instructs the power supply CPU 131 to end the clock correction, and ends the clock correction. Thus, when the clock correction is completed, the first clock cycle is corrected such that the count number of the first clock counted during the cycle of the correction signal becomes the first count number. For this reason, the power supply CPU 131 holds the cycle of the first clock in the power supply storage unit 132 when receiving a clock correction end instruction. Then, the power supply CPU 131 operates based on the first clock whose cycle is corrected after the clock correction is completed.

<Flow of clock correction>
First, the processing flow of the jig CPU 210 at the time of clock correction will be described with reference to FIG. The start of the flowchart of FIG. 5 is when an operation for starting clock correction is performed on the jig operation unit 230.

  In step S1, the jig CPU 210 instructs the power supply CPU 131 to start clock correction. Thereafter, in step S2, the jig CPU 210 determines whether or not the reference signal from the power source CPU 131 has been input. As a result, if the reference signal is input, the process proceeds to step S3. If the reference signal is not input, the determination in step S2 is repeated.

  In step S3, the second clock measurement unit 216 measures the period of the reference signal using the second clock. In step S4, the comparison unit 217 compares the actual count number of the second clock measurement unit 216 with the second count number. As a result, if the actual count number of the second measurement unit 216 is different from the second count number, the process proceeds to step S5.

  In step S5, the comparison unit 217 determines whether the actual count number of the second clock measurement unit 216 is larger or smaller than the second count number. As a result, if the actual count number of the second clock measurement unit 216 is greater than the second count number, the process proceeds to step S6. If the actual count number of the second measurement unit 216 is less than the second count number, the process proceeds to step S7. To do. When the process proceeds to step S <b> 6, the second clock output unit 215 generates a correction signal having a cycle shorter than the cycle of the reference signal by a predetermined value and outputs the correction signal to the power supply CPU 131. On the other hand, when the process proceeds to step S7, the second clock output unit 215 generates a correction signal having a period longer by a predetermined value than the period of the reference signal and outputs the correction signal to the power supply CPU 131.

  After outputting the correction signal to the power supply CPU 131, in step S2, the jig CPU 210 repeats the determination of whether or not the reference signal from the power supply CPU 131 has been input. As a result, when the reference signal is input, the process proceeds to step S3, and the second clock measurement unit 216 measures the period of the reference signal using the second clock.

  In step S4, when the comparison unit 217 determines that the actual count number of the second clock measurement unit 216 is the same as the second count number, the process proceeds to step S8. In step S8, the jig CPU 210 instructs the power supply CPU 131 to end the clock correction.

  Next, a processing flow of the power supply CPU 131 at the time of clock correction will be described with reference to FIG. The start of the flowchart of FIG. 6 is when a clock correction start instruction is received from the correction jig 200.

  In step S <b> 21, the first clock output unit 137 generates a reference signal having a period corresponding to the first count number using the first clock, and outputs the reference signal to the jig CPU 210. In step S22, the power supply CPU 131 determines whether or not the correction signal from the jig CPU 210 has been input. As a result, if a correction signal is input, the process proceeds to step 23.

  In step S23, the first clock measurement unit 138 measures the period of the correction signal using the first clock. In step S24, the correction unit 139 corrects the cycle of the first clock so that the count number of the first clock counted during the cycle of the correction signal becomes the first count number. Thereafter, the process proceeds to step S <b> 21, and the first clock output unit 137 generates a reference signal having a period corresponding to the first count number using the first clock, and outputs the reference signal to the jig CPU 210. Note that the period of the first clock counted at this time is corrected in step S24.

  If the power supply CPU 131 determines in step S22 that the correction signal has not been input, the process proceeds to step S25. In step S25, the power supply CPU 131 determines whether or not a clock correction end instruction has been received from the jig CPU 210. As a result, if there is an instruction to end clock correction, the process proceeds to step S26, and if there is no instruction to end clock correction, the process returns to step S22. In step S <b> 26, the power supply CPU 131 holds the first clock cycle (the corrected cycle) in the power storage unit 132 when receiving the clock correction end instruction.

  As described above, the clock adjustment mechanism of the present embodiment includes the power supply CPU 131 (first processing unit) and the jig CPU 210 (second processing unit). The power supply CPU 131 generates a first clock that generates a first clock, and a first clock output that generates and outputs a reference signal having a period corresponding to a predetermined first count using the first clock. A first clock measuring unit 138 that measures the period of the signal input to the power supply CPU 131 using the first clock, and a correction unit 139 that corrects the period of the first clock. The jig CPU 210 includes a second clock generation unit 214 that generates a second clock, a second clock measurement unit 216 that measures the period of the reference signal output from the power supply CPU 131 using the second clock, and a reference signal A comparison unit 217 that compares the actual count number of the second clock measurement unit 216 when the period is measured with a second count number predetermined as the count number of the second clock corresponding to the period of the reference signal; When the actual count number of the two-clock measuring unit 216 is larger than the second count number, a correction signal having a shorter cycle than the reference signal is output to the power supply CPU 131, and the actual count number of the second clock measuring unit 216 is smaller than the second count number. And a second clock output unit 215 that outputs a correction signal having a period longer than that of the reference signal to the power supply CPU 131. When the correction signal is output from the jig CPU 210 to the power supply CPU 131, the first clock measurement unit 138 measures the period of the correction signal using the first clock, and the correction unit 139 determines the period of the correction signal. The cycle of the first clock is corrected so that the count number of the first clock counted in between becomes the first count number, and the first clock output unit 137 uses the corrected first clock to A reference signal having a period corresponding to the count number is generated and output. When the actual count number of the second clock measurement unit 216 matches the second count number, the jig CPU 210 instructs the power supply CPU 131 to end the correction of the first clock cycle.

  In the configuration of this embodiment, a reference signal having a period corresponding to the first count number is transmitted from the power supply CPU 131 to the jig CPU 210, and the period of the reference signal is measured by the jig CPU 210. Here, if the frequency accuracy of the first clock is low, a deviation occurs between the actual count number of the second clock measurement unit 216 and the second count number. Specifically, if the period of the first clock is longer than the ideal value, the period of the reference signal is longer, so that the actual count number of the second clock measuring unit 216 is larger than the second count number. On the other hand, if the cycle of the first clock is shorter than the ideal value, the cycle of the reference signal is shortened, so that the actual count number of the second clock measurement unit 216 is smaller than the second count number. Therefore, the second clock output unit 215 outputs a correction signal having a shorter cycle than the reference signal to the power supply CPU 131 when the actual count number of the second clock measurement unit 216 is larger than the second count number, and the second clock measurement unit 216. When the actual count number is less than the second count number, a correction signal having a longer cycle than the reference signal is output to the power supply CPU 131. When such a correction signal is output to the power supply CPU 131, the first clock measurement unit 138 measures the period of the correction signal using the first clock. The correction unit 139 corrects the cycle of the first clock so that the count number of the first clock counted during the cycle of the correction signal becomes the first count number. The first clock output unit 137 generates and outputs a reference signal having a period corresponding to the first count number using the corrected first clock. When the actual count number of the second clock measurement unit 216 matches the second count number, the jig CPU 210 instructs the power supply CPU 131 to end the correction of the first clock cycle. In other words, the correction unit 139 ends the correction of the first clock cycle. As a result, the frequency accuracy of the first clock is increased, and the timing accuracy of the power supply CPU 131 is improved.

  Further, in the present embodiment, as described above, the second clock output unit 215 performs the period of the correction signal output to the power supply CPU 131 until the actual count number of the second clock measurement unit 216 matches the second count number. Is increased or decreased by a predetermined value. With this configuration, the frequency accuracy of the first clock is further improved.

  In the present embodiment, as described above, since the clock correction of the power supply CPU 131 (first clock generation unit 136) is performed, the timing for switching on / off the power supply to the plurality of power supplied units 10 is shifted. Can be suppressed.

  Further, in the present embodiment, as described above, clock correction is performed using the correction jig 200, so that it is not necessary to previously install a processing unit for performing clock correction in the multi-function device 100.

  It should be thought that embodiment disclosed this time is an illustration and restrictive at no points. The scope of the present invention is shown not by the description of the above-described embodiment but by the scope of claims for patent, and further includes meanings equivalent to the scope of claims for patent and all modifications within the scope.

  For example, in the above-described embodiment, the case where clock correction is performed using the correction jig 200 has been described. However, the present invention is not limited to this, and the main CPU 111 may have the function of the correction jig 200. That is, the “second clock output unit”, “second clock measurement unit”, and “comparison unit” of the present invention may be mounted on the main CPU 111. This eliminates the need to separately prepare a correction jig when performing clock correction.

10 Power Supply Unit 100 MFP (Image Forming Apparatus)
120 power supply unit 131 power supply CPU (first processing unit)
136 First clock generation unit 137 First clock output unit 138 First clock measurement unit 139 Correction unit 200 Correction jig 210 Jig CPU (second processing unit)
214 Second clock generation unit 215 Second clock output unit 216 Second clock measurement unit 217 Comparison unit

Claims (3)

A first processing unit and a second processing unit;
The first processing unit is a processing unit mounted on the image forming apparatus,
The image forming apparatus includes: a plurality of power supply units that are driven by power supply; and a power supply unit that generates power to be supplied to the plurality of power supply units.
On / off control of power supply to the plurality of power supplied units is performed by the first processing unit,
The first processing unit includes:
A first clock generator for generating a first clock;
A first clock output unit configured to generate and output a reference signal having a period corresponding to a predetermined first count using the first clock;
A first clock measurement unit that measures a period of a signal input to the first processing unit using the first clock;
A correction unit for correcting the period of the first clock,
The second processing unit includes:
A second clock generator for generating a second clock;
A second clock measurement unit that measures a period of the reference signal output from the first processing unit using the second clock;
The actual count number of the second clock measurement unit when the period of the reference signal is measured is compared with a second count number predetermined as the count number of the second clock corresponding to the period of the reference signal. A comparison unit;
When the actual count number of the second clock measuring unit is larger than the second count number, a correction signal having a shorter cycle than the reference signal is output to the first processing unit, and the actual count number of the second clock measuring unit is A second clock output unit that outputs the correction signal having a longer period than the reference signal to the first processing unit when the count is less than the second count number;
When the correction signal is output from the second processing unit to the first processing unit,
The first clock measurement unit measures the period of the correction signal using the first clock,
The correction unit corrects the cycle of the first clock so that the count number of the first clock counted during the cycle of the correction signal becomes the first count number,
The first clock output unit generates and outputs the reference signal having a period corresponding to the first count number, using the corrected first clock.
When the actual count number of the second clock measurement unit matches the second count number,
The clock adjusting mechanism, wherein the second processing unit instructs the first processing unit to end the correction of the cycle of the first clock.   The second clock output unit increases or decreases the period of the correction signal output to the first processing unit by a predetermined value until the actual count number of the second clock measurement unit matches the second count number. The clock adjustment mechanism according to claim 1. The second processing unit is a correction jig, said the corrected during the period of the first clock, clock adjustment mechanism according to claim 1 or 2, characterized in that it is connected to the first processing unit.

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