JP6224703B2 - Silicon ingot manufacturing method and silicon ingot - Google Patents

Description

  The present invention relates to a method for manufacturing a silicon ingot and a silicon ingot.

  Silicon substrates are widely used as semiconductor substrates in solar cell elements. This silicon substrate is obtained by slicing a monocrystalline or polycrystalline silicon ingot to a desired thickness.

  As a method for producing a single crystal silicon ingot, for example, the Czochralski method and the floating zone method are known. As a method for producing a polycrystalline silicon ingot, for example, a casting method or the like is known. A polycrystalline silicon ingot can be manufactured more easily than a single crystal silicon ingot (see, for example, JP-A-2007-9597). However, the photoelectric conversion efficiency of a solar cell element using a polycrystalline silicon substrate as a semiconductor substrate is the photoelectric conversion efficiency of a solar cell element using a single crystal silicon substrate due to the presence of crystal defects such as grain boundaries. Is generally known to be lower.

  In view of this, there has been proposed a method of manufacturing a silicon ingot with few defects such as crystal grain boundaries and having a uniform crystal orientation by using a casting method (for example, Japanese Patent Laid-Open No. 10-194718 and Japanese Translation of PCT International Publication No. 2009-523893). See the publication). In this manufacturing method, in a state where single crystal silicon as a seed crystal is arranged on the bottom surface in the mold, the silicon melt is injected in one direction from the seed crystal as a starting point by injecting the silicon melt into the mold. A solidifying method (seed casting method) is employed.

  However, the seed casting method causes a complicated manufacturing process for preparing the seed crystal and an increase in manufacturing cost. Also, when arranging a plurality of seed crystals on the bottom surface of the mold, unless the seed crystals are arranged with high accuracy, the silicon melt is difficult to solidify in one direction, and has a region with few defects and excellent crystallinity. It is difficult to manufacture a silicon ingot.

  Therefore, a silicon ingot manufacturing method and a silicon ingot that can easily manufacture a silicon ingot having a region with few defects and excellent crystallinity are desired.

  In order to solve the above-described problem, a silicon ingot manufacturing method according to an aspect includes a first step of preparing a mold, a first silicon melt supplied into the mold, and the first silicon melt being used as the mold. By solidifying on the bottom of the first region, a first region and a second region having a higher density of defects that can become etch pits by etching in the cross section than the first region are formed on the first region. A second step of forming one solidified layer; supplying a second silicon melt onto the first solidified layer in the mold; and passing the second silicon melt in a direction upward from the first solidified layer. And a third step of forming a second solidified layer having a third region having a lower density of defects that can be etched pits by etching in the cross section than the second region.

In addition, the silicon ingot according to one embodiment includes a first region, a second region, and a third region that are sequentially stacked from the bottom, and the density of defects that can become etch pits by etching in the cross section of the second region is height from the by etching rather higher than the density of defects that may be etch pits, the sum of the thickness of the first region and the second region is the bottom portion of each cross section of the first region and the third region 2 to 20% .

Further, a silicon ingot according to another embodiment includes a first region, a second region, and a third region, which are sequentially stacked from the bottom and contain carbon and nitrogen, and the atomic density of carbon in the second region the sum of the sum of the nitrogen atom density, the first much larger than the sum of the atom density of the atomic density and nitrogen atoms in the region, and the third carbon atom density in the region and the nitrogen atom density Bigger than .

Further, the silicon ingot according to another aspect, from the bottom toward the top, a silicon ingot having a specific resistance value has an area of maximum increases, toward the upper direction from the bottom A first portion having a tendency of increasing the specific resistance value, and a second portion having a tendency of decreasing the specific resistance value and having a minimum specific resistance value , the first portion and the second portion Each contain carbon and nitrogen, and the sum of the atomic density of carbon and the atomic density of nitrogen in the first part is larger than the sum of the atomic density of carbon and the atomic density of nitrogen in the second part .

  According to the above-described silicon ingot manufacturing method, dislocations and strain propagation from the first region are stopped in the second region where the defects are present at high density, so that there are few crystals on the first solidified layer. A region having excellent properties can be formed. Therefore, a silicon ingot having a region with few defects and excellent crystallinity can be easily produced.

  According to the above silicon ingot, a region having excellent crystallinity with few defects can be formed when the silicon ingot is manufactured. Accordingly, a silicon ingot having a region with few defects and excellent crystallinity can be provided.

FIG. 1 is a cross-sectional view showing a configuration example of a silicon ingot manufacturing apparatus. FIG. 2 is a cross-sectional view showing an example of the operation of the cooling plate. FIG. 3 is a flowchart illustrating the flow of the manufacturing process of the silicon ingot. FIG. 4 is a cross-sectional view showing a state in which a release material is applied to the inner wall of the mold. FIG. 5 is a cross-sectional view showing a state in which raw material silicon is filled in the crucible. FIG. 6 is a cross-sectional view showing how the mold is preheated and the raw silicon is heated. FIG. 7 is a cross-sectional view showing how the silicon melt is intermittently supplied. FIG. 8 is a cross-sectional view showing how the initial solidified layer is formed on the bottom in the mold. FIG. 9 is a cross-sectional view showing an example of the formation mode of the initial solidified layer. FIG. 10 is a cross-sectional view showing an example of the formation mode of the initial solidified layer. FIG. 11 is a cross-sectional view showing the configuration of the initial solidified layer. FIG. 12 is a cross-sectional view showing an example of the formation mode of the initial solidified layer. FIG. 13 is a cross-sectional view showing how the melt layer is formed on the initial solidified layer. FIG. 14 is a cross-sectional view showing how the silicon melt is continuously supplied. FIG. 15 is a cross-sectional view showing a state in which the cooling plate is in contact with the mold holding portion. FIG. 16 is a cross-sectional view showing how the silicon melt is solidified in one direction. FIG. 17 is a top view showing the configuration of the silicon ingot. FIG. 18 is a cross-sectional view showing the configuration of the silicon ingot. FIG. 19 is a diagram showing the atomic density of carbon and nitrogen in a silicon ingot. FIG. 20 is a diagram showing the relationship between the height and the ρb value in a silicon ingot. FIG. 21 is a diagram showing the relationship between height and EPD in a silicon ingot. FIG. 22 is a plan view showing the appearance of the light receiving surface of the photoelectric conversion element. FIG. 23 is a plan view showing the appearance of the non-light-receiving surface of the photoelectric conversion element. 24 is a diagram showing a cross section at the position indicated by the alternate long and short dash line XXIV-XXIV in FIGS. 22 and 23. FIG. 25 is a diagram illustrating the relationship between the height of the silicon ingot and the conversion efficiency of the photoelectric conversion element. FIG. 26 is a flowchart illustrating the flow of the manufacturing process of the silicon ingot. FIGS. 27A and 27B are diagrams showing the relationship between the solidification rate and the specific resistance value in the silicon ingot, respectively. FIGS. 28A and 28B are diagrams showing the relationship between the solidification rate and the dopant concentration in the silicon ingot, respectively.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, parts having the same configuration and function are denoted by the same reference numerals. Further, the drawings are schematically shown, and the apparatus and the like are illustrated in a simplified manner. In addition, the size and positional relationship of various structures in each drawing can be changed as appropriate. 1, 2, and FIGS. 4 to 18 have a right-handed XYZ coordinate system in which the upward direction of the silicon ingot manufacturing apparatus (the upward direction in the drawing of FIG. 1) is the + Z direction. 2, FIG. 6 to FIG. 8 and FIG. 13 to FIG. 16, the movement of the cooling plate 123 is indicated by black arrows, and the movement of heat is indicated by white arrows. The grant is indicated by the hatched arrows. 7 and 9, the direction in which the droplet of the silicon melt MS1 falls is indicated by a thick arrow. In FIGS. 9 to 12 and FIG. 16, the solidification of the silicon melt MS <b> 1 proceeds with a thick broken arrow. In FIGS. 2, 4 to 8, and 13 to 16, a broken line representing a part of the outer shape of the heater or the like shown in FIG. 1 is omitted.

<(1) Embodiment 1>
<(1-1) Silicon Ingot Manufacturing Equipment>
As shown in FIG. 1, a manufacturing apparatus 100 that manufactures a silicon ingot includes an upper unit 110, a lower unit 120, and a control unit 130.

  The upper unit 110 includes a crucible 111, a crucible upper heater H1u, and a side heater H1s. The lower unit 120 includes a mold 121, a mold holding part 122, a cooling plate 123, a rotating shaft 124, a mold upper heater H2u, a lower heater H2l, and temperature measuring parts CH1 and CH2. The material of the crucible 111 and the mold 121 may be any material as long as it does not easily melt, deform, decompose, etc., and does not easily react with silicon at a temperature equal to or higher than the melting point of silicon.

  The crucible 111 includes a main body 111b, an upper opening 111uo, an internal space 111i, and a lower opening 111bo. The main body 111b has a generally cylindrical shape with a bottom. The material of the crucible 111 may be, for example, quartz glass. The crucible upper heater H1u is arranged in an annular shape in plan view just above the upper opening 111uo. The side heater H1s is arranged in an annular shape in plan view so as to surround the main body 111b from the side.

  Here, at the time of manufacturing the silicon ingot, the inner space 111i of the crucible 111 is filled with a plurality of solid silicon lumps (hereinafter referred to as raw material silicon) that are raw materials of the silicon ingot, for example, from the upper opening 111uo. In addition, this raw material silicon | silicone may contain the thing of a powder state. The raw material silicon filled in the internal space 111i is melted by heating with the crucible upper heaters H1u and H2u and the side heater H1s. Then, for example, molten silicon (silicon melt) in the internal space 111i is supplied toward the mold 121 of the lower unit 120 through the lower opening 111bo. A configuration may be employed in which the crucible 111 is not provided with the lower opening 111bo, and the silicon melt is poured from the crucible 111 toward the mold 121 by tilting the crucible 111.

  The mold 121 has a bottomed cylindrical shape as a whole. Specifically, the mold 121 includes a bottom part 121b, a side wall part 121s, an internal space 121i, and an upper opening part 121o arranged on the upper part of the mold 121. The bottom 121b and the upper opening 121o may be, for example, a substantially square shape. And one side of bottom 121b and upper opening 121o should just be 300 mm or more and about 800 mm or less, for example. The upper opening 121o accepts supply of silicon melt from the crucible 111 into the internal space 121i. Here, as a material of the side wall part 121s and the bottom part 121b, for example, silica or carbon may be employed. The side wall 121s may be formed by being combined with, for example, a carbon fiber reinforced carbon composite material, a felt as a heat insulating material, or the like.

  As shown in FIG. 1, the mold upper heater H <b> 2 u is arranged in an annular shape directly above the upper opening 121 o of the mold 121. The lower heater H2l is arranged in an annular shape so as to surround a portion from the lower part to the upper part in the + Z direction of the side wall part 121s of the mold 121 from the side. Lower heater H2l may be divided into a plurality of regions, and the temperature of each region may be controlled independently.

  The mold holding unit 122 holds the mold 121 from below and is in close contact with the lower surface of the mold 121. The material of the mold holding part 122 may be a material having high heat conductivity such as graphite, and may further include a heat insulating part (not shown) between the side wall part 121 s of the mold 121. In this case, heat can be preferentially transmitted from the bottom 121b to the cooling plate 123 rather than the side wall 121s. The material of the heat insulating part may be, for example, felt.

  As shown in FIG. 2, the cooling plate 123 rises by the rotation of the rotating shaft 124 and contacts the lower surface of the mold holding unit 122. For example, the cooling plate 123 may have a structure in which water or gas circulates inside a hollow metal plate or the like. When the silicon ingot is manufactured, the cooling plate 123 comes into contact with the lower surface of the mold holding part 122 in a state where the internal space 121i is filled with the silicon melt MS1, thereby cooling from the silicon melt MS1 via the mold holding part 122. Heat removal is performed so that heat is transmitted to the plate 123. That is, the silicon melt MS1 is cooled from the bottom 121b side by the cooling plate 123.

  The temperature measuring parts CH1 and CH2 are parts for measuring the temperature. The temperature measuring units CH1 and CH2 can measure the temperature with a thermocouple or the like covered with a thin tube made of alumina, for example. In the temperature detection unit (not shown), the voltage generated in each temperature measuring unit CH1 and CH2 A temperature corresponding to is detected.

  Here, the temperature measuring unit CH1 is arranged in the vicinity of the lower heater H2l. The temperature measuring part CH2 is arranged near the lower surface of the central part of the bottom 121b of the mold 121.

  The control unit 130 is a part that controls the entire manufacturing apparatus 100. The control unit 130 includes, for example, a processor, a storage unit, and the like, and may be any unit that performs various controls by executing a program stored in the storage unit by the processor. For example, the controller 130 controls the outputs of the crucible upper heaters H1u and H2u, the side heater H1s, and the lower heater H2l. In addition, in the control part 130, the output of each heater H1s, H1u, H2l, H2u is controlled according to at least one of the temperature obtained by each temperature measuring part CH1, CH2 and the passage of time, for example.

<(1-2) Manufacturing method of silicon ingot>
Next, a method for manufacturing a silicon ingot using the manufacturing apparatus 100 will be described. As shown in FIG. 3, in the method for manufacturing a silicon ingot according to the present embodiment, the steps Sp <b> 1 to Sp <b> 3 as the first to third steps are sequentially performed, so that the silicon ingot has a region with few defects and excellent crystallinity. Ig1 is produced.

  In the present embodiment, in the first process of step Sp1, two processes of steps Sp11 and Sp12 are performed in order. Further, in the second process of step Sp2, four processes of steps Sp21 to Sp24 or five processes of steps Sp21 to Sp25 are performed in order. Furthermore, in the third process of step Sp3, the three processes of steps Sp31 to Sp33 are performed in order. 4 to 16 schematically show the state of the mold 121 in each step, the state of both the mold 121 and the crucible 111, or the manner in which the silicon melt MS1 is solidified.

<(1-2-1) First step>
In step Sp1, for example, as shown in FIGS. 4 and 5, the mold 121 and the crucible 111 are prepared. Here, two steps of Steps Sp11 and Sp12 performed in order in the first step will be described.

  In step Sp11, the mold 121 is prepared. For example, as shown in FIG. 4, a release material layer Mr <b> 1 is formed by applying a release material to the inner wall surface of the mold 121. Due to the presence of the release material layer Mr1, fusion of the silicon ingot Ig1 to the inner wall of the mold 121 during the process of solidifying the silicon melt MS1 is reduced. As a material of the release material layer Mr1, for example, one of silicon nitride, silicon carbide, and silicon oxide or a mixture of two or more types may be employed. The release material layer Mr1 can be formed, for example, by coating a slurry containing one or more of silicon nitride, silicon carbide, and silicon oxide on the inner wall of the mold 121 by application or spraying. Here, the slurry is, for example, in a solution in which the powder of any one or a mixture of two or more of silicon nitride, silicon carbide, and silicon oxide mainly contains an organic binder such as PVA (polyvinyl alcohol) and a solvent. It can be formed by stirring the mixture.

  In step Sp12, the crucible 111 is prepared. For example, as shown in FIG. 5, the raw material silicon PS <b> 1 is introduced into the internal space 111 i of the crucible 111. At this time, for example, the raw material silicon PS1 may be filled from the lower region in the crucible 111 toward the upper region. Further, for example, an element that becomes a dopant in the silicon ingot may be contained in the raw material silicon PS1. Here, the raw material silicon PS1 may be a lump of polysilicon as a raw material of a silicon ingot, for example. The polysilicon lump may be a relatively fine block lump of silicon, for example. In the case where a p-type silicon ingot is manufactured, the dopant element may be, for example, boron or gallium. When an n-type silicon ingot is manufactured, the element serving as a dopant may be, for example, phosphorus.

  In addition, before the 2nd process is started, it sets to the state in which the cooling plate 123 is not contact | abutting to the lower surface of the casting_mold | template holding part 122. FIG.

<(1-2-2) Second step>
In step Sp2, as shown in FIGS. 6 to 8, the silicon melt MS1 as the first silicon melt is supplied into the mold 121, and the silicon melt MS1 is solidified on the bottom 121b in the mold 121. . Thereby, the initial solidified layer (first solidified layer) PS2 is formed. Here, four steps of Steps Sp21 to Sp24 performed in order in the second step will be described.

  In step Sp21, preheating of the mold 121 is started. For example, as shown in FIG. 6, the mold 121 may be preheated to a temperature close to the melting point of silicon by a mold upper heater H2u and a lower heater H2l disposed above and to the side of the mold 121.

  In Step Sp22, heating of the raw material silicon PS1 in the crucible 111 is started. For example, as shown in FIG. 6, the crucible 111 is heated by the crucible upper heater H1u and the side heater H1s disposed above and on the side of the crucible 111. Thereby, the raw material silicon PS1 is heated to a temperature range of 1414 ° C. or higher and 1550 ° C. or lower exceeding the melting point, and gradually melts. At this time, the portion of the raw silicon PS1 in the crucible 111 that is disposed near the lower opening 111bo is also heated by the upper mold heater H2u disposed above the mold 121. For this reason, the raw material silicon PS1 disposed in the vicinity of the lower opening 111bo is easily melted.

  Here, heating of the raw material silicon PS1 in the crucible 111 is started after the preheating of the mold 121 is started, but the present invention is not limited to this. For example, the preheating of the mold 121 and the heating of the raw silicon PS1 in the crucible 111 may be started simultaneously, or after the heating of the raw silicon PS1 in the crucible 111 is started, the preheating of the mold 121 is started. May be.

  In step Sp23, the silicon melt MS1 is supplied from the crucible 111 into the mold 121. At this time, it is only necessary to realize a state where the silicon melt MS1 covers the bottom 121b in the mold 121. Such a state can be realized, for example, by melting a part of the raw material silicon PS1 in the crucible 111 and supplying the silicon melt MS1 from the crucible 111 into the mold 121. Here, the supply of the silicon melt MS1 from the crucible 111 into the mold 121 may be continuous or intermittent. However, if the silicon melt MS1 is intermittently supplied from the crucible 111 into the mold 121, the silicon melt MS1 corresponding to a part of the raw material silicon PS1 filled in the crucible 111 in step Sp12 becomes the mold 121. A state of covering the bottom 121b can be easily realized. Thereby, the initial solidified layer PS2 described later can be easily formed.

  Note that the continuous supply of the silicon melt MS1 means that the supply of the silicon melt MS1 occurs almost without interruption. Further, the intermittent supply of the silicon melt MS1 means that the supply and interruption of the supply of the silicon melt MS1 occur at irregular timings.

  For example, as shown in FIG. 7, the silicon melt MS1 is intermittently supplied into the mold 121 through the lower opening 111bo every time the raw material silicon PS1 is melted in the crucible 111. It can be realized by being supplied. Here, for example, the raw material silicon PS1 disposed in the vicinity of the lower opening 111bo in the crucible 111 is a mold upper heater disposed above the mold 121 in addition to the crucible upper heater H1u and the side heater H1s. It is also heated by H2u. Thereby, for example, whenever the raw material silicon PS1 disposed in the vicinity of the lower opening 111bo in the crucible 111 is melted, the silicon melt MS1 can be supplied into the mold 121 through the lower opening 111bo. .

  In step Sp24, the silicon melt MS1 supplied into the mold 121 in step Sp23 is solidified, whereby an initial solidified layer PS2 is formed on the bottom 121b in the mold 121. Here, as shown in FIG. 8, the silicon melt MS1 that covers the bottom 121b in the mold 121 rapidly solidifies, so that the initial solidified layer PS2 is formed to cover the bottom 121b in the mold 121. That's fine.

  For example, as shown in FIGS. 9 and 10, before the solidification of the region (lower region) MS1b on the bottom 121b side of the silicon melt MS1 sufficiently proceeds, the region (upper surface) near the upper surface forming the upper surface of the silicon melt MS1. Region) MS1u only needs to be rapidly solidified. Then, as shown in FIGS. 11 and 12, the initial solidified layer PS2 may be formed by the solidification of the lower region MS1b of the silicon melt MS1 progressing.

  As shown in FIG. 12, the initial solidified layer PS2 is obtained by solidifying the first region Ar1 obtained by solidification of the lower region MS1b and the upper surface region MS1u, and is disposed on the first region Ar1. And has a region Ar2.

  Here, in the second region Ar2, the density of defects particularly increases due to rapid solidification of the upper surface region MS1u of the silicon melt MS1. For this reason, for example, the density of defects in the second region Ar2 is larger than the density of defects in the first region Ar1. That is, for example, the density of defects that can become etch pits by the etching process in the cross section of the second region Ar2 (second density) is higher than the density of defects that can become etch pits by the etching process in the cross section of the first area Ar1 (second density). ) Becomes higher. In this case, when the first region Ar1 is formed by the solidification of the lower region MS1b, dislocation and strain propagation generated in the first region Ar1 are caused by the second region Ar2 in which defects exist at high density. Can be stopped. Note that dislocation and strain propagation generated in the first region Ar1 when the silicon ingot is cooled are also stopped in the second region Ar2 where defects exist at high density.

  In addition, the defect here should just be defects, such as a dislocation which can become an etch pit by the etching process in each cross section of 1st and 2nd area | region Ar1, Ar2. The density of defects that can become etch pits by the etching process is determined by, for example, using a microscope after the etching process is performed on each cross section of the first and second regions Ar1 and Ar2 of the silicon ingot Ig1 manufactured by this manufacturing method. Confirmed by observation. For example, if the etch pit density (EPD) derived by dividing the number of etch pits measured in the observation target area by the area of the observation target area is the density of defects that can become etch pits by the etching process. Good. The etching process may be, for example, a process in which a silicon plate (silicon plate) is sequentially subjected to mirror finishing etching (mirror etching) and etching (selective etching) for revealing crystal defects.

  More specifically, the etching process may be, for example, a process in which mirror etching and selective etching are sequentially performed on a silicon plate obtained by being sliced along the XZ plane from the silicon ingot Ig1 with a band saw. The mirror etching may be, for example, a process in which a silicon plate is sequentially immersed in a hydrofluoric acid solution for 180 seconds, washed with water, immersed in a hydrofluoric acid aqueous solution for 30 seconds, washed with water, and dried. In addition, the hydrofluoric acid solution should just be produced | generated by mixing 70 mass% nitric acid and 50 mass% hydrofluoric acid in the ratio of 7: 2, for example. The hydrofluoric acid aqueous solution may be generated, for example, by mixing pure water and 50% by mass hydrofluoric acid at a ratio of 20: 1. Further, the selective etching may be, for example, a process in which a silicon plate is sequentially subjected to 5-minute immersion in a selective etching solution described in JIS standard H0609, water washing, and drying. In the selective etching solution described in JIS standard H0609, for example, 70% by mass nitric acid, 99% by mass acetic acid, 50% by mass hydrofluoric acid and pure water are mixed at a ratio of 1: 12.7: 3: 3.7. Any solution may be used.

  Further, in this step Sp24, if a large amount of carbon and nitrogen is present in the upper surface region MS1u, the upper surface region MS1u is rapidly solidified. At this time, for example, the sum of the carbon atom density and the nitrogen atom density in the second region Ar2 becomes larger than the sum of the carbon atom density and the nitrogen atom density in the first region Ar1. In this case, when the first region Ar1 is formed by the solidification of the lower region MS1b, dislocation and strain propagation generated in the first region Ar1 are caused by the presence of carbon and / or nitrogen. It is stopped at the rising second region Ar2. Note that dislocation and strain propagation generated in the first region Ar1 when the silicon ingot is cooled are also stopped in the second region Ar2 where defects exist at high density.

  Here, if the atomic density of at least one of carbon and nitrogen is increased in the upper surface region MS1u of the silicon melt MS1 before the upper surface region MS1u is solidified, it does not solidify even if the silicon temperature is below the freezing point. (So-called compositional supercooling) occurs. For this reason, if the release material layer Mr1 contains at least one of carbon and nitrogen, the compositional supercooling is likely to occur. Further, the upper surface region MS1u in which such compositional supercooling occurs rapidly solidifies in accordance with, for example, the application of a physical stimulus.

  The atomic density of carbon and nitrogen is measured by, for example, secondary ion mass spectrometry (SIMS) for each cross section of the first and second regions Ar1 and Ar2. As physical stimulation applied to the upper surface region MS1u, for example, an impact caused by dripping the silicon melt MS1 from the crucible 111 onto the upper surface region MS1u, and a portion of the upper surface region MS1u in contact with the sidewall 121s of the mold 121 Examples include coagulation. Therefore, for example, if the supply of the silicon melt MS1 from the crucible 111 to the mold 121 in Step Sp23 is intermittent, rapid solidification of the upper surface region MS1u in Step Sp24 is easily realized.

  In step Sp2, after step Sp24 for forming the initial solidified layer PS2, a layer (silicon melt layer) MS1L of silicon melt MS1 is formed on the initial solidified layer PS2 in the mold 121 as shown in FIG. Step Sp25 may be executed. The silicon melt layer MS1L may be, for example, a layer of the molten silicon melt MS1 that covers the upper surface of the initial solidified layer PS2. The silicon melt layer MS1L is formed, for example, by intermittently supplying the silicon melt MS1 from the crucible 111 into the mold 121. For example, as shown in FIG. 13, the silicon melt MS1 is intermittently supplied every time the raw material silicon PS1 is melted in the crucible 111, into the mold 121 through the lower opening 111bo. It can be realized by being supplied.

<(1-2-3) Third step>
In step Sp3, the silicon melt MS1 as the second silicon melt is supplied onto the initial solidified layer PS2 in the mold 121, and the silicon melt MS1 is solidified in one direction upward from the initial solidified layer PS2. . That is, on the initial solidified layer PS2, the silicon melt MS1 is solidified in one direction (one-directional solidification) upward from the bottom 121b. Thereby, the silicon solid ingot Ig1 is formed by forming the second solidified layer having the third region Ar3 on the initial solidified layer PS2. Here, three steps of Steps Sp31 to Sp33 performed in order in the third step will be described.

  In step Sp31, the silicon melt MS1 is supplied onto the initial solidified layer PS2 in the mold 121. Thereby, as shown in FIG. 14, in the mold 121, the silicon melt MS1 is stored on the initial solidified layer PS2. Then, the supply of the silicon melt MS1 from the crucible 111 to the mold 121 is completed. For example, almost all the raw material silicon PS1 in the crucible 111 may be melted and supplied into the mold 121 as the silicon melt MS1.

  Here, the supply of the silicon melt MS1 from the crucible 111 into the mold 121 may be continuous or intermittent. However, if the silicon melt MS1 is continuously supplied from the crucible 111 into the mold 121, the silicon melt MS1 is rapidly supplied into the mold 121. As a result, the silicon ingot Ig1 can be manufactured quickly. In this case, if the silicon melt layer MS1L is formed on the initial solidified layer PS2 by executing Step Sp25, even if the supply of the silicon melt MS1 is continuous, The solidified layer PS2 is not easily heated rapidly by the supply of the high-temperature silicon melt MS1. As a result, since the initial solidified layer PS2 hardly dissolves and breaks down, the silicon ingot Ig1 having a region with few defects and excellent crystallinity can be manufactured.

  In step Sp32, the cooling plate 123 is abutted against the lower surface of the mold holder 122. Thereby, heat removal from the silicon melt MS1 in the mold 121 to the cooling plate 123 via the mold holding unit 122 is started. Here, for example, as shown in FIG. 15, in the state where the silicon melt MS1 is stored on the initial solidified layer PS2, the cooling of the silicon melt MS1 from the bottom 121b side by the cooling plate 123 is started. Immediately before the cooling plate 123 comes into contact with the lower surface of the mold holding part 122, for example, the outputs of the mold upper heater H2u and the lower heater H2l may be reduced. Note that the timing of bringing the cooling plate 123 into contact with the lower surface of the mold holding part 122 is the timing after all the raw material silicon PS1 in the crucible 111 is melted and supplied as the silicon melt MS1 into the mold 121. That's fine.

  In Step Sp33, the silicon melt MS1 in the mold 121 is unidirectionally solidified upward from the initial solidified layer PS2. Here, for example, as shown in FIG. 16, unidirectional solidification of the silicon melt MS1 in the mold 121 proceeds by cooling the silicon melt MS1 in the mold 121 from the bottom 121b side. As a result, a third region Ar3 whose outer edge is indicated by a broken line in FIG. 12 is formed on the second region Ar2 of the initial solidified layer PS2. The third region Ar3 may be a polycrystalline silicon.

  Here, for example, the outputs of the upper mold heater H2u and the lower heater H2l arranged above and on the side of the mold 121 are controlled according to the temperature detected by the temperature measuring sections CH1, CH2, etc. in the manufacturing apparatus 100. The For example, the temperature in the vicinity of the mold upper heater H2u and the lower heater H2l only needs to be maintained in the vicinity of the melting point of silicon. Thereby, silicon crystal growth from the side of the mold 121 is difficult to occur, and silicon crystal growth in the + Z direction as the upper side is likely to occur.

  And silicon ingot Ig1 is manufactured in the casting_mold | template 121 because unidirectional solidification of silicon melt MS1 progresses slowly.

  By the way, in the above-mentioned step Sp24 as the initial stage of solidification of the silicon melt MS1 in the mold 121, when the first region Ar1 is formed by solidification of the lower region MS1b, dislocations and strains generated in the first region Ar1. Is stopped in the second region Ar2. For this reason, the influence of various defects and distortions that are likely to occur at the portion of the mold 121 in contact with the bottom 121b of the silicon melt MS1 is difficult to affect the third region Ar3 due to the presence of the second region Ar2.

  Thereby, in this step Sp33, the third region Ar3 with few defects and excellent crystallinity can be formed on the second region Ar2 of the initial solidified layer PS2. Specifically, the density of defects in the third region Ar3 is smaller than the density of defects in each of the first region Ar1 and the second region Ar2. Therefore, the silicon ingot Ig1 having a region with few defects and excellent crystallinity can be easily manufactured. In addition, the defect here should just be a defect which can become an etch pit by the etching process in each cross section of 2nd and 3rd area | region Ar2, Ar3. The defect density (third density) in the third region Ar3 is confirmed by a method similar to the defect density in the first and second regions Ar1 and Ar2, for example.

<(1-3) Silicon ingot>
FIG. 17 illustrates a top view schematically illustrating the silicon ingot Ig1 according to this embodiment manufactured by the manufacturing method according to this embodiment described above. FIG. 18 illustrates a cross-sectional view schematically showing an XZ cross-section at a position indicated by a one-dot chain line XVIII-XVIII in FIG. 17 of the silicon ingot Ig1.

  As shown in FIG. 18, the silicon ingot Ig1 according to this embodiment includes a first region Ar1, a second region Ar2, and a third region Ar3 that are sequentially stacked from the bottom in the −Z direction. The first and second regions Ar1, Ar2 correspond to the initial solidified layer PS2.

  Here, for example, the density of defects that can become etch pits by etching in the cross section of the second region Ar2 is larger than the density of defects that can become etch pits by etching in the cross sections of the first and third regions Ar1 and Ar3. That's fine. In this case, in the manufacturing process of the silicon ingot Ig1, when the first region Ar1 is formed by solidification of the lower region MS1b and when the silicon ingot Ig1 is cooled, dislocations and strain propagate in the first region Ar1. Is stopped in the second region Ar2. For this reason, the influence of various defects and distortions that are likely to occur at the portion of the mold 121 in contact with the bottom 121b of the silicon melt MS1 is difficult to affect the third region Ar3 due to the presence of the second region Ar2. As a result, the third region Ar3 above the second region Ar2 can be a region with few defects and excellent crystallinity. That is, the silicon ingot Ig1 having a region with few defects and excellent crystallinity can be easily manufactured.

  Note that the etching process here may be a process similar to the above-described etching process. In addition, the density of defects that can become etch pits by the etching process in the first to third regions Ar1 to Ar3 is confirmed by observation with a microscope for the silicon plate subjected to the above-described etching process.

  Here, the density of defects (first to third densities) that can become etch pits by the etching process in each cross section of the first to third areas Ar1 to Ar3 is in the order of the third density, the first density, and the second density. growing. Specifically, the second density in the cross section of the second region Ar2 is larger than the first density in the cross section of the first region Ar1, and the third region is larger than the first density in the cross section of the first region Ar1. The third density in the cross section of Ar3 is smaller. That is, the third region Ar3 is a region with few defects and excellent crystallinity.

  In the silicon ingot Ig1, for example, if the sum of the carbon atom density and the nitrogen atom density in the second region Ar2 is larger than the sum of the carbon atom density and the nitrogen atom density in the first region Ar1, The density of defects in the second region Ar2 increases. Here, in the second region Ar2, the amount of carbon and nitrogen entering the silicon crystal lattice in a substitutional form is large, and the defect density is increased. Also in this case, in the manufacturing process of the silicon ingot Ig1, when the first region Ar1 is formed by solidification of the lower region MS1b and when the silicon ingot Ig1 is cooled, dislocations and strains generated in the first region Ar1. Is stopped in the second region Ar2. For this reason, the influence of various defects and distortions that are likely to occur at the portion of the mold 121 in contact with the bottom 121b of the silicon melt MS1 is difficult to affect the third region Ar3 due to the presence of the second region Ar2. As a result, the third region Ar3 above the second region Ar2 can be a region with few defects and excellent crystallinity. That is, the silicon ingot Ig1 having a region with few defects and excellent crystallinity can be easily manufactured.

  Note that the thickness in the Z direction of the initial solidified layer PS2 having the first and second regions Ar1 and Ar2 may be, for example, about several to 50% of the height in the Z direction of the silicon ingot Ig1. For example, if the thickness in the Z direction of the initial solidified layer PS2 is about 2 to 20% of the height in the Z direction of the silicon ingot Ig1, the third region Ar3 with few defects and excellent crystallinity is formed in the silicon ingot. It can be formed over a wide range of Ig1.

<Specific example of (1-4) silicon ingot>
<Production of (1-4-1) Silicon Ingot>
Here, the silicon ingot Ig1 according to one specific example of the present embodiment was manufactured using the silicon ingot manufacturing apparatus 100 shown in FIG. 1 and the silicon ingot manufacturing method shown in FIGS.

  In the silicon ingot manufacturing apparatus 100, quartz glass is used as the material of the crucible 111. Further, the mold 121 has a first layer including a portion on the side of the internal space 121i of the side wall 121s and a bottom 121b. Further, in the side wall 121s, the second layer and the third layer are sequentially arranged around the first layer. Adopted what is arranged. Here, silica was used as the material for the first layer, a carbon fiber reinforced carbon composite material was used as the material for the second layer, and felt of a heat insulating material was used as the material for the third layer.

  First, as shown in FIG. 4, a release material layer Mr <b> 1 was formed by applying a release material to the inner wall surface of the mold 121. Here, a release material made into a slurry by mixing a powder of silicon nitride, a powder of silicon oxide, and a PVA aqueous solution as a binder solution was used.

  Next, as shown in FIG. 5, a large number of raw material silicon PS1 having a total amount of about 45 kg was put into the crucible 111. At this time, boron as an element serving as a dopant was added to the raw material silicon PS1.

  Next, as shown in FIG. 6, preheating of the mold 121 was started by the mold upper heater H2u and the lower heater H2l arranged around the mold 121. By this preheating, the mold 121 was heated to about 1300 ° C. close to the melting point of silicon.

  In addition, the heating of the raw material silicon PS1 disposed in the crucible 111 was started by the crucible upper heater H1u and the side heater H1s disposed around the crucible 111. As a result, the raw material silicon PS1 was heated to a temperature range of 1414 ° C. or higher exceeding the melting point and 1550 ° C. or lower and gradually melted. At this time, a portion of the raw material silicon PS1 in the crucible 111 disposed near the lower opening 111bo was also heated by the mold upper heater H2u disposed above the mold 121.

  Next, as shown in FIG. 7, intermittent supply of the silicon melt MS1 into the mold 121 was started. Here, every time the raw silicon PS1 is melted in the crucible 111, the silicon melt MS1 is supplied into the mold 121 through the lower opening 111bo.

  Next, as shown in FIG. 8, an initial solidified layer PS <b> 2 was formed on the bottom 121 b in the mold 121. Here, a small amount of the silicon melt MS1 stored on the bottom 121b in the mold 121 is solidified to form an initial solidified layer PS2 on the bottom 121b in the mold 121.

  Next, as shown in FIG. 13, the silicon melt MS1 was intermittently supplied from the crucible 111 into the mold 121. Here, every time the raw silicon PS1 is melted in the crucible 111, the silicon melt MS1 is supplied into the mold 121 through the lower opening 111bo. As a result, the silicon melt MS1 as the third silicon melt was intermittently supplied onto the initial solidified layer PS2 in the mold 121. As a result, the upper surface of the initial solidified layer PS2 was covered with the molten silicon melt MS1. That is, the silicon melt layer MS1L was formed on the initial solidified layer PS2 in the mold 121.

  Next, as shown in FIG. 14, the silicon melt MS1 was continuously supplied from the crucible 111 into the mold 121. Here, in the crucible 111, silicon as a raw material (also referred to as raw material silicon) that has closed the lower opening 111bo of the crucible 111 is completely melted, so that the silicon melt MS1 is formed in the lower opening. It was continuously fed into the mold 121 via 111bo. At this time, all the raw material silicon PS1 in the crucible 111 was melted and supplied into the mold 121 as the silicon melt MS1. Here, the time required from the start to the end of the supply of the silicon melt MS1 from the crucible 111 to the mold 121 is about 90 minutes.

  Thereafter, as shown in FIG. 15, the cooling plate 123 was brought into contact with the lower surface of the mold holding part 122. As a result, the silicon melt MS1 in the mold 121 is cooled from the bottom 121b side, and unidirectional solidification occurs upward from the bottom 121b side of the silicon melt MS1. At this time, the temperature in the vicinity of the mold upper heater H2u and the lower heater H2l was maintained at about 1413 to 1414 ° C., which is in the vicinity of the melting point of silicon. That is, the silicon melt MS1 was heated by the mold upper heater H2u and the lower heater H2l. Thereby, the unidirectional solidification of the silicon melt MS1 was performed, and the p-type silicon ingot Ig1 was manufactured in the mold 121 by the subsequent air cooling.

  In addition, a silicon ingot according to a reference example was manufactured using a manufacturing apparatus having the same configuration as the manufacturing apparatus 100 described above. Specifically, the silicon melt MS1 obtained by melting the raw material silicon PS1 in the crucible 111 is continuously injected into the mold 121 in a short time, and then the unidirectional solidification of the silicon melt MS1 is performed. The silicon ingot was manufactured. Here, the temperature of the mold 121 when the silicon melt MS1 is injected into the mold 121 is about 750 ° C. In addition, when the crucible 111 is heated in a state where the lower opening 111bo of the crucible 111 is closed with a relatively large raw material silicon, the start and end of the supply of the silicon melt MS1 from the crucible 111 into the mold 121 is completed. The time required to complete (called supply time) has been shortened. This supply time was set to about 1/30 of the supply time when the silicon ingot Ig1 according to the specific example of this embodiment is manufactured. Further, after the supply of the silicon melt MS1 from the crucible 111 into the mold 121 was completed, the cooling plate 123 was brought into contact with the mold holding part 122. The other manufacturing conditions of the silicon ingot according to the reference example are substantially the same as the manufacturing conditions of the silicon ingot Ig1 according to the specific example of the present embodiment.

<(1-4-2) Analysis method and analysis result of silicon ingot>
As shown in FIG. 17, a portion of the width from one end to the other end in the Y direction of the silicon ingot Ig1 that is about 1/4 from the one end is sliced along the XZ plane by a band saw. A silicon plate having a thickness of about 10 mm was obtained. Thereafter, the silicon plate was subjected to mirror etching for mirror finishing. Further, selective etching for revealing crystal defects was performed on the silicon plate subjected to mirror etching. Thereafter, the board surface of the silicon plate was photographed, and a cross section as shown in FIG. 18 was obtained.

  In mirror etching, the silicon plate was sequentially immersed in a hydrofluoric acid solution for 180 seconds, washed with water, immersed in a hydrofluoric acid aqueous solution for 30 seconds, washed with water, and dried. Here, the hydrofluoric acid solution was produced by mixing 70 mass% nitric acid and 50 mass% hydrofluoric acid in a ratio of 7: 2. The hydrofluoric acid aqueous solution was produced by mixing pure water and 50% by mass hydrofluoric acid in a ratio of 20: 1. In the selective etching, a selective etching solution described in JIS standard H0609, that is, 70% by mass nitric acid, 99% by mass acetic acid, 50% by mass hydrofluoric acid, and pure water is applied to the silicon plate at 1: 12.7: A 5-minute immersion in a solution mixed at a ratio of 3: 3.7, washing with water, and drying were sequentially performed. Note that mirror etching and selective etching described below were all performed under substantially the same conditions.

  As shown in FIG. 18, the silicon ingot Ig1 according to one specific example includes a first region Ar1, a second region Ar2, and a third region Ar3 that are sequentially stacked from the bottom in the −Z direction. Further, the silicon plate subjected to the selective etching described above was observed with a scanning electron microscope (SEM). As a result, it was recognized that grain boundaries were concentrated at the interface between the first region Ar1 and the second region Ar2 and at the interface between the second region Ar2 and the third region Ar3. Further, according to the observation by the SEM, huge crystal grains having a grain size of 300 μm or more are recognized mainly in the third region Ar3, and the grain sizes of less than 300 μm are mainly used in the first and second regions Ar1 and Ar2. Small crystal grains were observed.

Further, according to observation by SEM, it was recognized that the density of etch pits (EPD) decreased in the order of the second region Ar2, the first region Ar1, and the third region Ar3. For example, the EPD related to the second region Ar2 is about 6 × 10 ⁵ pieces / cm ² , the EPD related to the first region Ar1 is about 1 × 10 ⁵ pieces / cm ² , and the EPD related to the third region Ar3 EPD was about 5 × 10 ⁴ pieces / cm ² . Since the thickness of the second region Ar2 was around 200 μm, each EPD is obtained by dividing the number of etch pits measured in a rectangular region having a side of about 100 μm by the area of the rectangular region. Obtained.

  From the relationship of the above EPD, the density of defects that can become etch pits by etching in the cross section of the second region Ar2 is higher than the density of defects that can become etch pits by etching in the cross sections of the first and third regions Ar1 and Ar3. I found it expensive. The density of defects (second density) that can become etch pits by etching in the cross section of the second region Ar2 is higher than the density of defects (first density) that can become etch pits by etching in the cross section of the first region Ar1. I found that it was higher. Furthermore, it has been found that the density of defects (third density) that can become etch pits by the etching process in the cross section of the third region Ar3 is lower than the first density.

  Further, according to the analysis result by the Raman spectroscopy for the silicon plate subjected to the selective etching described above, the crystallinity is observed in any of the first to third regions Ar1 to Ar3 in the vicinity of the second region Ar2. The presence of amorphous components was not confirmed. In addition, due to an increase in the half-value width of the peak in the observed Raman spectrum, a tendency of stress fluctuation is observed at the interface between the first region Ar1 and the second region Ar2 and in the vicinity thereof, and local stress is generated. It was confirmed that From this, when the first region Ar1 is formed by the solidification of the lower region MS1b and when the silicon ingot Ig1 is cooled, dislocation and strain propagation generated in the first region Ar1 are caused in the second region Ar2. Presumed to have been stopped.

FIG. 19 shows the atomic densities of carbon and nitrogen in the first to third regions Ar1 to Ar3. In FIG. 19, the relationship between the position in the Z direction (height direction) and the atomic density of carbon in the silicon ingot Ig1 is indicated by black circles. The position in the Z direction and the nitrogen atom The relationship with density is indicated by a black diamond mark. In FIG. 19, the horizontal axis indicates the position in the Z direction with the approximate center of the second region Ar2 as a reference, and the vertical axis indicates the atomic density. Here, the atomic density of carbon and nitrogen in the first to third regions Ar1 to Ar3 was measured by SIMS for the silicon plate subjected to the selective etching. IMS-6F manufactured by Cameca was used as the SIMS device. The measurement by SIMS was performed under conditions where the primary ion species was Cs ⁺ , the primary ion acceleration voltage was 14.5 kV, the secondary ion polarity was negative, and the mass resolution was standard. In addition, the measurement positions (measurement positions) by SIMS were set to a total of five locations in which the ± 200 μm and ± 400 μm portions were added, with the approximate center of the second region Ar2 as a reference in the Z direction.

As shown in FIG. 19, it was confirmed that the atomic density of carbon was significantly increased in the second region Ar2 as compared with the first and third regions Ar1 and Ar3. The atomic density of nitrogen is less than the lower limit of mass resolution in SIMS in the first and third regions Ar1 and Ar3, whereas in the second region Ar2, it is about 1 × 10 ¹⁸ atoms / cm ^3. It was confirmed that. Therefore, for the initial solidified layer PS2, the sum of the atomic density of carbon and the atomic density of nitrogen in the second region Ar2 is greater than the sum of the atomic density of carbon and the atomic density of nitrogen in the first region Ar1. I understood. And in 2nd area | region Ar2, compared with 1st and 3rd area | region Ar1, Ar3, since the atomic density of carbon and nitrogen is high, the carbon and nitrogen which have entered into the crystal lattice of silicon in the form of a substitution type etc. It was estimated that the defect density was increased due to the large amount of.

Here, when the upper limit (solid solution limit) of the amount of carbon that can be dissolved in silicon in the equilibrium state is expressed by atomic density, it is 1 × 10 ¹⁸ atoms / cm ³ or less, whereas the second region The atomic density of carbon in Ar2 was as high as about 1 × 10 ²⁰ atoms / cm ³ . Due to such a tendency of the atomic density of carbon, it was estimated that the silicon melt MS1 rapidly solidified when the second region Ar2 was formed.

  Here, the crystal orientation in the region including the first to third regions Ar1 to Ar3 centering on the second region Ar2 of the silicon ingot Ig1 according to one specific example was analyzed by an electron beam backscatter diffraction (EBSD) method. As the EBSD device, an EBSD device (OSL orientation analyzer manufactured by TSL) installed in an SEM (JSM-6500F manufactured by JEOL Ltd.) equipped with a field emission electron gun was used. In the analysis in the EBSD apparatus, the acceleration voltage is 15.0 kV, the irradiation current is 7.0 nA, the sample inclination is 70 degrees, the measurement area is 1.7 mm × 2.6 mm, and the measurement interval. Was performed under the condition of 2 μm / step.

  On the other hand, for the silicon ingot according to one reference example, it was confirmed that the initial solidified layer PS2 as in one specific example was not formed by visual observation of an XZ cross section subjected to mirror etching and selective etching and observation with an optical microscope. did.

  FIG. 20 shows the relationship between the position from the lower surface of the silicon ingot Ig1 according to one specific example and the normalized specific resistance (ρb value). Here, the concentration of boron as a dopant is measured by measuring the electrical resistance between the front surface and the back surface of the silicon plate subjected to the selective etching, which was the subject of the cross-sectional photograph shown in FIG. The resistivity distribution corresponding to the distribution was obtained. In FIG. 20, when the distance (height) from the lower surface to the upper surface of the silicon ingot Ig1 is 100 (solidification rate is 100%), the distance (height) from the lower surface of the silicon ingot Ig1 is 6.3, Normalization in each part of 12.5, 18.8, ..., 87.5 (solidification ratios of 6.3%, 12.5%, 18.8%, ..., 87.5%) The ρb value is shown. For example, the relationship between the height and the ρb value for the silicon ingot Ig1 according to one specific example is indicated by a black circle. In FIG. 20, the vertical axis represents the normalized ρb value, and the horizontal axis represents the position in the height direction (Z direction) of the silicon ingot Ig1. In FIG. 20, the relationship between the height and the ρb value for a silicon ingot according to a reference example manufactured without forming the initial solidified layer PS2 is indicated by black rhombus marks. Here, the solidification rate represents the ratio of the mass of the solidified ingot to the total mass of the silicon raw material used for casting the ingot, and is 0% at the lower end of the ingot after casting (the first solidified end surface that contacts the mold bottom), It becomes 100% at the upper end of the ingot (the end face on the mold open side and finally solidified).

  As shown in FIG. 20, for the silicon ingot Ig1 according to one specific example, it was confirmed that the ρb value was relatively low for the first and second regions Ar1 and Ar2 corresponding to the initial solidified layer PS2. On the other hand, about 3rd area | region Ar3, according to the distance from the lower surface of silicon ingot Ig1, it confirmed that (rho) b value was decreasing monotonously from a high state. From these results, the first and second regions Ar1 and Ar2 are formed by rapid solidification of the silicon melt MS1, so that the boron concentration is relatively high and the ρb value is relatively small. It was estimated. On the other hand, in the third region Ar3, since the silicon melt MS1 is formed by unidirectional solidification at a very low speed, the concentration of boron as an impurity in the silicon melt MS1 increases from the initial stage of solidification to the end of solidification. It is presumed that it showed a trend.

  On the other hand, with respect to the silicon ingot according to one reference example, it was confirmed that the ρb value simply decreased according to the distance from the lower surface of the silicon ingot. This tendency of the ρb value is consistent with the fact that when the silicon melt MS1 is solidified, the concentration of boron as an impurity in the silicon melt MS1 increases from the initial stage of solidification to the end of solidification. It is considered a thing.

  FIG. 21 shows the measurement results of the change in EPD according to the distance (height) from the lower surface of the silicon ingot Ig1 according to one specific example. Specifically, in FIG. 21, the relationship between the height and the EPD for a silicon ingot Ig1 according to a specific example of the present embodiment is indicated by black circles. In FIG. 21, the relationship between the height and the EPD of a silicon ingot according to a reference example manufactured without forming the initial solidified layer PS2 is indicated by black rhombus marks.

  Here, as shown in FIG. 17, the silicon ingot Ig1 is divided into two parts by cutting the substantially central part in the Y direction along the X plane by the band saw, and further, the substantially central part in the Z direction is YZ by the band saw. It was divided into two by cutting along a plane. That is, an ingot piece Ig11 having a size of a quarter of the silicon ingot Ig1 was cut out from the silicon ingot Ig1. Next, when the distance (height) from the lower surface to the upper surface of the ingot piece Ig11 is 100 (solidification rate is 100%), the distance (height) from the lower surface of the ingot piece Ig11 is 8, 10, 16 , 20, 25, 30, 40, 50 and 82 (solidification rate 8%, 10%, 16%, 20%, 25%, 30%, 40%, 50% and 82%) It was sliced to a thickness of ˜300 μm. Here, the ingot piece Ig11 was sliced along the XY plane by a band saw, so that nine silicon plates substantially parallel to the lower surface of the silicon ingot Ig1 were formed. Further, mirror etching and selective etching were sequentially performed on these nine silicon plates. Thereafter, for each silicon plate, 15 rectangular regions at approximately equal intervals in the substantially central portion of the silicon plate in the Y direction (the portion along the broken line in FIG. 17) are observed by SEM, and the number of etch pits is measured. Then, the EPD was calculated by dividing by the area of the observation region. The rectangular area has a side of 250 μm.

  As shown in FIG. 21, in the silicon ingot Ig1 according to one specific example, the EPD is slightly higher in the second region Ar2 than in the first region Ar1, and the third region Ar3 is higher than in the first and second regions Ar1 and Ar2. It was confirmed that EPD was significantly lower in the region Ar3. That is, with respect to the silicon ingot Ig1, it was confirmed that the EPD was lowered significantly after once rising according to the distance from the lower surface. As a result, the density of defects (first to third densities) that can become etch pits by etching processing in the cross sections of the first to third regions Ar1 to Ar3 increases in the order of the third density, the first density, and the second density. Confirmed that. On the other hand, about the silicon ingot which concerns on one reference example, it confirmed that the EPD showed the tendency to rise monotonously according to the distance from a lower surface. Therefore, in the silicon ingot Ig1 according to one specific example, it is estimated that the EPD of the third region Ar3 is significantly reduced due to the presence of the second region Ar2 having a high EPD. Then, when the first region Ar1 is formed and when the silicon ingot Ig1 is cooled, dislocation and strain propagation generated in the first region Ar1 are stopped in the second region Ar2, and the third region Ar3 It is presumed that this is a region with less crystallinity and excellent crystallinity.

<(1-5) Solar cell element>
The silicon substrate cut out from the silicon ingot Ig1 according to this embodiment described above can be used as a semiconductor substrate of the solar cell element 10.

  Here, the basic configuration of the solar cell element 10 will be described. As shown in FIGS. 22 to 24, the solar cell element 10 includes a light receiving surface (upper surface in FIG. 24) on which light is incident and a non-light receiving surface (lower surface in FIG. 24) that is the surface opposite to the light receiving surface 10a. ) 10b. This solar cell element 10 has a semiconductor substrate 1. The semiconductor substrate 1 includes a first semiconductor layer 1p which is a one-conductivity-type semiconductor layer, and a second semiconductor layer 1n which is a reverse-conductivity-type semiconductor layer provided on the light-receiving surface 10a side of the first semiconductor layer 1p. Have. An antireflection layer 2 is provided on the first main surface 1 a on the light receiving surface 10 a side of the semiconductor substrate 1. Further, the solar cell element 10 includes a first electrode 4 provided on the first main surface 1 a on the light receiving surface 10 a side of the semiconductor substrate 1 and a second main surface 1 b on the non-light receiving surface 10 b side of the semiconductor substrate 1. And a second electrode 5 provided.

  Next, a more specific configuration example of the solar cell element 10 will be described. First, a silicon substrate having one conductivity type (for example, p-type) is prepared as the semiconductor substrate 1. As the silicon substrate, the silicon ingot Ig1 manufactured by the method for manufacturing a silicon ingot according to the present invention was cut into a block having a desired shape, and then formed into a substrate shape by a cutting operation using a multi-wire saw device or the like, for example. Things are used. The thickness of the semiconductor substrate 1 may be, for example, 300 μm or less, and if it is 200 μm or less, the manufacturing cost of the solar cell element 10 can be reduced by effective use of resources.

For example, boron is used as an element serving as a dopant for changing the conductivity type of the silicon ingot to p-type. If the boron concentration in the silicon ingot is about 1 × 10 ¹⁶ to 1 × 10 ¹⁷ [atoms / cm ³ ], the specific resistance of the silicon substrate is about 0.2 to 2 Ω · cm. As a method for doping boron into the silicon substrate, for example, a method in which an appropriate amount of elemental boron element or an appropriate amount of raw silicon having a known boron concentration is mixed at the time of manufacturing the silicon ingot may be employed.

  When the semiconductor substrate 1 is a silicon substrate exhibiting p-type conductivity, impurities such as phosphorus are diffused into the surface layer portion on the first main surface 1a side of the semiconductor substrate 1 to form the second semiconductor layer 1n. obtain. The first semiconductor layer 1p and the second semiconductor layer 1n form a pn junction region.

  The antireflection layer 2 serves to reduce the reflectance of the light receiving surface 10a with respect to light in a desired wavelength region, and facilitate the absorption of light in the desired wavelength region in the semiconductor substrate 1. Thereby, the amount of carriers generated by photoelectric conversion in the semiconductor substrate 1 can be increased. As a material of the antireflection layer 2, for example, silicon nitride, titanium oxide, silicon oxide, or the like can be employed. By appropriately setting the thickness of the antireflection layer 2 depending on the material of the antireflection layer 2, it is only necessary to realize a condition (non-reflection condition) in which appropriate incident light is hardly reflected by the presence of the antireflection layer 2. For example, when the semiconductor substrate 1 is a silicon substrate, the refractive index of the antireflection layer 2 may be about 1.8 to 2.3, and the thickness of the antireflection layer 2 is about 500 to 1200 mm. Good.

A BSF (Back-Surface-Field) region 1Hp is provided on the second main surface 1b side of the semiconductor substrate 1. The BSF region 1Hp has a role of forming an internal electric field on the second main surface 1b side of the semiconductor substrate 1 and reducing carrier recombination in the vicinity of the second main surface 1b. Thereby, the fall of the photoelectric conversion efficiency in the solar cell element 10 can be reduced. The BSF region 1Hp has the same conductivity type as the first semiconductor layer 1p, and the concentration of majority carriers contained in the BSF region 1Hp is higher than the concentration of majority carriers contained in the first semiconductor layer 1p. When the semiconductor substrate 1 is p-type, for example, an element serving as a dopant such as boron or aluminum is diffused in the surface layer portion on the second main surface 1b side of the semiconductor substrate 1 to form the BSF region 1Hp. obtain. At this time, the concentration of the dopant in the BSF region 1Hp may be about 1 × 10 ^{18 to} 5 × 10 ²¹ atoms / cm ³ , for example.

  As shown in FIG. 22, the first electrode 4 has a first output extraction electrode 4a and a plurality of linear first current collecting electrodes 4b. At least a part of the first output extraction electrode 4a intersects the first collector electrode 4b. The line width of the 1st output extraction electrode 4a should just be about 1.3-2.5 mm, for example. On the other hand, the line width of the 1st current collection electrode 4b is narrower than the line width of the 1st output extraction electrode 4a, for example, should just be about 50-200 micrometers. In addition, the plurality of first current collecting electrodes 4b are arranged with an interval. This interval may be about 1.5 to 3 mm. Moreover, the thickness of the 1st electrode 4 should just be about 10-40 micrometers. The first electrode 4 may include a linear auxiliary electrode 4c that connects one end portions and the other end portions of the plurality of first current collecting electrodes 4b. For example, the line width of the auxiliary electrode 4c may be equal to the line width of the first current collecting electrode 4b. The 1st electrode 4 which has the said structure can be formed by baking, after apply | coating the silver paste to the area | region of the desired pattern on the 1st main surface 1a of the semiconductor substrate 1, for example. The silver paste may be generated by mixing, for example, silver powder, glass frit, organic vehicle, and the like. The silver paste application method may be, for example, a screen printing method.

  As shown in FIG. 23, the second electrode 5 has a second output extraction electrode 5a and a second collector electrode 5b. The thickness of the 2nd output extraction electrode 5a should just be about 10-30 micrometers, for example. The line width of the second output extraction electrode 5a may be about 1.3 to 7 mm. The second output extraction electrode 5a can be formed of the same material and manufacturing method as the first electrode 4 described above. For example, the silver paste can be formed by being applied to a desired pattern region on the second main surface 1b of the semiconductor substrate 1 and then firing. Moreover, the thickness of the 2nd current collection electrode 5b should just be about 15-50 micrometers. The second current collecting electrode 5b is formed on substantially the entire surface of the second main surface 1b of the semiconductor substrate 1 except for most of the region where the second output extraction electrode 5a is formed. The second current collecting electrode 5b can be formed, for example, by applying an aluminum paste to a region of a desired pattern on the second main surface 1b of the semiconductor substrate 1 and then baking it. The aluminum paste may be generated, for example, by mixing aluminum powder, glass frit, organic vehicle, and the like. The method for applying the aluminum paste may be, for example, a screen printing method.

<Specific Example of (1-6) Solar Cell Element>
Below, the specific example which further actualized the solar cell element 10 which concerns on this embodiment mentioned above is demonstrated.

  Here, the silicon ingot Ig1 according to the specific example and the silicon ingot according to the reference example are sliced along a plane parallel to the bottom surface of the silicon ingot, so that the silicon substrate corresponding to the semiconductor substrate 1 is obtained. Made. And the solar cell element 10 (refer FIGS. 22-24) which uses the silicon substrate obtained here as the semiconductor substrate 1 was produced by the following processes.

  Here, first, a silicon substrate was produced from a silicon ingot. At this time, a silicon substrate having a square board surface with a thickness of 200 μm and a side of 150 mm was manufactured using a wire saw device. Specifically, when the distance from the lower surface to the upper surface of the silicon ingot is 100 (solidification rate is 100%), the distance from the lower surface of the silicon ingot is 6.3, 12.5, 18.8,. .., 87.5 (solidification rate 6.3%, 12.5%, 18.8%,..., 87.5%) Eight silicon substrates according to one reference example were produced. At this time, the damage layer generated when the silicon ingot was cut in the surface layer of each silicon substrate was removed by etching with a sodium hydroxide solution.

Next, a texture structure with fine irregularities was formed on the first main surface 1a of the semiconductor substrate 1 by dry etching. Then, the second semiconductor layer 1n and the phosphor glass on the second semiconductor layer 1n were formed by vapor phase thermal diffusion using POCl ₃ as a diffusion source. At this time, the sheet resistance of the second semiconductor layer 1n was 70Ω / □. Further, after removing phosphorus glass by etching using a hydrofluoric acid solution and performing pn separation using a laser beam, a silicon nitride film as an antireflection layer 2 was formed on the first main surface 1a by PECVD.

  Thereafter, an aluminum paste was applied to the second main surface 1b of the semiconductor substrate 1 over substantially the entire surface, and this aluminum paste was baked to form the BSF region 1Hp and the second current collecting electrode 5b. Also, the first electrode 4 and the second output extraction electrode 5a are formed by applying a silver paste on the first main surface 1a and the second main surface 1b of the semiconductor substrate 1 and firing the silver paste. did. The solar cell element 10 was produced by the above.

  And the photoelectric conversion efficiency was measured with respect to each solar cell element 10 using the semiconductor substrate 1 obtained from each of the silicon ingot Ig1 which concerns on the said one specific example, and the silicon ingot which concerns on the said one reference example. This photoelectric conversion efficiency was measured according to JIS C 8913 (1998). The measurement result is shown in FIG. When the distance from the lower surface to the upper surface of the silicon ingot is 100 (solidification rate: 100%), the distance from the lower surface of the silicon ingot is 6.3, 12.5, 18.8,. The semiconductor substrate 1 of each part which is 5 was used. FIG. 25 shows the normalized photoelectric conversion efficiency for each solar cell element 10 using these semiconductor substrates 1. Here, the measurement result of the photoelectric conversion efficiency according to one specific example is indicated by a black circle, and the measurement result of the photoelectric conversion efficiency according to one reference example is indicated by a black rhombus. .

  As shown in FIG. 25, when the silicon substrate in the third region Ar3 of the solar cell element 10 according to one specific example is used, compared to the case where the silicon substrate in the solar cell element 10 according to one reference example is used. It was confirmed that the photoelectric conversion efficiency was increased. That is, it is presumed that the third region Ar3 is a region having few defects and excellent crystallinity, so that the photoelectric conversion efficiency is increased.

<(1-7) Summary>
As described above, in the method for manufacturing a silicon ingot according to an embodiment, when the initial solidified layer PS2 is formed and when the silicon ingot Ig1 is cooled, dislocations and strain are propagated from the first region Ar1 with high density of defects. It is stopped by the existing second region Ar2. For this reason, the third region Ar3 with few defects and excellent crystallinity can be formed on the initial solidified layer PS2. Therefore, a silicon ingot having a region with few defects and excellent crystallinity can be easily produced.

  In the method for manufacturing a silicon ingot according to an embodiment, dislocation and strain propagation from the first region Ar1 are present in at least one of carbon and nitrogen when the initial solidified layer PS2 is formed and when the silicon ingot Ig1 is cooled. Thus, the second region Ar2 where the defect density is increasing is stopped. For this reason, the third region Ar3 with few defects and excellent crystallinity can be formed on the initial solidified layer PS2. Therefore, a silicon ingot having a region with few defects and excellent crystallinity can be easily produced.

  Further, in the silicon ingot Ig1 according to the embodiment, when the silicon ingot Ig1 is manufactured, dislocation and strain propagation from the first region Ar1 are stopped in the second region Ar2 where defects exist at high density. It is done. For this reason, the third region Ar3 above the second region Ar2 can be a region with few defects and excellent crystallinity. Therefore, the silicon ingot Ig1 having a region with few defects and excellent crystallinity can be easily manufactured.

  Further, in the silicon ingot Ig1 according to the embodiment, when the silicon ingot Ig1 is manufactured, dislocation and strain propagation from the first region Ar1 increase in defect density due to the presence of carbon and / or nitrogen. Stopped in the second region Ar2. For this reason, the third region Ar3 above the second region Ar2 can be a region with few defects and excellent crystallinity. Therefore, the silicon ingot Ig1 having a region with few defects and excellent crystallinity can be easily manufactured.

<(2) Embodiment 2>
Next, a second embodiment different from the above-described first embodiment will be described.

<(2-1) Silicon Ingot Manufacturing Equipment>
Since the manufacturing apparatus is the same as that of the first embodiment, the description thereof is omitted.

<(2-2) Silicon Ingot Manufacturing Method>
As shown in FIG. 26, in the method of manufacturing a silicon ingot according to the present embodiment, when forming the first solidified layer in the step of preparing the mold and the second step (step Sp2) described in the first embodiment. Then, a fourth silicon melt containing a dopant is supplied into the mold, and a first solidified region in which the dopant concentration decreases as the solidification rate increases is formed in the first solidified layer. Further, in the third step (step Sp3) described in the first embodiment, the fifth silicon melt containing the dopant is supplied into the mold, and the dopant concentration increases as the solidification rate increases, so that the maximum dopant concentration is obtained. A second solidified region is formed in the second solidified layer.

  Through the above steps, a silicon ingot having a region with few defects such as dislocations and excellent crystallinity is manufactured. FIG. 26 shows an example in which the preparation step (step Sq1), the first solidified region forming step (step Sq2), and the second solidified region forming step (step Sq3) are sequentially performed from step Sq11 to step Sq34.

<(2-2-1) Preparation step>
In the preparation step, for example, as shown in FIGS. 4 and 5, the mold 121 and the crucible 111 are prepared. Here, two processes of steps Sq11 and Sq12 performed in order in the preparation process will be described.

  In step Sq11, the mold 121 is prepared. For example, as shown in FIG. 4, a release material layer Mr <b> 1 is formed by applying a release material to the inner wall surface of the mold 121. The presence of the release material layer Mr1 reduces the fusion of the silicon ingot to the inner wall of the mold 121 in the process of solidifying the silicon melt MS1. As the material of the release material layer Mr1, for example, any one of silicon nitride, silicon carbide, and silicon oxide or a mixture of two or more may be employed. The release material layer Mr1 can be formed, for example, by coating a slurry containing one or more of silicon nitride, silicon carbide, and silicon oxide on the inner wall of the mold 121 by coating or spraying. Here, the slurry is, for example, a powder of any one or a mixture of silicon nitride, silicon carbide, and silicon oxide mixed in a solution mainly containing an organic binder such as PVA and a solvent. Things can be formed by stirring.

  In step Sq12, the crucible 111 is prepared. For example, as shown in FIG. 5, raw material silicon PS <b> 1 that is polysilicon is introduced into the internal space 111 i of the crucible 111. At this time, for example, the raw material silicon PS1 may be filled from the lower region in the crucible 111 toward the upper region. Further, for example, an element that becomes a dopant in the silicon ingot may be contained in the raw material silicon PS1. Here, the raw material silicon PS1 may be a lump of polysilicon as a raw material of a silicon ingot, for example. The polysilicon lump may be a relatively fine block lump of silicon, for example. In the case where a p-type silicon ingot is manufactured, the dopant element may be, for example, boron or gallium. When an n-type silicon ingot is manufactured, the element serving as a dopant may be, for example, phosphorus.

  In addition, before the 1st solidification area | region formation process is started, it sets to the state by which the cooling plate 123 is not contact | abutted on the lower surface of the casting_mold | template holding | maintenance part 122. FIG.

<(2-2-2) First solidified region forming step>
In the first solidified region forming step, as shown in FIGS. 6 to 8, the silicon melt MS1 is supplied into the mold 121, and the silicon melt MS1 is solidified on the bottom 121b in the mold 121. A first solidified region is formed. Here, each process of step Sq21-Sq25 performed in order in a 1st solidification area | region formation process is demonstrated.

  In step Sq21, preheating of the mold 121 is started. For example, as shown in FIG. 6, the mold 121 may be preheated from 200 ° C. to 800 ° C. by the mold upper heater H2u and the lower heater H2l disposed above and to the side of the mold 121.

  In step Sq22, heating of the raw material silicon PS1 in the crucible 111 is started. For example, as shown in FIG. 6, the raw silicon PS1 has a temperature range of 1414 ° C. or higher and 1550 ° C. or lower exceeding the melting point by the crucible upper heater H1u and the side heater H1s disposed above and laterally of the crucible 111 Until it melts gradually. At this time, since the raw material silicon PS1 in the crucible 111 is heated from the crucible upper heater H1u, the side heater H1s, and the portion disposed in the vicinity of the mold upper heater H2u disposed above the mold 121, these The raw material silicon PS1 disposed in the vicinity of the heater is easily melted.

  Here, heating of the raw material silicon PS1 in the crucible 111 is started after the preheating of the mold 121 is started, but the present invention is not limited to this. For example, the preheating of the mold 121 and the heating of the raw silicon PS1 in the crucible 111 may be started simultaneously, or after the heating of the raw silicon PS1 in the crucible 111 is started, the preheating of the mold 121 is started. May be.

  In step Sq23, the silicon melt MS1 is supplied from the crucible 111 into the mold 121. At this time, the supply of the silicon melt MS1 from the crucible 111 into the mold 121 may be continuous or intermittent. Further, the timing of the supply may be controlled by an external control means (control supply), or may be supplied by natural falling sequentially from the melted silicon without being controlled (natural supply). Regardless of the supply method, by appropriately setting the preheating temperature in step Sq21 and the amount of melt supplied, it is possible to create a situation where the solidification rate is equal to or higher than the rising rate of the upper surface of silicon supplied into the mold. Yes (step Sq24). In other words, the solidification rate exceeds the rising speed of the melt surface by supplying the silicon melt MS1 from the crucible 111 into the mold 121. Thereby, a 1st solidification area | region can be formed easily.

  Note that the continuous supply of the silicon melt MS1 means that the supply of the silicon melt MS1 occurs almost without interruption. Further, the intermittent supply of the silicon melt MS1 means that the supply and interruption of the supply of the silicon melt MS1 occur at irregular timings.

  For example, as shown in FIG. 7, the silicon melt MS1 is intermittently supplied into the mold 121 through the lower opening 111bo every time the raw material silicon PS1 is melted in the crucible 111. It can be realized by being supplied. Here, for example, in the crucible 111, the raw material silicon PS1 disposed in the vicinity of any of the crucible upper heater H1u, the side heater H1s, and the mold upper heater H2u disposed above the mold 121 is the earliest. Since they are melted, each time they are melted, the silicon melt MS1 can be supplied into the mold 121 through the lower opening 111bo.

  For example, as shown in FIG. 14, the silicon melt MS1 is continuously supplied after the raw material silicon PS1 is melted in the crucible 111 with the lower opening 111bo closed by a supply control means (not shown). This can be realized by opening the lower opening 111bo by control means (not shown) and supplying the silicon melt MS1 into the mold 121 via the lower opening 111bo. The supply control means may be a valve provided in the lower opening 111bo, or by controlling the temperature of each heater, the raw silicon PS1 that closes the lower opening 111bo is melted last, and the raw silicon that closes the lower opening 111bo The silicon melt MS1 in the crucible 111 may be supplied into the mold 121 at the same time as PS1 is dissolved.

  In step Sq25, the silicon melt MS1 supplied into the mold 121 in step Sq23 is solidified to form a first solidified region on the bottom 121b in the mold 121. Here, as shown in FIG. 8, the first solidified region is formed so as to cover the bottom 121b in the mold 121 by rapidly solidifying the silicon melt MS1 that covers the bottom 121b in the mold 121. That's fine.

  In the first solidified region, the solidified region is formed so that the dopant concentration decreases as the solidification rate increases. Here, in order to form the first solidified region, it rapidly solidifies under the condition that the solidification rate of the silicon melt MS1 supplied into the mold 121 is equal to or higher than the rising rate of the upper surface of the silicon supplied into the mold 121. You can do it. Hereinafter, the relationship between the solidification rate and the dopant concentration will be described. In the case of solidification in a general equilibrium state, impurities in the silicon melt MS1 are taken into the silicon ingot according to a certain segregation coefficient. The segregation coefficient is a ratio between the impurity concentration (Cl) in the melt and the impurity concentration (Cs) in the crystal at the solid-liquid interface when the crystal is solidified from the melt, and is expressed by k0 = Cs / Cl. For example, the segregation coefficient of boron (B) used as a dopant in a silicon ingot is 0.8 and the segregation coefficient of phosphorus (P) is 0.35, which is smaller than 1 (the dopant concentration in the crystal at the solid-liquid interface is in the melt) Therefore, as the solidification progresses in the equilibrium solidification state (the solidification rate increases), the concentration of boron and phosphorus in the melt increases, and the concentration of the dopant in the silicon ingot proceeds ( It increases as the solidification rate increases).

  On the other hand, when the solidification rate is higher than the rising rate of the upper surface of silicon supplied into the mold, the segregation coefficient approaches 1, and the dopant concentration in the silicon ingot is almost equal to the dopant concentration in the silicon melt MS1. Become. For example, in step Sq21, the solidification rate can be adjusted by controlling the temperatures of the bottom 121b and the side 121s of the mold 121 with a heater. The melt surface rising speed can be adjusted by controlling the supply amount of the melt per unit time by, for example, changing the diameter of the lower opening in step Sq23. As the solidification progresses (solidification rate increases), the segregation coefficient approaches a normal equilibrium state (0.8 for boron and 0.35 for phosphorus) by reducing the solidification rate. A first solidified region having an arbitrary thickness in which the doping concentration decreases as the solidification rate increases can be formed. Further, in the first solidified region thus produced, not only the dopant but also other impurity elements having a segregation coefficient smaller than 1, such as iron (Fe), copper (Cu), carbon (C), nitrogen (N ), Oxygen (O) and the like also decrease as the solidification rate increases.

  As another means for forming the first solidified region, there is a method of decreasing the dopant concentration in the silicon melt MS1 supplied to the mold 121 as the solidification progresses. For example, when the raw material silicon PS1 is filled in the crucible 111, the raw material silicon PS1 containing a high concentration dopant is placed in a region near a heater that is relatively easy to melt, and a lower concentration dopant is placed in another region. In a state where the raw material silicon PS1 containing is placed, melting of the raw material silicon PS1 is started, and the molten silicon is supplied to the mold 121 in order.

  Thus, the defect density in an ingot can be reduced by providing a 1st solidification area | region in the solidification initial stage (namely, ingot bottom part). The reasons why the defect density is reduced are listed below.

  First, mechanical strength and yield strength increase with increasing dopant concentration (boron, phosphorus, etc.) at the bottom, and as a result, the occurrence of dislocations due to heat shock is suppressed. If the dislocations at the bottom decrease, the dislocations at the top that take over it will also decrease.

  Boron and iron are known to form a B-Fe bond, and boron contamination (gettering) during solidification of the ingot causes Fe contamination diffusion from the release material on the bottom and bottom side surfaces. As a result, the impurity concentration in the ingot is reduced. Further, it is conceivable that dislocations move, disappear, and decrease during iron gettering by boron, and there is a possibility that dislocation reduction occurs during iron gettering.

  Also, by increasing the growth rate of the first solidified region, the growth rate in the direction parallel to the bottom surface becomes relatively smaller than the direction perpendicular to the bottom surface, and the crystal grain size and stress in the direction parallel to the bottom surface are reduced. It becomes small and the strain relaxation effect by a grain boundary becomes large and it becomes difficult to produce defects, such as a dislocation.

  In addition, since the temperature in the mold at the initial stage of growth is lower than usual in order to increase the growth rate, latent heat during crystal growth is easily lost, and since there is little growth stress, defects such as dislocations are less likely to occur.

  Further, in silicon containing a high dopant concentration, misfit dislocations are generated due to the lattice constant difference between silicon atoms and dopant atoms, and the misfit dislocations block the propagation of dislocations generated by heat shock.

  Thus, by reducing the dislocations at the bottom of the ingot, the total dislocations including the upper portion of the ingot can be reduced, so that a high-quality silicon ingot with few dislocations can be obtained.

  Note that crystal defects such as dislocations can be observed as etch pits using a microscope by etching treatment in each cross section of the silicon ingot. For example, the density of etch pits (EPD) derived by dividing the number of etch pits measured in the observation target region by the area of the observation target region may be the defect density. The etching process may be, for example, a process in which a silicon plate (silicon plate) is sequentially subjected to mirror finishing etching (mirror etching) and etching (selective etching) for revealing crystal defects.

  More specifically, the etching process may be, for example, a process in which mirror etching and selective etching are sequentially performed on a silicon plate obtained by slicing along a XZ plane from a silicon ingot with a band saw. The mirror etching may be, for example, a process in which a silicon plate is sequentially immersed in a hydrofluoric acid solution for 180 seconds, washed with water, immersed in a hydrofluoric acid aqueous solution for 30 seconds, washed with water, and dried. In addition, the hydrofluoric acid solution should just be produced | generated by mixing 70 mass% nitric acid and 50 mass% hydrofluoric acid in the ratio of 7: 2, for example. The hydrofluoric acid aqueous solution may be generated, for example, by mixing pure water and 50% by mass hydrofluoric acid at a ratio of 20: 1. Further, the selective etching may be, for example, a process in which a silicon plate is sequentially subjected to 5-minute immersion in a selective etching solution described in JIS standard H0609, water washing, and drying. In the selective etching solution described in JIS standard H0609, for example, 70% by mass nitric acid, 99% by mass acetic acid, 50% by mass hydrofluoric acid and pure water are mixed at a ratio of 1: 12.7: 3: 3.7. Any solution may be used.

  Further, in this step Sq25, if there are a lot of carbon and nitrogen other than the dopant atoms in the melt, the carbon and nitrogen taken into the ingot have the same role as the crystal defect reducing effect by the dopant. Even better.

  In addition, the atomic density of carbon and nitrogen is measured by SIMS for each cross section of the first solidified region and the second solidified region, for example.

<(2-2-3) Second solidified region forming step>
When the supply of the melt is further continued, the solidification rate decreases as the ingot grows, and the solidification rate becomes lower than the rising rate of the upper surface of the silicon supplied into the mold (step Sq31). Thereby, as shown in FIG. 14, in the mold 121, the silicon melt MS1 is stored on the first solidified region, and the second solidified region is formed (step Sq32). In the second solidification region, the dopant concentration increases as the solidification rate increases as in the conventional ingot. Here, the supply of the silicon melt MS1 from the crucible 111 into the mold 121 may be continuous or intermittent. However, if the silicon melt MS1 is continuously supplied from the crucible 111 into the mold 121, the silicon melt MS1 is rapidly supplied into the mold 121. As a result, the silicon ingot can be manufactured quickly.

  In step Sq33, the supply of the silicon melt MS1 from the crucible 111 to the mold 121 is terminated.

  Further, in the second solidified region forming step, the cooling plate 123 is brought into contact with the lower surface of the mold holding unit 122. Thereby, heat removal from the silicon melt MS1 in the mold 121 to the cooling plate 123 via the mold holding unit 122 is started. Here, for example, as shown in FIG. 15, in the state where the silicon melt MS1 is stored on the first solidified region, the cooling of the silicon melt MS1 from the bottom 121b side by the cooling plate 123 is started. Note that the timing when the cooling plate 123 is brought into contact with the lower surface of the mold holding part 122 is the timing after all the raw material silicon PS1 in the crucible 111 is melted and supplied as the silicon melt MS1 into the mold 121. Good.

  In the second solidified region forming step, the silicon melt MS1 in the mold 121 is unidirectionally solidified upward from the first solidified region. Here, for example, as shown in FIG. 16, unidirectional solidification of the silicon melt MS1 in the mold 121 proceeds by cooling the silicon melt MS1 in the mold 121 from the bottom 121b side. Thereby, a second solidified region is formed on the first solidified region. Since crystal defects such as dislocations in the second solidified region are formed by taking over the crystal defects in the first solidified region, by reducing the crystal defects in the first solidified region, in the second solidified region including the upper portion of the ingot. In addition, a high-quality silicon ingot with few crystal defects can be obtained.

  Here, for example, the outputs of the upper mold heater H2u and the lower heater H2l arranged above and on the side of the mold 121 are controlled according to the temperature detected by the temperature measuring sections CH1, CH2, etc. in the manufacturing apparatus 100. The For example, the temperature in the vicinity of the mold upper heater H2u and the lower heater H2l only needs to be maintained in the vicinity of the melting point of silicon. Thereby, silicon crystal growth from the side of the mold 121 is difficult to occur, and silicon crystal growth in the + Z direction as the upper side is likely to occur.

  Then, the unidirectional solidification of the silicon melt MS1 proceeds slowly, whereby a silicon ingot is manufactured in the mold 121, and when the silicon melt MS1 is completely solidified, the formation of the silicon ingot is finished (step Sq34).

  The density of defects in the second solidified region is confirmed by the same method as that for the first solidified region.

  So far, the method of forming a silicon ingot having the first solidified region and the second solidified region has been described. However, the method can be appropriately changed without depending on the above method as long as it is within the scope of the present invention. For example, even if the formation of the first solidified region is started while the cooling plate 123 is in contact with the cooling plate 123 and the contact state of the cooling plate 123 is released, the heat removal amount can be adjusted to adjust the solidification rate. Good. Also, for example, in the first solidified region forming step, the melt surface is supplied intermittently to reduce the rising speed of the melt surface, and in the second solidified region forming step, the melt surface is supplied continuously. You may increase the ascending speed.

<(2-3) Summary>
As described above, in the present embodiment, a step of preparing a mold and a silicon melt containing a dopant in the mold are supplied to form a first solidified region in which the dopant concentration decreases as the solidification rate increases. And a step of further supplying a silicon melt containing a dopant in the template to form a second solidified region having a maximum dopant concentration by increasing the dopant concentration as the solidification rate increases. Further, in the step of forming the first solidified region, the solidification rate of the silicon melt in the mold is set to be equal to or higher than the rising rate of the upper surface of silicon supplied into the mold. Further, in the step of forming the second solidified region, the solidification rate of the silicon melt in the mold is made smaller than the rising rate of the upper surface of silicon supplied into the mold. Further, in the step of preparing the mold, a release material layer containing at least one of carbon and nitrogen is formed on the inner wall of the mold.

  According to this embodiment, dislocations near the bottom of the ingot and dislocations propagating from the vicinity of the bottom to the upper direction can be reduced, so that the dislocation density of the entire ingot is small and suitable for the production of a solar cell element with high conversion efficiency. A crystal silicon ingot can be provided.

<(2-4) Silicon ingot>
The polycrystalline silicon ingot according to the present embodiment has a region in which the specific resistance value increases and increases as the solidification rate increases, in the direction in which the solidification rate increases. The first portion has a tendency that the specific resistance value increases with the increase in the number, and the second portion has a minimum specific resistance value with a tendency that the specific resistance value decreases as the solidification rate increases. In contrast, the conventional polycrystalline silicon ingot has a specific resistance value corresponding to the segregation coefficient of the dopant as the solidification rate increases. For example, when a dopant having a segregation coefficient of less than 1 is used, the bottom (solidification) When the dopant having a segregation coefficient larger than 1 is used, the specific resistance is maximum at the upper portion (solidification rate 100%).

  The reason why the specific resistance value increases and becomes the maximum as the solidification rate increases is that a region containing a high concentration of dopant is formed at the initial stage of solidification (that is, the bottom of the ingot). Thus, crystal defects such as dislocations in the ingot can be reduced.

  Crystal defects such as dislocations can be observed by observation using a microscope as etch pits by the above-described etching treatment in each cross section of the silicon ingot.

  Note that the solidification rate at which the specific resistance value is maximum in the first solidified region and the second solidified region may be greater than 0% and 30% or less, and more preferably 12% or greater and 24% or less. This is because, if the first solidified region is thin, the dislocation reduction effect in the second solidified region is insufficient, and if the first solidified region is thick, the concentration of impurities such as iron increases and the dislocation increases due to supercooling. This is because the overall device characteristics deteriorate.

The specific resistance value of the ingot may be, for example, from 0.5 Ωcm to 2.1 Ω · cm. A relational expression between the specific resistance value ρb and the carrier concentration n is represented by ρb = 1 / (q · μ · n). Here, q is the charge of the electron, 1.60 × 10 ⁻¹⁹ C, μ is the majority carrier mobility, and is about 1200 cm ² / V / s for the N-type substrate and about 420 cm ² / P for the P-type substrate at room temperature. Since the resistivity is about V / s, when boron is used as the dopant when the specific resistance value is in the above range, the dopant concentration is 3.2 × 10 ¹⁶ atoms / cm ³ or more and 6.5 × 10 ¹⁵ atoms / cm ³ or less. . If the specific resistance value is too large (dopant concentration is too high), the conversion efficiency of the solar cell element is lowered, for example, the open circuit voltage of the solar cell element is lowered due to an increase in dark current due to an increase in minority carriers. Moreover, if the specific resistance value is too small (dopant concentration is too high), the conversion efficiency of the solar cell element decreases due to a decrease in short circuit current due to an increase in carrier scattering by dopant atoms, a decrease in open circuit voltage due to a decrease in BSF effect, etc. To do.

  Further, as described above, if a large amount of carbon, nitrogen, or the like is present in the first solidified region, that is, the sum of the atomic density of carbon and the atomic density of nitrogen in the first solidified region is the carbon in the second solidified region. If it is larger than the sum of the atomic density of nitrogen and the atomic density of nitrogen, carbon and nitrogen incorporated in the ingot can play the same role as the crystal defect reducing effect by the dopant described above.

  Note that the atomic density of carbon and nitrogen is measured by SIMS, for example, for each cross section of the first and second solidified regions PS2 and PS3 as described above.

<(2-5) Solar cell element>
The silicon substrate cut out from the silicon ingot according to this embodiment described above can be used as a semiconductor substrate of the solar cell element 10.

  Here, the basic configuration of the solar cell element 10 will be described. As shown in FIGS. 22 to 24, the solar cell element 10 includes a light receiving surface (upper surface in FIG. 24) on which light is incident and a non-light receiving surface (lower surface in FIG. 24) that is the surface opposite to the light receiving surface 10a. ) 10b. This solar cell element 10 has a semiconductor substrate 1. The semiconductor substrate 1 includes a first semiconductor layer 1p which is a one-conductivity-type semiconductor layer, and a second semiconductor layer 1n which is a reverse-conductivity-type semiconductor layer provided on the light-receiving surface 10a side of the first semiconductor layer 1p. Have. An antireflection layer 2 is provided on the first main surface 1 a on the light receiving surface 10 a side of the semiconductor substrate 1. Further, the solar cell element 10 includes a first electrode 4 provided on the first main surface 1 a on the light receiving surface 10 a side of the semiconductor substrate 1 and a second main surface 1 b on the non-light receiving surface 10 b side of the semiconductor substrate 1. And a second electrode 5 provided.

  Next, a more specific configuration example of the solar cell element 10 will be described. First, a silicon substrate having one conductivity type (for example, p-type) is prepared as the semiconductor substrate 1. As a silicon substrate, after the silicon ingot manufactured by the method for manufacturing a silicon ingot according to the present invention is cut into blocks having a desired shape, the substrate is formed into a substrate shape by using a multi-wire saw device or the like to make a thin slice. Can be used. The thickness of the semiconductor substrate 1 may be, for example, 300 μm or less, and if it is 200 μm or less, the manufacturing cost of the solar cell element 10 can be reduced by effective use of resources.

For example, boron is used as an element serving as a dopant for making the conductivity type of the silicon ingot p-type. If the boron concentration in the silicon ingot is about 1 × 10 ¹⁶ to 1 × 10 ¹⁷ [atoms / cm ³ ], the specific resistance of the silicon substrate is about 0.2 to 2 Ω · cm. As a method for doping boron into the silicon substrate, for example, a method in which an appropriate amount of elemental boron element or an appropriate amount of raw silicon having a known boron concentration is mixed at the time of manufacturing the silicon ingot may be employed.

  When the semiconductor substrate 1 is a silicon substrate exhibiting p-type conductivity, impurities such as phosphorus are diffused into the surface layer portion on the first main surface 1a side of the semiconductor substrate 1 to form the second semiconductor layer 1n. obtain. The first semiconductor layer 1p and the second semiconductor layer 1n form a pn junction region.

  The antireflection layer 2 serves to reduce the reflectance of the light receiving surface 10a with respect to light in a desired wavelength region, and facilitate the absorption of light in the desired wavelength region in the semiconductor substrate 1. Thereby, the amount of carriers generated by photoelectric conversion in the semiconductor substrate 1 can be increased. As a material of the antireflection layer 2, for example, silicon nitride, titanium oxide, silicon oxide, or the like can be employed. By appropriately setting the thickness of the antireflection layer 2 depending on the material of the antireflection layer 2, it is only necessary to realize a condition (non-reflection condition) in which appropriate incident light is hardly reflected by the presence of the antireflection layer 2. For example, when the semiconductor substrate 1 is a silicon substrate, the refractive index of the antireflection layer 2 may be about 1.8 to 2.3, and the thickness of the antireflection layer 2 is about 500 to 1200 mm. Good.

A BSF (Back-Surface-Field) region 1Hp is provided on the second main surface 1b side of the semiconductor substrate 1. The BSF region 1Hp has a role of forming an internal electric field on the second main surface 1b side of the semiconductor substrate 1 and reducing carrier recombination in the vicinity of the second main surface 1b. Thereby, the fall of the photoelectric conversion efficiency in the solar cell element 10 can be reduced. The BSF region 1Hp has the same conductivity type as the first semiconductor layer 1p, and the concentration of majority carriers contained in the BSF region 1Hp is higher than the concentration of majority carriers contained in the first semiconductor layer 1p. When the semiconductor substrate 1 is p-type, for example, an element serving as a dopant such as boron or aluminum is diffused in the surface layer portion on the second main surface 1b side of the semiconductor substrate 1 to form the BSF region 1Hp. obtain. At this time, the concentration of the dopant in the BSF region 1Hp may be about 1 × 10 ^{18 to} 5 × 10 ²¹ atoms / cm ³ , for example.

  As shown in FIG. 22, the first electrode 4 has a first output extraction electrode 4a and a plurality of linear first current collecting electrodes 4b. At least a part of the first output extraction electrode 4a intersects the first collector electrode 4b. The line width of the 1st output extraction electrode 4a should just be about 1.3-2.5 mm, for example. On the other hand, the line width of the 1st current collection electrode 4b is narrower than the line width of the 1st output extraction electrode 4a, for example, should just be about 50-200 micrometers. In addition, the plurality of first current collecting electrodes 4b are arranged with an interval. This interval may be about 1.5 to 3 mm. Moreover, the thickness of the 1st electrode 4 should just be about 10-40 micrometers. The first electrode 4 may include a linear auxiliary electrode 4c that connects one end portions and the other end portions of the plurality of first current collecting electrodes 4b. For example, the line width of the auxiliary electrode 4c may be equal to the line width of the first current collecting electrode 4b. The 1st electrode 4 which has the said structure can be formed by baking, after apply | coating the silver paste to the area | region of the desired pattern on the 1st main surface 1a of the semiconductor substrate 1, for example. The silver paste may be generated by mixing, for example, silver powder, glass frit, organic vehicle, and the like. The silver paste application method may be, for example, a screen printing method.

  As shown in FIG. 23, the second electrode 5 has a second output extraction electrode 5a and a second collector electrode 5b. The thickness of the 2nd output extraction electrode 5a should just be about 10-30 micrometers, for example. The line width of the second output extraction electrode 5a may be about 1.3 to 7 mm. The second output extraction electrode 5a can be formed of the same material and manufacturing method as the first electrode 4 described above. For example, the silver paste can be formed by being applied to a desired pattern region on the second main surface 1b of the semiconductor substrate 1 and then firing. Moreover, the thickness of the 2nd current collection electrode 5b should just be about 15-50 micrometers. The second current collecting electrode 5b is formed on substantially the entire surface of the second main surface 1b of the semiconductor substrate 1 except for most of the region where the second output extraction electrode 5a is formed. The second current collecting electrode 5b can be formed, for example, by applying an aluminum paste to a region of a desired pattern on the second main surface 1b of the semiconductor substrate 1 and then baking it. The aluminum paste may be generated, for example, by mixing aluminum powder, glass frit, organic vehicle, and the like. The method for applying the aluminum paste may be, for example, a screen printing method.

<Specific example of (2-6) silicon ingot>
<(2-6-1) Production of silicon ingot>
Here, using the silicon ingot manufacturing apparatus 100 shown in FIG. 1 and the silicon ingot manufacturing method shown in FIG. 3 to FIG. A silicon ingot according to the above was manufactured. Under conditions 1 to 4, the area of the lower opening 111bo of the crucible 111 was changed in order to adjust the supply speed of the silicon melt MS1. Further, the preheating temperature of the mold 121 was changed in order to adjust the solidification rate at the initial casting. FIG. 27 shows the relationship between the solidification rate and specific resistance value of the obtained ingot, and FIG. 28 shows the relationship between the solidification rate and dopant concentration in the ingot. Further, Table 1 shows the solidification rate (the range of the first solidification region) at which the specific resistance value of each ingot is maximum, as read from FIG.

  In the silicon ingot manufacturing apparatus 100, quartz glass is used as a material for the crucible 111. The mold 121 was a carbon fiber reinforced carbon composite material (CCM) mold having a side wall 121s and a bottom 121b. One side of the bottom surface of the mold 121 was 345 mm square.

  And the mold release material layer Mr1 was formed by apply | coating the mold release material to the inner wall face of the casting_mold | template 121. FIG. Here, a release material in which a silicon nitride powder, a silicon oxide powder, and a PVA aqueous solution as a binder solution were mixed to form a slurry was used.

  Next, a large number of raw material silicon PS1 having a total amount of about 90 kg was put into the crucible 111. At this time, the raw material silicon PS1 was mixed with boron as an element serving as a dopant.

  Next, preheating of the mold 121 was started by the mold upper heater H2u and the lower heater H2l arranged around the mold 121. By this preheating, the mold bottom 121b was heated to 400 ° C to 600 ° C. The lower the preheating temperature, the higher the solidification rate at the initial stage of solidification. That is, since the preheating temperature at the bottom of the mold is Condition 1> Condition 4> Condition 2> Condition 3, the solidification rate in the initial stage of solidification is as follows: Condition 1 <Condition 4 <Condition 2 <Condition 3 is satisfied.

  Moreover, the heating of the raw material silicon PS1 disposed in the crucible 111 was started by the crucible upper heater H1u and the side heater H1s arranged around the crucible 111. As a result, the raw material silicon PS1 was heated to a temperature range of 1414 ° C. or higher exceeding the melting point and 1550 ° C. or lower and gradually melted. At this time, a portion of the raw material silicon PS1 in the crucible 111 disposed near the lower opening 111bo was also heated by the mold upper heater H2u disposed above the mold 121.

  Next, after all the raw material silicon PS1 in the crucible 111 was dissolved, the supply of the silicon melt MS1 into the mold 121 was started. Conditions 1 to 3 and condition 4 are different in the melt supply amount per unit time supplied to the mold 121 because the diameter of the lower opening 111bo of the crucible 111 is different. That is, in conditions 1 to 3, the diameter of the lower opening 111bo is smaller than in condition 4, so the amount of melt supplied per unit time is small, and the rate of rise of the melt surface is small.

  According to the manufacturing conditions, in conditions 1 to 3, a first solidified region in which the dopant concentration decreases as the solidification rate increases is formed. The thickness of the first solidification region varies depending on the preheating temperature, that is, the solidification rate at the initial stage of solidification, and the solidification rates at which the specific resistance value is maximized are 12%, 18%, and 24%, respectively, in each of conditions 1 to 3. It was.

  If the supply of the silicon melt MS1 from the crucible 111 into the mold 121 and the unidirectional solidification are continued, the solidification speed decreases with the progress of solidification, and finally the lowering speed of the upper surface of silicon supplied into the mold is reduced. When the upper surface of the ingot being solidified was completely covered with the melt, the formation of the second solidified region began.

  Thereafter, the supply of the silicon melt MS1 to the mold 121 is finished, the cooling plate 123 is brought into contact with the lower surface of the mold holding part 122, and the silicon ingot MS1 in the mold 121 is cooled from the bottom 121b side while cooling the silicon ingot. Manufactured. At this time, heating was performed using a mold upper heater H2u and a lower heater H2l. Thus, unidirectional solidification of the silicon melt MS1 was performed, and then a p-type silicon ingot was manufactured in the mold 121 by air cooling.

<(2-6-2) Analysis and evaluation of silicon ingot>
The obtained silicon ingot was cut into a plurality of blocks while cutting the end region using a band saw. From one of the blocks, an evaluation silicon plate having a thickness of about 10 mm was produced using a band saw. Mirror etching and crystal for mirror finish on the silicon plate of the lower part (solidification rate 15%), middle part (solidification rate 50%) and upper part (solidification rate 80%) according to the solidification rate among the produced silicon plates Selective etching was performed to reveal defects.

  In mirror etching, the silicon plate was sequentially immersed in a hydrofluoric acid solution for 180 seconds, washed with water, immersed in a hydrofluoric acid aqueous solution for 30 seconds, washed with water, and dried. Here, the hydrofluoric acid solution was produced by mixing 70 mass% nitric acid and 50 mass% hydrofluoric acid in a ratio of 7: 2. The hydrofluoric acid aqueous solution was produced by mixing pure water and 50% by mass hydrofluoric acid in a ratio of 20: 1. In the selective etching, a selective etching solution described in JIS standard H0609, that is, 70% by mass nitric acid, 99% by mass acetic acid, 50% by mass hydrofluoric acid, and pure water is applied to the silicon plate at 1: 12.7: A 5-minute immersion in a solution mixed at a ratio of 3: 3.7, washing with water, and drying were sequentially performed. Note that mirror etching and selective etching described below were all performed under substantially the same conditions.

  Thereafter, the etched surface of the silicon plate was photographed and EPD measurement was performed. In the EPD measurement, for each silicon plate, a rectangular region at approximately 15 equidistant positions in a substantially central portion in the Y direction of the silicon plate is observed with an SEM, and the number of etch pits is measured. The EPD was calculated by dividing by. The rectangular area has a side of 250 μm. Table 2 shows the measurement results (each of the lower part, the middle part, and the upper part) and numerical values obtained by normalizing the average value of EPD in all regions under each condition with the average value of all regions in Condition 4 as 1. From Table 2, it was found that in the ingots according to the conditions 1 to 3, the EPD value was smaller than that of the condition 4 in all regions. As described above, this is presumably because the dislocation density in the ingot was reduced by the high concentration of boron contained in the initial growth stage (that is, the bottom of the ingot) of the first solidified region.

Table 3 shows the atomic concentrations of iron, carbon, oxygen and nitrogen under conditions 1 and 4. For the silicon plate subjected to the selective etching, the atomic concentration of iron was measured by inductively coupled plasma mass spectrometry (ICP-MS), and the atomic concentrations of carbon, oxygen, and nitrogen were measured by SIMS. The measurement position was set to a position from 0 to about 20 mm from the bottom of the ingot in the Z direction (SIMS measured five points at approximately equal intervals in the Z direction to calculate an average value). In Table 3, “AE + B” indicates “A × 10 ^{+ B} ”.

  As shown in Table 3, gettering of iron by boron occurs during the formation of the ingot due to the formation of the first solidified region carbon having a high boron concentration under the condition 1 and Fe—B. It is possible that a bond has been formed. Moreover, in the condition 1, the nitrogen concentration is also high, and it is considered that nitrogen contributed to the reduction of dislocations like boron.

<(2-6-3) Production of silicon substrate and solar cell element>
The other blocks were cut into a plurality of silicon substrates using a multi-wire saw device. The silicon substrate thus obtained was measured for specific resistance by a four-probe method, and a solar cell element was produced using the silicon substrate.

  Here, the silicon ingot according to the specific example and the silicon ingot according to the reference example were sliced along a plane parallel to the bottom surface of the silicon ingot to produce a silicon substrate corresponding to the semiconductor substrate 1. And the solar cell element 10 (refer FIGS. 22-24) which uses the obtained silicon substrate as the semiconductor substrate 1 was produced according to the following processes.

  First, a silicon substrate was produced by slicing a silicon ingot. At this time, a silicon substrate having a square board surface with a thickness of about 200 μm and a side of about 150 mm was produced by a wire saw device.

  Next, the damage layer generated at the time of cutting the silicon ingot in the surface layer of each silicon substrate was removed by etching with a sodium hydroxide solution.

Next, a texture structure with fine irregularities was formed on the first main surface 1a of the semiconductor substrate 1 by dry etching. Then, the second semiconductor layer 1n and the phosphor glass on the second semiconductor layer 1n were formed by a vapor phase thermal diffusion method using POCl ₃ as a diffusion source. At this time, the sheet resistance of the second semiconductor layer 1n was 70Ω / □. Further, after removing phosphorous glass by etching with a hydrofluoric acid solution and performing pn separation with a laser beam, a silicon nitride film as an antireflection layer 2 was formed on the first main surface 1a by PECVD.

  After that, the BSF region 1Hp and the second current collecting electrode 5b were formed by applying an aluminum paste to the second main surface 1b of the semiconductor substrate 1 over substantially the entire surface and firing the aluminum paste. Also, the first electrode 4 and the second output extraction electrode 5a are formed by applying a silver paste on the first main surface 1a and the second main surface 1b of the semiconductor substrate 1 and firing the silver paste. did. Thereby, the solar cell element 10 was produced.

  The solar cell element measured the photoelectric conversion efficiency based on JIS C 8913. The measurement results are averaged for each of the lower (solidification rate 0% to 33%), middle (solidification rate 33 to 67%), and upper (solidification rate 67% to 100%) regions according to the size of the solidification rate. Table 2 shows numerical values normalized with the photoelectric conversion efficiency average value of all regions in Condition 4 as 1. It was found that the ingots according to the conditions 1 to 3 have higher photoelectric conversion efficiency than the condition 4 in all regions.

  FIG. 27 shows the relationship between the solidification rate of a silicon ingot according to a specific example and the normalized specific resistance (ρb value). The specific resistance distribution corresponds to the concentration distribution of boron as a dopant. As shown in FIG. 27, for the silicon ingot according to condition 4, the region where the specific resistance value is maximum is formed at the end where the solidification rate is 0%, and the specific resistance value decreases monotonously as the solidification rate increases. ing. On the other hand, for the silicon ingots according to the conditions 1 to 3, since the region where the specific resistance value is maximum is not in the end portion but in the ingot, the specific resistance value tends to increase as the solidification rate increases. It has been found that the first solidified region has a first solidified region, and the second solidified region has a specific resistance value that tends to decrease as the solidification rate increases.

  From these results, as shown in FIG. 28, since the first solidified region is formed by rapid solidification of the silicon melt MS1, the segregation coefficient approaches 1, and the dopant in the silicon ingot It is presumed that the concentration of certain boron has increased and the ρb value has decreased. As the solidification progresses (the solidification rate increases), the solidification rate decreases, so the segregation coefficient approaches the normal equilibrium state (0.8), so that the doping concentration decreases as the solidification rate increases. One solidified region is formed.

  If the supply of the melt is further continued, the solidification rate decreases with the growth of the ingot, and the solidification rate becomes lower than the rise rate of the melt surface due to the supply of the melt (step Sq31). Thereby, in the casting_mold | template 121, it will be in the state by which the silicon melt MS1 was stored on the 1st solidification area | region, and formation of a 2nd solidification area | region will be started (step Sq32). It was found from FIGS. 13 and 14 that, in the second solidified region, the dopant concentration increases and the specific resistance value monotonously decreases as the solidification rate increases as in the entire ingot region related to Condition 4.

<(3) Other>
Note that the present invention is not limited to the above-described embodiment, and various modifications and improvements can be made without departing from the gist of the present invention.

  In the above-described embodiment, the release material is applied to the inner wall surface of the mold 121. However, the present invention is not limited to this. For example, each time a silicon ingot is formed in the mold 121, the mold 121 and a portion near the side surface of the silicon ingot are cut, so that when the silicon ingot in the mold 121 is taken out, The release material may not be applied. However, if a release material containing at least one of carbon and nitrogen is applied to the inner wall surface of the mold 121 to form the release material layer Mr1, compositional supercooling in the silicon melt MS1 is likely to occur, and the density of defects is increased. The initial solidified layer PS2 including the high second region Ar2 can be satisfactorily formed.

  Needless to say, all or a part of each of the above-described embodiment and other various aspects described above can be appropriately combined within a consistent range.

DESCRIPTION OF SYMBOLS 100 Manufacturing apparatus 111 Crucible 121 Mold 121b Bottom 123 Cooling plate 130 Control part Ar1-Ar3 1st-3rd region Ig1 Silicon ingot MS1 Silicon melt MS1L Silicon melt layer Mr1 Release material layer PS1 Raw material silicon PS2 Initial solidification layer (1st solidification layer) layer)

Claims (11)

A first step of preparing a mold;
A first silicon melt is supplied into the mold, and the first silicon melt is solidified on a bottom portion in the mold, so that the first region and the first region have a cross section that is more cross-sectional than the first region. A second step of forming a first solidified layer having a second region having a high density of defects that can become etch pits by an etching process;
A second silicon melt is supplied onto the first solidified layer in the mold, and the second silicon melt is solidified in one direction upward from the first solidified layer, so that the cross section is larger than the second region. A third step of forming a second solidified layer having a third region having a low density of defects that can become etch pits by etching in
A method for producing a silicon ingot having In the second step, the first silicon melt is intermittently supplied into the mold, and the first silicon melt is solidified on the bottom in the mold to form the first solidified layer,
In the third step, the second silicon melt is continuously supplied onto the first solidified layer in the mold, and the second silicon melt is solidified in the one direction to form the second solidified layer. The method for producing a silicon ingot according to claim 1 to be formed. In the second step, the first silicon melt is intermittently supplied into the mold, and the first silicon melt is solidified on the bottom in the mold to form the first solidified layer; A silicon melt layer is formed on the first solidified layer in the mold by intermittently supplying a third silicon melt on the first solidified layer in the mold.
In the third step, the second silicon melt is continuously supplied on the silicon melt layer, and the second silicon melt is solidified in the one direction to form the second solidified layer. 2. A method for producing a silicon ingot according to 1.   The method for producing a silicon ingot according to any one of claims 1 to 3, wherein in the first step, a release material layer containing at least one of carbon and nitrogen is formed on an inner wall of the mold. In the second step, when forming the first solidified layer, a fourth silicon melt containing a dopant is supplied into the mold instead of the first silicon melt, and the dopant is increased as the solidification rate increases. method for manufacturing a silicon ingot according to claim 1, the first solidified region formed in the first coagulation layer of decreasing concentration. In the third step, a fifth silicon melt containing a dopant is supplied into the mold instead of the second silicon melt, and the dopant concentration increases with an increase in the solidification rate and has a maximum dopant concentration. method for manufacturing a silicon ingot according to claim 1 or claim 5 to form a second solidified region in the second coagulation layer. Comprising a first region, a second region and a third region stacked in order from the bottom,
The density of defects that can become etch pits by the etching process in the cross section of the second region is higher than the density of defects that can become etch pits by the etching process in each cross section of the first region and the third region,
A silicon ingot in which the sum of the thicknesses of the first region and the second region is 2 to 20% of the height from the bottom. 8. The silicon ingot according to claim 7 , wherein in the cross section of the third region, the density of defects that can become etch pits by the etching process is minimized on the second region side. The first region, the second region, and the third region, which are sequentially stacked from the bottom and contain carbon and nitrogen,
The sum of the atomic density of carbon and the atomic density of nitrogen in the second region is greater than the sum of the atomic density of carbon and the atomic density of nitrogen in the first region, and the atomic density of carbon in the third region Ingot larger than the sum of the atomic density of nitrogen and nitrogen. A silicon ingot having a region where the specific resistance value increases and increases from the bottom toward the top,
A first portion having a tendency to increase in resistivity value from the bottom toward the upper direction, and a second portion having a tendency to decrease in resistivity value and having a minimum resistivity value,
The first part and the second part contain carbon and nitrogen, respectively, and the sum of the atomic density of carbon and the atomic density of nitrogen in the first part is the sum of the atomic density of carbon and the nitrogen in the second part. Silicon ingot larger than the sum of atomic density. 11. The silicon ingot according to claim 10 , wherein in the second portion, a portion having a maximum specific resistance value is within a range of a solidification rate of 30% or less from the bottom portion.

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