JP6222388B1 - Light emitting component, print head, and image forming apparatus - Google Patents

Abstract

In a structure in which a light emitting element and a driving thyristor for driving the light emitting element are stacked, mixing of light due to light emission of the driving thyristor into the light spectrum of the light emitting element is suppressed as compared with a case where a light absorption layer is not provided. Provide optical components. A light-emitting chip C includes a light-emitting diode LED that emits light of a predetermined wavelength, and a drive thyristor S that emits light from the light-emitting diode LED when turned on or increases the light emission amount of the light-emitting diode LED. And a light absorption layer 85 that is provided between the light emitting diode LED and the drive thyristor S so that the light emitting diode LED and the drive thyristor S are stacked, and absorbs light emitted from the drive thyristor S. [Selection] Figure 7

Description

  The present invention relates to a light emitting component, a print head, and an image forming apparatus.

  In Patent Document 1, a large number of light emitting elements whose threshold voltage or threshold current can be controlled from the outside are arranged one-dimensionally, two-dimensionally or three-dimensionally, and the threshold voltage or threshold current of each light-emitting element is arranged. A light emitting element array is described in which electrodes for controlling the above are connected to each other by electrical means, and a clock line for applying voltage or current from the outside is connected to each light emitting element.

  Patent Document 2 discloses a substrate, a surface emitting semiconductor laser arranged in an array on the substrate, and a thyristor as a switching element that is arranged on the substrate and selectively turns on and off the light emission of the surface emitting semiconductor laser. Is a self-scanning light source head.

  In Patent Document 3, a light emitting device having a pnpnpn6 layer semiconductor structure is configured, and electrodes are provided on the p-type first layer and the n-type sixth layer at both ends, and the p-type third layer and the n-type fourth layer at the center, A self-scanning light emitting device is described in which a pn layer has a light emitting diode function and a pnpn4 layer has a thyristor function.

JP-A-1-238996 JP 2009-286048 A JP 2001-308385 A

By the way, for example, when a light emitting element and a drive thyristor that drives the light emitting element by controlling on / off of the light emitting element are stacked, light from the light emission of the driving thyristor is mixed into the light from the light emitting element, and the emission spectrum of the light emitting element is obtained. There was a risk of disturbance.
Therefore, according to the present invention, in a configuration in which a light emitting element and a driving thyristor for driving the light emitting element are stacked, mixing of light due to light emission of the driving thyristor into the light emission spectrum of the light emitting element is suppressed compared to a case where a light absorption layer is not provided. Provided optical parts and the like.

The invention described in claim 1 is a light emitting element that emits light of a predetermined wavelength, a drive thyristor that emits light from the light emitting element by being turned on, or increases the light emission amount of the light emitting element, wherein the light emitting element and the driving thyristor is provided between the light-emitting element and the driving thyristor as laminated, comprising a light-absorbing layer which absorbs light to which the driving thyristor emits light, and the lower layer, the A light emitting component in which a driving thyristor, the light absorption layer, and the light emitting element are stacked in this order .
According to a second aspect of the present invention, in the light-emitting component according to the first aspect, the light absorption layer includes a semiconductor layer whose band gap is smaller than the band gap corresponding to the light emitted from the driving thyristor. is there.
According to a third aspect of the present invention, each of the light emitting element and the driving thyristor is configured by laminating a plurality of semiconductor layers, and the light absorption layer is a semiconductor layer constituting the light emitting element in contact with the light emitting element side. And a semiconductor layer constituting the driving thyristor in contact with the driving thyristor, the semiconductor layer having the same conductivity type as that of one of the semiconductor layers, and having a higher impurity concentration than the semiconductor layer. The light-emitting component according to claim 1 or 2.
According to a fourth aspect of the present invention, each of the light emitting element and the driving thyristor is configured by laminating a plurality of semiconductor layers, and the light absorption layer is a semiconductor layer constituting the light emitting element in contact with the light emitting element side. 4. A structure in which a direction in which current flows easily is maintained when a semiconductor layer constituting the driving thyristor in contact with the driving thyristor is directly bonded to the driving thyristor is maintained. It is a light emitting component as described in any one.
According to a fifth aspect of the present invention, each of the light emitting element, the drive thyristor, and the light absorption layer is configured by laminating a plurality of semiconductor layers, and the light absorption layer among the plurality of layers constituting the drive thyristor. And the layer in contact with the driving thyristor among the plurality of layers constituting the light absorption layer have the same conductivity type and are in contact with the light absorption layer among the plurality of layers constituting the light emitting element. The layer and the layer in contact with the light emitting element among the plurality of layers constituting the light absorption layer have the same conductivity type, and each of the plurality of layers constituting the light absorption layer constitutes the light emitting element 4. The impurity concentration is higher than a layer in contact with the light absorption layer among a plurality of layers and a layer in contact with the light absorption layer among the plurality of layers constituting the drive thyristor. either according to one of Is a light-emitting parts.
According to the sixth aspect of the present invention, a plurality of transfer elements that are sequentially turned on and a plurality of the transfer elements are connected to each other, and the transfer elements are turned on so that a transition to the on state is possible. A plurality of driving thyristors that are in a state; and a plurality of light emitting elements that are connected to each of the plurality of driving thyristors and that emit light or emit light when the plurality of driving thyristors are turned on; Optical means for imaging light emitted from the light emitting means, and the light emitting means is laminated in the order of the driving thyristor, the light absorbing layer for absorbing the light emitted by the driving thyristor, and the light emitting element from the lower layer. Thus, the drive thyristor and the light emitting element are connected to each other.
According to a seventh aspect of the present invention, an image carrier, a charging unit that charges the image carrier, a plurality of transfer elements that are turned on in order, and a plurality of the transfer elements are connected to each other. When a plurality of drive thyristors are turned on and connected to each of a plurality of drive thyristors that can be shifted to the on state by being turned on, and when the plurality of drive thyristors are turned on, light emission or light emission amount A plurality of light-emitting elements that increase, an exposure unit that exposes the image carrier through an optical unit, and a development that develops the electrostatic latent image that is exposed by the exposure unit and formed on the image carrier and means, a transfer means for transferring the developed image on the image holding member to a transfer member, wherein the exposure means, the light from said lower drive thyristor, the drive thyristor absorbs light emitted Osamuso, by being laminated in this order of the light emitting device, an image forming apparatus characterized by the said driving thyristor and the light-emitting element is connected.

According to the first aspect of the present invention, in the configuration in which the light emitting element and the driving thyristor for driving the light emitting element are stacked, the light generated by the light emission of the driving thyristor to the emission spectrum of the light emitting element is compared with the case where the light absorption layer is not provided. Mixing of is suppressed.
According to the second aspect of the present invention, the wavelength of light to be absorbed can be selected as compared with a case where a semiconductor layer having a small band gap is not included.
According to the third aspect of the present invention, the wavelength dependence of the absorbed light is reduced as compared with the case where a layer having a high impurity concentration is not included.
According to the fourth aspect of the present invention, the drive voltage is lower than when the direction in which the current easily flows is not maintained.
According to the fifth aspect of the present invention, the drive voltage is lower than when the layers in contact with each other are formed of different conductivity types.
According to the sixth aspect of the present invention, the optical system can be easily designed as compared with the case where the light absorption layer is not provided.
According to the seventh aspect of the present invention, the adverse effect on the image quality of the formed image is suppressed as compared with the case where the light absorption layer is not provided.

1 is a diagram illustrating an example of an overall configuration of an image forming apparatus to which a first exemplary embodiment is applied. FIG. 3 is a cross-sectional view illustrating an example of a configuration of a print head. It is a top view of an example of a light-emitting device. It is the figure which showed an example of the structure of the light emitting chip, the structure of the signal generation circuit of a light-emitting device, and the structure of the wiring (line) on a circuit board. It is an equivalent circuit diagram explaining the circuit configuration of the light emitting chip on which the self-scanning light emitting element array (SLED) according to the first embodiment is mounted. It is an example of the planar layout figure and sectional drawing of the light emitting chip which concerns on 1st Embodiment. (A) is a plane layout view of a light-emitting chip, and (b) is a cross-sectional view taken along line VIB-VIB of (a). It is an expanded sectional view of the island where the drive thyristor and the light emitting diode were laminated. It is a figure explaining a light absorption layer. (A) shows a case where the light absorption layer is a single n-type semiconductor layer, (b) shows a case where the light absorption layer is a single p-type semiconductor layer, and (c) shows a plurality of light absorption layers. (D) shows a case where the light absorption layer is made up of a plurality of p-type semiconductor layers, and (e) shows that the light absorption layer is composed of an n-type semiconductor layer and a p-type semiconductor layer. This is a case of being composed of a semiconductor layer. 6 is a timing chart illustrating operations of the light emitting device and the light emitting chip. It is an expanded sectional view of the island where the drive thyristor and light emitting diode explaining the modification 1-1 were laminated | stacked. It is an expanded sectional view of the island where the drive thyristor explaining a modification 1-2, and a light emitting diode were laminated. It is an expanded sectional view of the island where the drive thyristor and light emitting diode of the light emitting chip concerning a 2nd embodiment were laminated. It is an expanded sectional view of the island where the drive thyristor and light emitting diode which illustrate modification 2-1 were laminated. It is an expanded sectional view of the island where the drive thyristor and light emitting diode which explain modification 2-2 were laminated. It is an equivalent circuit diagram explaining the circuit configuration of the light emitting chip on which the self-scanning light emitting element array (SLED) according to the third embodiment is mounted. It is an expanded sectional view of the island where the drive thyristor and laser diode of the light emitting chip concerning a 3rd embodiment were laminated. It is an expanded sectional view of the island where the drive thyristor and laser diode explaining modification 3-1 were laminated. It is an expanded sectional view of the island where the drive thyristor and laser diode explaining the modification 3-2 were laminated | stacked. It is an expanded sectional view of the island where the drive thyristor and laser diode which explain modification 3-3 were laminated. It is an expanded sectional view of the island where the drive thyristor and laser diode which explain modification 3-4 were laminated. It is an equivalent circuit diagram for demonstrating the circuit structure of the light emitting chip in which the self-scanning light emitting element array (SLED) based on 4th Embodiment is mounted. It is an expanded sectional view of the island where the drive thyristor and vertical cavity surface emitting laser of the light emitting chip concerning a 4th embodiment were laminated. It is an expanded sectional view of the island where the drive thyristor and vertical cavity surface emitting laser which illustrate modification 4-1 were laminated. It is an expanded sectional view of the island where the drive thyristor and vertical cavity surface emitting laser which illustrate modification 4-2 were laminated.

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.
In the following description, element symbols are used, such as aluminum as Al.

[First Embodiment]
(Image forming apparatus 1)
FIG. 1 is a diagram illustrating an example of an overall configuration of an image forming apparatus 1 to which the first exemplary embodiment is applied. An image forming apparatus 1 shown in FIG. 1 is an image forming apparatus generally called a tandem type. The image forming apparatus 1 includes an image forming process unit 10 that forms an image corresponding to image data of each color, an image output control unit 30 that controls the image forming process unit 10, such as a personal computer (PC) 2 or an image reading device. 3 and an image processing unit 40 that performs predetermined image processing on image data received from these.

The image forming process unit 10 includes image forming units 11Y, 11M, 11C, and 11K that are arranged in parallel at predetermined intervals (in the case where they are not distinguished, they are referred to as image forming units 11). The image forming unit 11 is an example of an image carrier that forms an electrostatic latent image and holds a toner image, and an example of a charging unit that charges the surface of the photosensitive drum 12 with a predetermined potential. And a developing unit 15 as an example of a developing unit that develops an electrostatic latent image obtained by the print head 14. The charging unit 13 exposes the photosensitive drum 12 charged by the charging unit 13. Each of the image forming units 11Y, 11M, 11C, and 11K forms toner images of yellow (Y), magenta (M), cyan (C), and black (K).
Further, the image forming process unit 10 performs multiple transfer of the toner images of each color formed on the photosensitive drums 12 of the image forming units 11Y, 11M, 11C, and 11K onto a recording sheet 25 as an example of a transfer target. In addition, a sheet conveying belt 21 that conveys the recording sheet 25, a drive roll 22 that drives the sheet conveying belt 21, and a transfer roll 23 as an example of a transfer unit that transfers the toner image on the photosensitive drum 12 to the recording sheet 25. And a fixing device 24 for fixing the toner image on the recording paper 25.

  In the image forming apparatus 1, the image forming process unit 10 performs an image forming operation based on various control signals supplied from the image output control unit 30. The image data received from the personal computer (PC) 2 or the image reading device 3 under the control of the image output control unit 30 is subjected to image processing by the image processing unit 40 and supplied to the image forming unit 11. The For example, in the black (K) image forming unit 11K, the photosensitive drum 12 is charged in a predetermined potential by the charger 13 while rotating in the direction of arrow A, and the image supplied from the image processing unit 40 is supplied. Exposure is performed by the print head 14 that emits light based on the data. As a result, an electrostatic latent image related to a black (K) color image is formed on the photosensitive drum 12. The electrostatic latent image formed on the photosensitive drum 12 is developed by the developing device 15, and a black (K) toner image is formed on the photosensitive drum 12. In the image forming units 11Y, 11M, and 11C, yellow (Y), magenta (M), and cyan (C) color toner images are formed, respectively.

Each color toner image on the photosensitive drum 12 formed by each image forming unit 11 is applied to the transfer roll 23 on the recording paper 25 supplied with the movement of the paper conveying belt 21 moving in the direction of arrow B. Electrostatic transfer is sequentially performed by the transfer electric field, and a composite toner image in which toner of each color is superimposed on the recording paper 25 is formed.
Thereafter, the recording paper 25 on which the composite toner image has been electrostatically transferred is conveyed to the fixing device 24. The synthesized toner image on the recording paper 25 conveyed to the fixing device 24 is fixed on the recording paper 25 by the fixing device 24 by heat and pressure and discharged from the image forming apparatus 1.

(Print head 14)
FIG. 2 is a cross-sectional view showing an example of the configuration of the print head 14. The print head 14 as an example of an exposure unit includes a light source unit 63 including a housing 61 and a plurality of light emitting elements that expose the photosensitive drum 12 (light emitting diodes LED as an example of light emitting elements in the first embodiment). A light emitting device 65 as an example of the provided light emitting means, and a rod lens array 64 as an example of an optical means for imaging light emitted from the light source unit 63 on the surface of the photosensitive drum 12 are provided.
The light emitting device 65 includes a circuit board 62 on which the above-described light source unit 63, a signal generation circuit 110 that drives the light source unit 63 (see FIG. 3 described later), and the like are mounted.

  The housing 61 is made of, for example, metal, supports the circuit board 62 and the rod lens array 64, and is set so that the light emitting surface of the light emitting element of the light source unit 63 becomes the focal plane of the rod lens array 64. Further, the rod lens array 64 is arranged along the axial direction of the photosensitive drum 12 (the main scanning direction and the X direction in FIGS. 3 and 4B described later).

(Light emitting device 65)
FIG. 3 is a top view of an example of the light emitting device 65.
In the light emitting device 65 shown as an example in FIG. 3, the light source unit 63 is a light emitting chip C1 to C40 as an example of 40 light emitting components on the circuit board 62 (in the case of not distinguishing, it is expressed as a light emitting chip C). Are arranged in a staggered pattern in two rows in the X direction, which is the main scanning direction. The configurations of the light emitting chips C1 to C40 may be the same.
In the present specification, “to” indicates a plurality of constituent elements each distinguished by a number, and includes those described before and after “to” and those between them. For example, the light emitting chips C1 to C40 include the light emitting chip C1 to the light emitting chip C40 in numerical order.

In the first embodiment, a total of 40 light emitting chips C are used, but the present invention is not limited to this.
The light emitting device 65 includes a signal generation circuit 110 that drives the light source unit 63. The signal generation circuit 110 is configured by, for example, an integrated circuit (IC). Note that the light emitting device 65 does not have to include the signal generation circuit 110. At this time, the signal generation circuit 110 is provided outside the light emitting device 65 and supplies a control signal and the like for controlling the light emitting chip C via a cable or the like. Here, the light emitting device 65 will be described as including the signal generation circuit 110.
Details of the arrangement of the light emitting chips C will be described later.

  FIG. 4 is a diagram illustrating an example of the configuration of the light emitting chip C, the configuration of the signal generation circuit 110 of the light emitting device 65, and the configuration of the wiring (line) on the circuit board 62. 4A shows the configuration of the light-emitting chip C, and FIG. 4B shows the configuration of the signal generation circuit 110 of the light-emitting device 65 and the configuration of wiring (lines) on the circuit board 62. In FIG. 4B, the light emitting chips C1 to C9 among the light emitting chips C1 to C40 are shown.

First, the configuration of the light-emitting chip C shown in FIG.
The light-emitting chip C includes a plurality of light-emitting elements (in the first embodiment, light-emitting diodes) arranged in a row along the long side on the surface of the substrate 80 having a rectangular surface shape on the side close to one side of the long side. A light emitting unit 102 including LEDs 1 to 128 (represented as a light emitting diode LED when not distinguished) is provided. Further, the light emitting chip C has terminals (φ1 terminal, φ2 terminal, Vga terminal, φI terminal) which are a plurality of bonding pads for taking in various control signals and the like at both ends in the long side direction of the surface of the substrate 80. Prepare. These terminals are provided in order of the φI terminal and the φ1 terminal from one end of the substrate 80, and are provided in the order of the Vga terminal and the φ2 terminal from the other end of the substrate 80. The light emitting unit 102 is provided between the φ1 terminal and the φ2 terminal. Further, a back electrode 91 (see FIG. 6 described later) is provided on the back surface of the substrate 80 as a Vsub terminal.

  Note that the “column shape” is not limited to the case where a plurality of light emitting elements are arranged in a straight line as illustrated in FIG. 4A, and the light emitting elements of the plurality of light emitting elements are arranged in the column direction. It may be in a state where they are arranged with different amounts of displacement with respect to the orthogonal direction. For example, when a light emitting surface of a light emitting element (a region 311 of a light emitting diode LED in FIG. 6 described later) is a pixel, each light emitting element is displaced by several pixels or several tens of pixels in a direction orthogonal to the column direction. May be arranged. Moreover, you may arrange | position zigzag alternately between adjacent light emitting elements or for every some light emitting element.

Next, the configuration of the signal generation circuit 110 of the light emitting device 65 and the configuration of the wiring (line) on the circuit board 62 will be described with reference to FIG.
As described above, the signal generating circuit 110 and the light emitting chips C1 to C40 are mounted on the circuit board 62 of the light emitting device 65, and wirings (lines) for connecting the signal generating circuit 110 and the light emitting chips C1 to C40 are provided. ing.

First, the configuration of the signal generation circuit 110 will be described.
Image signal processed image data and various control signals are input to the signal generation circuit 110 from the image output control unit 30 and the image processing unit 40 (see FIG. 1). The signal generation circuit 110 performs rearrangement of image data, correction of light quantity, and the like based on these image data and various control signals.
The signal generation circuit 110 includes a transfer signal generation unit 120 that transmits the first transfer signal φ1 and the second transfer signal φ2 to the light emitting chips C1 to C40 based on various control signals.
Further, the signal generation circuit 110 transmits the lighting signals φI1 to φI40 (indicated as the lighting signal φI if not distinguished) to the light emitting chips C1 to C40 based on various control signals, respectively. 140.
Furthermore, the signal generation circuit 110 supplies a reference potential supply unit 160 that supplies a reference potential Vsub that serves as a potential reference to the light emitting chips C1 to C40, and a power supply potential that supplies a power supply potential Vga for driving the light emitting chips C1 to C40. A supply unit 170 is provided.

Next, the arrangement of the light emitting chips C1 to C40 will be described.
The odd-numbered light emitting chips C1, C3, C5,... Are arranged in a line at intervals in the long side direction of each substrate 80. The even-numbered light emitting chips C2, C4, C6,... Are similarly arranged in a row at intervals in the direction of the long side of each substrate 80. The odd numbered light emitting chips C1, C3, C5,... And the even numbered light emitting chips C2, C4, C6,... Are arranged so that the long sides on the light emitting unit 102 side provided in the light emitting chip C face each other. They are arranged in a zigzag pattern in a state rotated by 180 °. The positions of the light emitting chips C are also set so that the light emitting elements are arranged at predetermined intervals in the main scanning direction (X direction). In addition, in the light emitting chips C1 to C40 of FIG. 4B, the direction of the arrangement of the light emitting elements of the light emitting unit 102 shown in FIG. Is indicated by an arrow.

A wiring (line) connecting the signal generation circuit 110 and the light emitting chips C1 to C40 will be described.
The circuit board 62 is provided with a power supply line 200a that is connected to a back electrode 91 (see FIG. 6 described later) that is a Vsub terminal provided on the back surface of the substrate 80 of the light emitting chip C and supplies a reference potential Vsub. .
The circuit board 62 is provided with a power supply line 200b that is connected to a Vga terminal provided on the light emitting chip C and supplies a power supply potential Vga for driving.

  The circuit board 62 includes a first transfer signal line 201 for transmitting the first transfer signal φ1 from the transfer signal generator 120 of the signal generation circuit 110 to the φ1 terminals of the light emitting chips C1 to C40, and the light emitting chips C1 to C40. A second transfer signal line 202 for transmitting the second transfer signal φ2 to the φ2 terminal is provided. The first transfer signal φ1 and the second transfer signal φ2 are transmitted in common (in parallel) to the light emitting chips C1 to C40.

  Further, the lighting signals φI1 to φI40 are transmitted to the circuit board 62 from the lighting signal generation unit 140 of the signal generation circuit 110 to the respective φI terminals of the respective light emitting chips C1 to C40 via the current limiting resistors RI. Lighting signal lines 204-1 to 204-40 (indicated as lighting signal lines 204 if not distinguished) are provided.

  As described above, the reference potential Vsub and the power supply potential Vga are commonly supplied to all the light emitting chips C1 to C40 on the circuit board 62. The first transfer signal φ1 and the second transfer signal φ2 are also transmitted in common (in parallel) to the light emitting chips C1 to C40. On the other hand, the lighting signals φI1 to φI40 are individually transmitted to the light emitting chips C1 to C40, respectively.

(Light emitting chip C)
FIG. 5 is an equivalent circuit diagram for explaining the circuit configuration of the light-emitting chip C on which the self-scanning light-emitting element array (SLED: Self-Scanning Light Emitting Device) according to the first embodiment is mounted. Each element described below is arranged based on a layout (see FIG. 6 described later) on the light emitting chip C except for terminals (φ1 terminal, φ2 terminal, Vga terminal, φI terminal). Note that the positions of the terminals (φ1 terminal, φ2 terminal, Vga terminal, φI terminal) are different from those in FIG. . The Vsub terminal provided on the back surface of the substrate 80 is drawn out of the substrate 80.
Here, the light emitting chip C will be described taking the light emitting chip C1 as an example in relation to the signal generation circuit 110. Therefore, in FIG. 5, the light-emitting chip C is referred to as a light-emitting chip C <b> 1 (C). The configuration of the other light emitting chips C2 to C40 is the same as that of the light emitting chip C1.

The light-emitting chip C1 (C) includes a light-emitting unit 102 (see FIG. 4A) configured by light-emitting diodes LED1 to LED128.
The light-emitting chip C1 (C) includes drive thyristors S1 to S128 (in the case of not distinguishing, the light-emitting chip C1 (C) is expressed as drive thyristor S). In the light emitting diodes LED1 to LED128 and the driving thyristors S1 to S128, the light emitting diode LED and the driving thyristor S having the same number are connected in series.
As shown in FIG. 6B described later, the light emitting diodes LED are stacked on the drive thyristors S arranged in a line on the substrate 80. Therefore, the light emitting diodes LED1 to LED128 are also arranged in a line.

The light emitting chip C1 (C) includes transfer thyristors T1 to T128 arranged in a row like the light emitting diodes LED1 to LED128 and the drive thyristors S1 to S128 (in the case where they are not distinguished, they are referred to as transfer thyristors T). Prepare.
Here, the transfer thyristor T is used as an example of the transfer element. However, other circuit elements may be used as long as the elements are sequentially turned on, for example, a circuit combining a shift register and a plurality of transistors. An element may be used.
The light-emitting chip C1 (C) includes two pairs of transfer thyristors T1 to T128 in the order of numbers, and is represented by coupling diodes D1 to D127 (if not distinguished from each other), as coupling diodes D. ).
Further, the light emitting chip C1 (C) includes power supply line resistances Rg1 to Rg128 (in the case of not distinguishing, it is expressed as a power supply line resistance Rg).

Further, the light emitting chip C1 (C) includes one start diode SD. In order to prevent an excessive current from flowing through a first transfer signal line 72 to which a first transfer signal φ1 to be described later is transmitted and a second transfer signal line 73 to which a second transfer signal φ2 is transmitted. Current limiting resistors R1 and R2.
Here, the transfer unit 101 is configured by the drive thyristors S1 to S128, the transfer thyristors T1 to T128, the power supply line resistors Rg1 to Rg128, the coupling diodes D1 to D127, the start diode SD, and the current limiting resistors R1 and R2.

The light emitting diodes LED1 to LED128 of the light emitting unit 102, the transfer unit 101, the drive thyristors S1 to S128, and the transfer thyristors T1 to T128 are arranged in numerical order from the left side in FIG. Further, the coupling diodes D1 to D127 and the power supply line resistors Rg1 to Rg128 are also arranged in numerical order from the left side in the figure.
In FIG. 5, the transfer unit 101 and the light emitting unit 102 are arranged in this order from the top.

In the first embodiment, the number of light emitting diodes LED in the light emitting unit 102, the drive thyristor S, the transfer thyristor T, and the power supply line resistance Rg in the transfer unit 101 are 128. The number of coupling diodes D is 127, which is one less than the number of transfer thyristors T.
The number of light emitting diodes LED is not limited to the above, and may be a predetermined number. The number of transfer thyristors T may be larger than the number of light emitting diodes LED.

The light emitting diode LED includes a two-terminal semiconductor element having an anode terminal (anode) and a cathode terminal (cathode), a thyristor (driving thyristor S, transfer thyristor T), an anode terminal (anode), a gate terminal (gate), and The semiconductor element having three terminals of the cathode terminal (cathode), the coupling diode D1, and the start diode SD are two-terminal semiconductor elements having an anode terminal (anode) and a cathode terminal (cathode).
As will be described later, the light emitting diode LED, thyristor (drive thyristor S, transfer thyristor T), coupling diode D1, and start diode SD may not necessarily include an anode terminal, a gate terminal, and a cathode terminal configured as electrodes. is there. Therefore, hereinafter, the terminal may be abbreviated and indicated in parentheses.

Next, electrical connection of each element in the light emitting chip C1 (C) will be described.
The anodes of the transfer thyristor T and the drive thyristor S are connected to the substrate 80 of the light emitting chip C1 (C) (anode common).
These anodes are connected to a power supply line 200a (see FIG. 4B) via a back electrode 91 (see FIG. 6B described later) which is a Vsub terminal provided on the back surface of the substrate 80. . The power supply line 200a is supplied with the reference potential Vsub from the reference potential supply unit 160.
This connection is a configuration when a p-type substrate 80 is used. When an n-type substrate is used, the polarity is reversed, and when an intrinsic (i) -type substrate to which no impurity is added is used. Is provided with a terminal connected to the power supply line 200a for supplying the reference potential Vsub on the side where the transfer unit 101 and the light emitting unit 102 are provided.

Along with the arrangement of the transfer thyristors T, the cathodes of the odd-numbered transfer thyristors T1, T3,... Are connected to the first transfer signal line 72. The first transfer signal line 72 is connected to the φ1 terminal via the current limiting resistor R1. The first transfer signal line 201 (see FIG. 4B) is connected to the φ1 terminal, and the first transfer signal φ1 is transmitted from the transfer signal generator 120.
On the other hand, the cathodes of the even-numbered transfer thyristors T2, T4,... Are connected to the second transfer signal line 73 along the arrangement of the transfer thyristors T. The second transfer signal line 73 is connected to the φ2 terminal via the current limiting resistor R2. The second transfer signal line 202 (see FIG. 4B) is connected to the φ2 terminal, and the second transfer signal φ2 is transmitted from the transfer signal generator 120.

  The cathodes of the light emitting diodes LED <b> 1 to LED <b> 128 are connected to the lighting signal line 75. The lighting signal line 75 is connected to the φI terminal. In the light emitting chip C1, the φI terminal is connected to the lighting signal line 204-1 via a current limiting resistor RI provided outside the light emitting chip C1 (C), and the lighting signal generating unit 140 transmits the lighting signal φI1. (See FIG. 4B). The lighting signal φI1 supplies a current for lighting to the light emitting diodes LED1 to LED128. The lighting signal lines 204-2 to 204-40 are connected to the φI terminals of the other light emitting chips C2 to C40 via current limiting resistors RI, respectively, and the lighting signals φI2 to φI40 are transmitted from the lighting signal generator 140. (See FIG. 4B).

  The gates Gt1 to Gt128 of the transfer thyristors T1 to T128 (represented as the gate Gt if not distinguished) are represented by the gates Gs1 to Gs128 of the setting diodes S1 to S128 having the same number (represented as the gate Gs if not distinguished). To 1). Therefore, the gates Gt1 to Gt128 and the gates Gs1 to Gs128 have the same number and are electrically at the same potential. Therefore, for example, it is expressed as a gate Gt1 (gate Gs1) and indicates that the potentials are the same.

  Coupling diodes D1 to D127 are respectively connected between the gates Gt in which the gates Gt1 to Gt128 of the transfer thyristors T1 to T128 are paired in order of two numbers. That is, the coupling diodes D1 to D127 are connected in series so as to be sandwiched between the gates Gt1 to Gt128, respectively. The direction of the coupling diode D1 is connected in a direction in which current flows from the gate Gt1 to the gate Gt2. The same applies to the other coupling diodes D2 to D127.

  The gate Gt (gate Gs) of the transfer thyristor T is connected to the power supply line 71 via the power supply line resistance Rg provided corresponding to each of the transfer thyristors T. The power supply line 71 is connected to the Vga terminal. A power supply line 200b (see FIG. 4B) is connected to the Vga terminal, and the power supply potential Vga is supplied from the power supply potential supply unit 170.

  The gate Gt1 of the transfer thyristor T1 is connected to the cathode terminal of the start diode SD. On the other hand, the anode of the start diode SD is connected to the second transfer signal line 73.

FIG. 6 is an example of a plan layout view and a cross-sectional view of the light emitting chip C according to the first embodiment. 6A is a plan layout view of the light-emitting chip C, and FIG. 6B is a cross-sectional view taken along line VIB-VIB in FIG. 6A. Here, since the connection relationship between the light-emitting chip C and the signal generation circuit 110 is not shown, it is not necessary to use the light-emitting chip C1 as an example. Therefore, it is expressed as a light emitting chip C.
FIG. 6A shows a portion centering on the light emitting diodes LED1 to LED4, the drive thyristors S1 to S4, and the transfer thyristors T1 to T4. Note that the positions of the terminals (φ1 terminal, φ2 terminal, Vga terminal, φI terminal) are different from those in FIG. 4A, but are shown at the left end in the figure for convenience of explanation. A Vsub terminal (back surface electrode 91) provided on the back surface of the substrate 80 is drawn out from the substrate 80. If the terminals are provided corresponding to FIG. 4A, the φ2 terminal, the φI terminal, and the current limiting resistor R2 are provided at the right end portion of the substrate 80. The start diode SD may be provided at the right end portion of the substrate 80.

6B, which is a cross-sectional view taken along line VIB-VIB of FIG. 6A, shows a light emitting diode LED1 / drive thyristor S1, a transfer thyristor T1, a coupling diode D1, and a power supply line resistance Rg1 from the bottom in the figure. ing. The light emitting diode LED1 and the drive thyristor S1 are stacked. Here, the stacked light emitting diode LED1 and driving thyristor S1 are referred to as light emitting diode LED1 / driving thyristor S1. The same applies to other cases.
6A and 6B, major elements and terminals are represented by names.

First, the cross-sectional structure of the light emitting chip C will be described with reference to FIG.
On a p-type substrate 80 (hereinafter referred to as substrate 80), a p-type anode layer 81 (hereinafter referred to as p-anode layer 81. The same applies to others), an n-type gate layer. 82 (n gate layer 82), p type gate layer 83 (p gate layer 83), and n type cathode layer 84 (n cathode layer 84) are provided in this order. In the following, the notation in () is used. The same applies to other cases.
A light absorption layer 85 is provided on the n cathode layer 84.
Further, a p-type anode layer 86 (p-anode layer 86), a light-emitting layer 87, and an n-type cathode layer 88 (n-cathode layer 88) are provided on the light absorption layer 85.
On the light emitting diode LED1, a light emitting port protective layer 89 made of an insulating material that is transparent to the light (emitted light) from the light emitting diode LED is provided.

  As shown in FIG. 6B, the light-emitting chip C is provided with a protective layer 90 made of a light-transmitting insulating material provided so as to cover the surface and side surfaces of these islands. . These islands and wiring such as the power supply line 71, the first transfer signal line 72, the second transfer signal line 73, and the lighting signal line 75 are formed through holes (in FIG. 6A). It is connected via). In the following description, description of the protective layer 90 and the through hole is omitted.

  Further, as shown in FIG. 6B, a back surface electrode 91 serving as a Vsub terminal is provided on the back surface of the substrate 80.

  Each of the p anode layer 81, the n gate layer 82, the p gate layer 83, the n cathode layer 84, the light absorption layer 85, the p anode layer 86, the light emitting layer 87, and the n cathode layer 88 is a semiconductor layer, and is formed by epitaxial growth. Laminated sequentially. Then, the semiconductor layer between the islands is removed by etching (mesa etching) so as to become a plurality of islands (islands) separated from each other (islands 301, 302, 303,... Described later). The p anode layer 81 may or may not be separated. In FIG. 6B, the p anode layer 81 is partially separated in the thickness direction. The p anode layer 81 may also serve as the substrate 80.

Using the p anode layer 81, the n gate layer 82, the p gate layer 83, and the n cathode layer 84, the drive thyristor S, the transfer thyristor T, the coupling diode D, the power supply line resistance Rg, etc. (in FIG. 6B, the drive) A thyristor S1, a transfer thyristor T1, a coupling diode D1, and a power supply line resistance Rg1) are configured.
Here, the notations of the p anode layer 81, the n gate layer 82, the p gate layer 83, and the n cathode layer 84 correspond to functions (functions) when the drive thyristor S and the transfer thyristor T are configured. That is, the p anode layer 81 functions as an anode, the n gate layer 82 and the p gate layer 83 function as a gate, and the n cathode layer 84 functions as a cathode. When the coupling diode D and the power supply line resistance Rg are configured, different functions (functions) are performed as described later.

The p anode layer 86, the light emitting layer 87, and the n cathode layer 88 constitute a light emitting diode LED (light emitting diode LED1 in FIG. 6B).
The notation of the p anode layer 86 and the n cathode layer 88 is the same, and corresponds to the function (function) when the light emitting diode LED is configured. That is, the p anode layer 86 functions as an anode, and the n cathode layer 88 functions as a cathode.

As described below, the plurality of islands include a p anode layer 81, an n gate layer 82, a p gate layer 83, an n cathode layer 84, a light absorption layer 85, a p anode layer 86, a light emitting layer 87, and an n cathode layer 88. Among the plurality of layers, those not including some layers are included. For example, the island 302 does not include a part or all of the light absorption layer 85, the p anode layer 86, the light emitting layer 87, and the n cathode layer 88.
In addition, the plurality of islands include those that do not include part of the layer. For example, the island 302 includes a p anode layer 81, an n gate layer 82, a p gate layer 83, and an n cathode layer 84, but the n cathode layer 84 includes only a part.

Next, the planar layout of the light emitting chip C will be described with reference to FIG.
The island 301 is provided with a drive thyristor S1 and a light emitting diode LED1. In the island 302, a transfer thyristor T1 and a coupling diode D1 are provided. The island 303 is provided with a power supply line resistance Rg1. The island 304 is provided with a start diode SD. The island 305 is provided with a current limiting resistor R1, and the island 306 is provided with a current limiting resistor R2.
In the light emitting chip C, a plurality of islands similar to the islands 301, 302, and 303 are formed in parallel. These islands include drive thyristors S2, S3, S4,..., Light emitting diodes LED2, LED3, LED4,..., Transfer thyristors T2, T3, T4,. , 302, and 303.

Here, the island 301 to the island 306 will be described in detail with reference to FIGS.
As shown in FIG. 6A, the island 301 is provided with a drive thyristor S1 and a light emitting diode LED1.
The drive thyristor S <b> 1 includes a p anode layer 81, an n gate layer 82, a p gate layer 83, and an n cathode layer 84. Then, a p-type ohmic electrode 331 (p-ohmic electrode) provided on the p-gate layer 83 exposed by removing the n-cathode layer 88, the light-emitting layer 87, the p-anode layer 86, the light-absorbing layer 85, and the n-cathode layer 84 is removed. The electrode 331) is an electrode of the gate Gs1 (may be referred to as a gate terminal Gs1).

On the other hand, the light emitting diode LED1 is composed of a p anode layer 86, a light emitting layer 87, and an n cathode layer 88. The light emitting diode LED1 is stacked on the n cathode layer 84 of the drive thyristor S1 via the light absorption layer 85. An n-type ohmic electrode 321 (n-ohmic electrode 321) provided on the n-cathode layer 88 (region 311) is used as a cathode electrode.
The p anode layer 86 includes a current confinement layer 86b (see FIG. 7 described later). The current confinement layer 86b is provided to limit the current flowing through the light emitting diode LED to the central portion of the light emitting diode LED. That is, the periphery of the light emitting diode LED has many defects due to mesa etching. For this reason, non-radiative recombination tends to occur. Therefore, the current confinement layer 86b is provided so that the central portion of the light emitting diode LED becomes a current passage portion (region) α where current easily flows and the peripheral portion becomes a current blocking portion (region) β where current does not easily flow. . As shown in the light emitting diode LED1 in FIG. 6A, the inside of the broken line is the current passage part α, and the outside of the broken line is the current blocking part β.
In order to extract light from the central portion of the light emitting diode LED1, the n-ohmic electrode 321 is provided in the peripheral portion of the light emitting diode LED1 so that the central portion is an opening.
The current confinement layer 86b will be described later.

  When the current confinement layer 86b is provided, the power consumed for non-radiative recombination is suppressed, so that low power consumption and light extraction efficiency are improved. The light extraction efficiency is the amount of light that can be extracted per power consumption.

In the island 302, a transfer thyristor T1 and a coupling diode D1 are provided.
The transfer thyristor T1 includes a p anode layer 81, an n gate layer 82, a p gate layer 83, and an n cathode layer 84. That is, the n ohmic electrode 323 provided on the n cathode layer 84 (region 313) exposed by removing the n cathode layer 88, the light emitting layer 87, the p anode layer 86, and the light absorption layer 85 is used as a cathode terminal. When the light absorption layer 85 is n-type or includes an n-type layer, the light absorption layer 85 or the light absorption layer 85 or the light absorption layer 85 is not removed without removing the light absorption layer 85 or the light absorption layer 85. An n-ohmic electrode 323 may be provided on the n-type layer included in the absorption layer 85.
Further, the p ohmic electrode 332 provided on the p gate layer 83 exposed by removing the n cathode layer 84 is defined as a terminal of the gate Gt1 (may be referred to as a gate terminal Gt1).
Similarly, the coupling diode D <b> 1 provided on the island 302 includes a p gate layer 83 and an n cathode layer 84. That is, the n ohmic electrode 324 provided on the n cathode layer 84 (region 314) exposed by removing the n cathode layer 88, the light emitting layer 87, the p anode layer 86, and the light absorption layer 85 is used as a cathode terminal. When the light absorption layer 85 is n-type or includes an n-type layer, the light absorption layer 85 or the light absorption layer 85 or the light absorption layer 85 is not removed without removing the light absorption layer 85 or the light absorption layer 85. An n-ohmic electrode 324 may be provided on the n-type layer included in the absorption layer 85. Furthermore, the p ohmic electrode 332 provided on the p gate layer 83 exposed by removing the n cathode layer 84 is used as an anode terminal. Here, the anode terminal of the coupling diode D1 is the same as the gate Gt1 (gate terminal Gt1).

  The power supply line resistance Rg1 provided on the island 303 is constituted by a p gate layer 83. Here, the p ohmic electrode 333 and the p ohmic electrode provided on the p gate layer 83 exposed by removing the n cathode layer 88, the light emitting layer 87, the p anode layer 86, the light absorption layer 85, and the n cathode layer 84. A p-gate layer 83 between the gate and the gate 334 is provided as a resistor.

The start diode SD provided on the island 304 includes a p gate layer 83 and an n cathode layer 84. That is, the n ohmic electrode 325 provided on the n cathode layer 84 (region 315) exposed by removing the n cathode layer 88, the light emitting layer 87, the p anode layer 86, and the light absorption layer 85 is used as a cathode terminal. When the light absorption layer 85 is n-type or includes an n-type layer, the light absorption layer 85 or the light absorption layer 85 or the light absorption layer 85 is not removed without removing the light absorption layer 85 or the light absorption layer 85. An n ohmic electrode 325 may be provided on the n-type layer included in the absorption layer 85. Further, the p ohmic electrode 335 provided on the p gate layer 83 exposed by removing the n cathode layer 84 is used as an anode terminal.
The current limiting resistor R1 provided on the island 305 and the current limiting resistor R2 provided on the island 306 are provided in the same manner as the power supply line resistor Rg1 provided on the island 303, and each includes two p-ohmic electrodes (unsigned) The p gate layer 83 in between is used as a resistance.

In FIG. 6A, the connection relationship between each element will be described.
The lighting signal line 75 includes a trunk portion 75a and a plurality of branch portions 75b. The trunk portion 75a is provided so as to extend in the column direction of the light emitting diodes LED. The branch portion 75 b branches off from the trunk portion 75 a and is connected to an n ohmic electrode 321 that is a cathode terminal of the light emitting diode LED 1 provided on the island 301. The same applies to the cathode terminals of the other light emitting diodes LED.
The lighting signal line 75 is connected to a φI terminal provided on the light emitting diode LED1 side.

The first transfer signal line 72 is connected to an n-ohmic electrode 323 that is a cathode terminal of a transfer thyristor T1 provided on the island 302. The first transfer signal line 72 is connected to the cathode terminal of another odd-numbered transfer thyristor T provided on an island similar to the island 302. The first transfer signal line 72 is connected to the φ1 terminal via a current limiting resistor R1 provided on the island 305.
On the other hand, the second transfer signal line 73 is connected to an n-ohmic electrode (unsigned) that is a cathode terminal of an even-numbered transfer thyristor T provided on an island without a symbol. The second transfer signal line 73 is connected to the φ2 terminal via a current limiting resistor R2 provided on the island 306.

  The power supply line 71 is connected to the p ohmic electrode 334 which is one terminal of the power supply line resistance Rg1 provided on the island 303. One terminal of the other power supply line resistor Rg is also connected to the power supply line 71. The power supply line 71 is connected to the Vga terminal.

  The p ohmic electrode 331 (gate terminal Gs1) of the light emitting diode LED1 provided on the island 301 is connected to the p ohmic electrode 332 (gate terminal Gt1) of the island 302 by a connection wiring 76.

The p ohmic electrode 332 (gate terminal Gt1) is connected to the p ohmic electrode 333 (the other terminal of the power supply line resistance Rg1) of the island 303 by a connection wiring 77.
An n-ohmic electrode 324 (cathode terminal of the coupling diode D1) provided on the island 302 is connected to a p-type ohmic electrode (unsigned) which is a gate terminal Gt2 of the adjacent transfer thyristor T2 by a connection wiring 79.
Although not described here, the same applies to other light emitting diodes LED, drive thyristor S, transfer thyristor T, coupling diode D, and the like.

The p ohmic electrode 332 (gate terminal Gt1) of the island 302 is connected to the n ohmic electrode 325 (cathode terminal of the start diode SD) provided on the island 304 by a connection wiring 78. The p ohmic electrode 335 (the anode terminal of the start diode SD) is connected to the second transfer signal line 73.
The above connection and configuration are those when using a p-type substrate 80, and the polarity is reversed when an n-type substrate is used. When an i-type substrate is used, a terminal connected to the power supply line 200a for supplying the reference potential Vsub is provided on the side of the substrate where the transfer unit 101 and the light emitting unit 102 are provided. The connection and configuration are the same as when either a p-type substrate is used or when an n-type substrate is used.

(Laminated structure of driving thyristor S and light emitting diode LED)
FIG. 7 is an enlarged cross-sectional view of an island 301 in which the drive thyristor S and the light emitting diode LED are stacked. In addition, the light emission port protective layer 89 and the protective layer 90 are omitted. The same applies hereinafter.
As described above, the light emitting diode LED is stacked on the drive thyristor S with the light absorption layer 85 interposed therebetween. That is, the drive thyristor S and the light emitting diode LED are connected in series.

The light emitting chip C showing the island 301 in FIG. 7 has a p anode layer 81, an n gate layer 82, a p gate layer 83, an n cathode layer 84, a light absorption layer 85, and a p anode layer 86 on a p-type substrate 80. The light emitting layer 87 and the n cathode layer 88 are epitaxially grown in this order to form a semiconductor laminate. In the figure, they are expressed as n and p.
The drive thyristor S includes a p anode layer 81, an n gate layer 82, a p gate layer 83, and an n cathode layer 84. That is, it has a four-layer structure of pnpn.
The light emitting diode LED includes a p anode layer 86, a light emitting layer 87, and an n cathode layer 88.

  Here, the substrate 80 will be described by taking p-type GaAs as an example, but may be n-type GaAs or intrinsic (i) GaAs to which no impurity is added. Further, InP, GaN, InAs, sapphire, Si, or the like may be used. When the substrate is changed, a material that is monolithically stacked on the substrate is a material that substantially matches the lattice constant of the substrate (including a strain structure, a strain relaxation layer, and metamorphic growth). As an example, InAs, InAsSb, GaInAsSb, etc. are used on the InAs substrate, InP, InGaAsP, etc. are used on the InP substrate, and GaN, AlGaN, InGaN is used on the GaN substrate or sapphire substrate. Si, SiGe, GaP, etc. are used on the Si substrate. However, in the case where the substrate is attached to another support substrate after crystal growth, the semiconductor material does not need to be substantially lattice-matched to the support substrate.

The p anode layer 81 is, for example, p-type Al _0.9 GaAs having an impurity concentration of 1 × 10 ¹⁸ / cm ³ . You may change Al composition in the range of 0-1. GaInP or the like may be used.
The n gate layer 82 is, for example, n-type Al _0.9 GaAs having an impurity concentration of 1 × 10 ¹⁷ / cm ³ . You may change Al composition in the range of 0-1. GaInP or the like may be used.
The p gate layer 83 is, for example, p-type Al _0.9 GaAs having an impurity concentration of 1 × 10 ¹⁷ / cm ³ . You may change Al composition in the range of 0-1. GaInP or the like may be used.
The n cathode layer 84 is, for example, n-type Al _0.9 GaAs having an impurity concentration of 1 × 10 ¹⁸ / cm ³ . You may change Al composition in the range of 0-1. GaInP or the like may be used.

  The light absorption layer 85 will be described later.

The p anode layer 86 is formed by sequentially laminating a lower p layer 86a, a current confinement layer 86b, and an upper p layer 86c. The current confinement layer 86b includes a current passage portion α and a current blocking portion β. As shown in FIG. 6A, the current passage part α is provided in the central part of the light emitting diode LED, and the current blocking part β is provided in the peripheral part of the light emitting diode LED.
The lower p layer 86a and the upper p layer 86c are, for example, p-type Al _0.9 GaAs having an impurity concentration of 1 × 10 ¹⁸ / cm ³ . You may change Al composition in the range of 0-1. GaInP or the like may be used.
The current confinement layer 86b is, for example, p-type AlGaAs having a high impurity concentration of AlAs or Al. Any material may be used as long as the electrical resistance is increased by narrowing the current path by oxidizing Al to form Al ₂ O ₃ .

The current blocking portion β in the current confinement layer 86b is formed by oxidizing the current confinement layer 86b with exposed side surfaces from the side surfaces. The portion that remains without being oxidized becomes the current passage portion α.
The oxidation from the side surface of the current confinement layer 86b oxidizes Al of the current confinement layer 86b such as AlAs or AlGaAs by, for example, steam oxidation at 300 to 400 ° C. At this time, the oxidation proceeds from the exposed side surface, and a current blocking portion β is formed around the light emitting diode LED by Al ₂ O ₃ which is an oxide of Al.
The current blocking portion β in the p anode layer 86 may be formed by implanting hydrogen ions (H ⁺ ) into the p anode layer 86 (ion implantation). That is, after forming the p anode layer 86, the current blocking portion β may be formed by implanting H ⁺ into a portion that is to be the current blocking portion β.

  The light emitting layer 87 has a quantum well composition in which well layers and barrier layers are alternately stacked. The well layer is, for example, GaAs, AlGaAs, InGaAs, GaAsP, AlGaInP, GaInAsP, GaInP, or the like, and the barrier layer is AlGaAs, GaAs, GaInP, GaInAsP, or the like. The light emitting layer 87 may be an intrinsic (i) layer to which no impurity is added. The light emitting layer 87 may have a structure other than the quantum well structure, and may be, for example, a quantum beam (quantum wire) or a quantum box (quantum dot).

The n cathode layer 88 is, for example, n-type Al _0.9 GaAs having an impurity concentration of 1 × 10 ¹⁸ / cm ³ . You may change Al composition in the range of 0-1. GaInP or the like may be used.

  These semiconductor layers are stacked by, for example, metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or the like to form a semiconductor stacked body.

  The n ohmic electrode 321 is, for example, Au (AuGe) containing Ge that can easily make ohmic contact with an n-type semiconductor layer such as the n cathode layer 88.

The p ohmic electrode 331 is, for example, Au (AuZn) containing Zn that can easily make ohmic contact with a p-type semiconductor layer such as the p gate layer 83.
The back electrode 91 is, for example, AuZn, similarly to the p ohmic electrode 331.

The light exit protective layer 89 is formed of a material that is transparent to the emitted light on the light exit opening surrounded by the n-ohmic electrode 321.
The light exit protective layer 89 is made of, for example, SiO ₂ , SiON, SiN, or the like.

  In the above description, the p-ohmic electrode 331 is provided in the p-gate layer 83 and used as the gate terminal Gs of the drive thyristor S. However, the n-gate layer 82 may be used as the gate terminal of the drive thyristor S.

<Thyristor>
First, the basic operation of the thyristor (transfer thyristor T, drive thyristor S) will be described. As described above, the thyristor is a semiconductor element having three terminals of an anode terminal (anode), a cathode terminal (cathode), and a gate terminal (gate). (P anode layer 81, p gate layer 83) and n-type semiconductor layers (n gate layer 82, n cathode layer 84) are stacked on a substrate 80. That is, the thyristor has a pnpn structure. Here, a forward potential (diffusion potential) Vd of a pn junction composed of a p-type semiconductor layer and an n-type semiconductor layer is described as 1.5 V as an example.

Hereinafter, as an example, the reference potential Vsub supplied to the back electrode 91 (see FIGS. 5 and 6) which is a Vsub terminal is set to a high level potential (hereinafter referred to as “H”) at 0 V and the Vga terminal. The power supply potential Vga supplied will be described as −3.3 V as a low level potential (hereinafter referred to as “L”).
The anode of the thyristor is a reference potential Vsub (“H” (0 V)) supplied to the back electrode 91.

An off-state thyristor in which no current flows between the anode and the cathode is turned on (turned on) when a potential lower than the threshold voltage (a negative potential having a large absolute value) is applied to the cathode. Here, the threshold voltage of the thyristor is a value obtained by subtracting the forward potential Vd (1.5 V) of the pn junction from the potential of the gate.
When turned on, the gate of the thyristor becomes a potential close to the potential of the anode terminal. Here, since the anode is set to the reference potential Vsub (“H” (0 V)), the gate is assumed to be 0 V (“H”). Further, the cathode of the thyristor in the on state becomes a potential close to the potential obtained by subtracting the forward potential Vd (1.5 V) of the pn junction from the potential of the anode. Here, since the anode is set to the reference potential Vsub (“H” (0 V)), the cathode of the thyristor in the on state has a potential close to −1.5 V (a negative potential having an absolute value greater than 1.5 V). ) Note that the cathode potential is set in relation to a power supply that supplies current to the thyristor in the on state.

When the thyristor in the on state has a higher potential (a negative potential with a small absolute value, 0 V or a positive potential) than the potential necessary for maintaining the on state (the potential close to −1.5 V described above). , Transition to the off state (turn off).
On the other hand, a potential lower than the potential necessary for maintaining the on state (a negative potential having a large absolute value) is continuously applied to the cathode of the on thyristor, and the current that can maintain the on state (sustain current). Is supplied, the thyristor remains on.

The drive thyristor S is stacked with the light emitting diode LED and connected in series. Therefore, the voltage applied to the cathode (n cathode layer 84) of the drive thyristor S is a voltage obtained by dividing the voltage of the lighting signal φI by the drive thyristor S and the light emitting diode LED. Here, it is assumed that the voltage applied to the light emitting diode LED is −1.7V. The description will be made assuming that −3.3 V is applied to the drive thyristor S when the drive thyristor S is in the OFF state. That is, it is assumed that the lighting signal φI (“Lo” described later) applied when the light emitting diode LED is lit is −5V.
Note that the voltage applied to the light emitting diode LED is changed depending on the light emission wavelength and the amount of light.

Since the thyristor is made of a semiconductor such as GaAs, it emits light between the n gate layer 82 and the p gate layer 83 in the on state. The amount of light emitted by the thyristor is determined by the area of the cathode and the current flowing between the cathode and the anode. Therefore, when the light emission of the thyristor is irradiated onto the photosensitive drum 12, there is a possibility that the image quality of the formed image is adversely affected.
Therefore, in the transfer thyristor T, the area of the cathode is reduced, or the light is shielded by an electrode (the n-ohmic electrode 323 of the transfer thyristor T1 shown in FIGS. 6A and 6B) or the like, thereby shielding the transfer thyristor T. What is necessary is just to suppress unnecessary light irradiated to the photosensitive drum 12 by this light emission.

  On the other hand, since the drive thyristor S is laminated with the light emitting diode LED, the light emitted from the drive thyristor S passes through the light emitting diode LED and is irradiated onto the photosensitive drum 12. That is, the light emitted from the drive thyristor S is superimposed on the light emitted from the light emitting diode LED. In this case, the light emission spectrum of the drive thyristor S and the light emission spectrum of the light emitting diode LED are different in wavelength range, width, and the like. Therefore, when light from the light emission of the drive thyristor S is mixed, the light emission spectrum of the light emitting diode LED is disturbed. . For example, since the emission spectrum of the light emitting diode LED is narrower than that of the drive thyristor S, it is easy to design an optical system in the print head 14 or the like. However, if the emission spectrum of the drive thyristor S is mixed into the emission spectrum of the light emitting diode LED, this benefit cannot be obtained and the image quality of the formed image may be adversely affected.

Therefore, in the first embodiment, a light absorption layer 85 that absorbs light emitted from the drive thyristor S is provided between the drive thyristor S and the light emitting diode LED.
The light absorption layer 85 does not need to absorb 100% of the light emitted from the drive thyristor S. That is, the light absorption layer 85 reduces the amount of light emitted by the drive thyristor S to such an extent that the image quality of the formed image is not adversely affected even when the light emitted from the drive thyristor S is irradiated on the photosensitive drum 12. Anything that can be reduced is acceptable.

<Light absorption layer 85>
FIG. 8 is a diagram illustrating the light absorption layer 85. 8A shows the case where the light absorption layer 85 is a single n-type semiconductor layer 85a, and FIG. 8B shows the case where the light absorption layer 85 is a single p-type semiconductor layer 85b. 8C shows a case where the light absorption layer 85 is composed of a plurality of n-type semiconductor layers 85c and 85d. FIG. 8D shows a case where the light absorption layer 85 is composed of a plurality of p-type semiconductor layers 85e and 85f. FIG. 8E shows a case where the light absorption layer 85 is composed of an n-type semiconductor layer 85g and a p-type semiconductor layer 85h.

The light absorption layer 85 has at least one band gap of the semiconductor layers (n-type semiconductor layers 85a, 85c, 85d, 85g, and p-type semiconductor layers 85b, 85e, 85f, 85h) constituting the light absorption layer 85, so that the drive thyristor It is composed of a semiconductor layer smaller than the band gap corresponding to the wavelength of light emitted by S.
By doing so, the light emitted from the drive thyristor S is absorbed by the semiconductor layer having a smaller band gap than the band gap corresponding to the light emitted from the drive thyristor S in the light absorption layer 85.
Note that the wavelength of light emitted by the drive thyristor S is determined by the band gap of the n gate layer 82 and the p gate layer 83 in the drive thyristor S.

Therefore, for example, when the n gate layer 82 and the p gate layer 83 of the drive thyristor S are made of AlGaAs, the light absorption layer 85 (n-type semiconductor layers 85a, 85c, 85d, 85g, p-type semiconductor layers 85b, 85e, 85f). , 85h) may be GaAs or InGaAs.
For example, when the n gate layer 82 and the p gate layer 83 of the drive thyristor S are made of GaAs, the light absorption layer 85 (n-type semiconductor layers 85a, 85c, 85d, 85g, p-type semiconductor layers 85b, 85e, 85f). , 85h) may be InGaAs or InGaNAs.
Further, for example, when the n gate layer 82 and the p gate layer 83 of the drive thyristor S are made of InGaAs, the light absorption layer 85 (n-type semiconductor layers 85a, 85c, 85d, 85g, p-type semiconductor layers 85b, 85e, 85f). , 85h) may be InGaAs or InGaNAs.

  The thickness of the semiconductor layer (at least one of the n-type semiconductor layers 85a, 85c, 85d, and 85g, and the p-type semiconductor layers 85b, 85e, 85f, and 85h) that absorbs light emitted from the drive thyristor S in the light absorption layer 85. May be set by the amount of light absorption, for example, several nm to several hundred nm.

  A semiconductor layer with a small band gap is more likely to flow current than a semiconductor layer with a large band gap. Therefore, by providing the light absorption layer 85 including a semiconductor layer having a small band gap between the n cathode layer 84 of the drive thyristor S which is a reverse junction (reverse junction) and the p anode layer 86 of the light emitting diode LED. When the light emitting diode LED is turned on, the voltage (rising voltage) applied to the series connection of the drive thyristor S and the light emitting diode LED is reduced.

In addition, the light absorption layer 85 may be comprised with the III-V group material which has a metal characteristic. For example, InNAs, which is a compound of InN and InAs, has a band gap energy that is negative and has metallic properties when the InN composition ratio x is in the range of about 0.1 to about 0.8.
In addition, for example, InNSb has a metal characteristic in which the band gap energy becomes negative when the InN composition ratio x is in the range of about 0.2 to about 0.75.
The III-V group material having such metal characteristics absorbs light generated by the light emission of the drive thyristor S, and the resistance between the drive thyristor S and the light emitting diode LED is reduced due to metallic conductivity. Thereby, when the light emitting diode LED is turned on, the voltage (rising voltage) applied to the serial connection of the drive thyristor S and the light emitting diode LED is further reduced.

  Further, the light absorption layer 85 (at least one of the n-type semiconductor layers 85a, 85c, 85d, and 85g, and the p-type semiconductor layers 85b, 85e, 85f, and 85h) is in contact with the n cathode layer 84 that contacts the driving thyristor S and the light emitting diode LED. It may be a layer having a higher impurity concentration than either one of the p anode layer 86 in contact with the side. Here, “contact” does not mean only the state of direct contact, but is substantially the same as the case of direct contact in operation, such as when an i-type thin film layer sufficiently thinner than the light absorption layer 85 is interposed. Includes a state equivalent to.

When the impurity concentration of the semiconductor layer increases, the number of electrons and holes (free carriers) that can freely move in the semiconductor increases, and light is easily absorbed (free carrier absorption).
In this case, light is absorbed regardless of the band gap of the semiconductor layer. That is, the light to be absorbed has a small wavelength dependency.
For example, the impurity concentration causing free carrier absorption is 1 × 10 ¹⁸ / cm ³ or more. The thickness of a semiconductor layer (at least one of n-type semiconductor layers 85a, 85c, 85d, 85g, and p-type semiconductor layers 85b, 85e, 85f, 85h) that absorbs light emitted from the drive thyristor S in the light absorption layer 85 is: What is necessary is just to set with the amount of light absorption, for example, it is several nm to several hundred nm.

  A semiconductor layer with a high impurity concentration has a lower resistance and a current easily flows than a semiconductor layer with a low impurity concentration. Therefore, by providing the light absorption layer 85 including a semiconductor layer having a high impurity concentration between the n cathode layer 84 of the driving thyristor S and the p anode layer 86 of the light emitting diode LED, which is a reverse junction, the light emitting diode LED is turned on. In this case, the voltage (rising voltage) applied to the series connection of the drive thyristor S and the light emitting diode LED is reduced.

As shown in FIGS. 8A to 8E, the light absorption layer 85 is in contact with (adjacent to) the n cathode layer 84 of the driving thyristor S on the driving thyristor S side, and the light emitting diode LED p on the light emitting diode LED side. In contact with (adjacent to) the anode layer 86.
When the light absorption layer 85 is a single layer, the light absorption layer 85 has the same conductivity type as that of the n cathode layer 84 of the drive thyristor S or light emission, as shown in FIGS. Any p-type having the same conductivity type as the p-anode layer 86 of the diode LED may be used. When the light absorption layer 85 is a plurality of layers having the same conductivity type, the light absorption layer 85 has the same conductivity type as the n cathode layer 84 of the drive thyristor S, as shown in FIGS. Or the same conductivity type as the p anode layer 86 of the light emitting diode LED.
When the light absorption layer 85 is composed of two layers of n-type and p-type, the n-type cathode layer 84 side of the drive thyristor S of the light absorption layer 85 is n-type, as shown in FIG. The p anode layer 86 side of the light emitting diode LED may be p-type. By configuring as shown in FIG. 8E, the rising voltage is further reduced as compared with the configurations of FIGS. 8A to 8D.

That is, in the light absorption layer 85, the layer (n cathode layer 84) constituting the adjacent drive thyristor S and the layer (p anode layer 86) constituting the light emitting diode LED are in direct contact (directly joined). It is preferable that a junction in which a current flows in the same direction is maintained. That is, the light absorption layer 85 is in the opposite direction to the case where the layer (n cathode layer 84) constituting the adjacent drive thyristor S and the layer (p anode layer 86) constituting the light emitting diode LED are in direct contact. It is good to comprise so that the interface used as joining may not increase.
When the interface that forms a reverse junction increases between the n cathode layer 84 of the driving thyristor S and the p anode layer 86 of the light emitting diode LED, the driving thyristor is inhibited when the current flow is interrupted or the light emitting diode LED is turned on. The voltage (rising voltage) applied to the serial connection of S and the light emitting diode LED may increase.

  In other words, when the light absorption layer 85 is composed of a plurality of layers, the drive thyristor S is composed of the layers (n cathode layer 84) constituting the drive thyristor S and the layers constituting the light absorption layer 85. The layer in contact with the layer (n cathode layer 84) having the same conductivity type, and a layer constituting the light emitting diode LED (p anode layer 86) and a plurality of layers constituting the light absorption layer 85 The layer in contact with the layer constituting the light emitting diode LED (p anode layer 86) preferably has the same conductivity type. If this condition is satisfied, the light absorption layer 85 is not limited to two layers, and is constituted by three or four semiconductor layers having an impurity concentration higher than that of the n cathode layer 84 and the p anode layer 86. Also good. By increasing the impurity concentration, the rise voltage is suppressed from increasing even if the reverse junction increases.

(Operation of the light emitting device 65)
Next, the operation of the light emitting device 65 will be described.
As described above, the light emitting device 65 includes the light emitting chips C1 to C40 (see FIGS. 3 and 4).
Since the light emitting chips C1 to C40 are driven in parallel, it is sufficient to describe the operation of the light emitting chip C1.
<Timing chart>
FIG. 9 is a timing chart for explaining operations of the light emitting device 65 and the light emitting chip C.
FIG. 9 shows a timing chart of a portion that controls lighting (non-lighting) of the five light emitting diodes LED1 to LED5 of the light emitting chip C1. In FIG. 9, the light emitting diodes LED1, LED2, LED3, and LED5 of the light emitting chip C1 are turned on, and the light emitting diode LED4 is turned off (not lit).

In FIG. 9, it is assumed that time elapses from time a to time k in alphabetical order. The light emitting diode LED1 is turned on or off in the period T (1), the light emitting diode LED2 is turned on in the period T (2), the light emitting diode LED3 is turned on in the period T (3), and the light emitting diode LED4 is turned on or off in the period T (4). Lighting control (lighting control) is performed. Thereafter, lighting control of the light emitting diodes LED having a number of 5 or more is similarly performed.
Here, the periods T (1), T (2), T (3),... Have the same length, and are referred to as the period T when they are not distinguished from each other.

The first transfer signal φ1 transmitted to the φ1 terminal (see FIGS. 5 and 6) and the second transfer signal φ2 transmitted to the φ2 terminal (see FIGS. 5 and 6) are “H” (0 V) and “L”. ”(−3.3 V). The waveforms of the first transfer signal φ1 and the second transfer signal φ2 are repeated in units of two consecutive periods T (for example, the period T (1) and the period T (2)).
Hereinafter, “H” (0 V) and “L” (−3.3 V) may be abbreviated as “H” and “L”.

The first transfer signal φ1 shifts from “H” (0V) to “L” (−3.3V) at the start time b of the period T (1), and shifts from “L” to “H” at the time f. . Then, at the end time i of the period T (2), the state shifts from “H” to “L”.
The second transfer signal φ2 is “H” (0 V) at the start time b of the period T (1), and shifts from “H” (0 V) to “L” (−3.3 V) at the time e. Then, “L” is shifted to “H” at the end time i of the period T (2).
Comparing the first transfer signal φ1 and the second transfer signal φ2, the second transfer signal φ2 corresponds to the first transfer signal φ1 shifted after the period T on the time axis. On the other hand, in the second transfer signal φ2, in the period T (1), the waveform indicated by the broken line and the waveform in the period T (2) are repeated after the period T (3). The waveform of the period T (1) of the second transfer signal φ2 is different from that after the period T (3) because the period T (1) is a period during which the light emitting device 65 starts operating.

  As will be described later, a set of transfer signals of the first transfer signal φ1 and the second transfer signal φ2 propagates the ON state of the transfer thyristor T in the order of numbers, thereby emitting light having the same number as the transfer thyristor T in the ON state. The diode LED is designated as a target for lighting or non-lighting control (lighting control).

Next, the lighting signal φI1 transmitted to the φI terminal of the light emitting chip C1 will be described. Note that lighting signals φI2 to φI40 are transmitted to the other light emitting chips C2 to C40, respectively. The lighting signal φI1 is a signal having two potentials of “H” (0 V) and “Lo” (−5 V).
Here, the lighting signal φI1 will be described in the lighting control period T (1) for the light emitting diode LED1 of the light emitting chip C1. The lighting signal φI1 is “H” (0 V) at the start time b of the period T (1), and shifts from “H” (0 V) to “Lo” (−5 V) at the time c. Then, “Lo” is shifted to “H” at time d, and “H” is maintained at time e.

The operation of the light emitting device 65 and the light emitting chip C1 will be described according to the timing chart shown in FIG. 9 with reference to FIGS. In the following, the periods T (1) and T (2) for controlling the lighting of the light emitting diodes LED1 and LED2 will be described.
(1) Time a
<Light emitting device 65>
At time a, the reference potential supply unit 160 of the signal generation circuit 110 of the light emitting device 65 sets the reference potential Vsub to “H” (0 V). The power supply potential supply unit 170 sets the power supply potential Vga to “L” (−3.3 V). Then, the power supply line 200a on the circuit board 62 of the light emitting device 65 becomes “H” (0 V) of the reference potential Vsub, and the Vsub terminals of the light emitting chips C1 to C40 become “H”. Similarly, the power supply line 200b becomes “L” (−3.3 V) of the power supply potential Vga, and the Vga terminals of the light emitting chips C1 to C40 become “L” (see FIG. 4). Thereby, each power supply line 71 of the light emitting chips C1 to C40 becomes “L” (see FIG. 5).

  Then, the transfer signal generation unit 120 of the signal generation circuit 110 sets the first transfer signal φ1 and the second transfer signal φ2 to “H” (0 V), respectively. Then, the first transfer signal line 201 and the second transfer signal line 202 become “H” (see FIG. 4). Accordingly, the φ1 terminal and the φ2 terminal of each of the light emitting chips C1 to C40 become “H”. The potential of the first transfer signal line 72 connected to the φ1 terminal via the current limiting resistor R1 also becomes “H”, and the second transfer signal line 73 connected to the φ1 terminal via the current limiting resistor R2 is also set. It becomes “H” (see FIG. 5).

  Further, the lighting signal generator 140 of the signal generation circuit 110 sets the lighting signals φI1 to φI40 to “H” (0 V), respectively. Then, the lighting signal lines 204-1 to 204-40 become “H” (see FIG. 4). Thereby, each φI terminal of the light emitting chips C1 to C40 becomes “H” via the current limiting resistor RI, and the lighting signal line 75 connected to the φI terminal also becomes “H” (0 V) (FIG. 5). reference).

<Light emitting chip C1>
Since the anode terminals of the transfer thyristor T and the drive thyristor S are connected to the Vsub terminal, they are set to “H”.

  The cathodes of the odd-numbered transfer thyristors T1, T3, T5,... Are connected to the first transfer signal line 72 and set to “H” (0 V). The cathodes of the even-numbered transfer thyristors T2, T4, T6,... Are connected to the second transfer signal line 73 and set to “H”. Therefore, the transfer thyristor T is in the off state because both the anode and the cathode are “H”.

  The cathode terminal of the light emitting diode LED is connected to the lighting signal line 75 of “H” (0 V). That is, the light emitting diode LED and the drive thyristor S are connected in series via the light absorption layer 85. Since the cathode of the light emitting diode LED is “H” and the anode of the driving thyristor S is “H”, the light emitting diode LED and the driving thyristor S are in the off state.

  As described above, the gate Gt1 is connected to the cathode of the start diode SD. The gate Gt1 is connected to the power supply line 71 of the power supply potential Vga (“L” (−3.3 V)) via the power supply line resistance Rg1. The anode terminal of the start diode SD is connected to the second transfer signal line 73, and is connected to the φ2 terminal of “H” (0 V) via the current limiting resistor R2. Therefore, the start diode SD is forward-biased, and the cathode (gate Gt1) of the start diode SD has the pn junction forward potential Vd (1.5 V) from the anode potential (“H” (0 V)) of the start diode SD. The value obtained by subtracting (−1.5 V). When the gate Gt1 becomes −1.5V, the coupling diode D1 has an anode (gate Gt1) of −1.5V and a cathode connected to the power supply line 71 (“L” (−3.3V) via the power supply line resistance Rg2. )), It is forward biased. Therefore, the potential of the gate Gt2 is −3 V obtained by subtracting the forward potential Vd (1.5 V) of the pn junction from the potential (−1.5 V) of the gate Gt1. However, the gates Gt numbered 3 or more are not affected by the fact that the anode of the start diode SD is “H” (0 V), and the potential of these gates Gt is “L” which is the potential of the power supply line 71. (-3.3V).

  Since the gate Gt is the gate Gs, the potential of the gate Gs is the same as the potential of the gate Gt. Therefore, the threshold voltages of the transfer thyristor T and the drive thyristor S are values obtained by subtracting the forward potential Vd (1.5 V) of the pn junction from the potentials of the gates Gt and Gs. That is, the threshold voltage of the transfer thyristor T1 and the drive thyristor S1 is −3 V, the threshold voltage of the transfer thyristor T2 and the drive thyristor S2 is −4.5 V, the threshold voltage of the transfer thyristor T and the drive thyristor S having the number 3 or more. Is -4.8V.

(2) Time b
At time b shown in FIG. 9, the first transfer signal φ1 shifts from “H” (0 V) to “L” (−3.3 V). As a result, the light emitting device 65 starts operating.
When the first transfer signal φ1 shifts from “H” to “L”, the potential of the first transfer signal line 72 is changed from “H” (0 V) to “L” (−) via the φ1 terminal and the current limiting resistor R1. 3.3V). Then, the transfer thyristor T1 having a threshold voltage of −3V is turned on. However, an odd-numbered transfer thyristor T having a cathode terminal connected to the first transfer signal line 72 and having an odd number of 3 or more cannot be turned on because the threshold voltage is −4.8V. On the other hand, the even-numbered transfer thyristor T cannot be turned on because the second transfer signal φ2 is “H” (0 V) and the second transfer signal line 73 is “H” (0 V).
When the transfer thyristor T1 is turned on, the potential of the first transfer signal line 72 is −1.5 V obtained by subtracting the forward potential Vd (1.5 V) of the pn junction from the anode potential (“H” (0 V)). become.

When the transfer thyristor T1 is turned on, the potential of the gate Gt1 / Gs1 becomes “H” (0 V) that is the potential of the anode of the transfer thyristor T1. Then, the potential of the gate Gt2 (gate Gs2) is −1.5 V, the potential of the gate Gt3 (gate Gs3) is −3 V, and the potential of the gate Gt (gate Gl) having a number of 4 or more is “L”.
Thus, the threshold voltage of the drive thyristor S1 is -1.5V, the threshold voltage of the transfer thyristor T2, the drive thyristor S2 is -3V, the threshold voltage of the transfer thyristor T3 and the drive thyristor S3 is -4.5V, and the number is The threshold voltage of four or more transfer thyristors T and drive thyristors S becomes −4.8V.
However, since the first transfer signal line 72 is at −1.5 V by the transfer thyristor T1 in the on state, the odd-numbered transfer thyristor T in the off state is not turned on. Since the second transfer signal line 73 is “H” (0 V), the even-numbered transfer thyristor T is not turned on. Since the lighting signal line 75 is “H” (0 V), none of the light emitting diodes LED is lit.

  Immediately after time b (in this case, when the thyristor or the like is changed due to a change in the signal potential at time b and then enters a steady state), the transfer thyristor T1 is in the on state, The transfer thyristor T, the drive thyristor S, and the light emitting diode LED are in the off state.

(3) Time c
At time c, the lighting signal φI1 shifts from “H” (0 V) to “Lo” (−5 V).
When the lighting signal φI1 shifts from “H” to “Lo”, the lighting signal line 75 shifts from “H” (0 V) to “Lo” (−5 V) via the current limiting resistor RI and the φI terminal. Then, −3.3 V, which is the voltage 1.7 V applied to the light emitting diode LED, is applied to the driving thyristor S1, the driving thyristor S1 having a threshold voltage of −1.5 V is turned on, and the light emitting diode LED1 is turned on. Lights up (emits light). As a result, the potential of the lighting signal line 75 becomes a potential close to −3.2V (a negative potential whose absolute value is larger than 3.2V). The threshold voltage of the drive thyristor S2 is −3V, but the voltage applied to the drive thyristor S2 is −1.5V obtained by adding the voltage 1.7V applied to the light emitting diode LED to −3.2V. Therefore, the drive thyristor S2 is not turned on.
Immediately after time c, the transfer thyristor T1 and the drive thyristor S1 are in the on state, and the light emitting diode LED1 is lit (lights on).
Note that the driving thyristor S1 is in a state in which the transfer thyristor T1 is turned on at the time b, so that the driving thyristor S1 can be turned on.

(4) Time d
At time d, the lighting signal φI1 shifts from “Lo” (−5V) to “H” (0V).
When the lighting signal φI1 shifts from “Lo” to “H”, the potential of the lighting signal line 75 shifts from −3.2 V to “H” via the current limiting resistor RI and the φI terminal. Then, since both the cathode of the light emitting diode LED1 and the anode of the driving thyristor S1 are set to “H”, the driving thyristor S1 is turned off and the light emitting diode LED1 is turned off (not lit). During the lighting period of the light emitting diode LED1, the lighting signal φI1 from the time c when the lighting signal φI1 shifts from “H” to “Lo” until the time d when the lighting signal φI1 shifts from “Lo” to “H” is “ Lo ”(−5V).
Immediately after time d, the transfer thyristor T1 is in the ON state.

(5) Time e
At time e, the second transfer signal φ2 shifts from “H” (0 V) to “L” (−3.3 V). Here, the period T (1) for controlling the lighting of the light emitting diode LED1 ends, and the period T (2) for controlling the lighting of the light emitting diode LED2 starts.
When the second transfer signal φ2 shifts from “H” to “L”, the potential of the second transfer signal line 73 shifts from “H” to “L” via the φ2 terminal. As described above, the transfer thyristor T2 is turned on because the threshold voltage is -3V. As a result, the potential of the gate terminal Gt2 (gate terminal Gs2) becomes “H” (0 V), the potential of the gate Gt3 (gate Gs3) becomes −1.5 V, and the potential of the gate Gt4 (gate Gs4) becomes −3 V. Then, the potential of the gate Gt (gate Gs) having a number of 5 or more becomes −3.3V.
Immediately after time e, the transfer thyristors T1 and T2 are in the on state.

(6) Time f
At time f, the first transfer signal φ1 shifts from “L” (−3.3 V) to “H” (0 V).
When the first transfer signal φ1 shifts from “L” to “H”, the potential of the first transfer signal line 72 shifts from “L” to “H” via the φ1 terminal. Then, the transfer thyristor T1 in the on state is turned off because both the anode and the cathode become “H”. Then, the potential of the gate Gt1 (gate Gs1) changes toward the power supply potential Vga (“L” (−3.3 V)) of the power supply line 71 via the power supply line resistance Rg1. As a result, the coupling diode D1 is in a state in which a potential is applied in a direction in which no current flows (reverse bias). Therefore, the influence of the gate Gt2 (gate Gs2) being “H” (0 V) does not reach the gate Gt1 (gate Gs1). That is, in the transfer thyristor T having the gate Gt connected by the reverse-biased coupling diode D, the threshold voltage becomes −4.8V, and the first transfer signal φ1 of “L” (−3.3V) The 2 transfer signal φ2 does not turn on.
Immediately after time f, the transfer thyristor T2 is in the ON state.

(7) Others At time g, when the lighting signal φI1 shifts from “H” (0V) to “Lo” (−5V), the drive thyristor S1 is turned on similarly to the drive thyristor S1 and the light emitting diode LED1 at time c. Then, the light emitting diode LED2 is turned on (emits light).
Then, when the lighting signal φI1 shifts from “Lo” (−5V) to “H” (0V) at time h, the drive thyristor S2 is turned off similarly to the drive thyristor S1 and the light emitting diode LED1 at time d. The light emitting diode LED2 is turned off.
Further, when the first transfer signal φ1 shifts from “H” (0V) to “L” (−3.3V) at time i, similarly to the transfer thyristor T1 at time b or the transfer thyristor T2 at time e. The transfer thyristor T3 having a threshold voltage of -3V is turned on. At time i, the period T (2) for controlling the lighting of the light emitting diode LED2 ends, and the period T (3) for controlling the lighting of the light emitting diode LED3 starts.
Thereafter, the above description is repeated.

  When the light-emitting diode LED is not turned on (emitted) but remains turned off (non-lighted), the lighting signal shown from the time j to the time k in the period T (4) for controlling the lighting of the light-emitting diode LED4 in FIG. As with φI1, the lighting signal φI may remain “H” (0 V). By doing so, even if the threshold voltage of the drive thyristor S4 is −1.5 V, the drive thyristor S4 is not turned on, and the light emitting diode LED4 remains off (not lit).

As described above, the gate terminals Gt of the transfer thyristors T are connected to each other by the coupling diode D. Therefore, when the potential of the gate Gt changes, the potential of the gate Gt connected to the gate Gt whose potential has changed via the forward-biased coupling diode D changes. Then, the threshold voltage of the transfer thyristor T having the gate whose potential has changed changes. When the threshold voltage of the transfer thyristor T is higher than “L” (−3.3 V) (a negative value having a small absolute value), the first transfer signal φ1 or the second transfer signal φ2 is changed from “H” (0 V). Turns on at the timing of shifting to “L” (−3.3 V).
Since the threshold voltage of the drive thyristor S in which the gate Gs is connected to the gate Gt of the transfer thyristor T in the ON state is −1.5 V, the lighting signal φI changes from “H” (0 V) to “Lo” ( −5V), the light-emitting diode LED connected in series with the drive thyristor S is turned on (emits light).

That is, when the transfer thyristor T is turned on, the light emitting diode LED that is the object of lighting control is designated, and the lighting signal φI of “Lo” (−5V) is in series with the light emitting diode LED that is the object of lighting control. The connected drive thyristor S is turned on and the light emitting diode LED is turned on.
Note that the lighting signal φI of “H” (0 V) keeps the drive thyristor S in the off state and keeps the light emitting diode LED unlit. That is, the lighting signal φI sets lighting / non-lighting of the light emitting diode LED.
In this way, the lighting signal φI is set according to the image data to control lighting or non-lighting of each light emitting diode LED.

  As described above, in the light emitting chip C according to the first embodiment, the drive thyristor S and the light emitting diode LED are stacked. Thereby, the light emitting chip C becomes a self-scanning type in which the light emitting diodes LED are sequentially turned on by the transfer thyristor T and the drive thyristor S. Thereby, the number of terminals provided on the light emitting chip C is reduced, and the light emitting chip C and the light emitting device 65 are reduced in size.

  The light emitting diode LED may not be provided on the driving thyristor S, and the driving thyristor S may be used as a light emitting element. That is, light emission at the junction between the n gate layer 82 and the p gate layer 83 in the ON state of the drive thyristor S may be used. In this case, the transfer characteristic and the light emission characteristic cannot be set separately (independently). For this reason, it is difficult to achieve high-speed driving, high light output, high efficiency, low power consumption, low cost, and the like.

  For example, it is assumed that a thyristor (driving thyristor S) is used as a light emitting element and light of 780 nm is extracted. In this case, if an AlGaAs is used to form a quantum well structure, the Al composition will be 30%. In this case, if etching is performed to expose the p-gate layer 83, Al is oxidized and a gate terminal (such as the p-ohmic electrode 331 in FIG. 7) cannot be formed.

  On the other hand, in the first embodiment, light is emitted by the light emitting diode LED, and the transfer is performed by the transfer thyristor T and the drive thyristor S. Light emission and transfer are separated. The drive thyristor S does not need to emit light. Therefore, it is possible to improve the light emission characteristics by using the light emitting diode LED as a quantum well structure, and improve the transfer characteristics by the transfer thyristor T and the drive thyristor S. That is, the light emitting diode LED of the light emitting unit 102 and the transfer thyristor T and the drive thyristor S of the transfer unit 101 can be set separately (independently). As a result, it is easy to achieve high speed driving, high light output, high efficiency, low power consumption, low cost, and the like.

In the first embodiment, the light emitting diode LED and the drive thyristor S are stacked via the light absorption layer 85. In this case, the n cathode layer 84 of the drive thyristor S and the p anode layer 86 of the light emitting diode LED are reversely biased when directly stacked. However, as described above, since the light absorption layer 85 easily allows current to flow, stacking the driving thyristor S and the light emitting diode LED via the light absorption layer 85 facilitates current flow.
If the light absorption layer 85 is not provided, a voltage higher than the voltage at which the reverse-biased junction breaks down is applied in order to pass a current through the series connection of the drive thyristor S and the light emitting diode LED. That is, the drive voltage becomes high.
That is, by laminating the light emitting diode LED and the drive thyristor S via the light absorption layer 85, the drive voltage can be suppressed lower than when the light absorption layer 85 is not interposed.

Further, the light absorption layer 85 reduces the light from the drive thyristor S to such an extent that the light from the drive thyristor S is absorbed or does not affect image formation even if the drive thyristor S emits light. Therefore, the drive thyristor S may emit light.
The current confinement layer 86b provided in the p anode layer 86 of the light emitting diode LED may be provided in the n cathode layer 88 of the light emitting diode LED.

  Below, the modification of the light emitting chip C which concerns on 1st Embodiment is demonstrated. In the modification shown below, the part which laminated | stacked the drive thyristor S and light emitting diode LED in the island 301 of the light emitting chip C differs. Since other configurations are the same as those of the light-emitting chip C described so far, different portions will be described, and description of similar portions will be omitted.

(Modification 1-1 of the light-emitting chip C according to the first embodiment)
FIG. 10 is an enlarged cross-sectional view of an island 301 in which a drive thyristor S and a light emitting diode LED are described for explaining the modified example 1-1.
In Modification 1-1, a current confinement layer (current confinement layer 81 b in Modification 1-1) is provided in the p anode layer 81 instead of the p anode layer 86. That is, the p anode layer 81 includes a lower p layer 81a, a current confinement layer 81b, and an upper p layer 81c. Other configurations are the same as those of the light-emitting chip C according to the first embodiment.

Also in the light-emitting chip C of Modification 1, since the current flow is limited to the current passage part α in the central part of the light-emitting diode LED, the power consumed for non-light-emitting recombination is suppressed, thereby reducing power consumption and light. Extraction efficiency is improved.
The current confinement layer 81b provided in the p anode layer 81 of the drive thyristor S may be provided in the n cathode layer 84 of the drive thyristor S.

(Modification 1-2 of the light emitting chip C according to the first embodiment)
FIG. 11 is an enlarged cross-sectional view of an island 301 in which a drive thyristor S and a light-emitting diode LED are stacked for explaining a modified example 1-2.
In Modification 1-2, the light absorption layer 85 is provided in a portion corresponding to the current passage portion α instead of the current confinement layer 86b. Other configurations are the same as those of the light-emitting chip C according to the first embodiment.
As described above, the light absorption layer 85 tends to flow current in a reverse bias state. However, in the junction between the n cathode layer 84 and the p anode layer 86 without the light absorption layer 85, a current hardly flows in a reverse bias state where no breakdown occurs.
Therefore, when the light absorption layer 85 is provided in the portion corresponding to the current passage portion α, the current flowing through the light emitting diode LED is limited to the central portion.

  In FIG. 11, the p anode layer 86 is provided so as to fill the periphery of the light absorption layer 85. However, instead of the p anode layer 86, the periphery of the light absorption layer 85 may be filled with the n cathode layer 84.

  The light-emitting chip C of Modification 1-2 may be applied when using a semiconductor material to which steam oxidation is difficult to apply.

[Second Embodiment]
In the light-emitting chip C according to the second embodiment, the light-emitting layer 87 in the light-emitting diode LED is sandwiched between two distributed Bragg reflectors (DBR: Distributed Bragg Reflector) (hereinafter referred to as a DBR layer). The DBR layer is configured by stacking a plurality of semiconductor layers having a difference in refractive index. The DBR layer is configured to reflect light from the light emitting diode LED.
The configuration other than the island 301 in which the driving thyristor S and the light emitting diode LED in the light emitting chip C are stacked is the same as that of the first embodiment. Therefore, a different part is demonstrated and description of the same part is abbreviate | omitted.

FIG. 12 is an enlarged cross-sectional view of an island 301 in which the drive thyristor S and the light emitting diode LED of the light emitting chip C according to the second embodiment are stacked.
In the light emitting chip C according to the second embodiment, the p anode layer 86 and the n cathode layer 88 are configured as DBR layers. The p anode layer 86 includes a current confinement layer 86b. That is, the p anode layer 86 is laminated in the order of the lower p layer 86a, the current confinement layer 86b, and the upper p layer 86c, and the lower p layer 86a and the upper p layer 86c are configured as DBR layers.
The lower p layer 86a, the upper p layer 86c, and the n cathode layer 88 may be referred to as a lower pDBR layer 86a, an upper pDBR layer 86c, and an n cathode (nDBR) layer 88. In the figure, they are expressed as pDBR and nDBR.

The DBR layer is composed of, for example, a combination of a low refractive index layer having a high Al composition such as Al _0.9 Ga _0.1 As and a high refractive index layer having a low Al composition such as Al _0.2 Ga _0.8 As. ing. The film thickness (optical path length) of each of the low refractive index layer and the high refractive index layer is set to 0.25 (1/4) of the center wavelength, for example. In addition, you may change the composition ratio of Al of a low refractive index layer and a high refractive index layer in the range of 0-1.
Note that the film thickness (optical path length) of the current confinement layer 86b is determined by the structure employed. When importance is attached to the extraction efficiency and process reproducibility, it is preferable to set it to an integral multiple of the film thickness (optical path length) of the low refractive index layer and high refractive index layer constituting the DBR layer. .75 (3/4). In the case of an odd multiple, the current confinement layer 86b is preferably sandwiched between the high refractive index layer and the high refractive index layer. In the case of an even multiple, the current confinement layer 86b is preferably sandwiched between a high refractive index layer and a low refractive index layer. In other words, the current confinement layer 86b is preferably provided so as to suppress the disturbance of the refractive index period caused by the DBR layer. Conversely, when it is desired to reduce the influence (refractive index and strain) of the oxidized portion, the thickness of the current confinement layer 86b is preferably several tens of nm, and is inserted into the standing wave node standing in the DBR layer. Preferably it is done.

  In FIG. 12, the lower p layer 86a and upper p layer 86c of the p anode layer 86, and the n cathode layer 88 are formed as DBR layers. However, the lower p layer 86a and upper p layer 86a of the p anode layer 86 are formed. A part of the semiconductor layer such as one of the p layer 86c and a part of the n cathode layer 88 in the thickness direction may be a DBR layer. The same applies to other cases.

The p anode (pDBR) layer 86 and the n cathode (nDBR) layer 88 constitute a resonator (cavity), and light from the light emitting layer 87 is enhanced by resonance and output. That is, in the light emitting chip C according to the second embodiment, the resonance type light emitting diode LED is stacked on the drive thyristor S.
Since the current confinement layer 86b is provided, the power consumed for non-radiative recombination is suppressed, and the power consumption is reduced and the light extraction efficiency is improved.

  In the light emitting chip C according to the second embodiment, the light from the drive thyristor S is absorbed or reduced by the light absorption layer 85 and reflected by the p anode (pDBR) layer 86. It is suppressed that the light by the light emission of the thyristor S is mixed into the light emission spectrum of the light emitting diode LED.

  The light emitting chip C according to the second embodiment operates in accordance with the timing chart of FIG. 9 in the same manner as the light emitting chip C according to the first embodiment.

  The current confinement layer 86b provided in the p anode (pDBR) layer 86 of the light emitting diode LED may be provided in the n cathode (nDBR) layer 88 of the light emitting diode LED, and the p anode layer 81 or the n cathode of the driving thyristor S. It may be provided in the layer 84.

  Below, the modification of the light emitting chip C which concerns on 2nd Embodiment is demonstrated. In the modification shown below, the part which laminated | stacked the drive thyristor S and light emitting diode LED in the island 301 of the light emitting chip C differs. Since other configurations are the same as those of the light-emitting chip C described so far, description of similar parts is omitted, and different parts will be described.

(Modification 2-1 of the light-emitting chip C according to the second embodiment)
FIG. 13 is an enlarged cross-sectional view of an island 301 in which a drive thyristor S and a light-emitting diode LED are stacked for explaining the modification 2-1.
In Modification 2-1, the p anode (pDBR) layer 86 of the light emitting chip C shown in FIG. 12 is a p anode layer 86 that is not a DBR layer, and the p anode layer 81 is a DBR layer instead. Therefore, the p anode layer 81 is referred to as a p anode (pDBR) layer 81. Other configurations are the same as those of the light-emitting chip C according to the second embodiment.

In the modified example 2-1, the p anode (pDBR) layer 81 and the n cathode (nDBR) layer 88 constitute a resonator (cavity), and light from the light emitting layer 87 is enhanced by resonance and output. Here, the light emission wavelength of the light emitting diode LED is a wavelength that the light absorption layer 85 does not absorb, and resonates between the p anode (pDBR) layer 81 and the n cathode (nDBR) layer 88. On the other hand, the wavelength of light from the drive thyristor S is a wavelength that is absorbed by the light absorption layer 85 and is absorbed by the light absorption layer 85.
That is, the light from the drive thyristor S is suppressed from being mixed into the emission spectrum of the light emitting diode LED.

The current confinement layer 86b provided in the p anode layer 86 of the light emitting diode LED may be provided in the n cathode (nDBR) layer 88 of the light emitting diode LED, or the p anode (pDBR) layer 81 or the n cathode of the driving thyristor S. It may be provided in the layer 84.
Furthermore, current confinement may be performed by the light absorption layer 85 as in the modification 1-2 (see FIG. 11) of the light-emitting chip C according to the first embodiment.

(Modification 2-2 of Light-Emitting Chip C According to Second Embodiment)
FIG. 14 is an enlarged cross-sectional view of an island 301 in which a drive thyristor S and a light-emitting diode LED are stacked for explaining a modified example 2-2.
In the modified example 2-2, the n cathode (nDBR) layer 88 of the light emitting chip C shown in FIG. 12 is an n cathode layer 88 that is not a DBR layer. Other configurations are the same as those of the light-emitting chip C according to the second embodiment.

In the light emitting chip C of Modification 2-2, a p anode (pDBR) layer 86 is provided below the light emitting layer 87 (substrate 80). In this case, since a reflectance of 30% is obtained at the interface between the n cathode layer 88 and air, the light from the light emitting layer 87 is enhanced by resonance and output.
Of the light from the light emitting layer 87, light directed toward the substrate 80 is reflected and travels toward the exit port. Therefore, the light utilization efficiency is improved as compared with the case where the p anode layer 86 is not a DBR layer.

The current confinement layer 86b provided in the p anode (pDBR) layer of the light emitting diode LED may be provided in the n cathode layer 88 of the light emitting diode LED, or provided in the p anode layer 81 or the n cathode layer 84 of the drive thyristor S. May be.
Furthermore, current confinement may be performed by the light absorption layer 85 as in the modification 1-2 (see FIG. 11) of the light-emitting chip C according to the first embodiment.

[Third Embodiment]
In the light emitting chip C according to the third embodiment, a laser diode is used as an example of a light emitting element instead of the light emitting diode LED in the first embodiment and the second embodiment.
Except for the light emitting chip C, other configurations are the same as those of the first embodiment. Therefore, the light emitting chip C will be described, and description of similar parts will be omitted.

FIG. 15 is an equivalent circuit diagram illustrating a circuit configuration of a light-emitting chip C on which a self-scanning light-emitting element array (SLED) according to the third embodiment is mounted. The light-emitting diodes LED1 to LED128 of FIG. 5 in the first embodiment are laser diodes LD1 to LD128 (in the case where they are not distinguished, they are expressed as laser diodes LD). The other configuration is the same as that shown in FIG.
In the first embodiment, the light emitting diode LED may be replaced with the laser diode LD also in the plan layout view and the cross-sectional view of the light emitting chip C shown in FIG. Therefore, a plan layout view and a cross-sectional view of the light-emitting chip C according to the third embodiment are omitted.

In the light emitting chip C according to the third embodiment, the drive thyristor S and the laser diode LD are stacked.
In the laser diode LD, the light emitting layer 87 is sandwiched between two clad layers (hereinafter referred to as clad layers). The cladding layer is a layer having a refractive index larger than that of the light emitting layer 87. Light from the light emitting layer 87 is reflected at the interface between the light emitting layer 87 and the cladding layer, and the light is confined in the light emitting layer 87. Then, the laser is oscillated by resonating with a resonator formed between the side surfaces of the light emitting layer 87. The light emitting layer 87 may be referred to as an active layer.

FIG. 16 is an enlarged cross-sectional view of an island 301 in which the drive thyristor S and the laser diode LD of the light emitting chip C according to the third embodiment are stacked.
In the light emitting chip C, the p anode layer 86 is formed of a p-type cladding layer including the current confinement layer 86b. That is, in the p anode layer 86, the lower p layer 86a and the upper p layer 86c are configured as cladding layers. The n cathode layer 88 is configured as a cladding layer. The lower p layer 86a, the upper p layer 86c, and the n cathode layer 88 may be referred to as a lower p cladding layer 86a, an upper p cladding layer 86c, and an n cathode (n cladding) layer 88. The p anode layer 86 as a whole may be referred to as a p anode (p clad) layer 86. In the figure, they are expressed as p-clad and n-clad.

The lower p-cladding layer 86a and the upper p-cladding layer 86c of the p-anode (p-cladding) layer 86 are, for example, p-type Al _0.9 GaAs with an impurity concentration of 5 × 10 ¹⁷ / cm ³ . You may change Al composition in the range of 0-1. GaInP or the like may be used.
The n cathode (n clad) layer 88 is, for example, n-type Al _0.9 GaAs having an impurity concentration of 5 × 10 ¹⁷ / cm ³ . You may change Al composition in the range of 0-1. GaInP or the like may be used.

The p anode is configured so that light from the light emitting layer 87 is confined between the p anode (p clad) layer 86 and the n cathode (n clad) layer 88 and laser is oscillated between the side surfaces (end faces) of the light emitting layer 87. A (p clad) layer 86, an n cathode (n clad) layer 88, and a light emitting layer 87 are set. In this case, the light is emitted from the side surface (end surface) of the light emitting layer 87.
Therefore, the n ohmic electrode 321 is provided on the entire surface of the n cathode (n clad) layer 88.

  In FIG. 16, the light emission direction is the direction orthogonal to the y direction, that is, the −x direction shown in FIG. This is for convenience of explanation, and may be emitted in the -y direction. Further, it may be directed in a direction perpendicular to the substrate 80 via a mirror or the like. The same applies to the other light emitting chips C and the modified examples.

  Since the current confinement layer 86b is provided and the power consumed for non-radiative recombination is suppressed, the power consumption is reduced and the light extraction efficiency is improved.

  The light emitting chip C according to the third embodiment operates in accordance with the timing chart shown in FIG. 9, similarly to the light emitting chip C according to the first embodiment.

  The current confinement layer 86b provided in the p anode (p clad) layer 86 of the laser diode LD may be provided in the n cathode (n clad) layer 88 of the laser diode LD, or the p anode layer 81 of the drive thyristor S or The n cathode layer 84 may be provided.

  Below, the modification of the light emitting chip C which concerns on 3rd Embodiment is demonstrated. In the modification shown below, the portion where the drive thyristor S and the laser diode LD are stacked in the island 301 of the light emitting chip C is different. Since other configurations are the same as those of the light-emitting chip C described so far, different portions will be described, and description of similar portions will be omitted.

(Variation 3-1 of Light-Emitting Chip C According to Third Embodiment)
FIG. 17 is an enlarged cross-sectional view of an island 301 in which a drive thyristor S and a laser diode LD for explaining a modification 3-1 are stacked.
In Modification 3-1, similarly to Modification 1-2 in the first embodiment shown in FIG. 11, instead of the current confinement layer 86b, the light absorption layer 85 is provided in a portion corresponding to the current passage portion α. Is provided. Other configurations are the same as those of the light-emitting chip C according to the first embodiment.
As described above, the light absorption layer 85 easily flows current. However, the junction between the n cathode layer 84 and the p anode layer 86 hardly flows current in a reverse bias state where no breakdown occurs.
Therefore, when the light absorption layer 85 is provided in a portion corresponding to the current passing portion α in the central portion of the laser diode LD, the current flowing through the laser diode LD is limited to the central portion of the laser diode LD.

(Variation 3-2 of Light-Emitting Chip C According to Third Embodiment)
FIG. 18 is an enlarged cross-sectional view of an island 301 in which a drive thyristor S and a laser diode LD are stacked for explaining a modified example 3-2.
In the modified example 3-2, as in the modified example 2-2 of the light-emitting chip C according to the second embodiment, the lower p-cladding layer 86a and the upper p-cladding layer 86c of the p anode (p-cladding) layer 86 are formed. The DBR layer (pDBR clad) is used. Other configurations are the same as those of the light-emitting chip C according to the third embodiment.

  If a semiconductor material having a band gap smaller than the band gap corresponding to the wavelength oscillated by the laser diode LD is used for the light absorption layer 85, the light reaching the light absorption layer 85 is absorbed at the band edge and lost. For this reason, in Modification 3-1, a DBR layer is provided between the light emitting layer 87 and the light absorption layer 85, and the light absorption layer 85 is provided at a position corresponding to a node of a standing wave generated in the DBR layer. By doing in this way, band edge absorption by the semiconductor material used for the light absorption layer 85 is significantly suppressed.

  The current confinement layer 86b provided in the p anode (p clad) layer 86 of the laser diode LD may be provided in the n cathode (n clad) layer 88 of the laser diode LD, or the p anode layer 81 of the drive thyristor S or The n cathode layer 84 may be provided.

(Variation 3-3 of Light-Emitting Chip C According to Third Embodiment)
FIG. 19 is an enlarged cross-sectional view of an island 301 in which a drive thyristor S and a laser diode LD for explaining a modified example 3-3 are stacked.
In Modification 3-3, the current confinement layer 86b in the light-emitting chip C according to the third embodiment is not used. Instead, the surface area of the n cathode (n clad) layer 88 is reduced. Other configurations are the same as those of the light-emitting chip C according to the first embodiment.
Such a structure is the same as that of the ridge-type waveguide.

  By doing so, the current flowing through the laser diode LD flows from the n cathode (n clad) layer 88. Therefore, as shown in FIG. 19, the central portion of the laser diode LD is the current passage portion (region) α ′, and the peripheral portion is the current blocking portion (region) β ′. That is, the light emitting chip C according to the third embodiment using the current confinement layer 86b (see FIG. 16) and the modified example 3-1 using the light absorption layer 85 at the center of the laser diode LD (see FIG. 17). ), The current path is narrowed.

Since the modification 3-3 does not use the current confinement layer 86b, the manufacturing process is simplified.
In addition, since the configuration of the modification 3-3 does not use the current confinement layer 86b, it can be easily applied to a semiconductor material on a substrate such as InP, GaN, or sapphire that is difficult to apply steam oxidation.

(Modification 3-4 of Light-Emitting Chip C According to Third Embodiment)
FIG. 20 is an enlarged cross-sectional view of an island 301 in which a drive thyristor S and a laser diode LD are stacked to explain Modification 3-4.
In Modification 3-4, an n cathode (n cladding) layer 92 is provided on the light emitting layer 87 of Modification 3-3, and an n cathode (n cladding) layer 88 having a reduced area is provided. A p anode (p clad) layer 93 similar to the p anode (p clad) layer 86 is embedded around the n cathode (n clad) layer 88. Other configurations are the same as those of the light-emitting chip C according to the first embodiment.
Since the n cathode (n clad) layer 88, the n cathode (n clad) layer 92, and the p anode (p clad) layer 93 form a pn junction, the current flows to the n cathode (n clad) layer 88 side. Limited. Therefore, similarly to the case where the current confinement layer is provided, the power consumed for non-radiative recombination is suppressed, and the power consumption is reduced and the light extraction efficiency is improved.
Such a structure is similar to the buried waveguide.

  Modification 3-4 does not use the current confinement layer 86b in the light-emitting chip C (see FIG. 18) according to the third embodiment, and therefore, a semiconductor on a substrate such as InP, GaN, or sapphire that is difficult to apply steam oxidation. Easy to apply to materials.

[Fourth Embodiment]
In the light emitting chip C according to the fourth embodiment, instead of the light emitting diode LED in the first embodiment and the second embodiment and the laser diode LD in the third embodiment, as an example of the light emitting element. A vertical cavity surface emitting laser (VCSEL) is used.
Except for the light emitting chip C, other configurations are the same as those of the first embodiment. Therefore, the light emitting chip C will be described, and description of similar parts will be omitted.

FIG. 21 is an equivalent circuit diagram for explaining the circuit configuration of the light-emitting chip C on which the self-scanning light-emitting element array (SLED) according to the fourth embodiment is mounted. The light emitting diodes LED1 to LED128 of FIG. 5 in the first embodiment are vertical cavity surface emitting lasers VCSEL1 to VCSEL128 (in the case of not distinguishing, they are expressed as vertical cavity surface emitting lasers VCSEL). The other configuration is the same as that shown in FIG.
In the first embodiment, the light emitting diode LED may be replaced with the vertical cavity surface emitting laser VCSEL in the plan layout view and the cross-sectional view of the light emitting chip C shown in FIG. Therefore, a plan layout view and a cross-sectional view of the light emitting chip C according to the fourth embodiment are omitted.

FIG. 22 is an enlarged cross-sectional view of an island 301 in which the drive thyristor S of the light emitting chip C and the vertical cavity surface emitting laser VCSEL according to the fourth embodiment are stacked.
The driving thyristor S and the vertical cavity surface emitting laser VCSEL are stacked.
The basic configuration is the same as that of the light emitting chip C according to the second embodiment shown in FIG.
The vertical cavity surface emitting laser VCSEL causes laser oscillation by causing light to resonate in a light emitting layer 87 sandwiched between two DBR layers (p anode (pDBR) layer 86 and n cathode (nDBR) layer 88). . When the reflectivity of the two DBR layers (p anode (pDBR) layer 86 and n cathode (nDBR) layer 88) is 99% or more, for example, laser oscillation occurs.
In addition, in a figure, it describes with pDBR and nDBR.

  In the vertical cavity surface emitting laser VCSEL, a p anode (pDBR) layer 86 is provided between the light absorption layer 85 and the light emitting layer 87. For this reason, since light does not reach the light absorption layer 85, the band gap of the light absorption layer 85 is smaller than the band gap corresponding to the wavelength emitted by the drive thyristor S, and the transmission wavelength of the vertical cavity surface emitting laser VCSEL. It may be smaller than the corresponding band gap. Therefore, the resistance of the light absorption layer 85 can be reduced.

  The light emitting chip C according to the fourth embodiment operates in accordance with the timing chart of FIG. 9 in the same manner as the light emitting chip C according to the first embodiment.

  The current confinement layer 86b provided in the p anode (pDBR) layer 86 of the vertical cavity surface emitting laser VCSEL may be provided in the n cathode (nDBR) layer 88 of the vertical cavity surface emitting laser VCSEL, and the drive thyristor S. The p anode layer 81 or the n cathode layer 84 may be provided.

  Below, the modification of the light emitting chip C which concerns on 4th Embodiment is demonstrated. In the modification shown below, the portion where the drive thyristor S and the laser diode LD are stacked in the island 301 of the light emitting chip C is different. Since other configurations are the same as those of the light-emitting chip C described so far, different portions will be described, and description of similar portions will be omitted.

(Modification 4-1 of Light-Emitting Chip C According to Fourth Embodiment)
FIG. 23 is an enlarged cross-sectional view of an island 301 in which a drive thyristor S and a vertical cavity surface emitting laser VCSEL for explaining a modification 4-1 are stacked.
The basic configuration of Modification 4-1 is the same as that of Modification 2-1 of the light-emitting chip C according to the second embodiment shown in FIG.
The vertical cavity surface emitting laser VCSEL causes laser oscillation by resonating light from the light emitting layer 87 between two DBR layers (p anode (pDBR) layer 81 and n cathode (nDBR) layer 88).
Here, it is assumed that the light absorption layer 85 does not absorb (transmits) light oscillated by the vertical cavity surface emitting laser VCSEL and absorbs light from the drive thyristor S.

  The current confinement layer 86b provided in the p anode layer 86 of the vertical cavity surface emitting laser VCSEL may be provided in the n cathode (nDBR) layer 88 of the vertical cavity surface emitting laser VCSEL, and the p anode of the drive thyristor S. The layer 81 or the n cathode layer 84 may be provided.

(Variation 4-2 of Light-Emitting Chip C According to Fourth Embodiment)
FIG. 24 is an enlarged cross-sectional view of an island 301 in which a drive thyristor S and a vertical cavity surface emitting laser VCSEL for explaining a modification 4-2 are stacked.
The basic configuration of Modification 4-2 is that, in Modification 1-2 of the light-emitting chip C according to the first embodiment shown in FIG. 11, the n cathode layer 84 and the n cathode layer 88 are DBR layers. Is. The other configuration is the same as that of Modification 1-2, and thus the description thereof is omitted.
The vertical cavity surface emitting laser VCSEL includes a light emitting layer 87 between two DBR layers (an n cathode (nDBR) layer 84 and an n cathode (nDBR) layer 88) sandwiching the light emitting layer 87 and the p anode layer 86. The laser beam is oscillated by resonating.
Here again, it is assumed that the light absorption layer 85 does not absorb (transmits) light oscillated by the vertical cavity surface emitting laser VCSEL and absorbs light from the drive thyristor S.

Moreover, since the modification 4-2 does not use the current confinement layer 86b in the light-emitting chip C according to the fourth embodiment (see FIG. 22), it is difficult to apply steam oxidation on a substrate such as InP, GaN, or sapphire. Easy to apply to semiconductor materials.
In addition, since the light absorption layer 85 is used for current confinement, power consumed for non-radiative recombination is suppressed, and power consumption is reduced and light extraction efficiency is improved.

  In the first to fourth embodiments, the conductivity types of the light emitting element (light emitting diode LED, laser diode LD, vertical cavity surface emitting laser VCSEL) and thyristor (transfer thyristor T, drive thyristor S) are reversed. In addition, the polarity of the circuit may be changed. That is, the anode common may be the cathode common.

  In order to suppress light emission delay and relaxation oscillation at the time of turn-on of the light emitting element (light emitting diode LED, laser diode LD, vertical cavity surface emitting laser VCSEL), a small current equal to or higher than the threshold current is previously injected into the light emitting element. The light emission state or the oscillation state may be slightly set. That is, the light emitting element is caused to emit light slightly before the drive thyristor S is turned on, and when the drive thyristor S is turned on, the light emission amount of the light emitting element is increased to a predetermined light amount. Also good. As such a configuration, for example, an electrode is formed on the anode layer of a light emitting element (light emitting diode LED, laser diode LD, vertical cavity surface emitting laser VCSEL), and a voltage source or a current source is connected to the electrode. Before the driving thyristor S is turned on, a weak current may be injected from the voltage source or current source into the light emitting element.

Further, in the above, a self-scanning light emitting element array (SLED) composed of light emitting elements (light emitting diode LED, laser diode LD, vertical cavity surface emitting laser VCSEL) and thyristor (transfer thyristor T, drive thyristor S) is used. As described above, the self-scanning light emitting element array (SLED) may include other members such as a control thyristor, a diode, and a resistor in addition to the above.
Further, the transfer thyristors T are connected by the coupling diode D, but may be connected by a member that can transmit a change in potential such as a resistance.

  Further, the structure of the transfer thyristor T and the drive thyristor S in each embodiment may be other than the pnpn four-layer structure as long as it has the functions of the transfer thyristor T and the drive thyristor S in each embodiment. Good. For example, a pinin structure having a thyristor characteristic, a pinin structure, an npip structure, or a pnin structure may be used. In this case, any one of the i layer, the n layer, and the i layer sandwiched between the p and n of the pinin structure and the n layer and the i layer sandwiched between the p and the n of the pinin structure becomes the gate layer, and the gate layer The n-ohmic electrode provided above may be used as the terminal of the gate Gt (gate Gs). Alternatively, the i layer, the p layer, the i layer sandwiched between n and p of the npip structure, and the p layer or the i layer sandwiched between the n and p of the npip structure becomes the gate layer, and the gate layer The p-ohmic electrode provided on the gate may be used as the terminal of the gate Gt (gate Gs).

  Further, in each embodiment, a semiconductor structure in which a plurality of semiconductor layers constituting a thyristor and a plurality of semiconductor layers constituting a light emitting element are stacked via a semiconductor layer constituting a light absorption layer is self-scanning. It can also be used for applications other than the type light emitting element array (SLED). For example, it can be used as a single light-emitting element that is turned on by an external input of an electrical signal, an optical signal, or the like, or as a light-emitting element array other than a self-scanning light-emitting element array.

  In the above description, p-type GaAs has been mainly described as an example of the substrate 80. An example of each semiconductor layer constituting the semiconductor stacked body in the case of using another substrate will be described in the case where it is applied to the light emitting chip C shown in FIG. The light absorption layer 85 is the same as described above.

First, an example of a semiconductor stacked body when a GaN substrate is used is as follows.
The p anode layer 81 is, for example, p-type Al _0.9 GaN having an impurity concentration of 1 × 10 ¹⁸ / cm ³ . You may change Al composition in the range of 0-1.
The n gate layer 82 is, for example, n-type Al _0.9 GaN having an impurity concentration of 1 × 10 ¹⁷ / cm ³ . You may change Al composition in the range of 0-1.
The p gate layer 83 is, for example, p-type Al _0.9 GaN having an impurity concentration of 1 × 10 ¹⁷ / cm ³ . You may change Al composition in the range of 0-1.
The n cathode layer 84 is, for example, n-type Al _0.9 GaN having an impurity concentration of 1 × 10 ¹⁸ / cm ³ . You may change Al composition in the range of 0-1.

When the light absorption layer 85 is a layer whose band gap is smaller than the band gap corresponding to the light emitted by the drive thyristor S, the light absorption layer 85 is a ternary mixed crystal / quaternary mixed crystal whose lattice constant substantially matches that of GaN. Materials can be used. For example, GANP can be used. In addition, (1) InN layer or InGaN layer by metamorphic growth, (2) Quantum dot made of InN, InGaN, InNAs, InNSb, (3) InAsSb layer corresponding to twice the lattice constant (a-plane) of GaN Etc. can also be used. These may include Al, Ga, N, As, P, Sb, and the like. In the case of quantum dots, the lattice constants do not need to match and a binary mixed crystal material may be used.
Further, when the light absorption layer 85 is a layer having a high impurity concentration, for example, any one of n ⁺⁺ GaN, p ⁺⁺ GaN, n ⁺⁺ GaInN, p ⁺⁺ GaInN, n ⁺⁺ AlGaN, and p ⁺⁺ AlGaN is used as the light absorption layer 85. Can be used. For example, n ⁺⁺ or p ⁺⁺ is a high concentration if the impurity concentration is in the range of 1 × 10 ¹⁹ / cm ^{3 to} 3 × 10 ²⁰ / cm ³ .

The p anode layer 86 is formed by sequentially laminating a lower p layer 86a, a current confinement layer 86b, and an upper p layer 86c. The lower p layer 86a and the upper p layer 86c are, for example, p-type Al _0.9 GaN with an impurity concentration of 1 × 10 ¹⁸ / cm ³ . You may change Al composition in the range of 0-1.
Since it is difficult to use the oxidized constriction layer as the current confinement layer on the GaN substrate, the light absorption layer 85, the ridge structure, and the buried structure are used as the current confinement layer in FIGS. 20, 24 and the like are desirable structures. Alternatively, it is effective to use ion implantation as a current confinement method.

  The light emitting layer 87 has a quantum well composition in which well layers and barrier layers are alternately stacked. The well layer is, for example, GaN, InGaN, AlGaN, and the barrier layer is AlGaN, GaN, or the like. The light emitting layer 87 may be a quantum beam (quantum wire) or a quantum box (quantum dot).

The n cathode layer 88 is, for example, n-type Al _0.9 GaN having an impurity concentration of 1 × 10 ¹⁸ / cm ³ . You may change Al composition in the range of 0-1.

Next, an example of a semiconductor stacked body when an InP substrate is used is as follows.
The p anode layer 81 is, for example, p-type InGaAsP having an impurity concentration of 1 × 10 ¹⁸ / cm ³ . You may change Ga composition and Al composition in the range of 0-1.
The n gate layer 82 is, for example, n-type InGaAsP having an impurity concentration of 1 × 10 ¹⁷ / cm ³ . You may change Ga composition and Al composition in the range of 0-1.
The p gate layer 83 is, for example, p-type InGaAsP having an impurity concentration of 1 × 10 ¹⁷ / cm ³ . You may change Ga composition and Al composition in the range of 0-1.
The n cathode layer 84 is, for example, n-type InGaAsP having an impurity concentration of 1 × 10 ¹⁸ / cm ³ . You may change Ga composition and Al composition in the range of 0-1.

When the light absorption layer 85 is a layer having a band gap smaller than the band gap corresponding to the light emitted by the drive thyristor S, the light absorption layer 85 is a compound of InAs having a lattice constant substantially equal to InP or a compound of GaAs and InP. A ternary mixed crystal material / quaternary mixed crystal material such as a compound of InN and InSb or a compound of InN and InAs can be used. In the ternary mixed crystal material / quaternary mixed crystal material, a material having a small band gap energy may be used. In particular, a quaternary mixed crystal material based on GaInNAs is suitable. These may include Al, Ga, As, P, Sb, and the like. Further, (1) InAs layers and InGaAs layers formed by metamorphic growth and the like, and (2) quantum dots made of InAs, InGaAs, InNAs, InNSb, GaSb, GaSbP, and GaSbAs can also be used. These may include Al, Ga, N, As, P, Sb, and the like. In the case of quantum dots, the lattice constants do not need to match and a binary mixed crystal material may be used.
Further, when the light absorption layer 85 is a layer having a high impurity concentration, the light absorption layer 85 may be, for example, n ⁺⁺ InP, p ⁺⁺ InP, n ⁺⁺ InAsP, p ⁺⁺ InAsP, n ⁺⁺ InGaAsP, p ⁺⁺ InGaAsP, n ⁺⁺ InGaAsPSb. , P ⁺⁺ InGaAsPSb can be used. For example, n ⁺⁺ or p ⁺⁺ is a high concentration if the impurity concentration is in the range of 1 × 10 ¹⁹ / cm ^{3 to} 3 × 10 ²⁰ / cm ³ .

The p anode layer 86 is formed by sequentially laminating a lower p layer 86a, a current confinement layer 86b, and an upper p layer 86c. The lower p layer 86a and the upper p layer 86c are, for example, p-type InGaAsP having an impurity concentration of 1 × 10 ¹⁸ / cm ³ . You may change Ga composition and Al composition in the range of 0-1.
Since it is difficult to use the oxide confinement layer as the current confinement layer on the InP substrate, the light absorption layer 85, the ridge type structure, and the buried type structure are used as the current confinement layer. 20, 24 and the like are desirable structures. Alternatively, it is effective to use ion implantation as a current confinement method.

  The light emitting layer 87 has a quantum well composition in which well layers and barrier layers are alternately stacked. The well layer is, for example, InAs, InGaAsP, AlGaInAs, GaInAsPSb, or the like, and the barrier layer is InP, InAsP, InGaAsP, AlGaInAsP, or the like. The light emitting layer 87 may be a quantum beam (quantum wire) or a quantum box (quantum dot).

The n cathode layer 88 is, for example, n-type InGaAsP having an impurity concentration of 1 × 10 ¹⁸ / cm ³ . You may change Ga composition and Al composition in the range of 0-1.

  These semiconductor layers are stacked by, for example, metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), and the like to form a semiconductor stacked body.

DESCRIPTION OF SYMBOLS 1 ... Image forming apparatus, 10 ... Image forming process part, 11 ... Image forming unit, 12 ... Photosensitive drum, 14 ... Print head, 30 ... Image output control part, 40 ... Image processing part, 62 ... Circuit board, 63 ... Light source unit, 64 ... rod lens array, 65 ... light emitting device, 80 ... substrate, 81 ... p anode layer, 81b, 86b ... current confinement layer, 82 ... n gate layer, 83 ... p gate layer, 84 ... n cathode layer, 85: Light absorbing layer, 85a: n ⁺⁺ layer, 85b: p ⁺⁺ layer, 86 ... p anode layer, 87 ... Light emitting layer, 88 ... n cathode layer, 89 ... Light exit port protective layer, 90 ... Protective layer, 91 ... Back electrode 101, transfer unit 102, light emitting unit 110, signal generation circuit 120, transfer signal generation unit 140, lighting signal generation unit 160, reference potential supply unit 170, power supply potential supply unit 301 to 306 ... A Land, φ1 ... first transfer signal, φ2 ... second transfer signal, φI (φI1 to φI40) ... lighting signal, α ... current passing portion (region), β ... current blocking portion (region), C (C1 to C40) ... Light emitting chip, D (D1 to D127) ... Coupling diode, LED (LED1 to LED128) ... Light emitting diode, LD (LD1 to LD128) ... Laser diode, SD ... Start diode, T (T1 to T128) ... Transfer thyristor, VCSEL (VCSEL1 to VCSEL128) ... vertical cavity surface emitting laser, Vga ... power supply potential, Vsub ... reference potential

Claims (7)

A light-emitting element that emits light of a predetermined wavelength;
A driving thyristor that emits light from the light-emitting element by being turned on, or increases the light emission amount of the light-emitting element;
Wherein the light emitting element and the driving thyristor is provided between the light-emitting element and the driving thyristor as laminated, comprising a light-absorbing layer which absorbs light to which the driving thyristor emits light, a
A light-emitting component in which the drive thyristor, the light absorption layer, and the light-emitting element are stacked in that order from the lower layer .   The light-emitting component according to claim 1, wherein the light absorption layer includes a semiconductor layer having a band gap smaller than a band gap corresponding to light emitted from the driving thyristor. Each of the light emitting element and the driving thyristor is configured by laminating a plurality of semiconductor layers,
The light absorption layer has the same conductivity type as any one of the semiconductor layers of the semiconductor layer constituting the light emitting element in contact on the light emitting element side and the semiconductor layer constituting the drive thyristor in contact on the drive thyristor side. The light-emitting component according to claim 1, further comprising: a semiconductor layer having an impurity concentration higher than that of any one of the semiconductor layers. Each of the light emitting element and the driving thyristor is configured by laminating a plurality of semiconductor layers,
The light absorption layer has a direction in which a current easily flows when a semiconductor layer constituting the light emitting element in contact with the light emitting element side and a semiconductor layer constituting the drive thyristor in contact with the drive thyristor are directly joined. emission component according to any one of claims 1 to 3, characterized in that it is configured to be maintained. Each of the light emitting element, the driving thyristor, and the light absorption layer is configured by laminating a plurality of semiconductor layers,
Of the plurality of layers constituting the drive thyristor, the layer in contact with the light absorption layer and the layer in contact with the drive thyristor among the plurality of layers constituting the light absorption layer have the same conductivity type,
The layer in contact with the light absorption layer among the plurality of layers constituting the light emitting element and the layer in contact with the light emission element among the plurality of layers constituting the light absorption layer have the same conductivity type,
Each of the plurality of layers constituting the light absorption layer is a layer in contact with the light absorption layer among the plurality of layers constituting the light emitting element, and the light absorption layer among the plurality of layers constituting the drive thyristor. emission component according to any one of claims 1 to 3, wherein the high impurity concentration than the layer in contact with. A plurality of transfer elements that are sequentially turned on, and a plurality of drive thyristors that are respectively connected to the plurality of transfer elements and that can be shifted to an on state by being turned on; A plurality of light-emitting elements connected to each of the plurality of drive thyristors, and a plurality of light-emitting elements that emit light or emit light when the plurality of drive thyristors are turned on;
Optical means for imaging light emitted from the light emitting means,
The light emitting means includes
The driving thyristor, the light-emitting layer that absorbs light emitted from the driving thyristor, and the light-emitting element are stacked in this order from the lower layer, so that the driving thyristor and the light-emitting element are connected. head. An image carrier,
Charging means for charging the image carrier;
A plurality of transfer elements that are sequentially turned on, and a plurality of drive thyristors that are respectively connected to the plurality of transfer elements and that can be shifted to an on state by being turned on; A plurality of light-emitting elements connected to each of the plurality of drive thyristors and increasing light emission or light emission amount when the plurality of drive thyristors are turned on, and exposing the image carrier via optical means Means,
Developing means for developing the electrostatic latent image exposed by the exposure means and formed on the image carrier;
Transfer means for transferring the image developed on the image holding member to a transfer target,
The exposure means includes
The driving thyristor, the light-emitting layer that absorbs light emitted from the driving thyristor, and the light-emitting element are stacked in this order from the lower layer, so that the driving thyristor and the light-emitting element are connected. Forming equipment.

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