JP6215487B2 - System and method for common level shifting - Google Patents

Description

Cross-reference of related applications

  [0001] This application is filed on March 27, 2014, and is referred to US Provisional Patent Application No. 14 / No. 14/90, entitled “System and Method for Common Mode Level Shifting,” which is incorporated herein by reference in its entirety. Insist on the benefits of 228,049.

  [0002] This application relates to voltage control, and more particularly to common mode voltage level shifting.

  [0003] In differential signal transmission, conversion from a low common mode voltage region to a high common mode voltage region is as usual. For example, the receiver can use a differential pair of NMOS transistors that require a relatively high common mode voltage. However, transmitters or other components of the system may use low common mode voltages.

  [0004] For example, in some high speed wireline applications, the receiver input signal is terminated at a low common mode voltage level, such as 0V or several hundred mV. Even though some applications use PMOS to process higher speed signals (eg 6-10 Gb / s), the NMOS differential pair is generally lower than PMOS due to lower parasitics. desirable. The conversion buffer is used to convert a low common mode voltage high speed signal to a high common mode voltage level.

  [0005] It is normal to receive each differential input signal through a shunt capacitor to perform level shifting for the high common mode region. For example, one actuation input signal can be shown as rxinp (receiver input positive) while a complementary differential input signal can be shown as rxinn (receiver input negative). Rxinp will be received through the shunt capacitor. Similarly, rxinn will also be received via the shunt capacitor. The shunt capacitor then blocks the received common mode voltage so that the received signal is then increased using, for example, a voltage divider to provide the desired relatively high common mode voltage. However, this type of device generally only operates on relatively high frequency differential signals. As the input frequency decreases, the shunt capacitor will not only block the received common mode voltage, but will also block the alternating current (AC) portion of the signal. Therefore, such conventional level shifting devices are not suitable for some broadband applications.

  [0006] Therefore, there is a need for techniques for improved common level shifters that operate in both low and high frequency regions (broadband operation).

  [0007] A circuit for level shifting a common mode voltage is provided. In one example, a circuit applies a level-shifting differential input signal to a pair of output nodes via a shunt capacitor so that the output differential voltage across the output node has a common mode voltage equal to the threshold voltage of the threshold voltage generator. provide. The output node is driven by a current source that is inversely controlled in a feedforward manner based on the common mode voltage of the differential input signal.

  [0008] In one embodiment, the operation of the circuit includes driving the gates of a pair of PMOS transistors, respectively, with a differential input voltage, while each of the PMOS transistors is connected to the source of each PMOS transistor via a capacitor. Combine differential input voltages. The operation of the circuit also includes controlling the current driven through each PMOS transistor as opposed to the common mode voltage for the differential input voltage.

  [0009] In another embodiment, each component of the differential input voltage is coupled to the drain of the NMOS transistor via a capacitor, but the operation of the circuit causes the source of the pair of NMOS transistors to be driven by the differential input voltage. Including driving. The operation of the circuit also includes controlling the current through each NMOS transistor as opposed to the common mode voltage for the differential input voltage.

  [0010] Various embodiments provide one or more advantages over conventional solutions. For example, a feedforward current source allows an application to receive a signal having a high or low common mode voltage and provides reliable level shifting of the common mode voltage. Also, the AC component of the differential signal—the information holding portion—modulates the voltage at the output node even at a lower frequency by driving the port of the output transistor. As such, various embodiments can be used in broadband applications. These and other advantages can be fully understood by the following detailed description.

[0011] FIG. 1 illustrates an example system having a voltage level shifting circuit in accordance with the disclosed embodiments. [0012] FIG. 2 illustrates an example architecture for a common mode voltage level shifting circuit in accordance with the disclosed embodiments. [0013] FIG. 3 illustrates another example architecture for a common mode voltage level shifting circuit in accordance with the disclosed embodiments. [0014] FIG. 4 illustrates a flowchart of an example usage for the system of FIGS. 2 and 3 in accordance with the disclosed embodiments.

  [0015] Before discussing various embodiments, a description of some concepts may help in understanding the following examples. Differential signaling involves transmitting information over two pairs of conductors. Here, the component on one conductor is complementary to the component on the other conductor. Thus, the two complementary components of the differential signal are often referred to as positive and negative signals. A conventional differential signal receiver detects the difference between two complementary signals.

  [0016] In contrast to single-ended signaling, such as when the signal is referred to as ground, differential signals can be advantageous for high speed data. For example, in single-ended signal transmission, the transmission line receives noise as when a transistor close to the transmission line switches state. Single-ended receivers can thus be cheated by noise and cause bit errors. However, in differential signaling, noise affects the positive signal and negative signal equally (or at least nearly equally), and a conventional receiver detects noise when it detects the difference between the positive and negative signals. Is excluded.

[0017] A common mode voltage includes a component of a differential signal that exists with a single sign on both conductors of a conductor pair. The common mode voltage is half the vector sum of the voltages on each conductor. The common mode voltage is given by Equation 1. Where V1 is the voltage of one conductor and V2 is the voltage of the other conductor:
(Formula 1) Vcom = (V1 + V2) / 2
[0018] FIG. 1 illustrates an example application 100 for a level shifting circuit 110, according to one embodiment. The system of FIG. 1 includes a circuit 102 that operates at a relatively low common mode voltage, eg, on the order of several hundred mV. The circuit 104 operates at a relatively high common mode voltage, for example, about VDD / 2. Of course, the examples given for the common mode voltage are for ease of explanation only, and it is understood that the various embodiments can operate at any suitable common mode voltage.

  [0019] An example of circuit 102 includes a circuit in a data receiver that terminates a signal at or near 0V, and an example of circuit 104 is differential to receive a signal at a high common mode voltage of approximately VDD / 2. It includes other parts of the RF receiver circuit that uses a pair of NMOS transistors (not shown here). In circuit 104, one NMOS transistor receives a positive signal on its gate, while the other NMOS transistor receives a negative signal on its gate. The differential pair conducts a tail current that is responsive to the differential input. Since the positive input exceeds VDD / 2, the corresponding NMOS conducts substantially all tail current. Since the negative input exceeds VDD / 2, the corresponding NMOS conducts substantially all tail current. For the VDD / 2 common mode, the differential pair is balanced in this way and can make quick bit decisions.

  [0020] The circuit 110 includes a level shifting circuit for the common mode voltage. Specifically, circuit 110 receives a differential signal from circuit 102 and shifts the common mode voltage to a level compatible with that of circuit 104. As described below, the circuit 110 maintains the AC component of the differential signal over a wide spectrum of frequencies. While the above example describes a level shifting circuit 110 used in an RF receiver, various embodiments can be used in any of a variety of other applications where the common mode voltage is shifted. Understood.

  [0021] These concepts and features can be better understood with the following description of exemplary embodiments.

Exemplary circuit embodiment
[0022] Various embodiments are directed to common mode level shifting circuits that can be applied in devices having wideband operation. In order to provide broadband operation, the received differential signal passes through a shunt capacitor similarly to the output node as discussed above for conventional solutions. However, the common mode voltage is controlled through feed forward control of the current source, which drives the output node through the individual current paths in reverse in response to the common mode voltage for the differential input signal. As the common mode voltage for the differential input signal increases, the reverse feedforward control of the current source reduces the current driven through the current path driving the output node. On the other hand, if the common mode voltage for the differential input signal decreases, the reverse feedforward control of the current source increases the current driven through the current path driving the output node.

  [0023] Each output node is coupled to a threshold voltage device that maintains the output node at a higher threshold voltage than the respective input node voltage. Since the shunt capacitor blocks which input common mode voltage passes, the common mode voltage for the output differential voltage (which can be specified as eqinp and eqinn) is equal to the threshold voltage for the instrument. The AC portion of the differential signal is applied to the output node on the path avoiding the shunt capacitor, thereby maintaining AC information even at lower frequencies.

  [0024] Returning to the drawings, FIG. 2 illustrates a level shifting circuit 250 applied according to one embodiment. Circuit 250 may be used as level shifting circuit 110 in the architecture of FIG.

  [0025] Circuit 250 includes an input node 202 that receives a differential signal. In this case, the positive and negative components of the differential signal are given as rxinp and rxinn, respectively. Resistors R 1 and R 2 act as a voltage divider to provide an input common mode voltage (Vcom) to current source 204. The circuit 250 also includes a threshold voltage circuit 206 that sets the output common mode voltage to a differential signal at the output of the circuit 250. The threshold voltage circuit 206 receives the input differential signal at the output node 208 via the gates of the PMOS transistors P1 and P2 and further through the shunt capacitors C1 and C2. The plus and minus components of the level shifted differential signal are given as eqinp and eqinn. The operation of circuit 100 is described in further detail below.

  [0026] Output node 208 is the source of transistors P1 and P2. A positive differential input signal rxinp directly drives the gate of P1, and drives its source through shunt capacitor C1. Similarly, a negative differential input signal rxinn directly drives the gate of P2 and drives the source of P2 through shunt capacitor C2. For high frequency input signals, one can thus know that the AC portion of the input signals rxinp and rxinn will transition to the sources of P1 and P2 via shunt capacitors C1 and C2, respectively. Eqinp is the positive differential output voltage at the source of P1, and eqinn is the negative differential output voltage at the source of P2.

  [0027] Note that returning to the various current sources in circuit 250, both transistors P5 and P6 drive current through threshold voltage circuit 206. Transistors P5 and P6 are both connected to the gate of transistor P4 through their gates. As will be described in detail later, transistor P4 is part of current source 204.

  [0028] Current source PMOS transistor P5 drives the source of transistor P1, and current source PMOS transistor P6 drives the source of transistor P2. These current source transistors P5 and P6 are controlled in a feedforward manner via a PMOS transistor P3. The gate of transistor P3 is coupled to common mode input voltage Vcom. Therefore, the current I1 generated by transistor P3 will be inversely related to Vcom. As Vcom increases, I1 decreases. However, when Vcom falls, I1 rises. Mirrored through NMOS transistors M1 and M as well as PMOS transistor P4 to control P5 and P6 such that current I1 is driven through P1 and P2. Thus, transistors P5 and P6 similarly act as current sources.

  [0029] Of course, the values of I2, I3, and I4 may not be the same as that of I1, although they may be the same in some embodiments. The values of currents I1, I2, I3 and I4 depend on the characteristics of the various transistors P3, P4, P5 and P6, and those skilled in the art have the appropriate characteristics to achieve the desired value of the current generated thereby. Understand how to select transistors. Nevertheless, as the value of I1 increases, the values of I2, I3 and I4 also increase. In other words, the values of I2, I3, and I4 are proportional to the value of I1, and the value of I1 is inversely proportional to the value of Vcom. Thus, as Vcom changes, the values of I1, I2, I3, and I4 change in reverse.

  [0030] Circuit 250 provides a first current path from the VDD rail to ground through transistor P5 and transistor P1. Similarly, there are other current paths from the VDD rail to ground through P6 and P2.

  [0031] Current I3 undergoes a voltage drop across both P5 and P1. It is these voltage drops that determine the voltage at output node 208a. Current I4 also undergoes a voltage drop across transistors P6 and P2, thus determining the voltage at output node 208b. The level-shifted common mode voltage is a common mode voltage present in the differential signal at the output node 208. It is not expected that the input common mode voltage Vcom will change substantially, at least during steady state operation. However, to some extent in the common mode voltage Vcom, the current source and threshold voltage circuit 206 stabilizes the level shifted common mode voltage through corresponding adjustments in I3 and I4. Thus, circuit 250 provides a stable level shifted common mode voltage at output node 208.

  [0032] During high frequency operation, the AC portion of the differential signal (the portion carrying the information) passes through shunt capacitors C1 and C2. In this way, the AC portion modulates the voltage at the output node 208 and the differential signal information can be transmitted to a circuit (not shown) that receives the output signal from the threshold voltage circuit 206.

  [0033] Note that as the AC frequency decreases in the differential signal, the shunt capacitors C1 and C2 become increasingly useless to pass the AC portion because the capacitor impedance increases as the frequency decreases. However, circuit 250 includes technology that passes the AC portion to output node 208 even at lower frequencies. Specifically and as described above, the differential signal plus and minus components (rxinp and rxinn) are input to the gates of the transistors P1 and P2, respectively. In this case, P1 and P2 then act as source followers so that the voltage at their source (output node 208) is modulated by the AC portion of the signal. Thus, a stable high common mode voltage is generated at the sources of P1 and P2 via the feedforward control of P5 and P6, while the AC portion of the differential signal is maintained over a wide range of frequencies.

  [0034] FIG. 3 illustrates a level shifting circuit 350 configured in accordance with one embodiment. In contrast to the embodiment of FIG. 2, the embodiment of FIG. 3 uses an NMOS transistor for its threshold voltage circuit 306. On the other hand, the operation of the embodiment of FIG. 3 is similar to the operation of the embodiment of FIG. Circuit 350 may be used as level shifting circuit 110 in the architecture of FIG.

  [0035] FIG. 3 includes a current source 304, which receives an input common mode voltage Vcom from a voltage divider formed by R11 and R12. The current source 304 operates in the same manner as the current source 204 (FIG. 2) as described above. For example, as Vcom decreases, the current I11 through the PMOS transistor P13 and the NMOS transistor M11 increases. As Vcom increases, current I11 through transistors P13 and M11 decreases. Current I11 is mirrored by current I12, which passes through transistors P14 and M12.

  [0036] The gates of transistors P15 and P16 are both connected to the gate of transistor P14. Thus, the current I11 is mirrored to the transistors P15 and P16 via the currents I13 and I14 by the feedforward control. As Vcom changes with time, currents I13 and I14 change in reverse.

  [0037] The threshold voltage circuit 306 includes NMOS transistors M3 and M4. Transistor M3 receives the positive component rxinp of the differential signal at its drain via shunt capacitor C11. A positive component rxinp is also added to resistor R13, which also affects the response of transistor M3.

  [0038] Similarly, transistor M4 receives the negative component rxinn of the differential signal at its drain via shunt capacitor C12. A negative component rxinn is added to resistor R14, which affects the response of transistor M4.

  [0039] The sources of M3 and M4 are isolated from ground via bias transistors M5 and M6, respectively, and their gates are controlled by the gate voltage of M11. Typically, as I11 increases, the current through transistors M5 and M6 increases as well.

  [0040] As current I13 transitions from VDD to ground, circuit 350 provides a current path for I13 as shown through transistors P15 and M5. Current I13 experiences a voltage drop at each of transistors P15 and M5, which are these voltage drops that determine the voltage at output node 308a.

  [0041] Current I14 also undergoes a voltage drop at transistors P16 and M6 between VDD and ground. It is these voltage drops that determine the voltage at output node 308b. The level-shifted common mode voltage at the output node 308 is a common mode voltage of a differential signal having positive and negative components eqinp and eqinn.

  [0042] As noted above, large changes in the input common mode voltage Vcom are generally not expected during steady state operation. Nevertheless, the level shifted output voltage at output node 308 is generated in a stable manner by the inverse feedforward relationship of currents I13 and I14 with respect to input common mode voltage Vcom. In the embodiment of FIGS. 2 and 3, some applications may include setting a common mode voltage level shifted to VDD / 2 during steady state operation. Those skilled in the art will configure transistors P15, P16, M3, M4, M5, and M6 so that the resistor divider characteristics of the current paths of currents I13 and I14 will drop the voltage by half at output node 308 (as well as various resistors). You will understand that you choose. In this way, the voltage at the output node 308 is stably corrected to VDD / 2.

  [0043] Of course, the VDD / 2 level-shifted common mode voltage is merely an example, and other embodiments may include any suitable level-shifted common mode voltage. Other level-shifted common mode voltages can be generated by designing circuits 250 (FIG. 2) and 350 (FIG. 3) so that the voltage drops at output nodes 208 and 308 have the desired voltages, respectively.

  [0044] During high frequency operation, returning to the AC component of the differential signal, the AC portion of the differential signal passes through the shunt capacitors C11 and C12 without significant attenuation. In this way, the AC portion modulates the voltage at the output node 308 and the differential signal information can be conveyed to a circuit (not shown) that receives the output signal from the threshold voltage circuit 306.

  [0045] However, as the AC frequency decreases in the differential signal, the attenuation of the capacitors C11 and C12 in the AC portion increases (due to the increasing impedance of the capacitors as the frequency decreases). The circuit of FIG. 3 also provides an input differential signal at node 310. As shown in FIG. 3, a positive component rxinp is applied to node 310a, which is separated from the source of transistor M3 by resistor R13. Thus, the AC signal of component rxinp modulates the voltage at node 308a. Similarly, a negative component rxinn is added to node 310b, thereby modulating the voltage appearing at node 308b. Thus, a stable high common mode voltage is generated at the drains of M3 and M4 via P15 and P16 feedforward controls while the AC portion of the differential signal is maintained over a wide range of frequencies.

  [0046] Illustrative methods for circuits 250 and 350 are discussed next.

Example usage
[0047] A flow diagram for an example method 400 of use of the common mode voltage level shifter of FIGS. 2 and 3 is shown in FIG. The method begins at block 410, which includes receiving a differential signal having a first common mode voltage level.

  [0048] In the example of FIGS. 2 and 3, the received differential signal includes a relatively low common mode voltage, and the circuit shifts the common mode voltage level to another level. The differential signal also includes an AC portion that carries information. A circuit downstream (not shown) can receive an AC portion, can detect bits, or perform other processing there.

  [0049] At block 420, the differential signal is coupled to a pair of output nodes via a pair of shunt capacitors. In the embodiment of FIG. 2, the differential signal is coupled to the sources of transistors P1 and P2 via capacitors C1 and C2. In the embodiment of FIG. 3, the differential signal is coupled to the drains of transistors M3 and M4 via capacitors C11 and C12. The capacitor blocks the direct current (DC) component of the signal, and thus the shunt capacitor blocks the common mode voltage received by the input differential signal.

  [0050] At high frequencies, the AC portion of the differential signal is communicated to the output node, as will be described in detail below with respect to block 450.

  [0051] At block 430, the circuit generates a current driven by the first common mode voltage level. In the embodiment of FIGS. 2 and 3, the common mode voltage level of the input differential signal (Vcom) is detected by a resistor divider circuit and communicated to the current generator.

  [0052] Various embodiments may use any suitable constant current source to generate the current of block 430. For example, the embodiments of FIGS. 2 and 3 use a current source in which the gate of the PMOS transistor is coupled to the Vcom signal. As Vcom increases, the current source current decreases (and vice versa). Thus, in the embodiment described above, the current generated at block 430 is controlled in an inverse relationship with respect to the first common mode voltage.

  [0053] At block 44, the current generated at block 430 is mirrored through the output node to generate a second common mode voltage at the output node. In the embodiment of FIGS. 2 and 3, feedforward control is achieved by coupling together the gates of the transistors. Thus, the voltage at the gate of the current source transistor is applied to the gate of the transistor coupled to the first output node. As the current increases through the current source, the gate coupling described above increases the current through the transistor coupled to the first output node.

  [0054] The voltage of the transistor gate in the current source is also applied to the gate of the transistor coupled to the second output node. As the current increases through the current source, the current increases through the transistor coupled to the second output node.

  [0055] A current controlled by the current source in response to the first common mode voltage is generated at block 440. The first and second output nodes are arranged in the circuit such that the voltage drop along each current path results in the desired voltage at the output node. In some embodiments, the common mode voltage at the output node is somewhere between ground and VDD, and the common mode voltage can be generated with high stability at the output node by current mirroring of block 440.

  [0056] At block 450, the circuit modulates the voltage at the output node according to the AC portion of the differential signal. As described above in block 420, the input differential signal is coupled to the output node via a pair of shunt capacitors. If the AC signal is high frequency, the AC signal passes through a shunt capacitor that is relatively undamped.

  [0057] In contrast, when the AC signal is at a relatively low frequency, the impedance of the shunt capacitor is high. The embodiment of FIG. 2 modulates the voltage at the output node by supplying a differential signal to the gates of a pair of transistors at the output node. The embodiment of FIG. 3 modulates the voltage at the output node by supplying a differential signal to the source of a pair of transistors at the output node. Thus, various embodiments provide a differential signal to the output transistor port to maintain AC signal information even at lower frequencies.

  [0058] The scope of the embodiments is not limited to the particular method shown in FIG. Other embodiments can add one or more actions, can be omitted, can be rearranged, or can be modified. For example, in many real-world applications, the operations of blocks 410-450 are not performed serially, but rather in parallel as the level shifting circuit operates. Also, the operations of blocks 410-450 are performed continuously as the circuit receives the first common mode voltage level and outputs another common mode voltage level.

  [0059] Further, various embodiments may perform other operations. For example, other circuit downstreams can receive level-shifted differential signals from which binary voltage levels can be detected. Bit detection can be performed in any suitable manner, for example, by a conventional bit detection process, and is not further discussed herein.

  [0060] As one of ordinary skill in the art understands and depends on the particular application at hand, many variations, alternatives, and variations of the materials, apparatus, configurations, and use of the disclosed devices without departing from the spirit and scope thereof. It can be done in and against ways. In view of this, the scope of the present disclosure should not be limited to that of the specific embodiments illustrated and described herein. They are merely some examples thereof, but rather correspond to those of the claims attached below and their functional equivalents.

Claims (30)

A common mode voltage level shifting circuit comprising:
An input node configured to receive a differential signal having a first common mode voltage;
A pair of shunt capacitors coupled between the input node and a corresponding pair of output nodes;
A threshold voltage circuit including an output node and coupled to the differential signal via the shunt capacitor; and the threshold voltage circuit provides a second common mode voltage for the differential signal at the output node. Configured as
A current source controlled according to a level of the first common mode voltage, and the current source is coupled to the output node to achieve the second common mode voltage;
Common mode voltage level shifting circuit.   The common mode voltage level shifting circuit of claim 1, wherein the current source is inversely controlled with respect to the level of the first common mode voltage.   The common mode voltage level shifting circuit of claim 1, wherein the current source is controlled in a feed forward manner by another current source that receives the first common mode voltage. The threshold voltage circuit comprises:
A first transistor coupled at its gate to the first component of the differential signal through a first one of the shunt capacitors, and the drain of the first transistor is a first one of the output node. And
A second transistor coupled at its gate to a second component of the differential signal through a second one of the shunt capacitors, and a drain of the second transistor being a second of the output node; Wherein the first component of the differential signal modulates the first one voltage of the output node via the source of the first transistor;
Further, the second component of the differential signal modulates the second one voltage at the output node via the source of the second transistor.
The common mode voltage level shifting circuit according to claim 1. The threshold voltage circuit comprises:
A first bias transistor provided between the first transistor and ground; and the first bias transistor configured to provide a voltage drop between the first transistor and ground;
A second bias transistor provided between a second transistor and ground; and the second bias transistor is configured to provide a voltage drop between the second transistor and ground;
The common mode voltage level shifting circuit according to claim 4. The threshold voltage circuit comprises:
A first transistor coupled at its gate to a first component of the differential signal, and a source of the first transistor is a first one of the output nodes;
A second transistor coupled to the second component of the differential signal at its gate, and a source of the second transistor is a second one of the output nodes, wherein the differential signal The first component modulates the first one voltage at the output node, and the second component of the differential signal modulates the second one voltage at the output node;
The common mode voltage level shifting circuit according to claim 1.   The common mode voltage level shifting circuit of claim 6, wherein the output node is coupled to the gates of the first and second transistors by the shunt capacitor. The current source is
Controlled by an input transistor having a first current source configured to drive a first one of the output nodes, and the first current source having its gate coupled to the first common mode voltage. Coupled to the input transistor,
A second current source configured to drive a second one of the output nodes, and the second current source is controlled by the input transistor and connected to the input transistor;
The common mode voltage level shifting circuit according to claim 1.   The input transistor is included in a current mirror, and the current mirror is configured to generate a first current that controls a current in the first current source and a current in the second current source. Item 9. The common mode voltage level shifting circuit according to Item 8.   9. The first current source comprises a transistor having its gate coupled to the gate of the input transistor, further comprising a transistor having its gate coupled to the gate of the input transistor. The common mode voltage level shifting circuit described in 1. A method for shifting a common mode voltage level, the method comprising:
Receiving a differential signal having a first common mode voltage level;
Coupling the differential signal to a pair of output nodes via a pair of shunt capacitors;
Generating a current controlled by the first common mode voltage level;
Mirroring the current through the output node to generate a second common mode voltage level at the output node;
A method comprising:   The method of claim 11, wherein the current is inversely proportional to the first common mode voltage level. Driving the gates of a pair of PMOS transistors with the differential input signal;
A first component of the differential signal is coupled to a first one source of the PMOS transistor via a first one of the shunt capacitors;
A second component of the differential signal is coupled to a second one source of the PMOS transistor via a second one of the shunt capacitors;
The method of claim 11.   The method of claim 13, wherein the source of the PMOS transistor comprises the output node. Driving a source of a pair of NMOS transistors by the differential input signal;
A first component of the differential input signal is coupled to a first one drain of the NMOS transistor via a first one of the shunt capacitors;
A second component of the differential signal is coupled to a second one drain of the NMOS transistor via a second one of the shunt capacitors;
The method of claim 11.   The method of claim 14, wherein the drain of the NMOS transistor comprises the output node.   The method of claim 11, further comprising modulating the voltage at the output node by providing the differential signal to a gate of a pair of transistors at the output node.   The method of claim 11, further comprising modulating the voltage at the output node by providing the differential signal to a source of a pair of transistors at the output node. A common mode voltage level shifting circuit comprising:
An input node configured to receive a differential signal having a first common mode voltage;
A pair of shunt capacitors for coupling the differential signal to an output node of the circuit;
A threshold voltage circuit including an output node and configured to receive the differential signal via the shunt capacitor; and the threshold voltage circuit is a second common mode voltage for the differential signal at the output node. Is configured to provide
Means for driving an output node to achieve the second common mode voltage, and the means for driving is controlled according to a level of the first common mode voltage;
Common mode voltage level shifting circuit.   20. A common mode voltage level shifting circuit as claimed in claim 19, wherein the driving means is controlled inversely with respect to the level of the first common mode voltage.   20. A common mode voltage level shifting circuit according to claim 19, wherein the driving means comprises a current source controlled in a feedforward manner by another current source receiving the first common mode voltage. The threshold voltage circuit comprises:
A first transistor coupled at its gate to a first component of the differential signal through a first one of the shunt capacitors, and a drain of the first transistor being a first of the output node; One,
A second transistor coupled at its gate to a second component of the differential signal through a second one of the shunt capacitors, and a drain of the second transistor being a second one of the output nodes. Wherein the first component of the differential signal modulates the first one voltage of the output node via the source of the first transistor, and further, The second component modulates the second one voltage of the output node via the source of the second transistor;
The common mode voltage level shifting circuit of claim 19. The threshold voltage circuit comprises:
A first bias transistor provided between the first transistor and ground; and the first bias transistor configured to generate a voltage drop between the first transistor and ground;
A second bias transistor provided between the second transistor and ground; and the second bias transistor is configured to generate a voltage drop between the second transistor and ground.
23. A common mode voltage level shifting circuit according to claim 22. The threshold voltage circuit comprises:
A first transistor coupled at its gate to a first component of the differential signal, and a source of the first transistor is a first one of the output nodes;
A second transistor coupled at its gate to the second component of the differential signal, and a source of the second transistor being a second one of the output nodes, wherein the second of the differential signal One component modulates the first one voltage at the output node, and further, the second component of the differential signal modulates the second one voltage at the output node;
The common mode voltage level shifting circuit of claim 19. Means for driving,
Controlled by an input transistor having a first current source configured to drive a first one of the output nodes, and the first current source having its gate coupled to the first common mode voltage. Coupled to the input transistor,
A second current source configured to drive a second one of the output nodes, and the second current source is controlled by the input transistor and connected to the input transistor;
The common mode voltage level shifting circuit of claim 19.   The input transistor is included in a current mirror, and the current mirror is configured to generate a first current that controls a current in the first current source and a current in the second current source. Item 26. The common mode voltage level shifting circuit according to Item 25.   26. The first current source comprises a transistor having its gate coupled to the gate of the input transistor, further comprising a transistor having its gate coupled to the gate of the input transistor. The common mode voltage level shifting circuit described in 1. A data receiver circuit comprising:
A first circuit configured to receive a differential signal having a first common mode voltage level;
A level shifting component coupled to the first circuit;
The level shifting component is
A current source configured to generate a current inversely related to the first common mode voltage and configured to drive the current at an output node of the level shifting component;
A pair of shunt capacitors for coupling the differential signal to the output node;
A pair of transistors in communication with the shunt capacitor and each of the transistors are configured to receive respective components of the differential signal and current from the current source, wherein each voltage at each of the transistors The drop defines a second common mode voltage level;
A second circuit in communication with the output node of the level shifting component;
The second circuit is configured to receive a modified version of the differential signal at the second common mode voltage level;
Data receiver circuit. The first transistor is configured to receive a first component of the differential signal at its gate through a first one of the shunt capacitors, and the drain of the first transistor is connected to the output node. The first one,
The second transistor is configured to receive a second component of the differential signal at its gate through a second one of the shunt capacitor, and the drain of the second transistor is connected to the output node. A second one, wherein a first component of the differential signal modulates a first one voltage of the output node, and further, the second component of the differential signal is the output. Modulating the second one voltage of the node;
30. A data receiver circuit according to claim 28. The threshold voltage circuit comprises:
The first transistor configured to receive the first component of the differential signal at its gate, and the source of the first transistor is the first one of the output nodes;
A second transistor configured to receive a second component of the differential signal at its gate; and a source of the second transistor is a second one of the output nodes;
Wherein the first component of the differential signal modulates the first one voltage of the output node, and the second one of the differential signal is the second component of the output node. Modulate the voltage of the
30. A data receiver circuit according to claim 28.

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