JP6207173B2 - Signal processing apparatus, control method thereof, and control program - Google Patents

Description

  The present invention relates to a signal processing device, a control method therefor, and a control program, and more particularly to a signal processing device that reduces a delay in display time when an image is displayed during shooting.

  In general, an imaging device such as a digital video camera or a digital camera includes a display device such as a display (panel) such as a liquid crystal or an organic EL or an electronic viewfinder (EVF) in order to confirm a subject at the time of shooting.

  It is desirable that the panel displays the subject viewed by the user in real time with the image quality of the recorded image. On the other hand, signal processing takes time due to the increase in the number of pixels of the recorded image and the enhancement of the image quality improvement function in recent years, causing a display delay when displaying on the panel. If there is a display delay, the user feels uncomfortable during operations such as panning, tilting, and zooming, making it difficult to check composition and focus.

  Since the display delay amount (delay time) also depends on the shooting frame rate, the display delay amount increases when the frame rate is slow. Although depending on the configuration of the imaging apparatus, for example, it is known that when the frame rate is 24 Hz, the display delay amount is 2.5 times larger than when the frame rate is 60 Hz.

  By the way, the same problem exists in television due to the multifunctional image quality improvement function. For example, when a game is connected to a television and a game is played, display delay occurs when image quality improvement processing is performed on the television. As a result, the user's operation is delayed, and the operation delay may not only affect the game result but also give the user a sense of incongruity.

  In order to reduce such display delay, for example, when processing a video signal and outputting the display video signal to a display panel, an operation of low delay processing with a short delay time of the display video signal with respect to the video signal is selectively performed. In this case, the scaling processing is performed in accordance with the display module. Here, the signal processing such as the image quality improvement processing is simplified to reduce the display delay (see Patent Document 1).

JP 2011-223457 A

  However, the technique described in Patent Document 1 reduces the delay between a video signal and a display video signal generated in a receiver such as a television. Here, a delay of at least one frame is inevitably generated. . For this reason, even if the method is used with an imaging device such as a digital camera, it is possible to reduce the uncomfortable feeling that occurs during shooting, that is, when operating the imaging device, and to check composition and focus well. Have difficulty.

  Therefore, an object of the present invention is to reduce the display delay time of the image displayed on the display unit during shooting, to reduce the uncomfortable feeling during the shooting operation, and to satisfactorily check the composition and focus. A signal processing apparatus, a control method thereof, and a control program are provided.

In order to achieve the above object, a signal processing apparatus according to the present invention is an optical geometric distortion based on a lens for condensing an image signal generated by an imaging device on an imaging surface of the imaging device. The first image processing unit that corrects the image and generates an image signal for recording, and the image that is generated by the imaging device and before the geometric distortion is corrected by the first image processing unit For the signal, a resizing process for adjusting the display size of the display unit having a smaller number of pixels than the image sensor and a correction process for the geometric distortion are performed to generate an image signal for display on the display unit . and second image processing means, the possess, the second image processing means, the target pixel of the image signal after resizing, and a plurality of pixels around the target pixel, the geometric distortion The corresponding interpolation factor By performing arithmetic processing have been, and performs the resizing process and the correction process of the geometric distortion.

A control method according to the present invention is a control method of a signal processing apparatus, and an optical geometrical method based on a lens for condensing an image signal generated by an image sensor on an image pickup surface of the image sensor. A first image processing step that corrects the distortion and generates an image signal for recording; and the image signal generated by the imaging device and before the geometric distortion is corrected in the first image processing step. The image signal is resized to match the display size of the display unit having a smaller number of pixels than the image sensor and the geometric distortion correction process to generate an image signal to be displayed on the display unit. possess a second image processing step, and wherein in the second image processing step, the target pixel of the image signal after resizing, and a plurality of pixels around the target pixel, the geometric distortion According to By performing arithmetic processing using an interpolation coefficient, and performs the resizing process and the correction process of the geometric distortion.

The control program according to the present invention is a control program used in a signal processing device, and focuses the image signal generated by the imaging device on the imaging surface of the imaging device on a computer included in the signal processing device. A first image processing step for correcting an optical geometric distortion based on a lens for generating an image signal for recording, and a first image processing step generated by the imaging device and the first image processing step. The image signal before the geometric distortion is corrected is subjected to a resizing process for adjusting to a display size of a display unit having a smaller number of pixels than the image sensor and a correction process for the geometric distortion, thereby performing the display. a second image processing step of generating an image signal for displaying the part, to the run, in the second image processing step, noted picture image signal after resizing Against performs a plurality of pixels around the target pixel, by performing arithmetic processing using an interpolation coefficient corresponding to the geometric distortion, the resizing process and the correction process of the geometric distortion It is characterized by that.

  According to the present invention, it is possible to reduce the display delay time of an image displayed on the display unit during shooting to reduce a sense of incongruity during a shooting operation, and to check the composition and focus well.

It is a block diagram which shows the example about the structure of an imaging device provided with the signal processing apparatus by the 1st Embodiment of this invention. It is a block diagram which shows an example of an imaging device provided with the conventional signal processing apparatus. 2 is a timing chart for explaining the operation timing of the imaging apparatus shown in FIG. 1. 3 is a timing chart for explaining the operation timing of the imaging apparatus shown in FIG. 2. It is a figure for demonstrating the distortion correction performed by the resizing circuit shown in FIG. It is a block diagram which shows the example about the structure of an imaging device provided with the signal processing apparatus by the 2nd Embodiment of this invention.

Hereinafter, an example of a signal processing apparatus according to an embodiment of the present invention will be described with reference to the drawings.
[First Embodiment]

  FIG. 1 is a block diagram illustrating an example of a configuration of an imaging apparatus including a signal processing device according to the first embodiment of the present invention.

  The illustrated imaging apparatus is, for example, a video camera and includes an imaging sensor 100. The image sensor 100 includes an image sensor such as a CCD or a CMOS. The imaging sensor 100 forms an optical image (subject image) in which the amount of incident light is adjusted and focused in a photographing lens group (not shown). The imaging sensor 100 and the photographing lens group constitute an imaging unit.

  The imaging sensor 100 generates an analog signal corresponding to the optical image by photoelectric conversion, converts the analog signal into a digital signal (image signal) by A / D conversion, and outputs the digital signal. That is, a captured image obtained as a result of imaging by the imaging unit is a digital signal.

  The imaging device has a plurality of pixels arranged in a matrix, and each pixel has a predetermined arrangement of color filters of R (red), G (green), and B (blue), for example, Bayer. They are arranged in an array or a honeycomb array. Thereby, the image sensor outputs an RGB image signal for each color. In addition, for high-speed output (high-speed reading), there is a case where an RGB image signal is output by performing a pixel addition process in which outputs of a plurality of pixels are added to form one output.

  The resizing circuit 101 has a size that can be processed by the signal processing circuit 102 while correcting the center of gravity of the RGB image signal output from the imaging sensor 100 for each color of R (red), G (green), and B (blue). Reduce to (size).

  The signal processing circuit 102 receives the RGB image signal resized by the resizing circuit 101 and first performs RGB offset adjustment, gain adjustment, and gamma correction processing. Next, the signal processing circuit 102 converts the RGB image signal into a luminance signal (Y) and a color difference signal (Cb, Cr), and temporarily writes the YCC image signal in the storage memory (for example, DRAM) 103.

  A signal processing circuit 104 is disposed following the signal processing circuit 102. The signal processing circuit 104 reads the YCC image signal from the DRAM 103 and performs, for example, a correction process for distortion aberration of the photographing lens group. Further, the signal processing circuit 104 performs an image stabilization process for reducing the blur of the YCC image signal caused by the blur of the imaging device in accordance with the motion vector of the subject, and writes the first processed YCC image signal in the DRAM 105.

  The signal processing circuit 106 reads the first processed YCC image signal from the DRAM 105, performs, for example, noise reduction processing, and writes the second processed YCC image signal in the DRAM 107.

  In this way, the signal processing circuits 104 and 106 sequentially perform image processing on the YCC image signal stored in the DRAM.

  The compression / decompression circuit 108 reads out the second processed YCC image signal from the DRAM 107, compresses and encodes the second processed YCC image signal in accordance with the recording format, and records it as a compressed image signal on the recording medium 109.

  The external output circuit 110 reads the second processed YCC image signal from the DRAM 107, and converts the format of the second processed YCC image signal in accordance with an image signal transmission format such as HDMI, SDI, component, or composite. And output to the outside of the imaging device.

  The illustrated imaging apparatus includes a resizing circuit 111, and the resizing circuit 111 includes a prefilter 120, an interpolation circuit 121, and an interpolation coefficient calculation circuit 122.

  The resizing circuit 111 receives the YCC signal that is the output of the signal processing circuit 102. Then, the resizing circuit 111 reduces the YCC image signal to the display size of a display device (for example, a panel) and generates a resized YCC image signal as described later. The resizing circuit 111 performs distortion correction and reduction processing as will be described later.

  The resized YCC image signal that is the output of the resize circuit 111 is supplied to the panel signal processing circuit 112. The panel signal processing circuit 112 performs signal processing such as color adjustment processing and resolution adjustment processing on the resized YCC image signal in accordance with the panel, and outputs the result as a panel YCC signal.

  The panel output circuit 113 converts the format of the panel YCC image signal in accordance with the reception format of the panel, sends it to the display device (display unit or panel) 114, and displays the image on the panel 114.

  The CPU 130 controls the entire imaging apparatus. In FIG. 1, control signal lines are not shown, but the CPU 130 controls the above-described blocks. In particular, the CPU 130 adjusts settings of the signal processing circuits 192, 104, and 106 and the panel signal processing circuit 112.

  Here, in order to easily understand the signal processing in the imaging apparatus shown in FIG. 1, the signal processing in the conventional imaging apparatus will be described.

  FIG. 2 is a block diagram illustrating an example of an imaging apparatus including a conventional signal processing apparatus. In FIG. 2, the same components as those shown in FIG. 1 are denoted by the same reference numerals. In FIG. 2, the CPU is omitted.

  In the imaging apparatus illustrated in FIG. 2, the second processed YCC image signal that is the output of the signal processing circuit 106 is provided to the resizing circuit 211. Then, the resize circuit 211 reduces the second processed YCC signal to the display size of the display device to obtain a resized YCC image signal, and writes the resized YCC signal in the DRAM 212.

  The panel output circuit 213 reads the resized YCC image signal from the DRAM 212, converts the format according to the reception format of the panel, sends it to the display device (panel) 114, and displays the image on the panel 114.

  As described above, in the conventional imaging apparatus, the resize circuit 211 receives the YCC image signal that has been subjected to all signal processing other than the compression / decompression processing, and sends the resized YCC image signal obtained by performing the resizing processing to the DRAM 212. Remember.

  Next, the operation timing of the imaging device shown in FIGS. 1 and 2 will be described.

  FIG. 3 is a timing chart for explaining the operation timing of the imaging apparatus shown in FIG. 1, and FIG. 4 is a timing chart for explaining the operation timing of the imaging apparatus shown in FIG.

  Here, the drive cycle of the image sensor 100 and the drive cycle of the panel 114 are both synchronized at 60 Hz, and the number of pixels of the image sensor 100 is horizontal 4096 pixels × vertical 2160 lines = 88847360 pixels. The number of pixels of the panel 114 is assumed to be 960 horizontal pixels × vertical 540 lines = 518400 pixels. The operation timing control shown in FIGS. 3 and 4 is performed under the control of the CPU.

  First, referring to FIG. 3, in step S310, the image sensor 100 outputs an RGB image signal (horizontal 4096 pixels × vertical 2160 lines). Subsequently, in step S311, the resizing circuit 101 reduces the RGB image signal output from the image sensor 101 to a size that can be processed by the signal processing circuit 102 (horizontal 2048 pixels × vertical 1080 lines).

  In step S312, the signal processing circuit 102 performs signal processing for converting the RGB image signal resized by the resizing circuit 101 into a luminance signal (Y) and a color difference signal (Cb, Cr). Then, the signal processing circuit 102 sends the YCC image signal to the resizing circuit 111 while storing it in the DRAM 103.

  In step S313, the signal processing circuit 104 reads the YCC image signal stored in the DRAM 103 after one frame time from the processing in step S312. Then, the signal processing circuit 104 performs signal processing on the YCC signal and writes the first processed YCC image signal in the DRAM 105.

  Subsequently, in step S314, the signal processing circuit 106 reads out the first processed YCC image signal stored in the DRAM 105 after one frame time from the processing in step S313. Then, the signal processing circuit 106 performs signal processing on the first processed YCC image signal and writes the second processed YCC image signal in the DRAM 107.

  In step S315, the external output circuit 110 reads out the second processed YCC image signal stored in the DRAM 107 after one frame time from the process in step S314. Then, as described above, the external output circuit 110 performs format conversion and outputs it to the outside of the imaging apparatus.

  On the other hand, after the process of step S312, the process of step S316 is performed, and the resizing circuit 111 reduces the YCC image signal to obtain a resized YCC panel image signal. Here, in order to obtain the display size of the panel 114 (horizontal 960 pixels × vertical 540 lines), the YCC image signal is reduced to horizontal 15/32 times and vertical ½ times.

  Next, in step S317, the panel signal processing circuit 112 performs signal processing such as color adjustment processing and resolution adjustment processing on the resized YCC image signal in accordance with the panel, and outputs the result as a panel YCC signal.

  Subsequently, in step S318, the panel output circuit 113 converts the format of the panel YCC image signal in accordance with the reception format of the panel 114, and sends it to the panel 114 to display the image.

  With reference to FIG. 4, the same steps as those shown in FIG. In the imaging device shown in FIG. 2, after the signal processing by the signal processing circuit 106 in step S314, the reduction processing by the resizing circuit 211 is performed in step S416. That is, the resizing circuit 211 reduces the second processed YCC image signal that is the output of the signal processing circuit 106 and stores it in the DRAM 212 as a resized YCC image signal.

  Subsequently, in step S417, the panel output circuit 213 reads the resized YCC image signal stored in the DRAM 212 after one frame time from the process of step S314. Then, the panel output circuit 213 converts the format of the resized YCC image signal in accordance with the reception format of the panel 114 and sends it to the panel 114 to display the image.

  As described above, the resize circuit 211 receives the second processed YCC image signal from the signal processing circuit 206 and stores the resized YCC image signal obtained by performing the reduction process in the DRAM 212.

  For this reason, the panel output process is performed in step S417 together with the process in step S315. If counted from step S310, the display delay time corresponding to three frame times is generated in the process in step S417. Since the frame rate is 60 Hz, this display delay time is about 50 [msec].

  In the timing chart shown in FIG. 3 described above, after the process of step S310, the process of step S318 is performed within one frame time, and the display delay time for displaying an image on the panel 114 at the time of shooting is 1 It can be within frame time.

  1, the resizing circuit 111 receives the YCC image signal from the signal processing circuit 102 and displays the image on the panel 114 via the panel signal processing circuit 112 and the panel output circuit 113. Therefore, an image captured by the image sensor 100 can be displayed on the panel 114 within one frame time.

  Incidentally, as described above, the resizing circuit 111 shown in FIG. 1 includes the prefilter 120, the interpolation circuit 121, and the interpolation coefficient calculation circuit 122, performs image reduction processing on the YCC image signal, and performs shooting. Distortion correction that occurs in the lens group is performed.

  Here, the distortion is an optical geometric distortion caused by a distortion aberration of a lens for focusing on the imaging surface (imaging surface) of the imaging sensor. This distortion occurs because the imaging magnification is different between the vicinity of the center of the image and its peripheral portion.

  In general, distortion aberration includes barrel-shaped distortion aberration in which the outer frame is swollen and pincushion distortion aberration in which the outer frame is depressed, and the distortion aberration changes depending on the zoom magnification of the lens.

  Although it is desirable to design a lens so as to reduce distortion, it is difficult to completely eliminate distortion, and a lens group that suppresses distortion is complicated and expensive. For this reason, in order to provide an inexpensive imaging device, it is necessary to correct distortion occurring in the lens group by image processing.

  As described above, in the imaging apparatus shown in FIG. 1, distortion correction processing is performed in the signal processing circuit 104. On the other hand, in the imaging apparatus shown in FIG. 1, the YCC image signal that is the output of the signal processing circuit 102 is input to the resizing circuit 111 and an image is displayed on the panel 114 via the panel signal processing circuit 112 and the panel output circuit 113. Therefore, it is desirable to perform distortion correction in the path to the panel 114.

  That is, when an image that has not been corrected for distortion is displayed on the panel 114, when the user performs imaging according to the display image, the image between the image intended by the user and the image recorded on the recording medium 109 is displayed. Differences will occur. For this reason, it is necessary to perform distortion correction in the path to the panel 114.

  FIG. 5 is a diagram for explaining the distortion correction performed by the resizing circuit 111 shown in FIG.

  Now, it is assumed that pincushion distortion or barrel distortion occurs on the image plane when there is no distortion. Since the pincushion distortion and barrel distortion are two-dimensional distortions, distortion correction can be performed by performing distortion correction using a two-dimensional reverse polarity distortion correction factor in the vertical and horizontal directions.

  Note that resizing processing (reduction processing) performed to display an image captured by the imaging sensor 100 on the panel 114 is also two-dimensional image deformation processing in the vertical and horizontal directions. Therefore, here, the resizing circuit 111 performs distortion correction and reduction processing.

  In the resizing circuit 111, the pre-filter 120 limits the band of the YCC image signal that is the output of the image processing circuit 102, and prevents aliasing due to reduction processing. The pre-filter 120 is, for example, a high-order FIR filter, and limits the band in the vertical direction and the horizontal direction.

  The interpolation circuit 121 interpolates a predetermined target pixel in the resized YCC signal from a plurality of surrounding pixels. In the interpolation circuit 121, for example, a known bilinear method or bicubic method is used.

  The interpolation coefficient calculation circuit 122 controls the coefficient of the interpolation calculation performed by the interpolation circuit 121, for example, the weighting calculation in the bicubic method, under the control of the CPU. When distortion correction is not performed, the interpolation coefficient calculation circuit 122 performs coefficient calculation according to the center of gravity position, and when performing distortion correction, performs coefficient calculation according to the distortion correction rate shown in FIG.

  The resize 111 receives the YCC pixel signal from the signal processing circuit 102 and the horizontal and vertical address position information of the pixel related to the YCC image signal. The address position information is given to the interpolation coefficient calculation circuit 122. The interpolation coefficient circuit 122 calculates an interpolation coefficient according to the address position information, and controls the interpolation circuit 121 based on the interpolation coefficient.

  For example, as shown in FIG. 5, when pincushion distortion or barrel distortion occurs, the distortion correction ratio (correction coefficient) increases toward the periphery. The interpolation coefficient calculation circuit 122 obtains a distortion correction coefficient by approximate calculation according to the address position information. Further, the interpolation coefficient calculation circuit 122 may read a correction coefficient from the LUT according to the address position information with reference to a built-in LUT (lookup table). When distortion correction is performed in the resizing circuit 111 in this manner, a resized YCC image signal that is an image after distortion correction is obtained.

  When the imaging apparatus (camera) shown in FIG. 1 can exchange lenses (that is, when the camera can exchange lenses), the distortion rate differs depending on the interchangeable lens. In this case, the CPU 130 shown in FIG. 1 recognizes the type of the interchangeable lens attached to the camera. Then, the CPU 130 changes the calculation processing in the interpolation coefficient calculation circuit 122 according to the type of the interchangeable lens attached to the camera.

  As described above, when calculating the correction coefficient with reference to the LUT, the CPU 130 rewrites the LUT table data according to the type of the interchangeable lens attached to the camera. In this case, when the interchangeable lens is attached, the CPU 130 rewrites the LUT table data.

  Furthermore, when the lens mounted on the camera is an optical zoom lens, the distortion rate varies depending on the focal length. In this case, the CPU 130 shown in FIG. 1 detects the zoom state of the zoom lens, and changes the calculation processing in the interpolation coefficient calculation circuit 122 according to the zoom state. As described above, when calculating the correction coefficient with reference to the LUT, the CPU 130 rewrites the LUT table data in accordance with the zoom rate of the zoom lens.

  Note that the second processed YCC image signal sent to the external output circuit 110 is 8 bits, 10 bits, or more, whereas the image signal sent to the panel 114 is 8 bits or less. Is the number of bits. Therefore, when outputting the YCC image signal to the resizing circuit 110, the signal processing circuit 102 may reduce the processing amount in the resizing circuit 111 by reducing the data amount to the required number of bits.

  One DRAM may be used as the DRAMs 103, 105, and 107 by address control.

  Note that the drive cycle of the image sensor 100 and the drive cycle of the panel 114 may not be the same cycle. In this case, when synchronously controlling the drive cycle of the image sensor 100 and the drive cycle of the panel 114, the CPU 130 measures the delay amount of the synchronization signal between the image sensor 100 and the panel 114 and uses the sensor drive cycle as a reference. The delay amount of the synchronization signal of the panel 114 is adjusted so as to fall within a predetermined range.

  As described above, in the first embodiment of the present invention, the YCC image signal that is the output of the signal processing circuit 102 is input to the resizing circuit 111 and an image is displayed on the display device 114. In addition, it is possible to reduce the display delay time of the image displayed on the display device 114 to reduce a sense of incongruity at the time of the shooting operation, and to check the composition and the focus well.

[Second Embodiment]
Subsequently, an imaging device including a signal processing device according to a second embodiment of the present invention will be described.

  FIG. 6 is a block diagram illustrating an example of the configuration of an imaging apparatus including a signal processing device according to the second embodiment of the present invention. In FIG. 6, the same constituent elements as those of the imaging apparatus shown in FIG.

  The illustrated imaging apparatus (camera) includes a gyro sensor 131, an analog-digital conversion circuit (ADC) 132, and a DRAM 115. The illustrated gyro sensor 131 detects camera shake in two horizontal axes with respect to the imaging surface. The camera shake is, for example, camera shake.

  The gyro sensor 131 detects camera shake and sends the amount of shake to the ADC 132. The ADC 132 A / D converts the blur amount and sends a digital signal (hereinafter referred to as a blur detection signal) indicating the blur amount to the CPU 130.

  As described with reference to FIG. 1, the signal processing circuit 104 performs image stabilization processing on the YCC image signal. In the second embodiment, the signal processing circuit 104 controls the YCC according to the blur detection signal under the control of the CPU 130. Anti-vibration processing is performed on the image signal.

  As shown in the figure, the resized YCC image signal that is the output of the resize circuit 111 is temporarily stored in the DRAM 115. The panel signal processing circuit 112 performs read address control on the DRAM 115 and performs cut-out reading that selectively reads out the YCC image signal stored in the DRAM 115.

  At this time, the panel signal processing circuit 112 changes the read address of the DRAM 115 in accordance with the shake detection signal under the control of the CPU 130, performs the image reading and reading of the YCC image signal so as to cancel the shake amount, and performs the image stabilization process. Run.

  Although a slight delay occurs due to the insertion of the DRAM 115, there is no problem because the size of the image signal stored in the DRAM 115 is small. That is, as described above, the image signals stored in the DRAMs 103, 105, and 107 are, for example, horizontal 2048 pixels × vertical 1080 lines, but the image signals stored in the DRAM 115 are reduced for panel display. An image signal, for example, horizontal 960 pixels × vertical 540 lines. Therefore, the total number of pixels stored in the DRAM 115 is about ¼ of the total number of pixels stored in the DRAMs 103, 105, and 107, and the delay time by the DRAM 115 is sufficiently small for one frame time.

  One DRAM may be used as the DRAM 115, DRAM 103, 105, and 107 by address control.

  As described above, also in the second embodiment of the present invention, the display delay time of the image displayed on the display device at the time of shooting is reduced to reduce a sense of incongruity at the time of shooting operation and confirmation of composition, focus, etc. Can be performed satisfactorily. Furthermore, blurring in an image displayed on the display device can be reduced.

  As is apparent from the above description, in the example shown in FIG. 1, at least the resizing circuits 101 and 111, the signal processing circuits 102, 104, and 106, the DRAMs 103, 105, and 107, the compression / decompression circuit 108, the CPU 130, and the panel The signal processing circuit 112 and the panel output circuit 113 constitute a signal processing device.

  As mentioned above, although this invention was demonstrated based on embodiment, this invention is not limited to these embodiment, Various forms of the range which does not deviate from the summary of this invention are also contained in this invention. .

  For example, the function of the above embodiment may be used as a control method, and this control method may be executed by the signal processing device. Further, a program having the functions of the above-described embodiments may be used as a control program, and the control program may be executed by a computer included in the signal processing device. The control program is recorded on a computer-readable recording medium, for example.

  The present invention can also be realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various recording media, and the computer (or CPU, MPU, etc.) of the system or apparatus reads the program. To be executed.

100 Image sensor 101, 111 Resizing circuit 102, 104, 106 Signal processing circuit 103, 105, 107, 115 DRAM
108 compression / decompression circuit 109 recording medium 110 external output circuit 112 signal processing circuit for panel 113 panel output circuit 114 display device (panel)

Claims (8)

A first image signal for recording is generated by correcting an optical geometric distortion based on a lens for condensing on an image pickup surface of the image pickup device with respect to an image signal generated by the image pickup device . Image processing means,
Resizing the image signal generated by the image sensor and before the geometric distortion is corrected by the first image processing means to match the display size of the display unit having a smaller number of pixels than the image sensor processing and performs correction processing of the geometric distortion, have a, a second image processing means for generating an image signal for displaying on the display unit,
The second image processing unit performs arithmetic processing on the target pixel of the image signal after the resizing process using a plurality of pixels around the target pixel and an interpolation coefficient according to the geometric distortion. And performing the resizing process and the geometric distortion correcting process . A shake detection means for outputting a vibration detection signal by detecting a blanking les,
Depending on the shake detection signal, to claim 1, characterized in that it comprises a and a shake correction unit which performs shake correction to the resize processing and image signal correction processing is performed in the geometric distortion only The signal processing apparatus as described. The blur correction unit includes a storage unit that stores an image signal that has undergone the resizing process and the geometric distortion correction process ;
The signal processing apparatus according to claim 2 , further comprising: a reading unit that performs cutout reading to change a read address in the storage unit in accordance with the blur detection signal to perform blur correction. It said second image processing means, wherein when performing the geometric distortion only correction means changes the correction factor for correcting the geometrical distortion in accordance with the zoom ratio of the front sharp lens The signal processing device according to claim 1. Before sharp lens are interchangeable with respect to the imaging unit provided with the imaging element,
It said second image processing means, according to the type of the mounted lenses in the imaging unit, according to claim 1-4, characterized in that to change the correction factor for correcting the geometric distortion The signal processing device according to any one of the above. Third image processing means for reducing the number of bits of the image signal generated by the image sensor to a predetermined number of bits ;
The signal processing apparatus according to claim 1 , wherein an image signal output from the third image processing unit is input to the second image processing unit . A control method for a signal processing device, comprising:
A first image signal for recording is generated by correcting an optical geometric distortion based on a lens for condensing on an image pickup surface of the image pickup device with respect to an image signal generated by the image pickup device . Image processing steps,
Resizing the image signal generated by the image sensor and before the geometric distortion is corrected in the first image processing step to match the display size of the display unit having a smaller number of pixels than the image sensor processing and performs correction processing of the geometric distortion, have a, a second image processing step of generating an image signal for displaying on the display unit,
In the second image processing step, an arithmetic process is performed on the target pixel of the resized image signal using a plurality of pixels around the target pixel and an interpolation coefficient corresponding to the geometric distortion. And performing the resizing process and the geometric distortion correcting process . A control program used in a signal processing device,
In the computer provided in the signal processing device,
A first image signal for recording is generated by correcting an optical geometric distortion based on a lens for condensing on an image pickup surface of the image pickup device with respect to an image signal generated by the image pickup device . Image processing steps,
Resizing the image signal generated by the image sensor and before the geometric distortion is corrected in the first image processing step to match the display size of the display unit having a smaller number of pixels than the image sensor processing and performs correction processing of the geometric distortion, and the second image processing step of generating an image signal for displaying on the display unit, is executed,
In the second image processing step, an arithmetic process is performed on the target pixel of the resized image signal using a plurality of pixels around the target pixel and an interpolation coefficient corresponding to the geometric distortion. A control program that performs the resizing process and the correction process for the geometric distortion .

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