JP6091216B2 - Image signal processing apparatus, control method therefor, and imaging apparatus - Google Patents

Description

  The present invention relates to a technique for reducing a display delay time when an input image signal is processed and displayed on a display device.

  An imaging device such as a digital video camera or a digital camera includes a display device for confirming a subject image, and a liquid crystal display, an organic EL (electroluminescence) display (panel), an electronic viewfinder (EVF), or the like is used. On the display screen, a subject image photographed by the user, that is, a recorded image can be displayed in real time with a predetermined image quality. In recent years, with the increase in the number of pixels of a recorded image and the increase in functionality of image quality improvement processing, display delay occurs when signal processing takes time. Due to the display delay, the user may feel uncomfortable when operating the camera such as panning, tilting, and zooming, and it may be difficult to check the composition, focus state, and the like. The display delay amount depends on the shooting frame frequency, and the display delay amount increases when the frame frequency is low. Although depending on the configuration of the imaging device, for example, when the frame frequency is 24 Hz (Hertz), the display delay amount is 2.5 times larger than when the frame frequency is 60 Hz.

  A television apparatus has the same problem due to the multi-functionality of image quality improvement processing. When a game device is connected to a television apparatus and a user performs a game operation, a display delay of several frame times occurs when image quality improvement processing is performed on the television apparatus. In some cases, the game result may change due to a delay in user operation, or the user may feel uncomfortable. Therefore, in order to reduce the display delay amount, Patent Document 1 discloses a method for performing low-delay processing that simplifies image quality improvement processing, and a control method for performing frame memory storage processing and readout processing simultaneously. .

Japanese Patent No. 4691193

A problem with conventional devices is how to reduce the display delay time from the generation of an image signal for display to output to the display unit while processing the input image signal. In the conventional technique, it is difficult to shorten the display delay time when displaying an image being shot on a display device when applied to an imaging device or the like.
It is an object of the present invention to shorten a display delay time until an image signal for display is generated and output to a display unit while an input image signal is processed.

In order to solve the above problems, the device according to the present invention, the size change processing means for generating a second image signal by reducing the first image signal, to the first image signal and the second image signal Signal processing means for performing signal processing, output means for outputting the first image signal subjected to signal processing by the signal processing means to a recording medium, and the second image subjected to signal processing by the signal processing means comprising a display signal processing hand stage for performing signal processing for display on the signal. The signal processing means time-divides one frame period into a plurality of periods, and performs signal processing on each of the first image signal and the second image signal in different periods within one frame period, so that the output Before the means outputs the first image signal to the recording medium, the display signal processing means performs the display signal processing on the second image signal generated from the first image signal.

  ADVANTAGE OF THE INVENTION According to this invention, the display delay time until it produces | generates the image signal for a display and it outputs to a display part can be shortened, processing an input image signal.

It is a functional block diagram which shows the structural example of the image signal processing apparatus which concerns on embodiment of this invention. It is a functional block diagram which shows the structure of a comparative example. It is a figure which shows the example of operation timing which concerns on embodiment of this invention. It is a figure which shows the example of operation timing of a comparative example. It is a block diagram which shows the structural example at the time of sharing one DRAM. It is a figure explaining the correction process of a distortion aberration. It is a figure explaining a noise reduction process. It is a figure explaining the noise reduction process in a time division process.

  Hereinafter, embodiments of the present invention will be described in detail. In this embodiment, an example in which an image signal processing apparatus that processes an input image signal for each frame period is applied to an imaging apparatus is shown. A block configuration for shortening the display delay time by extracting a predetermined signal (YCC signal) from a part of the recording image signal processing circuit and outputting it to the display image processing circuit will be described by taking a video camera as an example.

First, a configuration example of the signal processing apparatus according to the present embodiment will be described with reference to FIG.
The imaging sensor 100 is an imaging device using a CCD (charge coupled device), a CMOS (complementary metal oxide semiconductor), or the like. Although omitted in FIG. 1, the incident light amount and focus adjustment are performed on the subject light passing through the lens group constituting the imaging optical system. The sensor 100 photoelectrically converts the formed subject image, internally performs analog-digital conversion, and outputs a digital image signal corresponding to the light amount of each pixel. In each pixel of the image sensor, R (red), G (green), and B (blue) color filters are arranged in a predetermined arrangement, for example, a Bayer arrangement or a honeycomb arrangement. Thereby, an RGB image signal is obtained. In addition, in order to increase the output speed, there is a case where an RGB image signal is output by performing a pixel addition process for obtaining an output image by adding outputs of a plurality of pixels.

  The first resizing processing unit 101 acquires an input image signal (RGB image signal) from the sensor 100 and performs image reduction processing. The size to be reduced is a size that can be processed by the first signal processing unit 102, and the reduction process is executed while correcting the center of gravity for each color of R (red), G (green), and B (blue). The first signal processing unit 102 receives an RGB image signal and performs RGB offset adjustment, gain adjustment, and gamma correction processing. Next, the first signal processing unit 102 converts the RGB image signal into a luminance signal (Y) and a color difference signal (Cb, Cr), and temporarily writes the YCC image signal in the first DRAM 103.

  The second signal processing unit 104 reads the YCC image signal from the first DRAM 103. The second signal processing unit 104 performs lens distortion correction processing, image stabilization processing, and the like on the YCC image signal, and writes the processed YCC image signal to the second DRAM 105. Correction of lens distortion is an example of image distortion correction processing. In the image stabilization processing of the imaging apparatus, correction processing for image blur caused by camera shake or the like is executed. The third signal processing unit 106 reads the YCC image signal from the second DRAM 105. The third signal processing unit 106 performs noise reduction processing or the like on the YCC image signal, and writes the processed YCC image signal in the third DRAM 107. At this time, the third signal processing unit 106 uses the fourth DRAM 119 together as described later in order to realize the noise reduction function.

  The compression / decompression unit 108 reads the YCC image signal from the third DRAM 107 and performs compression encoding processing in accordance with the recording format. The processed signal is sent to the recording medium 109 and recorded. The external output unit 110 reads the YCC image signal from the third DRAM 107 and performs format conversion. A format conversion process is executed in accordance with an image signal transmission format such as HDMI, SDI, component or composite. HDMI is an abbreviation for “High-Definition Multimedia Interface”, and SDI is an abbreviation for “Serial Digital Interface”. The format-converted image signal is output outside the imaging apparatus.

  The second resizing processing unit 111 performs an image size changing process in which the image size of the input image signal is changed for display and written to the fifth DRAM 112. The second resize processing unit 111 of the present embodiment performs a process of reducing the YCC image output from the first signal processing unit 102 to the display size of the display panel. At the time of reduction, in order to prevent image aliasing, the image band is controlled by a band limiting filter in each of the horizontal direction and the vertical direction of the image. Thereafter, image reduction processing is performed by an interpolation method such as a bicubic method, and the processing result is stored in the fifth DRAM 112. The fourth signal processing unit 113 reads the YCC image signal from the fifth DRAM 112. The fourth signal processing unit 113 performs, for example, lens distortion correction processing, image stabilization processing of the imaging device, and the like. The processed YCC image signal is stored in the sixth DRAM 114. The fifth signal processing unit 115 reads the YCC image signal from the sixth DRAM 114. The fifth signal processing unit 115 performs noise reduction processing and the like, and writes the processed YCC signal in the seventh DRAM 116. At that time, the fifth signal processing unit 115 uses the eighth DRAM 120 together in order to realize the noise reduction function.

  The panel signal processing unit 117 performs display signal processing on the image signal whose image size has been changed for display. The panel signal processing unit 117 reads a YCC image signal having a panel display size from the seventh DRAM 116, and performs color adjustment processing, resolution adjustment processing, and the like in accordance with the display panel. The panel output unit 118 performs format conversion in accordance with the reception format of the display panel. The format-converted image signal is transmitted to the display panel and an image is displayed on the screen.

  Next, a comparative example for this embodiment will be described with reference to FIG. The output signal of the imaging sensor 200 is stored in the first DRAM 203 through the first resize processing unit 201 and the first signal processing unit 202. The first resizing processing unit 201, the first signal processing unit 202, the second signal processing unit 204, and the third signal processing unit 206 are the first resizing processing unit 101, the first signal processing unit 102, and the second signal processing shown in FIG. Correspond to the unit 104 and the third signal processing unit 106, respectively. The second DRAM 205, the third DRAM 207, and the fourth DRAM 219 correspond to the second DRAM 105, the third DRAM 107, and the fourth DRAM 119 of FIG. 1, respectively. The image signal output from the third signal processing unit 206 branches into two, one of which is stored in the third DRAM 207 and the other is output to the second resize processing unit 211. The compression / decompression unit 208, the recording medium 209, and the external output unit 210 correspond to the compression / decompression unit 108, the recording medium 109, and the external output unit 110 of FIG.

  The second resizing processing unit 211 has the same function as the second resizing processing unit 111 in FIG. The second resize processing unit 211 performs an image reduction process on the image that has been subjected to all the recorded image processes other than the compression / decompression process, and stores the processed image signal in the fifth DRAM 216. The panel signal processing unit 217 reads a panel display size YCC image signal from the fifth DRAM 216, and performs color adjustment processing, resolution adjustment processing, and the like according to the display panel. The panel output unit 218 performs format conversion in accordance with the reception format of the display panel. The format-converted image signal is transmitted to the display panel and an image is displayed on the screen.

  Next, the configuration of this embodiment in which one DRAM is shared by address control will be described. In FIG. 1, for convenience of explanation, a block configuration in which a plurality of DRAMs are individually used is used. Actually, DRAM is an integrated circuit having process characteristics different from those of an ASIC (Application Specific Integrated Circuit), so that it is often configured as a different chip without being integrated into one chip. The functions of the first to eighth DRAMs shown in FIG. 1 can be realized by address control of one DRAM used as a separate chip from the ASIC. This configuration will be described with reference to FIG. In FIG. 5, components having the same functions as those in FIG. 1 are given the same reference numerals as those used in FIG. 1, and detailed descriptions thereof are omitted.

  The DRAM 152 is connected to a DRAM-I / F (interface) unit 151. Each block that accesses the DRAM 152 and reads / writes data is connected to the DRAM-I / F unit 151. In FIG. 5, the switch unit 150, the second resize processing unit 111, the signal processing a block 153, the signal processing b block 154, the external output unit 110, the compression / decompression unit 108, the panel signal processing unit 117, and the control unit 130 are DRAM-I. / F section 151 is connected. The DRAM-I / F unit 151 arbitrates write requests and read requests received from the respective blocks, and gives permission according to a predetermined priority order. The permitted block, when writing to the DRAM 152, transmits an address and data to be written for a predetermined length. Further, in the case of reading, the permitted block transmits an address to be read, and receives data for a predetermined length from the DRAM 152 via the DRAM-I / F unit 151. Blocks that have low priority and have not been granted permission can send and receive data in sequence, waiting for the reading and writing of blocks with high priority to be completed.

  The output of the first signal processing unit 102 is sent to the switch unit 150. Here, the first path is divided into two paths according to the timing described later. The first path is directly transferred to the DRAM 152 via the DRAM-I / F unit 151. Is the path to write. The second path is a path for performing image reduction processing in accordance with the display size of the display panel 140 by the second resizing processing unit 111 and then writing to the DRAM 152 via the DRAM-I / F unit 151. The switch unit 150 is switched by the control unit 130.

The signal processing a block 153 is a signal processing block that combines the second signal processing unit 104 and the fourth signal processing unit 113 shown in FIG. 1 in time division. This block performs, for example, lens distortion correction processing, image stabilization processing of the imaging apparatus, and the like. This block operates with a high-speed clock signal (for example, 166 MHz) common to the DRAM-I / F unit 151, and the processing time varies depending on the number of pixels to be processed. Hereinafter, the lens distortion correction process will be briefly described with reference to FIG. FIG. 6A illustrates the coordinates of an image without image distortion, and FIG. 6B illustrates the coordinates of an image including image distortion.
Let true image coordinates without image distortion be (xu, yu), and image coordinates including image distortion be (xd, yd). The distortion in the radial direction of the lens is expressed by the following equation.

[Formula 1]
xd = (1 + k1 * r ^ 2 + k2 * r ^ 4 + k3 * r ^ 6) * xu
yd = (1 + k1 * r ^ 2 + k2 * r ^ 4 + k3 * r ^ 6) * yu
r ^ 2 = xu ^ 2 + yu ^ 2 (1)
Here, k1, k2, and k3 are distortion coefficients, which are determined from the lens and the zoom value. In the equation (1), r is a distance from the image center. “^” Represents a power.

The points 601, 602, 603, 604, and 605 having no image distortion shown in FIG. 6A correspond to the points 611, 612, 613, 614, and 615 including the image distortion shown in FIG. . For example, when obtaining pixel data at the coordinates of the point 601, the image data at the coordinate position of the point 611 calculated by the above equation is read from the DRAM 152. Similarly, image data at the coordinate position of point 612 is read out as image data at the coordinates of point 602. In this way, by sequentially reading out image data at the coordinate position corresponding to the calculation result from the DRAM 152, an image in which the lens distortion is corrected is obtained. In the lens distortion correction process, since the number of image coordinates indicated by (xu, yu) is obtained, the processing time is substantially proportional to the number of pixels to be processed. When the image distortion is barrel-shaped, the image area shown in FIG. 6B is slightly larger than the image area shown in FIG. For this reason, it is necessary to prepare a slightly larger image storage area.
In the case of the image stabilization process related to the imaging apparatus, a process for calculating the camera shake amount of the apparatus is executed by an angular velocity sensor, an image recognition processing unit, or the like (not shown). The captured image is subjected to a process of changing the extraction position when a predetermined range is cut out from the captured image area in accordance with the position according to the amount of camera shake, and image blur correction is performed. In this case, the processing time is substantially proportional to the number of pixels of the image generated by extraction.

  Returning to FIG. The signal processing b block 154 is a signal processing block that combines the third signal processing unit 106 and the fifth signal processing unit 115 of FIG. 1 in time division. In this block, for example, noise reduction processing is performed. This block also operates with a high-speed clock signal common to the DRAM-I / F unit 151, and the processing time varies depending on the number of pixels to be processed. The noise reduction process will be described with reference to FIG. FIG. 7 shows a frame cyclic noise reduction circuit as a specific example.

  The frame image signal input from the input terminal 701 is sent to the first subtraction unit 702 and the second subtraction unit 703, respectively. Pixel data at the same position one frame before is sent from the frame memory 705 to the other terminal of the first subtracting unit 702. The subtraction result of the first subtraction unit 702 is sent to the noise detection and motion determination unit 704. The difference data input to the noise detection and motion determination unit 704 is zero if there is no motion in the image. The residual remaining in the portion where there is no motion of the image is noise generated by the sensor 100 or the like, and the noise detection and motion determination unit 704 outputs the noise component to the second subtraction unit 703. The second subtracting unit 703 removes a noise component from the frame image signal input from the input terminal 701 and outputs the image signal through the output terminal 706 and also outputs it to the frame memory 705. Frame memory 705 stores the image signal, which is used in the next frame. When the residual added to the noise detection and motion determination unit 704 is large, the image has a motion, so the noise detection and motion determination unit 704 sets the output to 0. Therefore, the image input from the input terminal 701 is output as it is and stored in the frame memory 705. Since the configuration example of FIG. 7 is a cyclic type, a frame memory used as a FIFO (First In First Out) is required, and the processing time is almost proportional to the number of pixels to be processed.

  The control unit 130 of FIG. 5 includes a synchronization control unit that controls the synchronization timing of the input image signal and the synchronization timing of the display image signal. Control of the driving cycle of the sensor 100, the driving cycle of the display panel 140, and control of the delay time are performed for the sensor 100 and the display panel 140, respectively. Specifically, the delay amount related to the synchronization signal of the drive cycle of the display panel 140 is within a predetermined range with the measurement unit that measures the delay amount of the synchronization signal of the sensor 100 and the display panel 140 as a reference. A synchronization control unit is provided that adjusts to fit within. In addition, a known control block such as a CPU (Central Processing Unit) is provided to control each circuit unit. This control block performs setting adjustment of the first to fifth signal processing units and the panel signal processing unit 117.

Next, the operation of the image signal processing apparatus according to the present embodiment will be described with reference to the operation timing example of FIG.
In the present embodiment, it is assumed that the frequency corresponding to the driving cycle of the sensor 100 and the frequency corresponding to the driving cycle of the display panel 140 are equally synchronized at 24 Hz. As shown in FIG. 3, the synchronization timing is synchronized at a timing when the panel synchronization is delayed compared to the sensor synchronization. The number of pixels of the sensor 100 is 8847360 pixels (horizontal direction 4096 pixels × vertical direction 2160 lines), and the number of pixels of the display panel 140 is 518400 pixels (horizontal direction 960 pixels × vertical direction 540 lines). The signal processing a block and the signal processing b block are capable of processing a 30 Hz progressive image. In the present embodiment, since the sensor 100 is driven at a frequency of 24 Hz, each frame (1/24 seconds) has 8847360 pixels and has a processing capacity of 1 / 24-1 / 30 = 1/120 seconds. There is. Steps 310 to 320 in FIG. 3 represent each process.

First, in step (hereinafter referred to as “S”) 310, the sensor 100 outputs an RGB image signal (horizontal 4096 pixels × vertical 2160 lines). In S <b> 311, the first resize processing unit 101 reduces the RGB image signal output from the sensor 100 to a size that can be processed by the first signal processing unit 102 (horizontal 2048 pixels × vertical 1080 lines). In S312, the first signal processing unit 102 converts the RGB image signal into a luminance signal (Y) and a color difference signal (Cb, Cr). The converted YCC image signal is stored in the first DRAM 103 and transmitted to the second resize processing unit 111.
In S313, the YCC image signal stored in the first DRAM 103 in S312 is read after a lapse of one frame period and 1/120 second from the processing start time in S312 and the second signal processing unit 104 performs processing. The second signal processing unit 104 performs lens distortion correction processing, image stabilization processing of the imaging device, and the like, and writes the processed image signal into the second DRAM 105. Here, the reason why the processing is delayed by a delay time of 1/120 second is to perform processing of the fourth signal processing unit 113 described later (see S317).

  In S314, the YCC image signal stored in the second DRAM 105 in S313 is read after a lapse of one frame period from the processing start time in S313, and the third signal processing unit 106 performs processing. The third signal processing unit 106 performs noise reduction processing in the first period within the frame period, and writes the processed image signal (first image signal) in the third DRAM 107. Here, when the time of about 1/120 second has elapsed from the start of the process, the third signal processing unit 106 temporarily stops the process, and gives priority to the process of the fifth signal processing unit 115 described later. In the second period within the frame period, the fifth signal processing unit 115 performs processing, and writes the processed image signal (second image signal) in the seventh DRAM 116. After the processing of the fifth signal processing unit 115 ends, the third signal processing unit 106 continues the processing. The state of this time division processing will be described with reference to FIG.

  The configuration shown in the dotted line frame in FIG. 8 has the same function as in FIG. 7 except for the frame memory 705. Parts having the same function are denoted by the same reference numerals used in FIG. An image signal from the second DRAM 105 or the sixth DRAM 114 is input to the input terminal 701 through the selection switch unit 710. An image signal from the fourth DRAM 119 or the eighth DRAM 120 is input to the input terminal 714 through the selection switch unit 711. The output terminal 706 is connected to the third DRAM 107 or the seventh DRAM 116 via the selection switch unit 712. The output terminal 715 is connected to the fourth DRAM 119 or the eighth DRAM 120 via the selection switch unit 713. “L” shown at each contact of the selection switch units 710 to 713 represents line selection of the main line system (external output and recording signal processing system), and “P” represents line selection of the panel processing system (display panel signal processing system). Represent.

  In the noise reduction processing, in the case of main line processing performed by the third signal processing unit 106, the selection switch units 710 to 713 are switched to the L side. The output signal after the noise reduction process is written into the third DRAM 107 through the selection switch unit 712. When the time of 1/120 second has elapsed from the start of the processing, the main line processing is temporarily interrupted, the selection switches 710 to 713 are switched to the P side, and the noise reduction processing of the panel processing system is started. . This switching control is performed by, for example, an interrupt routine of a CPU (not shown), but timer switching may be performed. Since the number of pixels processed by the panel processing system is small, the processing is completed within 1/120 second. Again, the selection switch units 710 to 713 are switched to the L side, and the processing continues from the point where the main line processing is interrupted. Actually, selection control by the selection switch units 710 to 713 and address control in the DRAM can be realized by changing an address when a CPU (not shown) accesses the DRAM.

  Returning to FIG. 3, the description will be continued. In S315, the YCC image signal (first image signal) stored in the third DRAM 107 in S314 is read after a lapse of one frame period from the processing start time in S314, and the external output unit 110 performs processing. The external output unit 110 performs format conversion according to a predetermined image signal transmission format, and outputs the converted image signal to the outside of the imaging apparatus. In the case of recording processing, the compression / decompression unit 108 reads and processes the YCC image signal from the third DRAM 107 and records the image signal on the recording medium 109.

After S312, in S316, the second resizing processing unit 111 performs image reduction processing to reduce the image to the display size of the display panel 140 (horizontal direction 960 pixels × vertical direction 540 lines) (horizontal direction: 15/32, vertical). Direction: 1/2). In S317, the signal processing a block 153 (see FIG. 5) is preferentially used, so that lens distortion correction processing, image stabilization processing of the imaging apparatus, and the like are executed. In S318, the noise reduction process is executed by preferentially using the signal processing b block 154 (see FIG. 5). The processed YCC image signal (second image signal) is stored in the seventh DRAM 116. In S319, the panel signal processing unit 117 reads the image signal stored in the seventh DRAM 116 in S318, and performs format conversion in accordance with the reception format of the display panel 140. The panel output unit 118 transmits the format-converted image signal to the display panel 140 in S320, and an image is displayed on the screen of the display panel 140.
In the case of the present embodiment, the process is performed in a time of just over one frame period (see DL) from S310 to the start time of S320.

  Next, the operation of the comparative example illustrated in FIG. 2 will be described with reference to the operation timing example of FIG. Each process of processing is shown in S410 to S420. In S410, the signal of the sensor 200 is read, in S411, the first resize processing unit 201 is processed, and in S412, the first signal processing unit 202 is processed. In S413, the processing of the second signal processing unit 204 is performed after the elapse of one frame period from the processing start time of S412. Further, after the elapse of one frame period, the process of the third signal processing unit 206 is performed in S414. Further, after the elapse of one frame period, the process of the external output unit 210 is performed in S415. In S416, the second resizing processing unit 211 performs processing. The processing of the panel signal processing unit 217 in S419 and the processing of the panel output unit 218 in S420 are executed at the same time.

  In the case of the comparative example shown in FIG. 2, the second resize processing unit 211 receives the image signal from the third signal processing unit 206 and performs image reduction processing (see S416 in FIG. 4). To remember. Therefore, there is a panel output process period of S420 at the same time as the process of S415 in FIG. 4, and a display delay time corresponding to 3 frame periods (refer to DL) has occurred since S410. This is a display delay time of about 125 milliseconds when the frame frequency is 24 Hz.

As described above, according to the present embodiment, by giving priority to the processing of the display image signal by the time division processing of the signal processing unit, it is possible to shorten the display delay time when displaying the image being shot on the display device. . The display delay time is slightly longer than one frame period from S310 to S320 in FIG. 3, which is significantly shorter than the display delay time in the three frame period of the comparative example shown in FIG. By reducing the display delay time when displaying the captured image on the display device, it is possible to eliminate the user's uncomfortable feeling due to the display delay.
Further, when performing image signal recording processing and output processing, the signal processing a block 153 and the signal processing b block 154 have the ability to process the image signal in 1/30 second. A gap of 1/120 second is formed within a 1/24 second period corresponding to the frame frequency of the display image signal. By giving priority to the processing of the fourth signal processing unit 113 related to the image signal for display in the gap between the periods for processing the image signals of adjacent frames, the processing efficiency is increased.
In this embodiment, since the drive cycle of the imaging sensor and the drive cycle of the display panel are the same, control is facilitated, but each drive cycle may be different.

100 sensor (imaging means)
106 third signal processing unit 110 external output unit 111 second resize processing unit 115 fifth signal processing unit 117 signal processing unit for panel 118 panel output unit 140 display panel 152 DRAM

Claims (7)

Resizing processing means for generating a second image signal by reducing the first image signal;
Signal processing means for performing signal processing on the first image signal and the second image signal;
Output means for outputting the first image signal subjected to signal processing by the signal processing means to a recording medium;
Includes a display signal processing hand stage for performing signal processing for display to the second image signal which the signal processing has been performed by the signal processing means,
The signal processing means time-divides one frame period into a plurality of periods, and performs signal processing on each of the first image signal and the second image signal in different periods within one frame period, so that the output The display signal processing means performs the display signal processing on the second image signal generated from the first image signal before the means outputs the first image signal to the recording medium. An image signal processing apparatus. 2. The image signal processing according to claim 1, wherein the signal processing means performs signal processing on the first image signal after first performing signal processing on the second image signal in one frame period. apparatus. The image signal processing apparatus according to claim 1, wherein the signal processing unit interrupts signal processing on the first image signal and performs signal processing on the second image signal. Storage means for storing the first image signal subjected to signal processing by the signal processing means and the second image signal subjected to signal processing by the signal processing means;
The output means reads the first image signal from the storage means and outputs it to the recording medium,
4. The image signal processing apparatus according to claim 1, wherein the display signal processing unit reads the second image signal from the storage unit and performs the display signal processing. 5. Said signal processing means, noise reduction processing, the image distortion correction process, and image blur of claims 1 to 4, characterized in that one or more processing among the correction process according to any one of Image signal processing device. Imaging means;
Resizing processing means for reducing the first image signal generated by the imaging means to generate a second image signal ;
Signal processing means for performing signal processing on the first image signal and the second image signal;
Output means for outputting the first image signal subjected to signal processing by the signal processing means to a recording medium;
Includes a display signal processing hand stage for performing signal processing for display to the second image signal which the signal processing has been performed by the signal processing means,
The signal processing means time-divides one frame period into a plurality of periods, and performs signal processing on each of the first image signal and the second image signal in different periods within one frame period, so that the output The display signal processing means performs the display signal processing on the second image signal generated from the first image signal before the means outputs the first image signal to the recording medium. An imaging apparatus characterized by the above. A resizing step of reducing the first image signal to generate a second image signal ;
A signal processing step of performing signal processing on the first image signal and the second image signal;
An output step of outputting the first image signal that has undergone signal processing in the signal processing step to a recording medium;
A display signal processing steps for performing signal processing for display to the second image signal which the signal processing is performed in the signal processing step,
In the signal processing step, one frame period is time-divided into a plurality of periods, and signal processing is performed on each of the first image signal and the second image signal in different periods within one frame period, Control of the image signal processing apparatus, wherein the signal processing for display is performed on the second image signal generated from the first image signal before the first image signal is output to the recording medium. Method.

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