JP6206338B2 - Switching module - Google Patents

Description

  The present invention relates to a switching module including a series connection body of a high potential side semiconductor switch and a low potential side semiconductor switch, and a capacitor connected in parallel to the series connection body.

  Conventionally, as can be seen in Patent Document 1 below, electric power including a series connection body of a pair of semiconductor switches (IGBT) and a surge voltage absorbing capacitor connected in parallel to the series connection body via a conductor (bus bar) Conversion devices are known. Specifically, in this apparatus, the connection terminal of the capacitor is set close to the terminal position of the semiconductor switch. With such a configuration, the parasitic inductance of the loop circuit composed of the semiconductor switch and the capacitor is reduced. Thereby, the surge voltage applied to both ends of the semiconductor switch at the time of switching of the semiconductor switch is made lower than the rated voltage.

Japanese Patent No. 3447543

  Here, in the configuration described in Patent Document 1, the semiconductor switch and the capacitor are connected by a bus bar. Since the inductance of the bus bar is large, there is a concern that the configuration described in Patent Document 1 cannot sufficiently reduce the parasitic inductance of the loop circuit. In this case, there is a concern that the switching frequency of the semiconductor switch cannot be increased.

  The present invention has been made in order to solve the above-described problems, and an object thereof is to provide a series connection body of a high potential side semiconductor switch and a low potential side semiconductor switch, and a capacitor connected in parallel to the series connection body. And providing a switching module capable of reducing a closed-loop parasitic inductance including the series connection body and the capacitor.

  In order to achieve the above object, the present invention is a high-potential-side semiconductor switch comprising a semiconductor chip having a first electrode and a second electrode, which opens and closes a current flow path between the first electrode and the second electrode. Swp), and a series connection body of low-potential side semiconductor switches (Swn), which is composed of a semiconductor chip having a third electrode and a fourth electrode, and opens and closes a current flow path between the third electrode and the fourth electrode. , A capacitor (12) connected in parallel to the series connection body, a high potential side wiring (14H) connecting the first electrode and the first end of the capacitor, a fourth electrode and a second of the capacitor A low-potential-side wiring (14L) that connects the ends, and an intermediate wiring (14M) that connects the second electrode and the third electrode. Based on such a configuration, the high potential side semiconductor switch, the low potential side semiconductor switch, the capacitor, the high potential side wiring, the low potential side wiring, and the intermediate wiring are integrated using an insulator (20). By forming the module (10) having a multilayer structure, each of the high potential side wiring and the low potential side wiring is a layer different from a layer in which the intermediate wiring is provided in the module, The high potential side semiconductor switch and the low potential side semiconductor switch are provided in the module in the module stacking direction so as to be separated from each other in layers separated in the same direction from the layer in which the intermediate wiring is provided. Provided on a layer sandwiched between each of the potential-side wiring and the low-potential-side wiring and the intermediate wiring and spaced apart from each other. A sensor is provided between the high potential side semiconductor switch and the low potential side semiconductor switch in an inner layer sandwiched between the high potential side wiring and the low potential side wiring and the intermediate wiring. It is characterized by.

  In the above invention, the high-potential side semiconductor switch, the low-potential side semiconductor switch, the capacitor, the high-potential side wiring, the low-potential side wiring, and the intermediate wiring are integrally formed using an insulator, so that these members are modularized. Yes. In such a configuration, in the above invention, the capacitor is placed between the high potential side semiconductor switch and the low potential side semiconductor switch in the inner layer sandwiched between the high potential side wiring and the low potential side wiring and the intermediate wiring. Yes.

  By providing the capacitor at such a position, it is possible to bring the intermediate wiring and the capacitor closer in the stacking direction of the module as compared with a configuration in which the capacitor is provided on the outer surface of the module. For this reason, the closed loop including the high potential side semiconductor switch, the intermediate wiring, the low potential side semiconductor switch, the low potential side wiring, the capacitor, and the high potential side wiring can be reduced, and the parasitic inductance of the closed loop can be reduced. Further, since the direction of current flowing through the intermediate wiring is opposite to the direction of current flow through the capacitor, it is possible to obtain a magnetic flux canceling effect by bringing the intermediate wiring and the capacitor closer to each other. This effect also contributes to the reduction of parasitic inductance. Thus, according to the above invention, the parasitic inductance of the closed loop can be reduced, and consequently the switching frequency of the semiconductor switch can be increased.

The block diagram of the DC / DC converter concerning 1st Embodiment. Sectional drawing of the module concerning the embodiment. FIG. 3 is a sectional view taken along line 3-3 in FIG. 2. Sectional drawing of the module concerning 1st Embodiment. Sectional drawing of the module concerning 2nd Embodiment. The top view of the module concerning the embodiment.

(First embodiment)
Hereinafter, a first embodiment of a switching module according to the present invention will be described with reference to the drawings.

  As shown in FIG. 1, the module 10 includes a high potential side chip Swp, a low potential side chip Swn, and a first capacitor 12. Each of the chips Swp and Swn is a bare chip and includes a semiconductor switch. Each chip Swp, Swn constitutes a half bridge. In this embodiment, a voltage-controlled semiconductor switching element is used as the switch, and specifically, an N-channel MOSFET is used. Note that diodes FDp and FDn (for example, body diodes) are connected in antiparallel to the switch. In the present embodiment, it is assumed that the diodes FDp and FDn are also included in the chips Swp and Swn.

  The high potential side wiring 14H is connected to the drain (first electrode) of the high potential side chip Swp. The source (second electrode) of the high potential side chip Swp and the drain (third electrode) of the low potential side chip Swn are connected by an intermediate wiring 14M. The low potential side wiring 14L is connected to the source (fourth electrode) of the low potential side chip Swn. A high potential side wiring 14 </ b> H is connected to a first end of the first capacitor 12, and a low potential side wiring 14 </ b> L is connected to a second end of the first capacitor 12. As the first capacitor 12, for example, a chip capacitor can be used. A P terminal TP is connected to the high potential side wiring 14H, and an N terminal TN is connected to the low potential side wiring 14L. An output terminal TO is connected to the intermediate wiring 14M.

  Here, in the present embodiment, the module 10 constitutes a non-insulated DC / DC converter as a power conversion circuit. Specifically, a positive terminal (not shown) of a DC power supply (for example, a battery) is connected to the P terminal TP, and a negative terminal of the DC power supply is connected to the N terminal TN. The output terminal TO is connected to a first end of a reactor (not shown) for stepping down, and a positive terminal of an output load (not shown) is connected to the second end of the reactor. An N terminal TN is connected to the negative terminal of the output load. Further, an output smoothing capacitor (not shown) is connected in parallel to the output load.

  The P terminal TP is further connected to first ends of second and third capacitors 16 and 18. The N terminal TN is further connected to the second ends of the second and third capacitors 16 and 18. The first and second capacitors 12 and 16 are provided as snubber capacitors that absorb a surge voltage. The third capacitor 18 is provided as a smoothing capacitor that smoothes the input voltage between the P terminal TP and the N terminal TN. The capacitance C1 of the first capacitor 12 is set to be smaller than the capacitance C2 of the second capacitor 16. For this reason, the physique of the first capacitor 12 is smaller than the physique of the second capacitor 16. Further, the capacitance C2 of the second capacitor 16 is set smaller than the capacitance C3 of the third capacitor 18. For this reason, the physique of the second capacitor 16 is smaller than the physique of the third capacitor 18.

  In the present embodiment, the closed loop including the first capacitor 12, the high potential side wiring 14H, the high potential side chip Swp, the intermediate wiring 14M, the low potential side chip Swn, and the low potential side wiring 14L is referred to as a first closed loop. And A closed loop including the second capacitor 16, the high potential side wiring 14H, the high potential side chip Swp, the intermediate wiring 14M, the low potential side chip Swn, and the low potential side wiring 14L is referred to as a second closed loop. Further, a closed loop including the third capacitor 18, the high potential side wiring 14H, the high potential side chip Swp, the intermediate wiring 14M, the low potential side chip Swn, and the low potential side wiring 14L is referred to as a third closed loop.

  Incidentally, in FIG. 1, the parasitic inductance of the first closed loop is indicated by “L1”. Further, the parasitic inductance of the electric path that does not include the first closed loop among the second closed loops is indicated by “L2”. Furthermore, the parasitic inductance of the electrical path that does not include the second closed loop of the third closed loop is indicated by “L3”.

  FIG. 2 shows a cross-sectional view of a portion where the module 10 constituting the DC / DC converter is mounted on a circuit board.

  The DC / DC converter includes a module 10 incorporating each chip Swp, Swn, and a circuit board 40 (for example, a printed board). In the present embodiment, the high potential side chip Swp, the low potential side chip Swn, the first capacitor 12, the high potential side wiring 14H, the low potential side wiring 14L, and the intermediate wiring 14M are integrally formed using the insulator 20. Thus, a multilayer substrate is obtained. In FIG. 2, a multilayer substrate having a three-layer structure is illustrated. In addition, the multilayer board | substrate is what hot-pressed what laminated | stacked each wiring 14H, 14L, 14L formed as a pattern which consists of copper foil, and the base material (for example, thermoplastic resin film) as the insulator 20, for example. Can be formed integrally. An example of such an integration method is PALAP (registered trademark).

  The high potential side chip Swp and the low potential side chip Swn are provided in the same inner layer of the module 10 without being exposed to the outer surface of the module 10. Specifically, the high-potential side chip Swp and the low-potential side chip Swn are electrically insulated from each other by the insulator 20 in the layer in which these chips are provided. Here, each of the chips Swp and Swn is a vertical device. For this reason, a source and a gate are formed on one surface of each of the chips Swp and Swn, and a drain is formed on the surface opposite to this surface.

  A high potential side wiring 14 </ b> H is connected to the surface of the high potential side chip Swp on which the drain is formed via the first via conductor 22. An intermediate wiring 14 </ b> M is connected to the surface of the high potential side chip Swp on which the source is formed via the second via conductor 24. On the other hand, the low potential side wiring 14 </ b> L is connected to the surface of the low potential side chip Swn where the source is formed via the third via conductor 26. An intermediate wiring 14 </ b> M is connected to the surface of the low potential side chip Swn where the drain is formed via the fourth via conductor 28. The first and third via conductors 22 and 26 are formed in the same layer, and the second and fourth via conductors 24 and 28 are formed in the same layer.

  Each of the high potential side wiring 14H and the low potential side wiring 14L is a layer different from the layer in which the intermediate wiring 14M is provided, and is separated in the direction from the layer in which the intermediate wiring 14M is provided to the circuit substrate 40 in the stacking direction. The layers are separated from each other by an insulator 20. In the present embodiment, the high potential side wiring 14 </ b> H and the low potential side wiring 14 </ b> L are formed on the outer surface of the module 10. Each of the high potential side chip Swp and the low potential side chip Swn is provided in the module 10 so as to be separated from each other in a layer sandwiched between the high potential side wiring 14H and the low potential side wiring 14L and the intermediate wiring 14M. Yes. A first end of the first capacitor 12 is connected to the high potential side wiring 14 </ b> H through a fifth via conductor 30. The low potential side wiring 14 </ b> L is connected to the second end of the first capacitor 12 through the sixth via conductor 32. In the present embodiment, the first capacitor 12 is formed in the same layer as each of the chips Swp and Swn. The fifth and sixth via conductors 30 and 32 are formed in the same layer as the first and third via conductors 22 and 26 and sandwiched between the first and third via conductors 22 and 26.

  The module 10 is mounted on the circuit board 40. A circular main through hole 42 is formed in the circuit board 40. As a result, a space 44 is formed in the circuit board 40. The module 10 is mounted such that the low-potential side wiring 14L and the high-potential side wiring 14H face the circuit board 40. Hereinafter, in the circuit board 40, the mounting surface of the module 10 is referred to as a first surface, and the back surface of the first surface is referred to as a second surface.

  Each of the high potential side wiring 14 </ b> H and the low potential side wiring 14 </ b> L is provided in the vicinity of the main through hole 42 of the circuit board 40, with a part exposed from the joint surface between the circuit board 40 and the module 10. The first end of the second capacitor 16 is connected to the exposed portion of the high potential side wiring 14H, and the second end of the second capacitor 16 is connected to the exposed portion of the low potential side wiring 14L. The second capacitor 16 is provided on the outer surface of the pair of outer surfaces in the stacking direction of the module 10 where the high potential side wiring 14H and the low potential side wiring 14L are exposed. FIG. 2 shows a state in which the first end and the second end of the second capacitor 16 are soldered to the wirings 14H and 14L.

  The intermediate wiring 14 </ b> M is provided on the first surface of the circuit board 40, the seventh via conductor 34 extending over all the layers (three layers) of the module 10, the first wiring 36 patterned on the outer surface of the module 10, and the circuit board 40. The first conductor 38 is connected to the output terminal TO. The seventh via conductor 34 is formed outside the high potential side chip Swp in the direction in which the layer of the module 10 extends. The output terminal TO is formed on the first surface of the circuit board 40.

  A first through hole 46 and a second through hole 48 are formed in the circuit board 40 so as to sandwich the main through hole 42. The through holes 46 and 48 are filled with second and third conductors 50 and 52 (corresponding to “first and second conductive members”). The high potential side wiring 14 </ b> H includes a fourth conductor 54 sandwiched between the module 10 and the circuit board 40, a second wiring 56 patterned on the first surface of the circuit board 40, and the second conductor 50. The P terminal TP formed on the second surface of the circuit board 40 is connected. The low potential side wiring 14 </ b> L includes a fifth conductor 58 sandwiched between the module 10 and the circuit board 40, a third wiring 60 patterned on the first surface of the circuit board 40, and a third conductor 52. The N terminal TN formed on the second surface of the circuit board 40 is connected. The terminals TP and TN are formed with the main through hole 42 interposed therebetween.

  On the second surface of the circuit board 40, the first terminal of the third capacitor 18 is connected to the P terminal TP, and the second terminal of the third capacitor 18 is connected to the N terminal TN. FIG. 2 shows a state in which the first end and the second end of the third capacitor 18 are soldered to the terminals TP and TN.

  A radiator 64 is provided on the outer surface opposite to the outer surface facing the first surface of the circuit board 40 among the pair of outer surfaces in the stacking direction of the modules 10 via an insulating layer 62. The radiator 64 has a function of releasing heat generated in the module 10 to the outside. In addition, it is desirable to use a thing with high heat conductivity as the insulating layer 62, for example, a ceramic and an insulating film may be used.

  FIG. 3 is a sectional view taken along line 3-3 in FIG. In FIG. 3, each of the first wiring 36, the high potential side wiring 14 </ b> H, and the low potential side wiring 14 </ b> L projected on the cross section of the module 10 is indicated by a broken line. Each of these broken lines indicates that the entire interior is patterned. In addition, projections of the first via conductor 22 and the third via conductor 26 onto the cross section of the module 10 are also indicated by broken lines. In FIG. 3, the gates of the chips Swp and Swn are not shown. Incidentally, in the present embodiment, the intermediate wiring 14M is formed so that the projection of the intermediate wiring 14M on the cross section of the module 10 includes the wirings 14H and 14L and the first wiring 36.

  As illustrated, in the present embodiment, a plurality of capacitors are arranged in a row between the high potential side chip Swp and the low potential side chip Swn. A high potential side wiring 14H is connected to the first end of each capacitor, and a low potential side wiring 14L is connected to the second end of each capacitor. That is, the first capacitor 12 is configured by connecting these capacitors in parallel with each other. In the present embodiment, a plurality of seventh via conductors 34 are formed in a direction in which a plurality of capacitors constituting the first capacitor 12 are arranged.

  According to the embodiment described in detail above, the following effects can be obtained.

  (1) The first capacitor 12 is provided between the high potential side chip Swp and the low potential side chip Swn in the inner layer sandwiched between the high potential side wiring 14H and the low potential side wiring 14L and the intermediate wiring 14M. It was. For this reason, the intermediate wiring 14 </ b> M and the first capacitor 12 can be brought close to each other in the stacking direction of the modules 10. Thereby, a 1st closed loop can be minimized and the parasitic inductance L1 of a 1st closed loop can be reduced by extension.

  Moreover, as shown in FIG. 4, the 1st capacitor | condenser 12 and the intermediate wiring 14M can be made to oppose. The direction of the current flowing through the first capacitor 12 and the direction of the current flowing through the intermediate wiring 14M can be reversed. For this reason, the cancellation effect of the magnetic flux by the electric current which flows into the 1st capacitor | condenser 12 and the magnetic flux by the electric current which flows through the intermediate wiring 14M can be heightened. Thereby, the parasitic inductance L1 of the first closed loop can be further reduced. In FIG. 4, hatching indicating a cross section is omitted. As described above, according to the present embodiment, the switching frequency of the switches constituting the chips Swp and Swn can be increased by reducing the parasitic inductance L1.

  (2) The second capacitor 16 is provided on the outer surface of the pair of outer surfaces in the stacking direction of the module 10 where the high potential side wiring 14H and the low potential side wiring 14L are exposed. This is because, in the present embodiment, the first capacitor 12 alone cannot absorb the surge voltage generated due to the switching of the switches constituting the chips Swp and Swn. Here, in the second closed loop including the second capacitor 16, if the parasitic inductance L2 of the electric path not including the first closed loop is large, the surge voltage that the first capacitor 12 takes is increased. For this reason, in order to reduce the surge voltage that the first capacitor 12 is responsible for, it is required to reduce the second closed loop and reduce the parasitic inductance L2.

  Here, in the present embodiment, the outer surface on which the high potential side wiring 14H and the low potential side wiring 14L are exposed is the installation position of the second capacitor 16. According to such a configuration, the second capacitor 16 can be brought close to the high potential side wiring 14H and the low potential side wiring 14L in the stacking direction. For this reason, the second closed loop can be minimized. Thereby, the parasitic inductance L2 of the electric path which does not include the first closed loop among the second closed loops can be reduced. Therefore, it is possible to reduce the surge voltage applied to the first capacitor 12 in accordance with the switching of the switches constituting the chips Swp and Swn.

  (3) The module 10 is mounted on the circuit board 40 so that the second capacitor 16 is accommodated in the space 44 formed in the circuit board 40. For this reason, the outer surface opposite to the outer surface facing the first surface of the circuit board 40 among the pair of outer surfaces in the stacking direction of the modules 10 can be used as the installation region of the radiator 64. Thereby, the mounting area of the radiator 64 can be increased, and as a result, the cooling efficiency of the module 10 can be improved.

  (4) The third capacitor 18 is provided on the second surface of the circuit board 40 so as to straddle the main through hole 42. If the parasitic inductance L3 of the electric path that does not include the second closed loop among the third closed loops is large, the surge voltage applied to the second capacitor 16 increases with the switching of the switches constituting the chips Swp and Swn. Here, by providing the third capacitor 18 across the main through hole 42 on the second surface of the circuit board 40, the third capacitor 18 is connected to the high potential side wiring 14H and the low potential side in the stacking direction of the module 10. It can be brought close to the wiring 14L. Thereby, a 3rd closed loop can be minimized and the parasitic inductance L3 of the electrical path which does not contain a 2nd closed loop among 3rd closed loops can be reduced. Therefore, the surge voltage applied to the second capacitor 16 can be reduced.

  (5) The second capacitor 16 and the third capacitor 18 are disposed so that the region where the second capacitor 16 is projected onto the circuit board 40 is included in the region where the third capacitor 18 is projected onto the circuit board 40. According to such a configuration, an electrical path that does not include the second closed loop of the third closed loop can be shortened. For this reason, the parasitic inductance L3 can be reduced.

  (6) The first capacitor 12 and the second capacitor 16 are arranged so that the area where the second capacitor 16 is projected onto the circuit board 40 includes the area where the first capacitor 12 is projected onto the circuit board 40. According to such a configuration, it is possible to shorten the electrical path that does not include the first closed loop of the second closed loop. For this reason, the parasitic inductance L2 can be reduced.

  (7) The capacitance of the second capacitor 16 is set larger than the capacitance of the first capacitor 12. When the electrostatic capacity is large, the size of the capacitor increases and the inductance of the capacitor itself increases. As a result, the inductance of the second closed loop is also increased. For this reason, this embodiment in which the inductance of the second closed loop tends to be large has a great merit in adopting a configuration that can reduce the parasitic inductance L2.

  (8) In a plan view of the plate surface of the circuit board 40, a plurality of capacitors are arranged in a row between the high potential side chip Swp and the low potential side chip Swn in a direction orthogonal to the direction in which the chips Swp and Swn are arranged. did. And the 1st capacitor | condenser 12 was comprised by connecting these capacitors mutually in parallel. According to such a configuration, it is possible to reduce the capacity of the individual capacitors constituting the first capacitor 12, and thus to reduce the size of the individual capacitors. Therefore, the space between the chips Swp and Swn can be effectively used in the module 10 while ensuring the surge absorbing capacitance required for the first capacitor 12.

(Second Embodiment)
Hereinafter, the second embodiment will be described with reference to the drawings with a focus on differences from the first embodiment. In the present embodiment, the configuration of the DC / DC converter is changed as shown in FIG. In FIG. 5, the same members as those shown in FIG. 2 are denoted by the same reference numerals for convenience.

  As shown in the figure, the high potential side wiring 14H is connected to the surface of the high potential side chip Swp where the drain is formed via the second via conductor 24a. The intermediate wiring 14M is connected to the surface of the high potential side chip Swp on which the source is formed via the first via conductor 22a. On the other hand, the low potential side wiring 14L is connected to the surface of the low potential side chip Swn on which the source is formed via the fourth via conductor 28a. The intermediate wiring 14M is connected to the surface of the low potential side chip Swn where the drain is formed via the third via conductor 26a. The first and third via conductors 22a and 26a are formed in the same layer, and the second and fourth via conductors 24a and 28a are formed in the same layer.

  A first end of the first capacitor 12 is connected to the high potential side wiring 14H through a fifth via conductor 30a. The low potential side wiring 14L is connected to the second end of the first capacitor 12 via the sixth via conductor 32a. The fifth and sixth via conductors 30a and 32a are formed in the same layer as the second and fourth via conductors 24a and 28a.

  The module 10 is mounted on the circuit board 40 such that the intermediate wiring 14M faces the first surface of the circuit board 40. A radiator 65 is provided on the outer surface opposite to the outer surface facing the first surface of the circuit board 40 among the pair of outer surfaces in the stacking direction of the modules 10 via an insulating layer 62a. As shown in FIGS. 5 and 6, a circular main through hole 65 a is formed in the radiator 65. Thereby, a space 66 is formed in the radiator 65. Each of the high potential side wiring 14 </ b> H and the low potential side wiring 14 </ b> L is provided in the form exposed from the joint surface between the module 10 and the radiator 65 in the vicinity of the main through hole 65 a of the radiator 65. The first end of the second capacitor 16 is connected to the exposed portion of the high potential side wiring 14H, and the second end of the second capacitor 16 is connected to the exposed portion of the low potential side wiring 14L. The second capacitor 16 is provided on the outer surface of the pair of outer surfaces in the stacking direction of the module 10 where the high potential side wiring 14H and the low potential side wiring 14L are exposed. The module 10 is provided in the radiator 65 so that the second capacitor 16 is accommodated in the space 66 of the radiator 65.

  A first through hole 46 a and a second through hole 48 a are formed in the circuit board 40 so as to sandwich the second capacitor 16. The through holes 46a and 48a are filled with sixth and seventh conductors 50a and 52a. The high-potential-side wiring 14H includes an eighth via conductor 70 that extends over three layers of the module 10, a fourth wiring 72 that is patterned on the outer surface of the module 10, and an eighth sandwiched between the module 10 and the circuit board 40. The P terminal TP is connected through the conductor 74 and the fifth wiring 76 patterned on the first surface of the circuit board 40. The low potential side wiring 14L includes a ninth via conductor 80 extending over three layers, a sixth wiring 82 patterned on the outer surface of the module 10, and a ninth conductor 84 sandwiched between the module 10 and the circuit board 40. The N terminal TN is connected via the eighth wiring 86 patterned on the first surface of the circuit board 40. On the second surface of the circuit board 40, the first terminal of the third capacitor 18 is connected to the P terminal TP, and the second terminal of the third capacitor 18 is connected to the N terminal TN.

  According to this embodiment described above, in addition to the effects (1), (2), (4) to (8) obtained in the first embodiment, the following effects can be obtained.

  (9) The module 65 is provided with the radiator 65 so that the intermediate wiring 14 </ b> M faces the radiator 65 and the second capacitor 16 is accommodated in the space 66. Such a configuration is employed to suppress noise from being transmitted from the module 10 (DC / DC converter) to its ground line. That is, in the present embodiment, the radiator 65 is connected to the ground line. Here, since the insulating layer 62a is provided between each of the high-potential-side wiring 14H and the low-potential-side wiring 14L and the radiator 65, there is a parasitic between each of the wirings 14H and 14L and the radiator 65. A capacity is formed. Here, since the high potential side wiring 14H and the low potential side wiring 14L are connected to the positive terminal and the negative terminal of the DC power source, the potential fluctuation is smaller than that of the intermediate wiring 14M. For this reason, by disposing the high potential side wiring 14H and the low potential side wiring 14L on the radiator 65 side, noise transmitted to the ground line through the parasitic capacitance can be reduced.

(Other embodiments)
Each of the above embodiments may be modified as follows.

  In the first embodiment, the main through hole 42 penetrating from the first surface to the second surface of the circuit board 40 is formed in the circuit board 40, so that the space portion for accommodating the second capacitor 16 is formed. Not limited to this. For example, although not penetrating from the first surface to the second surface of the circuit board 40, a groove portion extending from the first surface to the second surface side is formed in the circuit board 40. The groove may be used as a space for accommodating the second capacitor 16.

  The semiconductor switch is not limited to a MOSFET but may be, for example, an IGBT. In this case, the semiconductor switch opens and closes a current flow path between the collector and the emitter.

  In the first embodiment, the second capacitor 16 and the third capacitor 18 are arranged so that the area where the second capacitor 16 is projected onto the circuit board 40 is included in the area where the third capacitor 18 is projected onto the circuit board 40. However, it is not limited to this. These capacitors 16 and 18 may be arranged so that at least a part of the third capacitor 18 and at least a part of the second capacitor 16 overlap in a plan view of the circuit board 40. Even in this case, an electrical path that does not include the second closed loop among the third closed loops can be shortened.

  Further, the capacitors 12 and 16 may be arranged so that at least a part of the second capacitor 16 and at least a part of the first capacitor 12 overlap in a plan view of the circuit board 40. Even in this case, an electrical path that does not include the first closed loop among the second closed loops can be shortened.

  In each of the above embodiments, the series connection body of the first capacitor 12 and the resistor may be connected in parallel to the series connection body of the chips Swp and Swn.

  The power conversion circuit configured by the module 10 is not limited to a DC / DC converter, and may be, for example, an inverter including a half bridge circuit or a full bridge circuit. Specifically, for example, the three modules 10 can constitute a three-phase inverter as a power conversion circuit. In this case, the series connection body of the high potential side chip Swp and the low potential side chip Swn of each module 10 is connected in parallel to each other. Moreover, for example, one end of each phase winding of the motor generator is connected to the output terminal TO of each module 10. The motor generator is, for example, an in-vehicle main machine. When the boost converter that boosts and outputs the voltage of the battery is connected to the input side of the inverter, the boost converter serves as a DC power source.

  DESCRIPTION OF SYMBOLS 10 ... Module, 12 ... 1st capacitor, 14H ... High potential side wiring, 14L ... Low potential side wiring, 14M ... Intermediate wiring, Swp ... High potential side chip, Swn ... Low potential side chip

Claims (10)

A high-potential-side semiconductor switch (Swp) configured by a semiconductor chip having a first electrode and a second electrode, and opening and closing a current flow path between the first electrode and the second electrode; and a third electrode and a fourth electrode A series connection body of low-potential side semiconductor switches (Swn) configured to open and close a current flow path between the third electrode and the fourth electrode;
A first capacitor (12) connected in parallel to the series connection body;
A high potential side wiring (14H) connecting the first electrode and the first end of the first capacitor;
A low-potential side wiring (14L) connecting the fourth electrode and the second end of the first capacitor;
An intermediate wiring (14M) for connecting the second electrode and the third electrode;
The high potential side semiconductor switch, the low potential side semiconductor switch, the first capacitor, the high potential side wiring, the low potential side wiring, and the intermediate wiring are integrally formed using an insulator (20). Thus, a module (10) having a multilayer structure is obtained.
Each of the high potential side wiring and the low potential side wiring is a layer different from the layer in which the intermediate wiring is provided in the module, and is in the same direction from the layer in which the intermediate wiring is provided in the stacking direction of the module. Spaced apart from each other,
Each of the high-potential side semiconductor switch and the low-potential side semiconductor switch is provided separately from each other in a layer sandwiched between the high-potential side wiring and the low-potential side wiring and the intermediate wiring in the module. And
The first capacitor is provided between the high potential side semiconductor switch and the low potential side semiconductor switch in an inner layer sandwiched between the high potential side wiring and the low potential side wiring and the intermediate wiring. ,
Each of the high potential side wiring and the low potential side wiring is provided in a form in which at least a part thereof is exposed to one of a pair of outer surfaces in the stacking direction of the module,
A second capacitor (16) having a first end connected to the exposed portion of the high potential side wiring and a second end connected to the exposed portion of the low potential side wiring;
The second capacitor is provided on an outer surface of the pair of outer surfaces in the stacking direction of the module, on which the high potential side wiring and the low potential side wiring are exposed. module. A circuit board (40) on which the module is mounted;
Of the pair of plate surfaces, the circuit board is formed with a space portion (44) extending from the module mounting surface to the back surface side thereof,
The module is mounted on the circuit board so that the low-potential side wiring and the high-potential side wiring face the mounting surface, and the second capacitor is accommodated in the space portion. The switching module according to 1 . The switching module according to claim 2 , further comprising a radiator (64) provided on a side opposite to the outer surface facing the mounting surface among the pair of outer surfaces in the stacking direction of the modules. A heat radiator (65) provided on the outer surface of the module in the stacking direction;
In the radiator, a space portion (66) extending from the module side to the outside in the stacking direction of the modules is formed,
The module is provided in the radiator so that each of the high-potential side wiring and the low-potential side wiring faces the radiator and the second capacitor is accommodated in the space portion. The switching module according to claim 1 . A circuit board (40) on which the module is mounted;
The capacitance of the second capacitor is set larger than the capacitance of the first capacitor,
The circuit board is formed with a first through hole (46; 46a) and a second through hole (48: 48a) across the space portion in plan view of the plate surface,
A third capacitor (18) having a capacitance set larger than that of the second capacitor;
A first conduction member (50; 50a) formed in the first through hole and electrically connecting the high potential side wiring and the first end of the third capacitor;
A second conduction member (52; 52a) formed in the second through hole and electrically connecting the low potential side wiring and the second end of the third capacitor;
The third capacitor is provided on a plate surface opposite to the mounting surface of the module among a pair of plate surfaces of the circuit board so as to straddle the second capacitor in a plan view of the plate surface. Item 5. The switching module according to any one of Items 2 to 4 . The switching module according to claim 5 , wherein the third capacitor is provided at a position overlapping with the second capacitor in a plan view of an outer surface in the stacking direction of the modules. 7. The switching module according to claim 1 , wherein the second capacitor is provided at a position overlapping the first capacitor in a plan view of an outer surface in the stacking direction of the modules. The switching module according to any one of claims 1 to 7 , wherein the second capacitor has a capacitance set larger than that of the first capacitor. Each of the high potential side semiconductor switch, the low potential side semiconductor switch, and the first capacitor is provided in the same inner layer in the module,
The high Each potential line and the low potential line, the switching module according to any one of claims 1 to 8 is provided in the same layer in the module. Wherein the first capacitor, the switching module according to any one of claims 1 to 9 comprising a parallel connection of a plurality of capacitors.

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