JP6171614B2 - Storage medium control device, disk-type storage device, and storage medium control method - Google Patents

Description

  The present invention relates to a storage medium control device, a disk-type storage device, and a storage medium control method, and more particularly to control when a plurality of storage media are operated in cooperation.

  Due to the downsizing and cost reduction of magnetic disk storage devices such as HDD (Hard Disk Drive), RAID (Redundant Arrays of Inexpensive Disks) technology that operates a plurality of devices in cooperation has become common. . According to RAID, for example, one data is distributed and stored in a plurality of devices, thereby reducing the time required for data writing and reading, and one data is stored in a plurality of devices, respectively. As a result, the risk of data loss can be reduced.

  When such a plurality of magnetic disk devices are linked, there is a problem that the performance cannot be exhibited because the rotation waiting time of each device is different. As a technique for solving such a problem, a method of synchronously rotating a plurality of HDDs has been proposed (see, for example, Patent Document 1). In addition, in order to shift the timing of transfer requests in each device and prevent collision of transfer requests, a method of synchronizing the rotation and shifting the data storage position for each device has been proposed (for example, see Patent Document 2). ).

  The techniques in both Patent Documents 1 and 2 are premised on the rotation synchronization of the magnetic disk in each apparatus. Therefore, it cannot be applied to a magnetic disk device that does not have a rotation synchronization function. Such a problem is not limited to a magnetic disk device, and can be similarly problematic if it is a storage device using a disk-type storage medium.

  The present invention has been made to solve such a problem, and in the case where a plurality of disk storage devices are operated in cooperation with each other, the rotation of each disk storage device is not synchronized and the waiting for rotation is performed. The purpose is to shorten the access time with the same time.

In order to solve the above problems, an aspect of the present invention is a storage medium control device that controls a plurality of disk storage devices in cooperation with each other, and rotates a disk that is a storage medium in the plurality of disk storage devices. A phase difference measuring unit for measuring a phase difference, an address offset amount calculating unit for calculating an offset amount of an address in the disk type storage device corresponding to the measured rotational phase difference, and an address to be accessed in the disk type storage device features and addressing accepting unit that accepts a designation based on the offset amount of the address calculated in the address offset computing unit, and an address converter for converting the specified address of the access target was, to include the And

  Another aspect of the present invention is a disk-type storage device including the storage medium control device described above.

According to still another aspect of the present invention, there is provided a storage medium control method for controlling a plurality of disk storage devices in cooperation with each other, and measuring a rotational phase difference of a disk that is a storage medium in the plurality of disk storage devices. and calculates the offset amount of address in said disk-type storage device corresponding to the measured rotational phase difference, receives designation of an address to be accessed in the disk-type storage device, offset amount before Symbol address calculated Based on the above, the designated address to be accessed is converted.

  According to the present invention, when a plurality of disk storage devices are operated in a coordinated manner, the rotation waiting time can be aligned and the access time can be shortened without synchronizing the rotation of each disk storage device. Become.

It is a block diagram which shows the structure of the storage medium control apparatus which concerns on embodiment of this invention. It is a figure which shows the track | truck and sector structure of the storage medium which concerns on embodiment of this invention. It is a figure which shows the distribution aspect of the data to two HDD which concerns on embodiment of this invention. It is a figure which shows the measurement aspect of the rotation phase difference which concerns on embodiment of this invention. It is a block diagram which shows the function structure of the sector address conversion part which concerns on embodiment of this invention. It is a figure which shows the example of the address position in two HDD which concerns on embodiment of this invention. It is a figure which shows the aspect of the buffer area | region in HDD which concerns on other embodiment of this invention. It is a block diagram which shows the function structure of the sector address conversion part which concerns on other embodiment of this invention. It is a figure which shows the example of a setting of the conversion object range register which concerns on other embodiment of this invention. It is a figure which shows the discrimination mode of the buffer area | region which concerns on other embodiment of this invention.

Embodiment 1 FIG.
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the present embodiment, a storage medium control device that operates two HDDs (Hard Disk Drives) in cooperation with each other will be described as an example.

  FIG. 1 is a block diagram illustrating an overall configuration of an electronic apparatus including a storage medium control device according to the present embodiment. As shown in FIG. 1, the electronic apparatus including the storage medium control device 100 according to the present embodiment includes an HDD 1, an HDD 2, a SATA (Serial Advanced Technology Attachment) control unit 3, a SATA control unit 4, a response time difference measurement unit 5, and a sector. An address conversion unit 6, a SATA control command issuing unit 7, a data shaping unit 8, a DMAC (Direct Memory Access Controller) 9, a CPU (Central Processing Unit) 10, and a RAM (Random Access Memory) 11 are included.

  HDD1 and HDD2 are disk-type storage devices each using a magnetic disk as a storage medium, and are a pair of hard disk drives of the same type conforming to the SATA standard for distributing and storing various programs and data. That is, in the present embodiment, the HDD 1 and the HDD 2 are used as disk-type storage devices that operate in cooperation. The distributed arrangement of data will be described in detail later.

  The SATA control unit 3 issues a control command to the HDD 1 in accordance with a command issued by the SATA control command issuing unit 7 and executes data read / write. At the time of data writing to the HDD 1, the SATA control unit 3 serializes the 32-bit width data output from the data shaping unit 8 and transmits it to the HDD 1. Further, when data is read from the HDD 1, the SATA control unit 3 receives data output from the HDD 1, converts the data into a 32-bit width, and transmits the data to the data shaping unit 8. When the read / write is completed, the SATA control unit 3 asserts a transfer completion signal.

  When the SATA control unit 4 receives a command issued by the SATA control command issuing unit 7 via the sector address conversion unit 6, the SATA control unit 4 issues a control command to the HDD 2 according to this command and executes data read / write. When writing data to the HDD 2, the SATA control unit 4 serializes the 32-bit width data output from the data shaping unit 8 and transmits the serial data to the HDD 2. In addition, when reading data from the HDD 2, the SATA control unit 4 receives data output from the HDD 2, converts it to a 32-bit width, and transmits it to the data shaping unit 8. When the read / write is completed, the SATA control unit 4 transfer completion signal is asserted.

  When the response time difference measurement unit 5 receives the command issuance timing signal output from the SATA control command issuance unit 7, the response time difference measurement unit 5 starts the timing count operation, the timing when the transfer completion signal from the SATA control unit 3 is asserted, and the SATA control unit 4 is measured, and the response time difference is transmitted to the sector address conversion unit 6. That is, the response time difference measuring unit 5 functions as a phase difference measuring unit.

  The sector address conversion unit 6 receives a command for the SATA control unit 4 output from the SATA control command issuing unit 7, that is, a control command for the HDD 2, and a range in which the received command reads data or writes data. That is, in the case of a command for setting a read / write target sector address and in the case of a preset conversion target sector address range, the sector address is converted according to the setting, and the converted command is sent to the SATA control unit. 4 to send.

  The sector address conversion is executed based on the response time difference output from the response time difference measuring unit 5 and the conversion parameter set by the CPU 10. If the received command is not a command for setting the read / write target sector address, or if it is out of the conversion target sector address range, the received command is transmitted to the SATA control unit 4 without being processed.

  The SATA control command issuing unit 7 receives a control command from the CPU 10 and issues a control command for each of the HDD 1 and the HDD 2. A control command for the HDD 1 is input to the SATA control unit 3, and a control command for the HDD 2 is input to the SATA control unit 4 via the sector address conversion unit 6. When a data read / write command from the CPU 10 is received, a command that triggers the start of read / write is issued simultaneously to the SATA control unit 3 and the sector address conversion unit 6. Further, when the command from the CPU 10 is “read”, a command issuance timing signal is output to the response time difference measuring unit 5 simultaneously with the issuance of the command.

  The data shaping unit 8 performs distribution processing of data stored in the HDD 1 and HDD 2 and integration processing of data read from the HDD 1 and HDD 2 respectively. During data write, when the data shaping unit 8 receives the 64-bit width data output from the DMAC 9, the data shaping unit 8 divides the received data into 32-bit width data and transmits the data to the SATA control unit 3 and the SATA control unit 4 by 32 bits. To do.

  At the time of data read, the data shaping unit 8 receives the 32-bit width data output from each of the SATA control unit 3 and the SATA control unit 4 and integrates the two received data to generate 64-bit width data. Send to.

  The DMAC 9 is a direct memory access controller that executes data transfer between the data shaping unit 8 and the RAM 11. The CPU 10 sets the transfer destination address, transfer source address, transfer direction, and data size of the DMAC 9. At the time of data writing, the DMAC 9 transmits the data read from the RAM 11 to the data shaping unit 8. At the time of data reading, the DMAC 9 writes the data output from the data shaping unit 8 to the RAM 11.

The CPU 10 is an arithmetic unit, and performs operation control by setting register values to the sector address conversion unit 6, the SATA control command issuing unit 7, the data shaping unit 8, and the DMAC 9. RAM11 is a volatile storage medium body, in addition to functioning as a storage area for programs for CPU10 performs an operation, temporarily stores data read write, or from HDD1 and HDD2 against HDD1 and HDD2.

  Next, storage areas and stored data in the HDDs 1 and 2 will be described with reference to FIG. As shown in FIG. 2, the present embodiment exemplifies an HDD in which the number of sectors per track is constant at 1024 sectors and the storage capacity per sector is 512 bytes. The sector address is a serial number assigned to all sectors of the HDD. A zero address is assigned to the outermost track of the HDD, and the value becomes larger as the inner track. In this embodiment, 1 GByte (addresses 0x0000 — 0000 to 0x001F_FFFF) of the outer track is used as a buffer area, and is used for writing / reading temporary data.

  In the present embodiment, sector address conversion by the sector address conversion unit 6 is executed only when accessing the buffer area of the HDD 2. That is, this buffer area is set as an address conversion target. When accessing the buffer area of the HDD 1, sector address conversion is not executed. The inner track is a program storage area, and stores an OS (Operating System), various application programs, and the like. When the sector address at the time of writing and at the time of reading is different, it cannot be normally accessed. Therefore, when the program storage area is accessed, sector address conversion is not executed.

  Next, an aspect of data distribution and arrangement for the HDDs 1 and 2 according to the present embodiment will be described with reference to FIG. As described in FIG. 1, the 64-bit width data output from the DMAC 9 is stored in the HDDs 1 and 2 as two 32-bit width data by the data shaping unit 8. Specifically, as shown in FIG. In addition, 8 bits are alternately stored in each of the HDDs 1 and 2. That is, the data shaping unit 8 inputs the 64-bit width data received from the DMAC 9 to the SATA control units 3 and 4 alternately every 8 bits at the time of data writing.

  As described above, the storage capacity per sector of the HDDs 1 and 2 according to the present embodiment is 512 bytes. In this embodiment, since data is distributed and arranged in two HDDs, when the connected HDDs 1 and 2 are viewed from the CPU 10, it appears that there is one HDD having a sector size of 1024 bytes.

  Next, how the response time difference is measured by the response time difference measuring unit 5 will be described with reference to FIG. The response time difference measurement unit 5 starts counting in response to the assertion of the command issue timing signal output from the SATA control command issue unit 7. As described above, the command issue timing signal is a signal that is asserted simultaneously with the read start command.

That is, when the response time difference is measured by the response time difference measuring unit 5, the same sector of each of the HDD1 and HDD2 is read, and the time difference required for completion of reading in each of the HDD1 and HDD2 is obtained. The response time difference measuring unit 5 stores the counter value “T _cmpA ” at the timing when the transfer completion signal from the SATA control unit 3 is asserted after the count is started in response to the assertion of the command issue timing signal, and the SATA control unit The counter value “T _cmpB ” at the timing when the transfer completion signal from 4 is asserted is stored. Then, the response time difference measurement unit 5 calculates a difference “T _cmpA −T _cmpB ” between the two count values, and transmits this response time difference to the sector address conversion unit 6.

  Next, the functional configuration of the sector address conversion unit 6 according to the present embodiment will be described with reference to FIG. As shown in FIG. 5, the sector address conversion unit 6 includes a selector 61, a control command determination unit 62, a sector address calculation unit 63, a conversion target range register 64, a disk rotation time register 65, a sector number register per track 66, a response time difference. An update permission register 67 and a response time difference register 68 are included.

  The selector 61 selects which of the command after address conversion and the command without processing to be output to the SATA control unit 4 according to the select signal input from the control command determination unit 62. The conversion target range register 64 is a register that is a value set by the CPU 10 and stores a value for setting an address range in the HDD 2 to be subjected to address conversion. That is, the conversion target range register 64 functions as a conversion target address range storage unit. In the present embodiment, as described in FIG. 2, the buffer area [0x0000_0000 to 0x001F_FFFF] of the HDD 2 is set.

Control command discriminator 62, the SATA control command issuing unit 7 receives a SATA control command for controlling the HDD 2. That is, it functions as an address 7 designation accepting unit that accepts designation of an address to be accessed. The control command determination unit 62 is a conversion target sector address range set in the conversion target range register 64 when the received command is a command for setting a read / write target sector address for the HDD 2. In this case, it is determined that address conversion is necessary.

  If it is determined that the address conversion is necessary, the control command determination unit 62 switches the selection signal input to the selector 61 and receives the command so that the sector address conversion command output by the sector address calculation unit 63 is output. The sector address information included in the SATA control command is input to the sector address calculation unit 63. That is, the control command determination unit 62 functions as a selector control unit.

  On the other hand, when the received command is not a command for setting the read / write target sector address, or when it is determined that the address conversion is unnecessary because it is out of the sector address range to be converted, the control command determination unit 62 The select signal input to the selector 61 is switched so as to output a command that has not been performed, and the sector address information included in the received SATA control command is input to the selector 61.

  The disk rotation time register 65 is a register that is a value set by the CPU 10 and stores a value of time required for one rotation of the HDD 2. When the rotational speed of the HDD 2 is 5400 (rpm), the time required for one rotation of the disk is approximately 11.111 (ms).

  The sector number register 66 per track is a value set by the CPU 10 and stores the number of sectors included in one track of the HDD 2. As described above, the number of sectors per track of the HDD 2 according to the present embodiment is 1024.

The response time difference register 68 is a register for storing the response time difference measured by the response time difference measurement unit 5. That is, the response time difference register 68 functions as a rotational phase difference storage unit. The response time difference register 68 takes in “T _cmpA −T _cmpB ”, which is the output value of the response time difference measurement unit 5, when the register value set in the response time difference update permission register 67 is a value indicating enable.

  The response time difference update permission register 67 is a register that stores a value that is set by the CPU 10 and that specifies that the value of the response time difference register 68 is updated. When instructing the update of the response time difference register 68, the CPU 10 sets the value of the response time difference update permission register 67 to a value corresponding to enable.

  For example, when the program storage area described with reference to FIG. 2 is accessed, by setting the setting value of the response time difference update permission register 67 to a value corresponding to enable, the response time difference can be obtained in the read operation when the OS is started. Can be updated. Also, even if HDD1 and HDD2 are the same type, there is a slight difference in the rotational speed in the steady state, so that a rotational phase difference will occur after a long time has elapsed. In order to perform remeasurement, the temporal change of the rotational phase difference can be corrected.

  Also, by disabling the response time difference update permission register 67 before or after writing to the buffer area, address conversion at the time of writing and reading can be made the same, and data in the buffer area is read many times. be able to. By enabling the response time difference update permission register 67 when the data in the buffer area becomes unnecessary, it is possible to correct the time change of the rotational phase difference during the next read operation.

  The sector address calculation unit 63 receives the access target sector address value input from the control command determination unit 62, the set value of the disk rotation time register 65, the set value of the number of sectors per track register 66, and the set value of the response time difference register 68. To calculate the converted sector address. The number of sectors per track according to the present embodiment is 1024. Therefore, the sector address in each track is represented by the lower 10 bits of the sector address which is a serial number. Therefore, conversion is performed on the lower 10 bits of the sector address. That is, the sector address calculation unit 63 functions as an address conversion unit.

  The calculation of the lower 10 bits of the converted sector address by the sector address calculation unit 63 is performed according to the formula: “(lower sector address after conversion 10 bits) = (lower address 10 bits of access target sector address) + (number of offset sectors)”. However, if the calculation result is 11 bits or more, the 11th bit is discarded. This process is equivalent to the process of subtracting 1024 when the calculation result is greater than 1024.

  The calculation of the number of offset sectors differs depending on whether the response time difference is positive or negative. When the response time difference is positive, “(offset sector number) = (response time difference) / (head for one sector” (Passing time) ". Further, “(head passing time for one sector)” is obtained by using the setting value of the disk rotation time register 65 and the setting value of the sector number per track register 66, “(time required for one disk rotation) / (per track). The number of sectors)) ”. That is, the sector address calculation unit 63 functions as an address offset amount calculation unit.

  On the other hand, when the response time difference is negative, the number of offset sectors is calculated according to the formula: “(offset sector number) = (response time difference) / (head passing time for one sector) +1024”. “(Head passing time for one sector)” is the same as described above.

  For example, when the response time difference is 4 (ms) and the access target sector address is 0x001F_F1AA, the number of offset sectors for canceling the rotational phase difference is “4 (ms) ÷ {11.111 (ms) / 1024} ≈369” It is. As a result, the lower 10 bits of the post-conversion sector address are 0x31B, and the post-conversion sector address is 0x001F_F31B.

  When the response time difference is −4 (ms) and the access target sector address is 0x001F_F1AA, the number of offset sectors for canceling the rotational phase difference is “−4 (ms) / {11.111 (ms) / 1024} +1024. ≈655 ". As a result, the lower 10 bits of the post-conversion sector address are 0x039, and the post-conversion sector address is 0x001F_F039.

  The sector address calculation unit 63 generates a SATA control command including the post-conversion address and inputs it to the selector 61 as the post-sector address conversion command. Accordingly, the selector 61 selects the post-conversion address input from the sector address calculation unit 63 according to the select signal input from the control command determination unit 62 and transmits it to the SATA control unit 4.

  FIG. 6 is a diagram showing the effect of address conversion according to the present embodiment. FIG. 6 is an image diagram of sector address positions in a certain track of HDD 1 and HDD 2 during steady rotation. In this embodiment, the HDD 1 and the HDD 2 are the same type as an example. Usually, since the rotation for each HDD is not synchronized, even when the same sector address “000” is accessed, the rotation waiting time until the access target sector reaches the head is different.

  On the other hand, in the storage medium control apparatus according to the present embodiment, the access to the HDD 1 is used as a reference, and the access to the HDD 2 has the same rotation waiting time instead of the original access target sector address “000”. The converted sector address “XXX” is accessed. For this reason, the rotation waiting time can be made uniform in HDD1 and HDD2.

  That is, in the storage medium control apparatus according to the present embodiment, when the HDD 2 is accessed, the address conversion is performed so as to cancel the rotational phase difference with the HDD 1, so that the rotation waiting times of the HDD 1 and the HDD 2 can be made uniform. . As a result, when a plurality of disk storage devices are operated in cooperation, the rotation waiting time can be aligned and the access time can be shortened without synchronizing the rotations of the respective disk storage devices.

Embodiment 2. FIG.
In the first embodiment, the case where only one buffer area is provided in the HDD to be controlled has been described as an example. In the present embodiment, a case where a plurality of buffer areas are provided in one HDD will be described as an example. In addition, about the structure which attaches | subjects the code | symbol same as Embodiment 1, it shall show the same or an equivalent part, and abbreviate | omits detailed description.

  FIG. 7 is a diagram showing storage areas in the HDDs 1 and 2 according to the present embodiment. As in FIG. 2, an HDD having a constant number of sectors per track of 1024 sectors and a storage capacity per sector of 512 bytes is taken as an example. As shown in FIG. 7, the HDDs 1 and 2 according to the present embodiment are provided with a plurality of 1 Gbyte buffer areas. Therefore, in the storage medium control apparatus according to the present embodiment, the functional configuration of the sector address conversion unit 6 is different from that of the first embodiment in order to correspond to a plurality of buffer areas.

  In the HDDs 1 and 2 according to the present embodiment, the area corresponding to 4 GBytes (addresses 0x0000 — 0000 to 0x007F_FFFF) of the outer track is temporarily stored as four buffer areas 0, 1, 2, and 3 for 1 GByte each. Used for writing / reading. When accessing each buffer area of the HDD 2, sector address conversion is executed independently for each area. When accessing the buffer area of HDD1 or when accessing the program storage areas of HDD1 and 2, sector address conversion is not executed.

  Next, the functional configuration of the sector address conversion unit 6 according to the present embodiment will be described with reference to FIG. As shown in FIG. 8, the sector address conversion unit 6 in this embodiment has substantially the same configuration as the sector address conversion unit 6 according to the first embodiment described in FIG. The control command discriminating unit 621, the conversion target range register 64 instead of the conversion target range register 641, the response time difference update permission register 67 instead of the response time difference update permission register 671, and the response time difference register 68 instead of the response time difference register 680 683 is included. Furthermore, a buffer area determination unit 691 and a selector 692 are included.

The conversion target range register 641 is a register that is a value set by the CPU 10 and stores a value for setting an address range in the HDD 2 to be subjected to address conversion. In the present embodiment, as described in FIG. 7, four buffer areas 0 [0x0000 — 0000 to 0x001F_FFFF], buffer area 1 [0x0020 — 0000 to 0x003F_FFFF], buffer area 2 [0x0040 — 0000 to 0x005F_FFFF], buffer area 3 [0x0060_0000] ˜0x007F_FFFF] is set.

  FIG. 9 is a diagram illustrating an example of setting in the conversion target range register 641. As shown in FIG. 9, in the conversion target range register 641, the address conversion target is set by setting the address range for each of the buffer areas 0 to 4.

Control command determination unit 621, the SATA control command issuing unit 7 receives a SATA control command for controlling the HDD 2. The control command determination unit 621 is a conversion target sector address range set in the conversion target range register 641 when the received command is a command for setting a read / write target sector address for the HDD 2. In this case, it is determined that address conversion is necessary.

  If it is determined that the address conversion is necessary, the control command determination unit 62 switches the selection signal input to the selector 61 and receives the command so that the sector address conversion command output by the sector address calculation unit 63 is output. The sector address information included in the SATA control command is input to the sector address calculation unit 63 and the buffer area determination unit 691. The difference from Embodiment 1 is that the sector address information is also input to the buffer area determination unit 691.

The response time difference registers 680 to 683 are registers for storing the response time differences measured by the response time difference measurement unit 5. The response time difference register 680 responds when the setting for the buffer area 0 of the response time difference update permission register 671 is enabled and the selection signal output from the buffer area determination unit 691 selects the buffer area 0. “T _cmpA −T _cmpB ” that is an output value of the time difference measuring unit 5 is taken in.

The response time difference register 681 is a response when the setting for the buffer area 1 of the response time difference update permission register 671 is enabled and the selection signal output from the buffer area determination unit 691 selects the buffer area 1. “T _cmpA −T _cmpB ” that is an output value of the time difference measuring unit 5 is taken in.

The response time difference register 682 is a response when the setting for the buffer area 2 of the response time difference update permission register 671 is enabled and the selection signal output from the buffer area determination unit 691 selects the buffer area 2. “T _cmpA −T _cmpB ” that is an output value of the time difference measuring unit 5 is taken in.

The response time difference register 683 is a response when the setting for the buffer area 3 of the response time difference update permission register 671 is enabled and the selection signal output from the buffer area determination unit 691 selects the buffer area 3. “T _cmpA −T _cmpB ” that is an output value of the time difference measuring unit 5 is taken in.

  The response time difference update permission register 671 is a register that stores values that are set by the CPU 10 and that specify that the values of the response time difference registers 680 to 683 are to be updated. That is, the response time difference update permission register 671 includes an enable bit for setting a value indicating whether or not each value of the response time difference registers 680 to 683 can be updated.

  The CPU 10 disables the enable bit corresponding to the buffer areas 0 to 3 of the response time difference update permission register 671 before or after writing to the buffer areas 0 to 3 of the HDD 2, so that the write time and the read time can be reduced. Address conversion can be made the same, and data in the buffer area can be read many times. Since the update / maintenance of the response time difference registers 680 to 683 can be controlled independently, the buffer areas 0 to 3 can be used for an area for storing data for executing only one read and data for executing two or more reads. Can be used properly in the memory area.

  The buffer area discriminating unit 691 discriminates which of the buffer areas 0 to 3 is to be accessed from the contents of the conversion target range register 641 and the access target sector address information output from the control command discriminating unit 621. A buffer area selection signal is output to the response time difference registers 680 to 683 and the selector 692.

  FIG. 10 is a diagram showing how the buffer area discriminating unit 691 discriminates the buffer area. As shown in FIG. 10, in this embodiment, buffer areas 0 to 3 and response time difference registers 680 to 683 are associated with each other. Such a determination method is realized, for example, by storing information of a table as illustrated in FIG. 10 in the buffer area determination unit 691.

  Then, the buffer area determination unit 691 determines the buffer area to be accessed by referring to the setting value described with reference to FIG. 9 based on the information on the access target sector address output from the control command determination unit 621. Based on the determination result, the corresponding response time difference registers 680 to 683 are selected as shown in FIG.

  The selector 692 selects any one of the register values input from the response time difference registers 680 to 683 in accordance with the selection signal output from the buffer area determination unit 691 and inputs the selected value to the sector address calculation unit 63. The sector address calculation unit 63 has the same function as in the first embodiment, but differs from the first embodiment in that a register value selected and output by the selector 692 is used.

  According to such a configuration, in addition to the effects described in the first embodiment, by providing a plurality of buffer areas, an area for storing data to be executed only once and a read at least twice are executed. It is possible to use different areas for storing data to be used.

  In the first and second embodiments, the case where two HDDs are used has been described as an example. However, this is an example, and the present invention can also be applied when three or more HDDs are linked. In this case, the value of the response time difference register 68 is set by determining any one of the plurality of HDDs as a reference HDD and obtaining a time difference from the response time of the reference HDD for each of the other HDDs. Then, the sector address calculation unit 63 performs address conversion by obtaining an address offset amount for each HDD other than the reference HDD by using the setting value of the corresponding response time difference register 68.

1, 2 HDD
3, 4 SATA control unit 5 Response time difference measurement unit 6 Sector address conversion unit 7 SATA control command issue unit 8 Data shaping unit 9 DMAC
10 CPU
11 RAM
61 Selector 62, 621 Control command determination unit 63 Sector address calculation unit 64, 641 Conversion target range register 65 Disk rotation time register 66 Sector number per track register 67, 671 Response time difference update enable register 68, 680, 681, 682, 683 Response Time difference register 691 Buffer area discriminator 692 Selector

JP 08-328759 A JP 2004-013827 A

Claims (9)

A storage medium control device that controls a plurality of disk-type storage devices in cooperation with each other,
A phase difference measuring unit that measures a rotational phase difference of a disk that is a storage medium in the plurality of disk type storage devices;
An address offset amount calculation unit for calculating an address offset amount in the disk type storage device corresponding to the measured rotational phase difference;
An address designation accepting unit for accepting designation of an address to be accessed in the disk-type storage device;
Based on said offset amount of said address calculated in the address offset computing unit, a storage medium control apparatus, characterized in that it comprises an address converter for converting the specified address of the access target and the.   The phase difference measuring unit reads the same sector from each of the plurality of disk-type storage devices, and measures a rotational phase difference of the disk based on a time difference required for completion of reading. 2. The storage medium control device according to 1. The address conversion unit is specified based on the offset amount of the address only when the specified address to be accessed is included in the address range determined as the conversion target among the addresses in the disk type storage device. 3. The storage medium control apparatus according to claim 1, wherein the address to be accessed is converted. The address conversion unit
A selector that outputs either a signal indicating the designated address to be accessed and a converted address;
A conversion target address range storage unit for storing an address range determined as the conversion target;
If the address of the designated the accessed is included in the address range determined above, according to claim 3, characterized in that it comprises a selector control unit for switching the output of said selector to said converted address Storage medium control device. A rotational phase difference storage unit for storing the measured rotational phase difference;
5. The storage medium control apparatus according to claim 1, wherein the address offset amount calculation unit calculates an offset amount of the address based on the stored rotational phase difference. 6. The address conversion unit is specified based on the offset amount of the address only when the specified address to be accessed is included in the address range determined as the conversion target among the addresses in the disk type storage device. The address to be accessed is converted,
The phase difference measuring unit measures the rotational phase difference of the disk when reading an address range other than the address range determined as the conversion target, and stores the measured rotational phase difference in the rotational phase difference storage unit. The storage medium control device according to claim 5, wherein An address range defined as a conversion target among addresses in the disk-type storage device, including a plurality of rotational phase difference storage units corresponding to different address ranges,
The phase difference measuring unit measures a rotational phase difference of the disk for each of the plurality of different address ranges, and stores the measured rotational phase difference in the rotational phase difference storage unit corresponding to the plurality of different address ranges. The storage medium control device according to claim 5 , wherein   A disk-type storage device comprising the storage medium control device according to claim 1. A storage medium control method for controlling a plurality of disk storage devices in cooperation with each other,
Measuring a rotational phase difference of a disk as a storage medium in the plurality of disk-type storage devices;
Calculating an offset amount of the address in the disk type storage device corresponding to the measured rotational phase difference;
Accepting designation of an address to be accessed in the disk type storage device,
Based on the offset amount before Symbol address calculated, the control method of the storage medium characterized by converting the specified address of the access target was.