JP6170553B2 - 異種プロセッサを使用するアプリケーションに低レイテンシを提供するためのシステムおよび方法 - Google Patents

異種プロセッサを使用するアプリケーションに低レイテンシを提供するためのシステムおよび方法 Download PDF

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JP6170553B2
JP6170553B2 JP2015516237A JP2015516237A JP6170553B2 JP 6170553 B2 JP6170553 B2 JP 6170553B2 JP 2015516237 A JP2015516237 A JP 2015516237A JP 2015516237 A JP2015516237 A JP 2015516237A JP 6170553 B2 JP6170553 B2 JP 6170553B2
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memory
requests
data
processors
gpu
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JP2015522878A5 (enExample
JP2015522878A (ja
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リャシェフスキー アレキサンダー
リャシェフスキー アレキサンダー
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/20—Information retrieval; Database structures therefor; File system structures therefor of structured data, e.g. relational data
    • G06F16/24—Querying
    • G06F16/245—Query processing
    • G06F16/24569—Query processing with adaptation to specific hardware, e.g. adapted for using GPUs or SSDs
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/90—Details of database functions independent of the retrieved data types
    • G06F16/901—Indexing; Data structures therefor; Storage structures
    • G06F16/9014—Indexing; Data structures therefor; Storage structures hash tables
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/5033—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering data affinity
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/005—General purpose rendering architectures

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Databases & Information Systems (AREA)
  • Data Mining & Analysis (AREA)
  • Computational Linguistics (AREA)
  • Computer Graphics (AREA)
  • Computer Hardware Design (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Retry When Errors Occur (AREA)
JP2015516237A 2012-06-08 2013-06-07 異種プロセッサを使用するアプリケーションに低レイテンシを提供するためのシステムおよび方法 Active JP6170553B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201261657404P 2012-06-08 2012-06-08
US61/657,404 2012-06-08
PCT/US2013/044682 WO2013185015A2 (en) 2012-06-08 2013-06-07 System and method for providing low latency to applications using heterogeneous processors

Publications (3)

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JP2015522878A JP2015522878A (ja) 2015-08-06
JP2015522878A5 JP2015522878A5 (enExample) 2016-07-28
JP6170553B2 true JP6170553B2 (ja) 2017-07-26

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JP2015516237A Active JP6170553B2 (ja) 2012-06-08 2013-06-07 異種プロセッサを使用するアプリケーションに低レイテンシを提供するためのシステムおよび方法

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Country Link
US (1) US9495718B2 (enExample)
EP (1) EP2859448A2 (enExample)
JP (1) JP6170553B2 (enExample)
KR (1) KR102086019B1 (enExample)
CN (1) CN104395890B (enExample)
WO (1) WO2013185015A2 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106164839B (zh) * 2014-02-04 2019-10-22 触觉实验室股份有限公司 以减小的等待时间提供对输入的视觉响应的方法
US9342384B1 (en) * 2014-12-18 2016-05-17 Intel Corporation Function callback mechanism between a central processing unit (CPU) and an auxiliary processor
US9711194B2 (en) * 2015-01-28 2017-07-18 Xilinx, Inc. Circuits for and methods of controlling the operation of a hybrid memory system
KR102352756B1 (ko) 2015-04-29 2022-01-17 삼성전자주식회사 애플리케이션 프로세서, 시스템 온 칩, 및 이를 포함하는 컴퓨팅 장치
KR101923210B1 (ko) * 2016-01-14 2018-11-28 서울대학교산학협력단 이종 멀티코어 프로세서를 활용한 암호화 처리 장치 및 암호화 처리 방법
US11513805B2 (en) * 2016-08-19 2022-11-29 Wisconsin Alumni Research Foundation Computer architecture with synergistic heterogeneous processors
US10929944B2 (en) 2016-11-23 2021-02-23 Advanced Micro Devices, Inc. Low power and low latency GPU coprocessor for persistent computing
US10795840B2 (en) 2018-11-12 2020-10-06 At&T Intellectual Property I, L.P. Persistent kernel for graphics processing unit direct memory access network packet processing
CN111447561B (zh) * 2020-03-16 2023-04-18 阿波罗智联(北京)科技有限公司 车辆的图像处理系统

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0285927A (ja) * 1988-09-22 1990-03-27 Hitachi Vlsi Eng Corp 記憶装置
FR2767939B1 (fr) * 1997-09-04 2001-11-02 Bull Sa Procede d'allocation de memoire dans un systeme de traitement de l'information multiprocesseur
US6636499B1 (en) * 1999-12-02 2003-10-21 Cisco Technology, Inc. Apparatus and method for cluster network device discovery
US8269793B2 (en) * 2003-02-18 2012-09-18 Serverside Group Limited Apparatus and method for manipulating images
US8484647B2 (en) * 2009-07-24 2013-07-09 Apple Inc. Selectively adjusting CPU wait mode based on estimation of remaining work before task completion on GPU
US8400458B2 (en) * 2009-09-09 2013-03-19 Hewlett-Packard Development Company, L.P. Method and system for blocking data on a GPU
US9400695B2 (en) * 2010-02-26 2016-07-26 Microsoft Technology Licensing, Llc Low latency rendering of objects
US9645866B2 (en) * 2010-09-20 2017-05-09 Qualcomm Incorporated Inter-processor communication techniques in a multiple-processor computing platform
EP2652634A1 (en) * 2010-12-16 2013-10-23 Et International Inc. Distributed computing architecture

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Publication number Publication date
KR102086019B1 (ko) 2020-04-14
US20130328891A1 (en) 2013-12-12
WO2013185015A3 (en) 2014-01-30
CN104395890A (zh) 2015-03-04
CN104395890B (zh) 2018-12-07
WO2013185015A2 (en) 2013-12-12
EP2859448A2 (en) 2015-04-15
JP2015522878A (ja) 2015-08-06
KR20150024884A (ko) 2015-03-09
US9495718B2 (en) 2016-11-15

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