JP6167826B2 - Manufacturing method of electronic parts - Google Patents

Description

  The present invention relates to a method for manufacturing an electronic component.

  In recent years, electronic components in which a plurality of device chips having different functions are integrated in a two-dimensional direction or a three-dimensional direction have been proposed in response to demands for higher performance and multi-functionality of electronic devices. Further, as a method for manufacturing such an electronic component, an integration technique using a pseudo wafer has been developed.

  In this type of integration technology, device chips having different functions are first manufactured individually, and these device chips are integrated with a mold resin to form one pseudo wafer. Then, using existing film forming technology and microfabrication technology, wiring for electrically connecting the device chips is formed on the pseudo wafer. The wiring formed on the pseudo wafer is called rewiring.

  After the formation of the rewiring is completed, the pseudo wafer is cut for each electronic component. Thereby, an electronic component in which a plurality of device chips are integrated on one chip is obtained.

  In the above-described method, there are few restrictions on the device chip to be integrated, and a new electronic component can be developed at a low cost. In addition, since the wiring for electrically connecting the device chips is formed using the existing film formation technique and microfabrication technique, the wiring can be easily miniaturized and high integration can be achieved.

JP 2012-129437 A

  An object of the present invention is to provide an electronic component manufacturing method capable of manufacturing an electronic component in which a plurality of device chips are integrated on one chip with a good yield while suppressing the warpage of the pseudo wafer.

According to one aspect of the disclosed technology, a step of arranging a plurality of device chips in a mold with the electrode formation surface of the device chip facing down, a step of injecting a mold resin into the mold, and obtaining a pseudo wafer and the mold resin and the device chip are integrated by curing the molding resin, a step of removing said pseudo wafer from the mold, forming a cut in said placebo wafer, the pseudo A step of applying an insulating material containing a solvent component to the surface of the wafer where the notch is formed, a step of forming a rewiring on the electrode forming surface of the device chip of the pseudo wafer, and possess a step of carving parts, the cuts a, an electronic component manufacturing method of forming the mold resin from the side opposite to the electrode forming surface of the device chip It is provided.

  According to the electronic component manufacturing method according to the above aspect, warping of the pseudo wafer can be suppressed, and an electronic component in which a plurality of device chips are integrated on one chip can be manufactured with a good yield.

FIG. 1 is a cross-sectional view (part 1) illustrating a method of manufacturing an electronic component according to the first embodiment in the order of steps. FIG. 2 is a cross-sectional view (part 2) illustrating the method of manufacturing the electronic component according to the first embodiment in the order of steps. FIG. 3 is a top view of the pseudo wafer. FIG. 4 is a top view showing cuts provided in the pseudo wafer. FIG. 5 is a diagram showing the results of measuring the amount of warping of the pseudo wafer before forming the cut and the amount of warping of the pseudo wafer after forming the notch. FIG. 6 is a cross-sectional view illustrating Modification Example 1 of the method for manufacturing an electronic component according to the first embodiment. FIG. 7 is a flowchart showing a method for manufacturing an electronic component according to Modification 2. FIG. 8 is a cross-sectional view (part 1) illustrating the method of manufacturing the electronic component according to the second embodiment in the order of steps. FIG. 9 is a cross-sectional view (part 2) illustrating the electronic component manufacturing method according to the second embodiment in the order of steps. FIG. 10 is a cross-sectional view illustrating the method for manufacturing the electronic component according to the third embodiment. FIG. 11 is a top view showing a pseudo wafer in which cuts are formed.

  Hereinafter, before describing the embodiment, a preliminary matter for facilitating understanding of the embodiment will be described.

  As described above, when a pseudo wafer is used, there are few restrictions on the device chips to be integrated, and high-performance and multifunctional electronic components can be manufactured. However, a large warp tends to occur in the pseudo wafer due to a difference in thermal expansion coefficient between the device chip and the mold resin.

  If there is a large warp in the pseudo wafer, a mounting error may occur when the pseudo wafer is mounted on a film forming apparatus, an exposure apparatus, or a transfer apparatus, or a positional shift may occur during exposure, resulting in a decrease in yield. .

  In the following embodiments, an electronic component manufacturing method capable of manufacturing an electronic component in which a plurality of device chips are integrated on a single chip with a good yield while suppressing warpage of the pseudo wafer will be described.

(First embodiment)
1 to 2 are cross-sectional views showing a method of manufacturing an electronic component according to the first embodiment in the order of steps, and FIG. 3 is a top view of a pseudo wafer.

  First, as shown in FIG. 1A, the adhesive sheet 12 is disposed on the mounting table 11, and the mold 13 is disposed so as to surround the periphery of the adhesive sheet 12. Then, device chips 14 a and 14 b are arranged at predetermined positions on the adhesive sheet 12. At this time, the device chips 14a and 14b are arranged with the electrode formation surface facing down.

  FIG. 1A shows an example in which two types of device chips 14a and 14b are arranged in each electronic component formation region. However, the number of device chips arranged in one electronic component forming region is not limited to two, and the number of device chips arranged in one electronic component forming region is arbitrary.

  The device chip may be, for example, a semiconductor chip in which transistors are highly integrated, and may include other active elements, passive elements, optical elements, or the like. A device chip in which a plurality of semiconductor chips are stacked via TSV (Through Silicon Via) can also be used.

  Next, as shown in FIG. 1B, the mold resin 15 is injected into the mold 13 up to above the device chips 14a and 14b. The mold resin 15 may be insulative, and various resins can be used. For example, as the mold resin 15, a thermosetting epoxy resin containing silica or the like, an acrylic resin, or the like can be used.

  Next, the mold resin 15 is cured. Thereby, the mold resin 15 and the device chips 14a and 14b are integrated. Hereinafter, the one in which the mold resin 15 and the device chips 14 a and 14 b are integrated is referred to as a pseudo wafer 10.

  In this embodiment, as shown in a top view in FIG. 3, the pseudo wafer 10 has a circular shape and is provided with a positioning notch 10a. Here, it is assumed that the pseudo wafer 10 has a diameter of 6 inches (about 152.4 mm) and a thickness of 600 μm. The thickness of the device chips 14a and 14b is assumed to be 200 μm. In addition, each area | region enclosed with the broken line in FIG. 3 has each shown the electronic component formation area.

  Thereafter, the pseudo wafer 10 is taken out from the mold 13. Further, after the adhesive sheet 12 is irradiated with ultraviolet rays (UV) to reduce the adhesiveness, the adhesive sheet 12 is removed from the pseudo wafer 10.

  FIG. 1C shows a state in which the mold 13 and the adhesive sheet 12 are removed from the pseudo wafer 10 and arranged with the electrode formation surfaces of the device chips 14a and 14b on the upper side. Hereinafter, the electrode formation surface side of the device chips 14a and 14b is referred to as the front surface of the pseudo wafer 10, and the opposite surface is referred to as the back surface.

  Next, using a dicing apparatus or the like, as shown in FIG. 1D, cuts 16 are formed in a lattice shape from the back side of the pseudo wafer 10. In the present embodiment, as shown in FIG. 4, a cut 16 is provided at the boundary portion of each electronic component forming region. However, the place where the cut 16 is formed is not limited to the boundary portion of the electronic component forming region, and the cut 16 may be provided below the device chips 14a and 14b, for example.

  It is preferable that the notch 16 has a depth that does not reach the device chips 14a and 14b. In the present embodiment, the depth of the notch 16 is slightly shallower than 400 μm. The width of the cut 16 is, for example, 60 μm.

  By providing the notches 16 on the back side of the pseudo wafer 10 in this way, the stress inherent in the mold resin 15 is released, and the warp of the pseudo wafer 10 is reduced.

  Note that if the notch 16 is provided to the edge of the pseudo wafer 10 (outside the circle indicated by the alternate long and short dash line in FIG. 4), not only the mechanical strength of the pseudo wafer 10 is reduced, but also the pseudo wafer 10 is transferred or It becomes difficult to vacuum-puck (chuck) the pseudo wafer 10 during holding. For this reason, in this embodiment, the notch 16 is not provided in the edge of the pseudo wafer 10.

  In the example shown in FIG. 4, the pitch of the cuts 16 in the X direction is the same as the pitch of the cuts 16 in the Y direction, but the pitches of the cuts in the X direction and the cuts in the Y direction are different depending on the amount of warpage. You may do it. For example, when the amount of warp in the X direction of the pseudo wafer 10 is 800 μm and the amount of warp in the Y direction is 400 μm, the pitch of the cut in the X direction is set to ½ of the pitch of the cut in the Y direction. The amount of warpage and the amount of warpage in the Y direction can be reduced to the same extent.

  Next, a rewiring layer 17 having a rewiring 17a having a desired pattern is formed on the pseudo wafer 10 as shown in FIG. 2A using a known film forming technique and microfabrication technique.

  In this embodiment, since the warp of the pseudo wafer 10 is suppressed by the notch 16 as described above, a mounting error or a position at the time of exposure when mounting the pseudo wafer 10 on a film forming apparatus, an exposure apparatus, a transfer apparatus, or the like. Misalignment is avoided.

  Next, as shown in FIG. 2B, the back surface of the pseudo wafer 10 is ground to reduce the thickness of the pseudo wafer 10 to a desired thickness. When a large warp is generated in the pseudo wafer 10 due to the formation of the rewiring layer 17, a cut may be provided again before or after the back surface grinding.

  Next, as shown in FIG. 2C, the pseudo wafer 10 is cut into electronic component forming regions by a dicing apparatus. In this way, an electronic component 19 in which a plurality of device chips 14a and 14b are integrated on one chip is obtained.

  In the present embodiment, as described above, since the notch 16 is provided on the back surface side of the pseudo wafer 10 after the mold resin 15 is cured, the stress inherent in the mold resin 15 is released, and the warp of the pseudo wafer 10 occurs. It is reduced.

  This avoids mounting errors when mounting the pseudo wafer 10 to a film forming apparatus, an exposure apparatus, a transfer apparatus, or the like, and a positional shift during exposure, and increases the manufacturing yield of electronic components in which a plurality of device chips are integrated into one chip. There is an effect of improving.

  When the mold resin is cured, it is also conceivable to form a groove in a lattice shape on the lower surface side of the pseudo wafer by pressing a mold having protrusions provided in a lattice shape into the mold resin. However, in that case, there is a problem that the mold resin hardly enters the space between the protruding portions. Further, since the contact area between the mold and the mold resin increases, there is a problem that it is difficult to peel off the mold after the mold resin is cured.

  On the other hand, in this embodiment, since the cut is formed by a dicing apparatus or the like after the mold resin is cured, the above-described problem does not occur.

  5A and 5B, the horizontal axis indicates the position, and the vertical axis indicates the height, and the amount of warpage of the pseudo wafer before forming the cut and the warpage of the pseudo wafer after forming the cut. It is a figure which shows the result of having measured quantity. The diameter of the pseudo wafer used for the measurement is 200 mm.

  FIG. 5A shows the result of measuring the warpage amount of the pseudo wafer before forming the notches, and FIG. 5B shows the warpage amount of the pseudo wafer having 20 incisions in the vertical and horizontal directions. The measurement results are shown.

  As can be seen from FIGS. 5A and 5B, the warpage amount of the pseudo wafer before forming the cut is about 1.2 mm, whereas the warpage amount of the pseudo wafer after forming the cut is About 0.5 mm. From this measurement result, it was confirmed that the warpage of the pseudo wafer was suppressed by providing the notches.

(Modification 1)
As shown in FIG. 6A, the pseudo wafer 10 is warped so that the back surface is convex, and the warping may not be sufficiently reduced only by providing the notch 16. In this case, as shown in FIG. 6B, an insulating material containing a solvent component such as SOG (Silicon-on-glass) or resin is applied to the back side of the pseudo wafer 10 by spin coating or the like, and the insulating film 18 is formed. It may be formed and then heat treated.

  Since the solvent component is volatilized from the insulating film 18 due to the heat treatment and the volume shrinks, a stress acts in the direction indicated by the arrow in FIG. Thereby, the curvature of the pseudo wafer 10 is corrected.

(Modification 2)
In the first embodiment, the cuts 16 are provided between the electronic component forming regions, but the number of cuts may be changed according to the amount of warpage.

  FIG. 7 is a flowchart showing a method for manufacturing an electronic component according to Modification 2. In addition, the manufacturing method of an electronic component is demonstrated here also with reference to FIGS.

  First, in step S11, a database representing the relationship between the amount of warpage and the number of cuts is created for each pseudo wafer size or product type.

  Next, in step S12, as described in the first embodiment, the device chips 14a and 14b and the mold resin 15 are integrated to produce the pseudo wafer 10 (see FIGS. 1A to 1C). ).

  Next, in step S <b> 13, the amount of warpage of the pseudo wafer 10 in the X direction and the Y direction is measured using a warp measuring device or the like.

  Next, the process proceeds to step S14, and it is determined whether the warpage amount is within a preset allowable range. If it is determined that the warping amount is within the allowable range (in the case of YES), the process proceeds to step S17. If it is determined that the warpage amount is outside the allowable range (in the case of NO), the process proceeds to step S15.

  When the process proceeds to step S15, the number of cuts is determined with reference to the database created in step S11. In this case, it is preferable to individually determine the number of cuts in the X direction and the number of cuts in the Y direction according to the amount of warp in the X direction and the amount of warp in the Y direction.

  Next, the process proceeds to step S16, and the number of cuts determined in step S15 is formed in the pseudo wafer 10 using a dicing apparatus (see FIG. 1D).

  Thereafter, the process returns to step S13, and the amounts of warpage of the pseudo wafer 10 in the X direction and the Y direction are measured again. Then, the process proceeds to step S14, and it is determined whether or not the warpage amount is within an allowable range. If it is determined in step S14 that the warping amount is within the allowable range (in the case of YES), the process proceeds to step S17. If it is determined that the warpage amount is outside the allowable range (in the case of NO), the process proceeds to step S15.

  In this way, steps S13 to S16 are repeated until the warpage amount of the pseudo wafer 10 falls within the allowable range, and when the warpage amount of the pseudo wafer 10 falls within the allowable range, the process proceeds from step S14 to step S17.

  In step S17, the rewiring layer 17 is formed on the pseudo wafer 10 (see FIG. 2A). Then, after the back surface of the pseudo wafer 10 is ground (see FIG. 2B) in step S18, the pseudo wafer 10 is cut into individual electronic components 19 in step S19 (see FIG. 2C). In this way, the manufacture of the electronic component 19 is completed.

  According to the method of manufacturing the electronic component of Modification 2 described above, since the cut is formed until the amount of warpage of the pseudo wafer 10 falls within an allowable range, problems caused by the warpage of the pseudo wafer 10 can be reliably avoided. Thereby, there is an effect that the manufacturing yield of electronic components is further improved.

  In the above-described modification 2, a database representing the relationship between the amount of warp and the number of cuts is created, but a database representing the relationship between the amount of warp and the number of cuts and the depth is created, and the amount of warp is calculated. The number and depth of cuts may be determined accordingly.

(Second Embodiment)
8 to 9 are cross-sectional views showing the electronic component manufacturing method according to the second embodiment in the order of steps.

  First, as illustrated in FIG. 8A, the adhesive sheet 12 is disposed on the mounting table 11 as in the first embodiment, and the mold 13 is disposed so as to surround the periphery of the adhesive sheet 12. Then, device chips 14 a and 14 b are arranged at predetermined positions on the adhesive sheet 12.

  Next, after injecting the mold resin 15 into the mold 13, the mold resin 15 is cured to obtain the pseudo wafer 10 in which the mold resin 15 and the device chips 14 a and 14 b are integrated.

  Next, the pseudo wafer 10 is taken out from the mold 13 and the adhesive sheet 12 is peeled off. Then, as shown in FIG. 8B, a cut 16 is formed on the back side of the pseudo wafer 10.

  Next, as shown in FIG. 8C, the adhesive tape 21 is attached to the back side of the pseudo wafer 10 on a flat plate to forcibly correct the warp of the pseudo wafer 10.

  In this embodiment, since the cut 16 is provided in the pseudo wafer 10, the warp of the pseudo wafer 10 can be easily corrected. As the adhesive tape 21, for example, a dicing tape can be used. The dicing tape has a reduced adhesive strength when irradiated with ultraviolet rays.

  In this embodiment, the adhesive tape 21 is directly attached to the back side of the pseudo wafer 10. However, after the reinforcing ring is attached to the pseudo wafer 10, the adhesive tape 21 is attached to the pseudo wafer 10 together with the reinforcing ring. Also good. Moreover, the adhesive tape 21 may be one whose adhesive force is reduced by heat.

  Next, as shown in FIG. 8D, a rewiring layer 17 provided with a rewiring 17a having a desired pattern is formed on the pseudo wafer 10 by using a known film forming technique and microfabrication technique. . At this time, since the warpage of the pseudo wafer 10 is corrected by the notch 16 and the adhesive tape 21, a mounting error when mounting the pseudo wafer 10 on a film forming apparatus, an exposure apparatus, a transfer apparatus, or the like, or a positional deviation at the time of exposure. Is avoided.

  Next, as shown in FIG. 9A, the adhesive tape 21 is peeled from the pseudo wafer 10 after the adhesive tape 21 is irradiated with ultraviolet rays to reduce the adhesive force. Thereafter, as shown in FIG. 9B, the back surface of the pseudo wafer 10 is ground to make the pseudo wafer 10 thin to a desired thickness.

  Next, as shown in FIG. 9C, the pseudo wafer 10 is cut into each electronic component forming region by a dicing apparatus. In this way, an electronic component 19 in which a plurality of device chips 14a and 14b are integrated on one chip is obtained.

  In this embodiment, after the cut 16 is formed in the pseudo wafer 10, the warp of the pseudo wafer 10 is corrected by the adhesive tape 21. Thereby, compared with 1st Embodiment, the curvature of the pseudo wafer 10 can be made still smaller, and there exists an effect that the manufacture yield of an electronic component improves further.

  In this embodiment, since the rewiring layer 17 is formed with the adhesive tape 21 attached to the back surface of the pseudo wafer 10, vacuum suction (chucking) is performed even if the notch 16 is provided to the edge of the pseudo wafer 10. King) is possible. Therefore, there is an advantage that the formation of the notch 16 is easier than in the first embodiment.

  Also in the present embodiment, when a large warp occurs in the pseudo wafer 10 due to the formation of the rewiring layer 17, a cut may be provided again before or after the back surface grinding.

(Third embodiment)
FIGS. 10A to 10E are cross-sectional views showing a method of manufacturing an electronic component according to the third embodiment in the order of steps, and FIG. 11 is a top view showing a pseudo wafer in which cuts are formed.

  First, as illustrated in FIG. 10A, the adhesive sheet 12 is disposed on the mounting table 11 as in the first embodiment, and the mold 13 is disposed so as to surround the periphery of the adhesive sheet 12. Then, device chips 14 a and 14 b are arranged at predetermined positions on the adhesive sheet 12.

  Next, after injecting the mold resin 15 into the mold 13, the mold resin 15 is cured to obtain the pseudo wafer 10 in which the mold resin 15 and the device chips 14 a and 14 b are integrated.

  Next, the pseudo wafer 10 is taken out from the mold 13 and the adhesive sheet 12 is peeled off. Then, as shown in FIG. 10B, a cut 16a is formed on the front side of the pseudo wafer 10, and a cut 16b is formed on the back side.

  The depth of the cut 16a is, for example, 200 μm, and the depth of the cut 16b is, for example, 300 μm to 400 μm. In the example shown in FIG. 10B and FIG. 11, the cut 16a is formed at the boundary portion of the electronic component formation region, and the cut 16b is formed so as to pass through the center of the electronic component formation region.

  By thus forming the cuts 16a and 16b on both the front surface side and the back surface side of the pseudo wafer 10, the warpage of the pseudo wafer 10 is further suppressed.

  Next, as shown in FIG. 10C, a rewiring layer 17 provided with a rewiring 17a having a desired pattern is formed on the pseudo wafer 10 by using a known fine processing technique. At this time, since the warpage of the pseudo wafer 10 is suppressed by the cuts 16a and 16b provided in the pseudo wafer 10, mounting errors or exposure of the pseudo wafer 10 when mounting the pseudo wafer 10 on a film forming apparatus, an exposure apparatus, a transfer apparatus, or the like. Misalignment is avoided.

  Next, as shown in FIG. 10D, the back surface of the pseudo wafer 10 is ground to reduce the thickness of the pseudo wafer 10 to a desired thickness.

  Next, as shown in FIG. 10E, the pseudo wafer 10 is cut into each electronic component forming region by a dicing apparatus. In this way, an electronic component 19 in which a plurality of device chips 14a and 14b are integrated on one chip is obtained.

  In the present embodiment, since the cuts 16a and 16b are formed from the front surface side and the back surface side of the pseudo wafer 10, the warpage of the pseudo wafer 10 is further reduced as compared with the first embodiment. This avoids mounting errors when mounting the pseudo wafer 10 to a film forming apparatus, an exposure apparatus, a transfer apparatus, or the like, and a positional shift during exposure, and increases the manufacturing yield of electronic components in which a plurality of device chips are integrated into one chip. There is an effect of further improvement.

  The following additional notes are disclosed with respect to the above embodiments.

(Appendix 1) A step of arranging a plurality of device chips in a mold with the electrode forming surface of the device chip facing down,
Injecting mold resin into the mold,
Curing the mold resin to obtain a pseudo wafer in which the device chip and the mold resin are integrated;
Removing the pseudo wafer from the mold,
Forming a cut in the pseudo wafer;
Forming rewiring on the electrode forming surface of the device chip of the pseudo wafer;
And a step of dividing the pseudo wafer into individual electronic components.

  (Additional remark 2) The manufacturing method of the electronic component of Additional remark 1 characterized by arranging multiple said device chips for every formation area of the said electronic component.

  (Additional remark 3) The manufacturing method of the electronic component of Additional remark 1 or 2 characterized by forming the said notch so that it may not reach the said device chip.

  (Additional remark 4) The said cut | notch is formed in the said mold resin from the opposite side to the said electrode formation surface of the said device chip, The manufacturing method of the electronic component any one of Additional remark 1 thru | or 3 characterized by the above-mentioned.

  (Supplementary Note 5) The method of manufacturing an electronic component according to any one of Supplementary notes 1 to 4, wherein a plurality of the cuts are formed along two directions orthogonal to each other of the surface of the pseudo wafer. .

  (Additional remark 6) The manufacturing method of the electronic component of any one of Additional remark 1 thru | or 5 characterized by not providing the said notch in the edge part of the said pseudo wafer.

  (Additional remark 7) It has the process of apply | coating the insulating material containing a solvent component to the surface in which the said notch of the said pseudo wafer was formed between the process of forming the said notch, and the process of forming the said rewiring. The manufacturing method of the electronic component of Claim 4.

  (Additional remark 8) The said notch is formed in the boundary part of each formation area of the said electronic component, The manufacturing method of the electronic component of any one of Additional remark 1 thru | or 5 characterized by the above-mentioned.

  (Supplementary note 9) The method for manufacturing an electronic component according to any one of supplementary notes 1 to 3, wherein the cut is formed in the mold resin from the electrode forming surface side of the device chip and the opposite side thereof. .

  (Additional remark 10) It has the process of affixing an adhesive tape on the surface in the side which formed the said notch of the said pseudo wafer between the process of forming the notch in the said pseudo wafer, and the process of forming the said rewiring. The method for manufacturing an electronic component according to any one of appendices 1 to 5.

  (Additional remark 11) The adhesive force of the said adhesive tape falls by ultraviolet rays or a heat | fever, The manufacturing method of the electronic component of Additional remark 10 characterized by the above-mentioned.

(Supplementary note 12) The step of forming a cut in the pseudo wafer includes:
Measuring the amount of warpage of the pseudo wafer;
Determining whether the amount of warpage of the pseudo wafer is within an allowable range based on the measurement result of the amount of warpage;
Determining the number of cuts based on the measurement result of the amount of warpage of the pseudo wafer;
The method for manufacturing an electronic component according to any one of appendices 1 to 11, further comprising a step of actually forming cuts in the pseudo wafer with the number determined in the step of determining the number of cuts.

  (Supplementary note 13) In the step of determining the number of cuts, the number of cuts is determined with reference to a database representing the relationship between the amount of warpage and the number of cuts. Production method.

  DESCRIPTION OF SYMBOLS 10 ... Pseudo wafer, 11 ... Mounting stand, 12 ... Adhesive sheet, 13 ... Formwork, 14a, 14b ... Device chip, 15 ... Mold resin, 16, 16a, 16b ... Cut, 17 ... Redistribution layer, 18 ... Insulating film , 19 ... electronic components, 21 ... adhesive tape.

Claims (7)

Arranging a plurality of device chips in a mold with the electrode forming surface of the device chip facing down;
Injecting mold resin into the mold,
Curing the mold resin to obtain a pseudo wafer in which the device chip and the mold resin are integrated;
Removing the pseudo wafer from the mold,
Forming a cut in the pseudo wafer;
Applying an insulating material containing a solvent component to the surface of the pseudo wafer where the cuts are formed;
Forming rewiring on the electrode forming surface of the device chip of the pseudo wafer;
Possess a step to isolate the pseudo wafer into individual electronic components,
The method of manufacturing an electronic component, wherein the cut is formed in the mold resin from a side opposite to the electrode forming surface of the device chip .   The method of manufacturing an electronic component according to claim 1, wherein a plurality of the device chips are arranged for each formation region of the electronic component.   The method of manufacturing an electronic component according to claim 1, wherein the cut is formed so as not to reach the device chip. The incision method of manufacturing an electronic component according to any one of claims 1 to 3, characterized in that the plurality of formed along each other two directions perpendicular to the surface of the placebo wafer. Method of manufacturing an electronic component according to any one of claims 1 to 4 at the edge portion of the pseudo wafer, characterized in that it is provided with cuts said.   The adhesive tape is attached to the surface of the pseudo wafer on the side where the cut is formed, between the step of forming a cut in the pseudo wafer and the step of forming the rewiring. The manufacturing method of the electronic component of any one of 1 thru | or 5. The step of forming a cut in the pseudo wafer includes:
Measuring the amount of warpage of the pseudo wafer;
Determining whether the amount of warpage of the pseudo wafer is within an allowable range based on the measurement result of the amount of warpage;
Determining the number of cuts based on the measurement result of the amount of warpage of the pseudo wafer;
The method for manufacturing an electronic component according to any one of claims 1 to 6 , further comprising a step of actually forming cuts in the pseudo wafer with the number determined in the step of determining the number of cuts. .

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