JP6157745B2 - Execution time estimation program and execution time estimation device - Google Patents

Description

  The present invention relates to an execution time estimation program and an execution time estimation device that estimate the execution time of a sequence program.

  With the sophistication and complexity of functions required for production equipment, the FA controller program that controls the operation of production equipment has become more complex and capacity has continued to expand. A programming language mainly used in the FA controller is a ladder program. This ladder program does not have tools for supporting the development of a large-scale program as compared with high-level languages such as C and C ++ widely used in general-purpose machines.

  Ladder program is a programming language that uses a control panel that creates sequence control signals from electronic components such as relays and coils as a metaphor, and is designed to be easily understood by electrical designers who have no programming knowledge and engineers on site. It was. In such a ladder program, it is possible to easily describe a process for determining an output device value by a logical expression from a number of input device values and internal state values. The control flow in the ladder program is basically executed in order from the top to the bottom of the ladder program, and when the execution is completed to the end, the process returns to the beginning and is executed again.

  As described above, ladder programs tend to become large-scale. Even in such a case, considering the control of the production device, the scan time, which is the time to execute the ladder program from top to bottom, is within a certain time due to the need for cooperative operation with peripheral devices and error determination. It is necessary to design the ladder program so that it fits in However, when the ladder program becomes large-scale, it is difficult to accurately estimate the scan time.

  For this reason, the PLC simulator described in Patent Document 1 uses execution processing time data in the PLC of each instruction used in the ladder program. The PLC simulator integrates the processing time for each mnemonic command constituting the ladder program and the peripheral processing time for communication in the simulation execution process of the ladder program, thereby generating an execution logic time.

JP 2001-209411 A

  However, the above-described conventional technique has a problem that only the average execution time of the ladder program can be obtained, and the scan time cannot be estimated in the case that takes the longest time.

  The present invention has been made in view of the above, and it is an object of the present invention to obtain an execution time estimation program and an execution time estimation device that can estimate the scan time in the case that takes the longest time for a ladder program. To do.

In order to solve the above-described problems and achieve the object, the present invention provides an execution time estimation program for causing a computer to execute a process for estimating the execution time of a ladder program used in a controller, wherein the computer includes the ladder From the program, a combination extraction step of extracting a plurality of sets of software instructions executed by firmware and execution conditions of the software instructions to set the set information, and a plurality of set information extracted, By performing grouping for each first set set which is a set of set information in which a common device is used under the execution condition, the device common group in which the first set set is included is changed to the first set. Common group generation step for each set and software that may be executed simultaneously in the device common group Simultaneously generating a simultaneous execution group in which the second set set is entered for each second set by performing grouping for each second set that is a set of set information having an air command An execution group generating step, and for each of the device common groups, a group extraction step of extracting a simultaneous execution group having the longest execution time of the software instruction from among the simultaneous execution groups in the device common group; Based on the execution time of the software instruction when the concurrent execution group is executed, the scan time for calculating the scan time when the execution time becomes the longest among the scan times when the ladder program is executed one by one a calculation step, is executed, in the common group generation step, the computer, Based on a process for selecting any one set information from the plurality of set information, a process for putting the selected set information into the device common group, and a device included in the execution condition of the selected set information, And a process of putting any group information that has not been grouped into the device common group .

  According to the present invention, it is possible to estimate the scan time in the case that takes the longest time for the ladder program.

FIG. 1 is a diagram showing a configuration of an execution time estimation apparatus according to an embodiment of the present invention. FIG. 2 is a diagram illustrating an example of a ladder program expressed as a ladder diagram. FIG. 3 is a diagram showing an example of a ladder program expressed in IL (Instruction List). FIG. 4 is a flowchart showing an execution time estimation processing procedure performed by the execution time estimation device. FIG. 5 is a diagram for explaining ladder branch extraction processing. FIG. 6 is a flowchart showing a device common group generation processing procedure. FIG. 7 is a diagram for explaining a device common group generation process. FIG. 8 is a flowchart showing a procedure for generating a simultaneous execution group. FIG. 9 is a diagram for explaining the simultaneous execution group generation process. FIG. 10 is a diagram for explaining an example of processing for calculating the maximum scan time. FIG. 11 is a diagram illustrating a hardware configuration of the execution time estimation apparatus.

  Hereinafter, an execution time estimation program and an execution time estimation apparatus according to embodiments of the present invention will be described in detail with reference to the drawings. In addition, this invention is not limited by this Embodiment.

Embodiment FIG. 1 is a diagram showing a configuration of an execution time estimation apparatus according to an embodiment of the present invention. The execution time estimation device 10 is a computer or the like that estimates the execution time of a sequence program. Hereinafter, a case where the sequence program is a ladder program used in a controller such as a PLC (Programmable Logic Controller) will be described.

  The execution time estimation device 10 calculates a scan time, which is a time for executing the ladder program from top to bottom, as the execution time of the ladder program. The execution time estimation apparatus 10 according to the present embodiment estimates a scan time (hereinafter referred to as a maximum scan time 30) when the execution time of the ladder program is the longest.

  The ladder program includes a SW (software) instruction that is executed only when the execution condition is true. For this reason, when the ladder program is executed, the execution time of the ladder program differs depending on whether the SW instruction is executed or not. The execution time estimation device 10 estimates the maximum scan time 30 in the case where it takes the longest time when the ladder program is executed from the beginning to the end.

  The execution time estimation apparatus 10 includes a reception unit 11, a circuit block extraction unit 12, a combination information extraction unit 13, a SW instruction group extraction unit (simultaneous execution group generation unit) 14, and an execution time estimation unit (group extraction unit, scan time calculation unit). ) 15, an output unit 16, a storage unit 17, and a common group generation unit 18.

  The accepting unit 11 accepts IL expression information 20 indicating an IL (Instruction List) expression of the ladder program. The accepting unit 11 sends the IL expression information 20 input from an external device such as a database to the circuit block extracting unit 12.

  A ladder program is represented by a ladder diagram expression or an IL expression. FIG. 2 is a diagram illustrating an example of a ladder program expressed as a ladder diagram. FIG. 3 is a diagram illustrating an example of a ladder program expressed in IL. The ladder program shown in FIGS. 2 and 3 is the same.

  The ladder program includes an HW (hardware) instruction executed by hardware and an SW instruction executed by firmware. In the PLC architecture, the HW instruction is executed regardless of the value of the logical expression in the previous stage, and the SW instruction is executed only when the logical expression in the previous stage is true.

  The HW command is a command that requires a certain time. Whether or not the SW instruction is executed is determined by the value of a logical expression (hereinafter referred to as an execution condition part) connected to the preceding stage of the SW instruction. Specifically, the SW instruction is executed only when the value of the execution condition part becomes true. For this reason, the SW instruction takes an execution time only when the value of the execution condition part becomes true. The execution time estimation apparatus 10 according to the present embodiment estimates the maximum scan time 30 based on a group of SW instructions that are not executed simultaneously among the SW instructions.

HW command is
LD X0
AND X1
OUT Y102
Etc.

The SW instructions are SwOp0 to SwOp5. And the execution condition part of SwOp0 is
LD X0
AND X1
It is.

Therefore,
LD X0
AND X1
SwOp0 is executed only when is true.

  The circuit block extraction unit 12 extracts the circuit block indicated by the IL expression from the IL expression information 20. The circuit block extraction unit 12 sends the extracted circuit blocks to the combination information extraction unit 13.

  The combination information extraction unit 13 extracts combination information (hereinafter referred to as a ladder branch) including a combination of the SW instruction and the execution condition part of the SW instruction from the circuit block expressed in IL. The combination information extraction unit 13 sends the extracted ladder branch to the common group generation unit 18.

  Based on the ladder branch, the common group generation unit 18 groups a first set set, which is a set of ladder branches in which devices common to the execution condition unit are used, for each ladder branch. The common group generation unit 18 groups ladder branches by generating a ladder branch set (hereinafter referred to as a device common group) in which a common device is used in the execution condition unit.

  In other words, the common group generation unit 18 groups the extracted plurality of ladder branches for each set of ladder branches (hereinafter referred to as common ladder branches) in which a common device is used in the execution condition unit. As a result, the common group generation unit 18 generates a device common group in which the common ladder branch is inserted for each common ladder branch. The common group generation unit 18 sends the device common group to the SW instruction group extraction unit 14.

  The SW instruction group extraction unit 14 groups a second set of ladder branch sets that may be executed simultaneously in the device common group for each ladder branch set (hereinafter referred to as SW instruction group). As a result, the SW instruction group extraction unit 14 generates, for each SW instruction group, a group in which the SW instruction group is inserted, that is, a simultaneous execution group described later.

  A ladder branch set in which a common device is used in the execution condition part is a common ladder branch, and a group including the common ladder branch is a device common group. Therefore, a device common group is generated for each common ladder branch. A set of ladder branches that may be executed simultaneously in the device common group is a SW instruction group, and a group including the SW instruction group is a simultaneous execution group.

  In the device common group, ladder branches are grouped for each simultaneous execution group, so that a set of ladder branches that are not executed simultaneously in the device common group is set to a different group. Therefore, ladder branches that belong to the same concurrent execution group are ladder branches that may be executed simultaneously, and ladder branches that belong to different concurrent execution groups do not execute simultaneously. It is a branch. The SW instruction group extraction unit 14 sends the grouping result to the execution time estimation unit 15.

  The storage unit 17 is, for example, a memory that stores instruction execution time data 21. The instruction execution time data 21 includes information on the execution time of each SW instruction and the execution time of each HW instruction. Specifically, in the instruction execution time data 21, the SW instruction and the execution time are associated with each other, and the HW instruction and the execution time are associated with each other.

The execution time estimation unit 15 estimates the maximum scan time 30 based on the grouping result and the instruction execution time data 21. Specifically, the execution time estimation unit 15 estimates the S W execution time of each instruction group Ru ladder branch group der never be executed simultaneously. The execution time estimation unit 15 sets a SW instruction group for each device common group, and estimates an execution time for each SW instruction group for each device common group.

  Then, the execution time estimating unit 15 employs the SW instruction group having the longest total execution time of each instruction among the SW instruction groups in the device common group as the SW instruction group contributing to the maximum scan time 30. The execution time estimation unit 15 sets a SW command group that contributes to the maximum scan time 30 for each device common group.

  The execution time estimation unit 15 calculates the execution time of the SW instruction group that contributes to the maximum scan time 30 based on the instruction execution time data 21 for the SW instruction group that contributes to the maximum scan time 30. Further, the execution time estimation unit 15 calculates the execution time of the HW instruction based on the instruction execution time data 21 for the HW instruction.

  The execution time estimation unit 15 estimates the maximum execution time of the SW instruction by adding all execution times of the SW instruction group for each device common group. The execution time estimation unit 15 estimates the maximum scan time 30 by adding the maximum execution time of the SW instruction and the execution time of the HW instruction.

  In other words, the execution time estimation unit 15 calculates the execution time of the SW instruction for each device common group, and adds the calculated total time of each execution time and the total execution time of the HW instruction. Is executed to calculate the maximum scan time 30. The execution time estimation unit 15 sends the maximum scan time 30 to the output unit 16. The output unit 16 outputs the maximum scan time 30 to the external device.

  Next, an execution time estimation processing procedure performed by the execution time estimation device 10 will be described. FIG. 4 is a flowchart showing an execution time estimation processing procedure performed by the execution time estimation device. Upon receiving the IL expression information 20, the reception unit 11 of the execution time estimation apparatus 10 sends the IL expression information 20 to the circuit block extraction unit 12.

  The circuit block extraction unit 12 extracts the circuit block indicated by the IL expression from the IL expression information 20 (step S10). The combination information extraction unit 13 extracts the SW instruction and the execution condition part of the SW instruction from the circuit block. Specifically, the combination information extraction unit 13 converts an AND node and an OR node into a tree representation using nesting (hereinafter referred to as a ladder tree) for the IL representation of each circuit block. Then, the combination information extraction unit 13 circulates the ladder tree in order from the top of each ladder tree, and extracts a ladder branch that is a set of the SW instruction and the execution condition part of the SW instruction from the ladder tree (step S20).

  FIG. 5 is a diagram for explaining ladder branch extraction processing. The IL representation of each circuit block is converted into a ladder tree. Then, from each ladder tree, a ladder branch that is a set of the SW instruction and the execution condition part of the SW instruction is extracted. The combination information extraction unit 13 sends the extracted ladder branch to the common group generation unit 18.

  Based on the ladder branch, the common group generation unit 18 performs grouping for each ladder branch in which a common device is used in the execution condition unit (step S30). The common group generation unit 18 groups ladder branches by generating a set of common ladder branches in which devices common to the execution condition unit are used, that is, a device common group. The common group generation unit 18 sends the device common group including the common ladder branch to the SW instruction group extraction unit 14.

  The SW instruction group extraction unit 14 groups ladder branch sets that may be executed simultaneously in the device common group. As a result, the SW instruction group extraction unit 14 groups the ladder branch sets that are not executed simultaneously in the device common group (step S40). The SW instruction group extraction unit 14 groups the ladder branch set for each device common group. The SW instruction group extraction unit 14 sends the ladder branch set that is not executed simultaneously in the device common group to the execution time estimation unit 15 as the SW instruction group that is not executed simultaneously.

  The execution time estimation unit 15 estimates the maximum scan time 30 based on a group of SW instructions that are not executed simultaneously (step S50). Specifically, the execution time estimation unit 15 compares the execution time for each SW instruction group within each device common group. At the time of this comparison, the execution time estimation unit 15 calculates the execution time of each SW instruction group based on the instruction execution time data 21 and compares the execution times of the SW instruction groups.

  The execution time estimation unit 15 extracts the execution time of the SW instruction group having the longest execution time among the SW instruction groups for each device common group, and adds up all the extracted execution times. The execution time estimation unit 15 uses the integration result as the maximum execution time of the SW instruction, and adds the execution time of the HW instruction to estimate the maximum scan time 30.

  Next, device common group generation processing will be described. FIG. 6 is a flowchart showing a device common group generation processing procedure. FIG. 7 is a diagram for explaining a device common group generation process.

  In FIG. 7, all ladder branch sets extracted in the description of FIG. 5 are shown as all ladder branch sets 50. The entire ladder branch set 50 includes ladder branches 41 to 45 corresponding to SwOp0 to SwOp5. The common group generation unit 18 generates one device common group (step S21). FIG. 7 shows a case where the device common group 51 is generated. This device common group 51 is empty at the time of generation (st100) and does not contain a ladder branch set.

  After generating the device common group 51, the common group generation unit 18 selects one arbitrary ladder branch from the entire ladder branch set 50 and places it in the generated device common group 51 (step S22). Ladder branches placed in the device common group 51 are deleted from the entire ladder branch set 50. FIG. 7 shows a case where the ladder branch 41 of SwOp0 is selected (st101) and placed in the device common group 51 (st102).

  The common group generation unit 18 checks whether there are other ladder branches that can be selected in the entire ladder branch set 50 (step S23). When there is a ladder branch that can be selected in the entire ladder branch set 50 (step S23, Yes), the common group generation unit 18 moves through the entire ladder branch set 50 for all devices X0 and X1 used in the ladder branch 41. It is confirmed whether it has been checked (step S24).

  If all the devices have not been checked (No in step S24), the common group generation unit 18 uses the devices X0 and X1 used in the execution condition unit of the ladder branch 41 in the device common group 51 and has not been checked. One device is selected (step S25). For example, the common group generation unit 18 selects the device X0.

  The common group generation unit 18 selects all ladder branches that use the selected device X0 in the execution condition unit from the entire ladder branch set 50 (step S26). The common group generation unit 18 puts the selected ladder branch into the device common group having the common device X0 and deletes it from the entire ladder branch set (step S27). FIG. 7 shows a case where the ladder branch 43 of SwOp3 is selected and placed in the device common group 51 (st103).

  Thereafter, the common group generation unit 18 confirms whether there are other ladder branches that can be selected in the entire ladder branch set 50 (step S23). When there is a ladder branch that can be selected in the entire ladder branch set 50 (step S23, Yes), the common group generation unit 18 moves through the entire ladder branch set 50 for all devices X0 and X1 used in the ladder branch 41. It is confirmed whether it has been checked (step S24).

  When all the devices X0 and X1 are not checked (step S24, No), the common group generation unit 18 is the devices X0 and X1 used in the execution condition unit included in the ladder branch 41 in the device common group 51. One uninvestigated device is selected (step S25). For example, the common group generation unit 18 selects the device X1.

  The common group generation unit 18 selects a ladder branch that uses the selected device X1 in the execution condition unit from the entire ladder branch set 50 (step S26). The common group generation unit 18 puts the selected ladder branch into a device common group having a common device and deletes it from the entire ladder branch set (step S27). FIG. 7 shows a case where the ladder branch 45 of SwOp5 is selected and placed in the device common group 51 (st104).

  Thereafter, the common group generation unit 18 confirms whether there are other ladder branches that can be selected in the entire ladder branch set 50 (step S23). When there is a ladder branch that can be selected in the entire ladder branch set 50 (Yes in step S23), the common group generation unit 18 confirms whether or not all devices X0 and X1 used in the ladder branch 41 have been checked (step S23). S24).

  When all the devices X0 and X1 are examined (step S24, Yes), the common group generation unit 18 repeats the processes of steps S21 to S27 for all ladder branch sets 50 until there are no ladder branches.

  That is, the common group generation unit 18 generates one device common group (step S21) (st105). FIG. 7 shows a case where the device common group 52 is generated. This device common group 52 is empty at the time of generation, and does not contain a ladder branch set.

  After setting the device common group 52, the common group generation unit 18 selects one arbitrary ladder branch from the entire ladder branch set 50 and places it in the generated device common group 52 (step S22). Ladder branches placed in the device common group 52 are deleted from the entire ladder branch set 50. FIG. 7 shows a case where the SwOp4 ladder branch 44 is selected and placed in the device common group 52 (st106).

  The common group generation unit 18 checks whether there are other ladder branches that can be selected in the entire ladder branch set 50 (step S23). If there is a ladder branch that can be selected in the entire ladder branch set 50 (Yes in step S23), the common group generation unit 18 has checked the entire ladder branch set 50 for all the devices X11 used in the ladder branch 44. Is confirmed (step S24).

  When all the devices have not been checked (No in step S24), the common group generation unit 18 is a device used in the execution condition unit included in the ladder branch 44 in the device common group 52, and the unexamined device is set to 1. Is selected (step S25). For example, the common group generation unit 18 selects the device X11.

  The common group generation unit 18 selects a ladder branch that uses the selected device X11 in the execution condition unit from the entire ladder branch set 50 (step S26). The common group generation unit 18 puts the selected ladder branch into a device common group having a common device and deletes it from the entire ladder branch set (step S27). FIG. 7 shows a case where the ladder branch 42 of SwOp1 is selected and placed in the device common group 52 (st107).

  Thereafter, the common group generation unit 18 confirms whether there are other ladder branches that can be selected in the entire ladder branch set 50 (step S23). When there is no ladder branch that can be selected in the entire ladder branch set 50 (No in step S23), the common group generation unit 18 ends the device common group generation process.

  As described above, the common group generation unit 18 sets a ladder branch having the same execution condition part as that of the selected arbitrary ladder branch in the same device common group. As a result, the common group generation unit 18 groups the ladder branches so that the ladder branches having the same execution condition unit are included in the same device common group. FIG. 7 shows a case in which SwOp0, SwOp3, and SwOp5 having devices X0, X1, and X2 as execution condition parts and SwOp4 and SwOp1 having devices X11 and X10 as execution condition parts are grouped.

  Next, processing for generating a ladder branch set (simultaneous execution group) that may be executed simultaneously in each device common group will be described. FIG. 8 is a flowchart showing a procedure for generating a simultaneous execution group. FIG. 9 is a diagram for explaining the simultaneous execution group generation process.

  The process shown in FIG. 8 is performed for each ladder branch set having a common device. In other words, the process illustrated in FIG. 8 is a process performed for each device common group. 8 and 9, a description will be given of a process of allocating each ladder branch in the device common group 51 to any one of the simultaneous execution groups.

  As shown in FIG. 9, the device common group 51 includes a ladder branch 41 of SwOp0, a ladder branch 43 of SwOp3, and a ladder branch 45 of SwOp5. The SW instruction group extraction unit 14 generates one simultaneous execution group as a ladder branch set that may be simultaneously executed (step S31). FIG. 9 shows a case where the simultaneous execution group 61 is generated. This simultaneous execution group 61 is empty at the time of generation (st200) and does not contain a ladder branch set.

  After generating the simultaneous execution group 61, the SW instruction group extraction unit 14 selects one arbitrary ladder branch from the device common group 51 and places it in the generated simultaneous execution group 61 (step S32). Ladder branches placed in the simultaneous execution group 61 are deleted from the device common group 51. FIG. 9 shows a case where the ladder branch 41 of SwOp0 is selected (st201) and placed in the simultaneous execution group 61 (st202).

  The SW instruction group extraction unit 14 checks whether or not the element of the ladder branch set having the common device is empty (step S33). In other words, the SW instruction group extraction unit 14 checks whether or not a ladder branch remains in any device common group.

  When there is a ladder branch that can be selected in the device common group 51 (step S33, No), the SW instruction group extraction unit 14 selects one unexamined ladder branch from the device common group 51 (step S34). The SW instruction group extraction unit 14 selects, for example, the ladder branch 43 of SwOp3.

  The SW instruction group extraction unit 14 determines whether or not the product of the execution condition of the ladder branch 41 belonging to the simultaneous execution group 61 and the execution condition of the selected ladder branch 43 has a solution (step S35). When the ladder branch 41 and the ladder branch 43 may be executed at the same time, the product of the execution conditions of the ladder branches 41 and 43 has a solution. On the other hand, if the ladder branch 41 and the ladder branch 43 are not executed simultaneously, the product of the execution conditions of the ladder branches 41 and 43 has no solution.

  Here, the SW instruction group extraction unit 14 determines whether (X0 * X1) * ((NOT X0) + (NOT X2)) = TRUE. When the product of the execution conditions of the ladder branches 41 and 43 has a solution (Yes in step S36), the SW instruction group extraction unit 14 puts the selected ladder branch 43 into the simultaneous execution group 61 and deletes it from the device common group 51. (Step S37). FIG. 9 shows a case where the ladder branch 43 of SwOp3 is selected and placed in the simultaneous execution group 61 (st203).

  The SW instruction group extraction unit 14 determines whether or not the product of the execution conditions has a solution based on, for example, SMT (SATISFIABLE MODULO THEORIES). The SMT is an arithmetic theory or a set theory representing a mathematical system of a specific field. Some SMT solvers can solve the first-order predicate logic satisfiability determination problem. The SMT includes not only whether or not the constraint is satisfied, but also information on how to assign the variable when the constraint is satisfied.

  The SW instruction group extraction unit 14 checks whether there is an unexamined ladder branch in the device common group 51 (step S38). When there is an unexamined ladder branch (step S38, Yes), the SW instruction group extraction unit 14 checks whether or not an element of the ladder branch set having the common device is empty (step S33).

  When there is a ladder branch that can be selected in the device common group 51 (step S33, No), the SW instruction group extraction unit 14 selects one unexamined ladder branch from the device common group 51 (step S34). For example, the SW instruction group extraction unit 14 selects the ladder branch 45 of SwOp5.

  The SW instruction group extraction unit 14 determines whether the product of the execution condition of the ladder branches 41 and 43 belonging to the simultaneous execution group 61 and the execution condition of the selected ladder branch 45 has a solution (step S35). ). Here, the SW instruction group extraction unit 14 determines whether (X0 * X1) * ((NOT X0) + (NOT X2)) * (NOT X1) = TRUE.

  When the product of the execution conditions of the ladder branches 41, 43, 45 does not have a solution (No in step S <b> 36), the SW instruction group extraction unit 14 converts the selected ladder branch 45 into another simultaneous operation different from the simultaneous execution group 61. Enter the execution group and delete from the device common group 51.

  When another concurrent execution group different from the concurrent execution group 61 has already been generated, the SW instruction group extraction unit 14 executes the execution condition of the ladder branch in the generated concurrent execution group and the selected ladder branch 45. It is determined whether the product with the execution condition of has a solution. When the SW instruction group extraction unit 14 has a solution, the SW instruction group extraction unit 14 puts the ladder branch 45 in the generated simultaneous execution group.

  On the other hand, if another concurrent execution group different from the concurrent execution group 61 has not been generated, the SW instruction group extraction unit 14 creates a new concurrent execution group and inserts the selected ladder branch 45. FIG. 9 shows the case where the ladder branch 45 of SwOp5 is selected and placed in the new simultaneous execution group 62 (st204, st205).

  Thereafter, the SW instruction group extraction unit 14 checks whether or not the element of the ladder branch set having the common device is empty (step S33). If not empty, the SW instruction group extraction unit 14 performs the processes of steps S34 to S38.

  Then, in the process of step S38, when the SW instruction group extraction unit 14 determines that there is no unexamined ladder branch in the device common group 51 (No in step S38), the SW instruction group extraction unit 14 determines that the device common group 51 Steps S31 to S38 are performed for another device common group different from 51. For example, the SW instruction group extraction unit 14 performs steps S31 to S38 for the device common group 52.

  When the SW instruction group extraction unit 14 determines that the element of the ladder branch set having the common device is empty in the process of step S33 (Yes in step S33), the simultaneous execution group of the SW instruction group extraction unit 14 is determined. The generation process ends.

  In this way, the SW instruction group extraction unit 14 groups ladder branches by generating a set of ladder branches that may be simultaneously executed in the device common group 51 as a simultaneous execution group.

  Of the simultaneous execution groups classified by the SW instruction group extraction unit 14, simultaneous execution groups generated from the same device common group are SW instruction groups that are not executed simultaneously. In other words, different simultaneous execution groups generated from the same device common group are SW instructions that are not executed simultaneously. For example, since the simultaneous execution groups 61 and 62 are both generated from the device common group 51, the simultaneous execution groups 61 and 62 are SW instruction groups that are not executed simultaneously.

  When the SW instruction group extraction unit 14 generates a simultaneous execution group from the device common group 52 shown in FIG. 7, a simultaneous execution group including the ladder branch 44 of SwOp4 and a simultaneous execution group including the ladder branch 42 of SwOp1 exist. Will be generated.

  As described above, as a result of the generation of the simultaneous execution group, SwOp0 and SwOp3 may be executed at the same time, but “SwOp0, SwOp3” and “SwOp5” are not executed at the same time. It can also be seen that SwOp1 and SwOp4 are not executed simultaneously.

  The execution time estimation unit 15 estimates the maximum scan time 30 based on the result of classification into simultaneous execution groups. FIG. 10 is a diagram for explaining an example of processing for calculating the maximum scan time.

  FIG. 10 shows the correspondence between the SW instruction or HW instruction and the execution time. FIG. 10 shows an estimated value of the maximum scan time 30. When there is a group of SW instructions that are not executed at the same time, it is considered that the execution time of the SW instruction group having the longer execution time of the SW instruction contributes to the maximum scan time 30. Therefore, the execution time estimation unit 15 applies the SW instruction group having the longer execution time to the calculation process of the maximum scan time 30.

  For example, “LD X0” of the HW instruction has an execution time Tld, and “AND X1” of the HW instruction has an execution time Tand. If the execution time of the SW instruction “SwOpi” is described as Ti, the execution times of SwOp0 to SwOp5 are T0 to T5, respectively. In this case, regarding SwOp0, SwOp3, and SwOp5 in the device common group 51, the larger one of “T0 + T3” and T5 is applied to the calculation process of the maximum scan time 30. As for SwOp1 and SwOp4 in the device common group 52, the larger of T1 and T4 is applied to the calculation process of the maximum scan time 30.

  FIG. 10 shows the calculation result of the maximum scan time 30 when (T0 + T3)> T5 and T1> T4. The execution time estimation unit 15 calculates the maximum scan time 30 by setting the execution time of the SW instruction group not applied to the calculation process of the maximum scan time 30 among the SW instruction groups to 0.

  The execution time estimation unit 15 applies (T0 + T3) of (T0 + T3) and T5 to the calculation process of the maximum scan time 30, and applies T1 of T1 and T4 to the calculation process of the maximum scan time 30. Therefore, the execution time estimation unit 15 calculates T0 + T3 + T1 as the execution time of the SW instruction.

  The execution time estimation unit 15 calculates the total execution time of all the HW instructions as the execution time of the HW instruction. Specifically, the execution time estimation unit 15 calculates 4Tld + 2Tldi + Tand + Tani + Tori + Tout as the execution time of the HW instruction. Then, the execution time estimation unit 15 sets the total time of the execution time of the SW instruction and the execution time of the HW instruction as an estimated value of the maximum scan time 30.

  FIG. 11 is a diagram illustrating a hardware configuration of the execution time estimation apparatus. The execution time estimation apparatus 10 includes a central processing unit (CPU) 91, a read only memory (ROM) 92, a random access memory (RAM) 93, a display unit 94, and an input unit 95. In the execution time estimation device 10, the CPU 91, ROM 92, RAM 93, display unit 94, and input unit 95 are connected via the bus line B.

  The CPU 91 estimates the maximum scan time 30 using an execution time estimation program 90 that is a computer program. The display unit 94 is a display device such as a liquid crystal monitor, and based on instructions from the CPU 91, a ladder program, SW command, HW command, execution condition unit, ladder branch, device common group, simultaneous execution group, maximum scan time 30 Etc. are displayed. The input unit 95 includes a mouse or a keyboard, and inputs instruction information (such as a parameter necessary for estimating the maximum scan time 30) input from the outside. The instruction information input to the input unit 95 is sent to the CPU 91.

  The execution time estimation program 90 is stored in a ROM 92 or the like, which is a computer-readable non-transitory recording medium (nontransitory computer readable medium), and is loaded into the RAM 93 via the bus line B.

  The CPU 91 executes the execution time estimation program 90 loaded in the RAM 93. Specifically, in the execution time estimation apparatus 10, the CPU 91 reads the execution time estimation program 90 from the ROM 92 and expands it in the program storage area in the RAM 93 in accordance with an instruction input from the input unit 95 by the user, and performs various processes. Run. The CPU 91 temporarily stores various data generated during the various processes in a data storage area formed in the RAM 93.

  The execution time estimation program 90 executed by the execution time estimation device 10 includes a circuit block extraction unit 12, a combination information extraction unit 13, a SW instruction group extraction unit 14, an execution time estimation unit 15, and a common group generation unit 18. These are loaded on the main storage device, and these are generated on the main storage device. As described above, the execution time estimation program 90 can be realized as software on the execution time estimation apparatus 10 which is a computer. The function of the circuit block extraction unit 12 may be stored in a different program different from the execution time estimation program 90.

  In the present embodiment, the case where the reception unit 11 receives a ladder program has been described. However, the reception unit 11 may receive a ladder tree. When the reception unit 11 receives a ladder tree, the combination information extraction unit 13 extracts a ladder branch from the ladder tree. Moreover, when the reception part 11 receives a ladder tree, the execution time estimation apparatus 10 does not need to be provided with the circuit block extraction part 12. FIG.

  According to the present embodiment, the maximum scan time 30 is calculated based on the simultaneous execution group in which the execution time of the software instruction is the longest among the simultaneous execution groups in the device common group. It is possible to estimate the scan time in a case.

  As described above, the execution time estimation program and the execution time estimation apparatus according to the present invention are suitable for estimating the execution time of a sequence program.

  DESCRIPTION OF SYMBOLS 10 execution time estimation apparatus, 12 circuit block extraction part, 13 combination information extraction part, 14 SW instruction group extraction part, 15 execution time estimation part, 18 common group production | generation part, 20 IL expression information, 21 instruction execution time data, 41- 45 Ladder branches, 50 All ladder branch sets, 51, 52 Device common group, 61, 62 Simultaneous execution group, 90 Execution time estimation program.

Claims (5)

An execution time estimation program for causing a computer to execute processing for estimating the execution time of a ladder program used in a controller,
In the computer,
From the ladder program, a combination extraction step of extracting a plurality of sets of software instructions to be executed by firmware and execution conditions of the software instructions into set information;
The first set set is entered by performing grouping for each first set set, which is a set of set information in which a common device is used in the execution condition, for the plurality of set information extracted. A common group generation step of generating a device common group for each first set set;
By grouping each second set, which is a set of set information having software instructions that may be executed simultaneously in the device common group, the second set is entered. A concurrent execution group generating step for generating the concurrent execution group for each second set set;
For each of the device common groups, a group extraction step of extracting a concurrent execution group having the longest execution time of the software instruction from among the concurrent execution groups in the device common group;
Based on the execution time of the software instruction when the extracted simultaneous execution group is executed, a scan for calculating the scan time when the execution time becomes the longest among the scan times when the ladder program is executed one by one A time calculation step;
And execute
In the common group generation step,
In the computer,
A process of selecting any one set information from the plurality of set information;
A process of putting the selected set information into the device common group;
Based on the device included in the execution condition of the selected set information, processing to put any of the set information that has not been grouped into the device common group,
An execution time estimation program characterized in that In the simultaneous execution group generation step,
In the computer,
A software instruction corresponding to the first execution condition based on whether a product of a first execution condition of the execution conditions and a second execution condition of the execution conditions has a solution; 2. The execution time estimation program according to claim 1, wherein a process for determining whether or not a software instruction corresponding to the second execution condition is likely to be executed simultaneously is executed. In the common group generation step,
In the computer,
When there is no group information that can be included in the device common group, a process of newly selecting any one group information that is not grouped from the plurality of group information;
The process of putting the newly selected set information into a new device common group,
Based on the device included in the execution condition of the newly selected set information, a process of putting any of the set information not grouped into the new device common group;
The execution time estimation program according to claim 1 , wherein: In the group extraction step,
In the computer,
For each device common group, execute the process of extracting the concurrent execution group that has the longest execution time,
In the scan time calculating step,
In the computer,
A process for calculating the execution time of the software instruction for each device common group, a total time of the calculated execution times, and a total time of execution times of hardware instructions executed by hardware in the ladder program; , By calculating the scan time when the execution time is the longest,
The execution time estimation program according to any one of claims 1 to 3 , wherein the execution time estimation program is executed. From the ladder program used in the controller, a combination extraction unit that extracts a plurality of sets of software instructions executed by firmware and execution conditions of the software instructions and sets them as set information;
The first set set is entered by performing grouping for each first set set, which is a set of set information in which a common device is used in the execution condition, for the plurality of set information extracted. A common group generation unit for generating a device common group for each first set set;
By grouping each second set, which is a set of set information having software instructions that may be executed simultaneously in the device common group, the second set is entered. A concurrent execution group generating unit that generates a concurrent execution group for each second set set;
A group extraction unit for extracting a concurrent execution group having the longest execution time of the software instruction from among the concurrent execution groups in the device common group;
Based on the execution time of the software instruction when the extracted simultaneous execution group is executed, a scan for calculating the scan time when the execution time becomes the longest among the scan times when the ladder program is executed one by one A time calculation unit;
Equipped with a,
The common group generation unit
A process of selecting any one set information from the plurality of set information;
A process of putting the selected set information into the device common group;
Based on the device included in the execution condition of the selected set information, processing to put any of the set information that has not been grouped into the device common group,
The execution time estimation apparatus characterized by performing.

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