JP6155671B2 - Auxiliary circuit of power supply device and power supply circuit having the auxiliary circuit - Google Patents

Description

  The present invention relates to an auxiliary circuit for controlling the operation of a power supply device having a control input terminal, and more particularly to an auxiliary circuit for operating the power supply device intermittently when the power supply device is in an overcurrent state.

  There are various types of protection circuits when the power supply device is overloaded. For example, Patent Document 1 discloses a power supply device that repeatedly stops and restarts a switching operation when an overcurrent state occurs (when an overcurrent flows). In this power supply device, the control of temporarily stopping the operation of the control IC and then restarting it is continued until it is removed from the overcurrent state.

Patent Document 2 discloses a power supply device that latches and stops a switching operation when an overcurrent state occurs. Further, the power supply device restarts when a signal for releasing the latch stop is given. Therefore, if an external circuit for giving a signal for releasing the latch stop when the power supply device is latched stopped is added to the power supply device, a protective operation for repeatedly stopping and restarting the switching operation can be performed.
JP 5-76170 JP 2003-169471 A

  As in Patent Document 2, there is a case where this protection operation is desired to be performed in a power supply device that does not have a function of performing a protection operation that repeatedly stops and restarts the switching operation. Further, as in Patent Document 2, when realizing this protection operation, a power supply device having a function of restarting when a signal for releasing the latch stop is given (latch stop release function) must be used. I must.

  However, there are many power supply devices that do not have this latch stop release function, and there are cases in which it is desired to realize a protective operation that repeatedly stops and restarts the switching operation. For example, there is a case where this protection operation is desired to be realized by using an external control function (a function of stopping a switching operation based on a control signal given from the outside) provided in a general power supply device.

  The present invention has been made to solve this problem, and it is an object of the present invention to provide an auxiliary circuit for causing a power supply device having an external control function to perform a protective operation that repeatedly stops and restarts a switching operation. And

  In order to achieve the above object, an auxiliary circuit of a power supply device according to the present invention is an auxiliary circuit of a power supply device externally attached to a power supply device having a function of stopping operation based on a signal input to an external control terminal. A pulse generation circuit that alternately outputs a first voltage and a second voltage having a voltage value higher than the first voltage at a constant period; an output voltage of the power supply device; and a predetermined threshold voltage. An output voltage detection circuit that outputs the first voltage or the second voltage based on a result of the comparison, and an output of the pulse generation circuit as a first input signal, the output voltage detection circuit A logic circuit that performs a logical operation using the output as a second input signal and generates a control signal to be supplied to the power supply device, the logic circuit including a voltage value of the first input signal and the second input signal The voltage value of Occasionally, and is configured to be able to stop the operation of the power supply device by the control signal.

  When the power supply device that stops operation when the voltage of the signal input to the external control terminal is the second voltage (H level), the logic circuit can be configured as follows. The output voltage detection circuit outputs the second voltage (H level) when the output voltage of the power supply device is lower than the predetermined threshold voltage, and the signal output from the pulse generation circuit is the second voltage. When the period maintained at (H level) corresponds to the period during which the power supply device is stopped, the logic circuit is configured to perform a logical operation of a logical product. In other words, the logic circuit is configured to stop the operation of the power supply apparatus when both the first input signal and the second input signal are in the combination of the second voltage (H level). .

  An auxiliary circuit for a power supply apparatus according to the present invention is an auxiliary circuit for a power supply apparatus externally attached to a power supply apparatus having a function of stopping operation based on a signal input to an external control terminal. And a pulse generation circuit that alternately outputs a second voltage having a voltage value higher than the first voltage at a constant cycle, and an input current of the power supply device and a predetermined first current value are compared. Or an output voltage detection circuit that compares the output current of the source device with a predetermined second current value and outputs the first voltage or the second voltage based on the result of the comparison, and the output A pulse output circuit in which the voltage value of the output signal shifts to the first voltage or the second voltage in synchronization with the rise or fall of the signal output from the voltage detection circuit; and the output of the pulse generation circuit 1 input signal and the pulse output circuit A logic circuit that performs a logical operation using a power as a third input signal and generates a control signal to be applied to the power supply device, the logic circuit including a voltage value of the first input signal and the third input signal. When the voltage value becomes a predetermined combination, the operation of the power supply device can be stopped by the control signal.

  In the case where the logic circuit is configured such that the power supply device stops operating while the signal output from the pulse generation circuit is maintained at the first voltage, the pulse generation circuit The period during which the output signal is maintained at the second voltage is longer than the time taken for the power supply device to start, and the signal output from the pulse generation circuit is maintained at the second voltage. When the logic circuit is configured to stop the operation of the power supply apparatus during a period during which the power supply apparatus is in a period during which the signal output from the pulse generation circuit is maintained at the first voltage Make it longer than the time it takes to start.

  A power supply circuit according to the present invention includes any one of the power supply device auxiliary circuit and the power supply device.

  Performs a logical operation using a pulse generation circuit that outputs a pulse signal, a detection circuit that detects an overcurrent state or an overload state, and a pulse signal output from the pulse generation circuit and a detection signal output from the detection circuit as input signals. By configuring an auxiliary circuit including a logic circuit, it is possible to cause a power supply device having an external control function to perform a protective operation that repeatedly stops and restarts a switching operation.

It is the block circuit which showed the structure of the auxiliary circuit of the power supply device which concerns on a 1st Example. It is a timing chart for demonstrating operation | movement of the auxiliary circuit of the power supply device which concerns on a 1st Example. It is the block circuit which showed the structure of the auxiliary circuit of the power supply device which concerns on a 2nd Example. It is the block circuit which showed the structure of the auxiliary circuit of the power supply device which concerns on a 3rd Example. It is the block circuit which showed the structure of the auxiliary circuit of the power supply device which concerns on a 4th Example. It is the block circuit which showed the structure of the auxiliary circuit of the power supply device which concerns on a 5th Example. It is a timing chart for demonstrating operation | movement of the auxiliary circuit of the power supply device which concerns on a 5th Example. It is the block circuit which showed the structure of the auxiliary circuit of the power supply device which concerns on a 5th Example. It is a circuit diagram showing an example of an output voltage detection circuit. It is a circuit diagram showing an example of an AND (logical product) circuit.

  Hereinafter, an auxiliary circuit of a power supply device according to the present invention will be described with reference to the drawings. In addition, if this auxiliary circuit is a power supply device provided with an external control terminal (external control function), even if it is a power supply device of AC (alternating current) input DC (direct current) output, it is a power supply device of DC input DC output. Even if it exists, it can be used. The external control terminal is a terminal for inputting a signal for instructing the power supply device to start or stop, and the power supply device operates based on the voltage value of the signal input to the external control terminal.

  FIG. 1 is a block diagram of a power supply circuit in which an auxiliary circuit according to the present invention is mounted as an external circuit. In this block diagram, the power supply device 1 includes an input terminal (+ Vinn, −Vin), an output terminal (+ Vout, −Vout), and an external control terminal (CTL). An input voltage Vin is input to the input terminal, and a load 2 is connected to the output terminal. Note that + Vin is a high potential side input terminal, −Vin is a low potential side input terminal, + Vout is a high potential side output terminal, and −Vout is a low potential side output terminal. The power supply device 1 performs a switching operation when a reference potential which is a potential of an input terminal of −Vin is applied to the external control terminal (CTL), but a predetermined voltage higher than the reference potential is applied. When switching operation is stopped. That is, the power supply device 1 can be forcibly stopped by applying a predetermined voltage higher than the reference potential to the external control terminal (CTL).

  In the following description, when the voltage value of the signal is equal to the reference potential which is the potential of the input terminal of −Vin is referred to as L level, and when the voltage value of the signal is a predetermined voltage value higher than the reference potential. It is called H level.

  The auxiliary circuit 10 includes an output voltage detection circuit 11, a pulse generation circuit 12, and an AND (logical product) circuit 13. The AND circuit 13 receives the detection signal S1 output from the output voltage detection circuit 11 and the pulse signal S2 output from the pulse generation circuit 12. The AND circuit 13 outputs a control signal S3 based on the detection signal S1 and the pulse signal S2. The control signal S3 is input to the external control terminal (CTL) of the power supply device 1.

  The output voltage detection circuit 11 outputs a detection signal S1 based on the output voltage Vout output from the power supply device 1. The output voltage detection circuit 11 has a detection signal S1 at L level when the output voltage Vout is equal to or higher than a predetermined threshold voltage (Vref), and the detection signal S1 is H when the output voltage Vout is lower than the predetermined threshold voltage (Vref). It is configured to be a level.

  The pulse generation circuit 12 outputs a pulse signal S2 that periodically repeats the transition from the L level to the H level and the transition from the H level to the L level. The period during which the pulse signal S2 is maintained at the L level is longer than the time taken for the power supply device 1 to start up (the time from when the switching operation is started until the output voltage Vout reaches the threshold voltage (Vref)). Is set to be The period during which the pulse signal S2 is maintained at the H level corresponds to the period during which the switching operation of the power supply device 1 is stopped when the power supply device 1 is intermittently operated. Therefore, if the period during which the pulse signal S2 is maintained at the H level is lengthened, the period during which the power supply device 1 stops the switching operation is lengthened.

  The AND circuit 13 is a logic circuit that performs a logical operation of a logical product. The AND circuit 13 outputs the H level only when both of the two input signals are at the H level, and outputs the L level when at least one of the two input signals is at the L level. That is, the control signal S3 output from the AND circuit 13 is at the H level when both the detection signal S1 and the pulse signal S2 are at the H level, and when at least one of the detection signal S1 and the pulse signal S2 is at the L level. Becomes L level.

  Since the control signal S3 is input to the external control terminal (CTL) of the power supply device 1, the control signal S3 is in the H level (period in which both the detection signal S1 and the pulse signal S2 are in the H level), and the power supply The device 1 stops operating. A period in which the detection signal S1 is at an H level corresponds to a period in which the output voltage Vout is less than Vref. Accordingly, when the pulse signal S2 becomes H level during the period when the output voltage Vout is less than Vref, the power supply device 1 stops the switching operation. During the period when the output voltage Vout is less than Vref, when the pulse signal S2 shifts from the H level to the L level, the power supply device 1 is released from the stopped state, and the power supply device 1 starts to start. However, when the output voltage Vout cannot reach a voltage value equal to or higher than Vref within the period in which the pulse signal S2 is at the L level, the pulse signal S2 shifts from the L level to the H level, and the power supply device 1 performs the switching operation again. Stop.

  Next, the operation of the power supply circuit in which the auxiliary circuit according to the present invention is mounted as an external circuit will be described with reference to the timing chart shown in FIG. FIG. 2 shows voltage waveforms of the output voltage Vout, the detection signal S1, the pulse signal S2, and the control signal S3.

<Operation from t0 to t1>
At t0, the power supply device 1 starts up (starts a switching operation). At this time, since the output voltage Vout is less than the threshold voltage (Vref), the detection signal S1 is at the H level. Accordingly, the power supply device 1 starts to start when the pulse signal S2 is at the L level. That is, even if the detection signal S1 is at the H level, if the pulse signal S2 is at the L level, the control signal S3 is at the L level. Therefore, the power supply device 1 is switched during the period in which the pulse signal S2 is at the L level. Start operation.

  When the power supply device 1 starts the switching operation, the output voltage Vout increases, and the output voltage Vout reaches the threshold voltage (Vref) at t1. Then, when the output voltage Vout reaches the threshold voltage (Vref), the detection signal S1 shifts from the H level to the L level. Note that the period T1 in which the pulse signal S2 is maintained at the L level is set to be longer than the time from the start-up until the output voltage Vout reaches the threshold voltage (Vref) (the time from t0 to t1). The Further, this period T1 corresponds to a period during which the power supply device 1 continues to operate in this state when the power supply device 1 enters an overcurrent state. Therefore, it is necessary to set this period T1 within a range that the power supply device 1 can withstand.

<Operation from t1 to t2>
In the period from t1 to t2, since the output voltage Vout is equal to or higher than the threshold voltage (Vref), the detection signal S1 is maintained at the L level. Since the detection signal S1 is maintained at the L level, the control signal S3 is maintained at the L level even when the pulse signal S2 is at the H level. Therefore, the power supply device 1 continues the switching operation.

<Operation from t2 to t3>
The output voltage Vout drops due to a short circuit or the like, and the output voltage Vout becomes less than the threshold voltage (Vref) at t2. When the output voltage Vout becomes less than the threshold voltage (Vref), the detection signal S1 shifts from the L level to the H level. In the period from t2 to t3, since the pulse signal S2 is maintained at the L level, the control signal S3 is maintained at the L level even when the detection signal S1 shifts from the L level to the H level. Continues the switching operation.

<Operation from t3 to t4>
At t3, the pulse signal S2 shifts from the L level to the H level. At this time, since the detection signal S1 is at the H level, the control signal S3 also shifts from the L level to the H level in synchronization with the rise of the pulse signal S2. Since the control signal S3 becomes H level, the power supply device 1 stops the switching operation.

<Operation from t4 to t5>
At t4, the pulse signal S2 shifts from the H level to the L level. At this time, the detection signal S1 is maintained at the H level, but the pulse signal S2 becomes the L level. Therefore, the control signal S3 also shifts from the H level to the L level in synchronization with the falling of the pulse signal S2. Since the control signal S3 becomes L level, the power supply device 1 starts a switching operation.

  However, since the power supply device 1 has not left the state such as a short circuit, the output voltage Vout cannot reach the threshold voltage (Vref) during the period from t4 to t5. Therefore, the detection signal S1 is maintained at the H level.

<Operation from t5 to t6>
At t5, the pulse signal S2 shifts from the L level to the H level. At this time, since the detection signal S1 is maintained at the H level, the control signal S3 also shifts from the L level to the H level in synchronization with the rise of the pulse signal S2. Since the control signal S3 becomes H level, the power supply device 1 stops the switching operation.

<Operation from t6 to t7>
At t6, the pulse signal S2 shifts from the H level to the L level. At this time, the detection signal S1 is maintained at the H level, but the pulse signal S2 becomes the L level. Therefore, the control signal S3 also shifts from the H level to the L level in synchronization with the falling of the pulse signal S2. Since the control signal S3 becomes H level, the power supply device 1 starts a switching operation.

Since the power supply device 1 has escaped from a state such as a short circuit, the output voltage Vout starts to increase, and at t7, the output voltage Vout reaches the threshold voltage (Vref).
When the output voltage Vout reaches the threshold voltage (Vref), the detection signal S1 shifts from the H level to the L level. Since the detection signal S1 shifts from the H level to the L level, the control signal S3 is maintained at the L level even when the pulse signal S2 subsequently changes to the H level.

  As described above, when the output voltage Vout becomes lower than the threshold voltage (Vref) due to a short circuit or the like, the power supply device 1 repeatedly stops and restarts the switching operation. This operation is continued until the state such as a short circuit is removed. Then, in a period T1 in which the pulse signal S2 is maintained at the L level, the power supply device 1 returns to the normal operation when the output voltage Vout can reach the threshold voltage (Vref) in a period T1 where the pulse signal S2 is maintained at the L level.

  FIG. 3 is a block diagram of a power supply circuit according to the second embodiment. In the second embodiment, using the power supply device 1 ′ that stops the switching operation when the control signal input to the external control terminal (CTL) is at the L level and restarts the switching operation when the control signal becomes the H level. Yes. In this case, in the auxiliary circuit 10 ′ corresponding to the auxiliary circuit 10 of FIG. 1, the AND (logical product) circuit 13 is replaced with a NAND (negative logical product) circuit 13. Since the control signal S4 output from the NAND (Negative AND) circuit 13 is a signal obtained by inverting the control signal 3, the power supply circuit according to the second embodiment operates in the same manner as the power supply circuit according to the first embodiment. .

  That is, in FIG. 2, the control signal 3 is simply changed to the control signal S4 that is a signal obtained by inverting the control signal 3, and the period during which the power supply device 1 ′ is performing the switching operation is exactly the same. become. For example, in the period from t0 to t3, since the control signal S4 is at the H level, the power supply device 1 'performs the switching operation. Further, in the period from t3 to t4, the control signal S4 is at the L level, so that the power supply device 1 'stops the switching operation.

  FIG. 4 is a block diagram of a power supply circuit according to the third embodiment. In this power supply circuit, an OR (logical sum) circuit 15 is added so that the power supply device 1 can be forcibly stopped by the external control signal S5.

  The control signal S3 is input to one input terminal of the OR (logical sum) circuit 15, and the external control signal S5 is input to the other input terminal. Then, the logical sum signal S6 output from the OR (logical sum) circuit 15 is input to the external control terminal (CTL) of the power supply device 1.

  The logical sum signal S6 becomes H level when the external control signal S5 is H level regardless of whether the control signal S3 is H level or L level. Therefore, the power supply device 1 can be forcibly stopped by setting the external control signal S5 to the H level.

  FIG. 5 is a block diagram of a power supply circuit according to the fourth embodiment. In this power supply circuit, the output terminals of the power supply device 1 and the power supply device 3 are connected in parallel to the load 2. The control signal S3 is also input to the external control terminal (CTL) of the power supply device 3. In this way, the power supply device 3 can be operated in the same manner as the power supply device 1. That is, when the output voltage Vout drops due to a short circuit or the like, both the power supply device 1 and the power supply device 3 repeatedly stop and restart the switching operation.

  FIG. 6 is a block diagram of a power supply circuit according to the fifth embodiment. In this power supply circuit, the output voltage detection circuit 11 is replaced with a flip-flop circuit 16 and an overcurrent detection circuit 17. The overcurrent detection signal S7 output from the overcurrent detection circuit 17 becomes H level when the output current Iout becomes equal to or higher than a predetermined current value (Iref1). The flip-flop circuit 16 is set in synchronization with the rising edge of the signal input to the set input terminal (S), and is reset in synchronization with the falling edge of the signal input to the reset input terminal (R).

  Since the overcurrent detection signal S7 is input to the set input terminal (S) of the flip-flop circuit 16, when the overcurrent detection signal S7 shifts from the L level to the H level, that is, the output current Iout is equal to or higher than Iref1. The output signal S8 output from the output terminal (Q) of the flip-flop circuit 16 shifts from the L level to the H level. Since the pulse signal S2 is input to the reset input terminal (R) of the flip-flop circuit 16, the output signal S8 is changed from the H level to the L level when the pulse signal S2 shifts from the H level to the L level. Migrate to

  Next, the operation of the power supply circuit according to the present embodiment will be described with reference to the timing chart shown in FIG. FIG. 7 shows voltage waveforms of the output voltage Vout, the output signal S8 output from the flip-flop circuit 16, the pulse signal S2, and the control signal S3. Since the operation during the period from t0 to t2 is the same as that in the first embodiment, the operation during the period from t2 to t7 will be described with reference to the timing chart.

<Operation from t2 to t3>
The output current Iout increases due to a short circuit or the like, and the output current Iout becomes equal to or higher than Iref1 at t2. When the output current Iout becomes Iref1 or more, the overcurrent detection signal S7 shifts from the L level to the H level, and the output signal S8 output from the flip-flop circuit 16 in synchronization with the rising of the overcurrent detection signal S7 Transition from L level to H level. Since the pulse signal S2 is maintained at the L level during the period from t2 to t3, the power supply device 1 continues the switching operation even when the output signal S8 shifts from the L level to the H level.

<Operation from t3 to t4>
At t3, the pulse signal S2 shifts from the L level to the H level. At this time, since the output signal S8 is maintained at the H level, the control signal S3 also shifts from the L level to the H level in synchronization with the rise of the pulse signal S2. Since the control signal S3 becomes H level, the power supply device 1 stops the switching operation.

<Operation from t4 to t5>
At t4, the pulse signal S2 shifts from the H level to the L level, and the output signal S8 also shifts from the H level to the L level in synchronization with the falling of the pulse signal S2. Further, the control signal S3 also shifts from the H level to the L level in synchronization with the falling edge of the pulse signal S2. Since the control signal S3 becomes L level, the power supply device 1 starts a switching operation.

  However, since the power supply device 1 has not left the state such as a short circuit, the overcurrent detection signal S7 shifts from the L level to the H level at t4 ′, and the flip-flop circuit 16 is synchronized with the rising of the overcurrent detection signal S7. The output signal S8 output from L shifts from L level to H level.

<Operation from t5 to t6>
At t5, the pulse signal S2 shifts from the L level to the H level. At this time, since the output signal S8 output from the flip-flop circuit 16 is maintained at the H level, the control signal S3 also shifts from the L level to the H level in synchronization with the rise of the pulse signal S2. Since the control signal S3 becomes H level, the power supply device 1 stops the switching operation.

<Operation from t6 to t7>
At t6, the pulse signal S2 shifts from the H level to the L level, and the output signal S8 also shifts from the H level to the L level in synchronization with the falling of the pulse signal S2. Further, the control signal S3 also shifts from the H level to the L level in synchronization with the falling edge of the pulse signal S2. Since the control signal S3 becomes L level, the power supply device 1 starts a switching operation. Since the power supply device 1 is out of a short circuit state, the output signal S8 output from the flip-flop circuit 16 is maintained at the L level, and the output voltage Vout increases.

  As described above, when the output current Iout becomes equal to or higher than Iref1 due to a short circuit or the like, the power supply device 1 repeatedly stops and restarts the switching operation. This operation is continued until the state such as a short circuit is removed. And when it remove | emits from states, such as a short circuit, the power supply device 1 returns to normal operation | movement.

  FIG. 8 is a block diagram of a power supply circuit according to the sixth embodiment. The power supply circuit of the present embodiment operates in the same manner as in the fifth embodiment, but the overcurrent detection circuit 18 is connected to the input terminal side of the power supply device 1.

  The overcurrent detection signal S9 output from the overcurrent detection circuit 18 becomes H level when the input current Iin becomes equal to or higher than a predetermined current value (Iref2). Since the overcurrent detection signal S9 is input to the set input terminal (S) of the flip-flop circuit 16, when the overcurrent detection signal S9 shifts from the L level to the H level, that is, the input current Iin is equal to or higher than Iref2. The output signal S10 output from the output terminal (Q) of the flip-flop circuit 16 shifts from the L level to the H level. Since the pulse signal S2 is input to the reset input terminal (R) of the flip-flop circuit 16, the output signal S10 is changed from the H level to the L level when the pulse signal S2 shifts from the H level to the L level. Migrate to Since the output signal S10 is the same signal as the output signal S8 of the fifth embodiment, the power supply circuit of the present embodiment operates in the same manner as the fifth embodiment.

  That is, in this power supply circuit, when the input current Iin becomes Iref2 or more due to a short circuit or the like, the power supply device 1 repeatedly stops and restarts the switching operation. This operation is continued until the state such as a short circuit is removed. And when it remove | emits from states, such as a short circuit, the power supply device 1 returns to normal operation | movement.

  Next, an example of the output voltage detection circuit 11 will be described with reference to the drawings. FIG. 9 is a circuit diagram showing an example of the output voltage detection circuit 11. In this circuit, the terminal A is connected to the output terminal (+ Vout) on the high potential side of the power supply device 1, and the terminal B is connected to the output terminal (+ Vout) on the low potential side. Therefore, the output voltage Vout is applied to both ends of the voltage dividing circuit composed of the resistors R3 and R4. A divided voltage, which is a voltage at a connection point between the resistors R3 and R4, is applied to the reference terminal of the shunt regulator 22. The resistance values of the resistors R3 and R4 are set so that the shunt regulator 22 is turned on when the output voltage Vout becomes equal to or higher than the threshold voltage (Vref). When the shunt regulator 22 is turned on, a current flows to the light emitting element (input-side semiconductor element) of the photocoupler 21 via the resistor R2.

  In this circuit, the voltage at the connection point between the output-side terminal of the photocoupler 21 and the resistor R1 corresponds to the detection signal S1. Therefore, when the semiconductor element on the output side of the photocoupler 21 is turned on, the voltage of the output signal S1 becomes the reference potential (L level). When the semiconductor element is turned off, the voltage of the output signal S1 is the operating voltage Vcc (H level). become.

In this example, since the semiconductor element on the output side of the photocoupler 21 is set to be turned on when the output voltage Vout becomes equal to or higher than the threshold voltage (Vref),
When the output voltage Vout becomes equal to or higher than the threshold voltage (Vref), the output signal S1 becomes L level. On the other hand, when the output voltage Vout is less than the threshold voltage (Vref), the output signal S1 becomes H level because the semiconductor element on the output side of the photocoupler 21 is off.

  As described above, the auxiliary circuit of the power supply device according to the present invention includes the pulse generation circuit that outputs a pulse signal that is a signal that alternately repeats the L level and the H level at a constant period, and the output voltage Vout is a threshold voltage ( An output voltage detection circuit that outputs a detection signal that becomes an H level when it becomes less than Vref), and a logic circuit that performs a logical operation using the pulse signal and the detection signal as input signals. The logic circuit may have various configurations, and may be a circuit other than the above embodiment as long as the object of the present invention can be achieved. In addition, the logic circuit may be a circuit configured with a transistor or the like as long as it operates as a logic operation. For example, as shown in FIG. 10, it may be a circuit composed of transistors Q11-14 and resistors R11-13. In this circuit, the terminal X and the terminal Y correspond to the input terminal of the AND (logical product) circuit, and the terminal Z corresponds to the output terminal of the AND (logical product) circuit. The voltage at the terminal Z becomes H level only when both the transistor Q13 and the transistor Q14 are turned off. The transistor Q13 is turned off when the transistor Q11 is turned on, and the transistor Q14 is turned off when the transistor Q12 is turned on. Therefore, the voltage at the terminal Z becomes H level only when the H level is applied to both the terminal X and the terminal Y.

  Even if the output voltage detection circuit is a circuit that outputs a detection signal that becomes L level when the output voltage Vout becomes less than the threshold voltage (Vref), the object of the present invention can be achieved by changing the logic circuit. Can be achieved.

  In the above embodiment, in the period when the output voltage Vout is less than the threshold voltage (Vref), the power supply device is operated if the pulse signal is L level, and the operation of the power supply device is performed if the pulse signal is H level. However, if the pulse signal is at the H level, the power supply device may be operated, and if the pulse signal is at the L level, the operation of the power supply device may be stopped.

  An overcurrent detection circuit that detects that the output current Iout has exceeded a predetermined current value (Iref1) or that the input current Iin has exceeded a predetermined current value (Iref2), and an overcurrent detection circuit are provided. If a pulse output circuit that outputs a pulse in synchronization with the detection of such an overcurrent state is used instead of the output voltage detection circuit, the same operation can be performed even when an overcurrent state occurs. The overcurrent detection circuit may be any circuit that outputs a signal that shifts to H level when an overcurrent state is detected or a signal that shifts to L level when an overcurrent state is detected. The pulse output circuit outputs a pulse that rises in synchronization with the detection of such an overcurrent state or a pulse that falls in synchronization with the detection of such an overcurrent state. Any circuit such as a flip-flop circuit or a latch circuit may be used.

DESCRIPTION OF SYMBOLS 1 Power supply device 2 Load 11 Output voltage detection circuit 12 Pulse generation circuit 13 AND (logical product) circuit 14 NAND (logical product) circuit 15 OR (logical product) circuit 16 Flip-flop circuit 17 Overcurrent detection circuit 18 Overcurrent detection circuit

Claims (3)

An auxiliary circuit of a power supply device externally attached to a power supply device having a function of stopping operation based on a signal input to an external control terminal,
A pulse generation circuit for alternately outputting a first voltage and a second voltage having a voltage value higher than the first voltage at a constant period;
An output voltage detection circuit that compares an output voltage of the power supply device with a predetermined threshold voltage, and outputs the first voltage or the second voltage based on a result of the comparison;
A logic circuit that performs a logical operation using the output of the pulse generation circuit as a first input signal and the output of the output voltage detection circuit as a second input signal, and generates a control signal to be supplied to the power supply device;
The logic circuit can stop the operation of the power supply device by the control signal when the voltage value of the first input signal and the voltage value of the second input signal have a predetermined combination. is configured to,
If the logic circuit is configured such that the power supply device stops operating while the signal output from the pulse generation circuit is maintained at the first voltage, the signal is output from the pulse generation circuit. The period during which the signal is maintained at the second voltage is longer than the time taken for the power supply device to start, and the signal output from the pulse generation circuit is maintained at the second voltage. When the logic circuit is configured such that the operation of the power supply device is stopped during the period, the power supply device is activated during a period in which the signal output from the pulse generation circuit is maintained at the first voltage. A power supply auxiliary circuit that is longer than the time it takes to do.
An auxiliary circuit of a power supply device externally attached to a power supply device having a function of stopping operation based on a signal input to an external control terminal,
A pulse generation circuit for alternately outputting a first voltage and a second voltage having a voltage value higher than the first voltage at a constant period;
The input current of the power supply apparatus is compared with a predetermined first current value, or the output current of the power supply apparatus is compared with a predetermined second current value, and the first current value is compared based on the comparison result. An output voltage detection circuit for outputting a voltage or the second voltage;
A pulse output circuit in which the voltage value of the output signal shifts to the first voltage or the second voltage in synchronization with the rise or fall of the signal output from the output voltage detection circuit;
A logic circuit that performs a logical operation using the output of the pulse generation circuit as a first input signal and the output of the pulse output circuit as a third input signal to generate a control signal to be supplied to the power supply device;
The logic circuit can stop the operation of the power supply device by the control signal when the voltage value of the first input signal and the voltage value of the third input signal have a predetermined combination. is configured to,
If the logic circuit is configured such that the power supply device stops operating while the signal output from the pulse generation circuit is maintained at the first voltage, the signal is output from the pulse generation circuit. The period during which the signal is maintained at the second voltage is longer than the time taken for the power supply device to start, and the signal output from the pulse generation circuit is maintained at the second voltage. When the logic circuit is configured such that the operation of the power supply device is stopped during the period, the power supply device is activated during a period in which the signal output from the pulse generation circuit is maintained at the first voltage. A power supply auxiliary circuit that is longer than the time it takes to do. Auxiliary circuit and a power supply circuit with a power supply of a power supply device according to claim 1 or 2.