JP6151976B2 - Recording / reproducing apparatus and control method - Google Patents

Description

  The present invention relates to a recording / reproducing apparatus and a control method, and more particularly to a timing control technique related to data writing / reading on a recording medium.

  2. Description of the Related Art Conventionally, there are apparatuses that write image data, audio data, or the like on a recording medium such as a memory card, or read and reproduce data recorded on a recording medium. Reading and writing data between the recording medium connected to such a recording medium (host device) and the recording medium is performed in accordance with a clock signal generated by the host apparatus. In response to data read / write and command, one clock pulse of a clock signal is transmitted, and then data to be written or read is transmitted / received or a response is received. For this reason, the clock pulse and the data and response are not transmitted and received at completely synchronized timing. For example, when data is read from an SD memory card, there is a delay of a standardized fixed value from the time when a clock pulse is given to the card from the host device until the data is transmitted. Therefore, the host device acquires the data transmitted from the recording medium by latching the data transmitted from the recording medium after being delayed by a fixed value from the transmission of the clock pulse.

  On the other hand, in recent years, with an increase in the read / write data rate for such a recording medium, it is necessary to speed up the transmission of the clock pulse, and the delay amount from the clock pulse for data acquisition can be specified as a fixed value. It has become difficult. In contrast, in UHS-I (Ultra High Speed), which is a high-speed standard for SD memory cards, when data is read using a high-speed clock, data read is performed after adjusting the timing of data latch for each card. It is prescribed to do. The operation of adjusting the latch timing is called tuning (see, for example, Patent Document 1).

JP 2010-157058 A

  The processing related to the tuning of the recording medium is generally performed when the host apparatus is started up or when the recording medium is recognized by the host apparatus. However, since the amount of delay from the clock pulse can vary depending on external factors such as the temperature of the recording medium, tuning at the time of start-up or medium recognition may not be effective. That is, even if tuning is performed at the time of startup or medium recognition, there is a possibility that data read / write may fail due to a variation in the delay amount due to an external factor.

  Therefore, a method of performing tuning again at a timing other than at the time of starting or checking the medium can be considered. However, since data cannot be written or read during the tuning process, excessively performing the process related to tuning may adversely reduce the data writing / reading efficiency.

  The present invention has been made in view of the above-described problems, and provides a recording / reproducing apparatus and a control method that prevent performance degradation due to unnecessary tuning processing while ensuring the reliability of data read from a recording medium. With the goal.

In order to achieve the above object, a recording / reproducing apparatus of the present invention is characterized by having the following configuration. Specifically, the recording / reproducing apparatus outputs an output means for outputting a clock signal to the recording medium, and sends a command to the recording medium, and in accordance with a timing signal obtained by delaying the clock signal, Communication means for acquiring data transmitted from the recording medium, and in response to an access request to the recording medium, the communication means is controlled to output an output command of predetermined data having a predetermined data string to the recording medium. the data obtained by the transmission has been communicating means from the recording medium have a control means for processing to ensure that it has a predetermined data sequence in response to an output instruction, the control unit has been acquired If the data has a predetermined data string, the command corresponding to the access request is transmitted to the recording medium without executing the phase adjustment process of the timing signal. When the acquired data does not have a predetermined data string, the timing signal phase adjustment processing is executed, and the timing signal phase adjustment processing is executed, and then an instruction corresponding to the access request is executed. The communication means is controlled to transmit to the recording medium .

  With this configuration, according to the present invention, it is possible to prevent performance degradation due to unnecessary tuning processing while ensuring the reliability of data read from the recording medium.

1 is a block diagram showing a functional configuration of a digital camera 100 according to an embodiment of the present invention. The block diagram which showed the internal structure of the memory card controller 113 which concerns on embodiment of this invention. The flowchart which illustrated the tuning process performed in the digital camera 100 which concerns on embodiment of this invention. The figure for demonstrating the determination method of the delay stage number by the tuning process which concerns on embodiment of this invention The flowchart which illustrated the delay check process performed in the digital camera 100 which concerns on Embodiment 1 of this invention. The figure for demonstrating the operation | movement by the delay check process which concerns on Embodiment 1 of this invention. The flowchart which illustrated the delay check process performed in the digital camera 100 which concerns on Embodiment 2 of this invention. The figure which illustrated the pattern used for judgment of a reception result in the delay check processing concerning Embodiment 2 of the present invention.

[Embodiment 1]
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the drawings. In the following embodiment, an example in which the present invention is applied to a digital camera capable of writing / reading data to / from a connected memory card as an example of a recording / reproducing apparatus will be described. However, the present invention can be applied to any device (host device) capable of writing / reading data to / from a recording medium.

<< Configuration of Digital Camera 100 >>
FIG. 1 is a block diagram showing a functional configuration of a digital camera 100 according to an embodiment of the present invention.

  The main microcomputer 118 is a CPU, for example. The main microcomputer 118 controls the operation of each block included in the digital camera 100. Specifically, the main microcomputer 118 controls the operation of each block by reading a program stored in the ROM 119 for executing various sequences to be described later for each block, developing the program in the SDRAM 116, and executing the program. The main microcomputer 118 also controls display of the liquid crystal panel 111 by controlling a liquid crystal driver 112 described later.

  The ROM 119 is a non-volatile memory that can electrically erase and record data, for example. The ROM 119 stores not only an operation program for each block of the digital camera 100 but also information such as constants necessary for the operation of each block.

  The image sensor 103 is, for example, a CCD or a CMOS sensor. The image sensor 103 photoelectrically converts a subject image formed on the imaging surface by the photographing lens 101 and outputs an analog image signal. The amount of light of the subject image formed by the photographing lens 101 is limited by controlling the opening amount of the diaphragm 102 by the main microcomputer 118. The analog image signal output from the image sensor 103 is converted into digital image data by applying A / D conversion processing by the A / D converter 104. The obtained image data is stored as uncompressed image data in the frame memory 106 after the processing relating to gamma correction, white balance correction, and noise reduction is applied in the image processing unit 105. The imaging lens 101, the aperture 102, the imaging element 103, the A / D converter 104, the image processing unit 105, and the frame memory 106 constitute an imaging unit of the digital camera 100 according to the present embodiment.

  The JPEG encoding unit 108 compresses and encodes uncompressed image data according to an encoding format (JPEG format) when the digital camera 100 of the present embodiment records a still image, and generates JPEG still image data. The MPEG encoding unit 109 generates MPEG moving image data by compressing and encoding uncompressed image data as frames in accordance with the moving image encoding format (MPEG format) when the digital camera 100 of the present embodiment records moving images. To do. Various data generated by the JPEG encoding unit 108 and the MPEG encoding unit 109 are temporarily written in the SDRAM 116 via the data bus 107.

  The SDRAM 116 is a volatile memory. The SDRAM 116 stores image data converted for display on the liquid crystal panel 111 in addition to the data generated by the JPEG encoding unit 108 and the MPEG encoding unit 109. In addition, the SDRAM 116 is used as a buffer memory space for data reading according to the writing status and mediation of the recording speed with the memory card 115 when writing data to the memory card 115.

  The liquid crystal panel 111 is a display device included in the digital camera 100 such as an LCD. As described above, the display control of the liquid crystal panel 111 is performed by the main microcomputer 118. Specifically, the liquid crystal driver 112 that has received a command from the main microcomputer 118 converts display image data stored in the SDRAM 116 into a liquid crystal display signal and outputs the liquid crystal display signal to the liquid crystal panel 111, thereby performing display control. Is called. The liquid crystal panel 111 functions as an electronic viewfinder by converting the non-compressed image data, which has been changed to the number of display pixels of the liquid crystal panel 111 by the pixel number conversion circuit 110, into a liquid crystal display signal and inputting it (through display). ).

  The memory card 115 is a recording medium capable of writing / reading data by being detachably connected to the digital camera 100. In this embodiment, the memory card 115 is a memory card composed of a NAND flash memory, and data is managed in a format conforming to a FAT (File Allocation Table) file system having PC compatibility. The memory card 115 is connected to the digital camera 100 via the card slot 114. The card slot 114 has a card detection switch, and outputs a detection signal to the main microcomputer 118 when it is detected that the memory card 115 is inserted into the card slot 114.

  Communication such as data writing to the memory card 115 and data reading from the memory card 115 is performed by the memory card controller 113. The memory card controller 113 reads data for recording from the SDRAM 116 and writes the data to the memory card 115 when writing data. The memory card controller 113 reads data from the memory card 115 and stores it in the SDRAM 116 at the time of reading data.

<Configuration of Memory Card Controller 113>
Here, the detailed configuration of the memory card controller 113 of the present embodiment will be described in detail with reference to FIG.

  The memory card controller 113 transmits and receives signals and data through the CLK line, the CMD line, and the DAT line in writing and reading data to and from the memory card 115. Specifically, the clock source 201 outputs a clock signal (CLK signal) composed of clock pulses used for read / write timing control via the CLK line. The host controller 202 outputs a command signal related to reading and writing and receives a response signal for the command from the memory card 115 via the CMD line. The host controller 202 performs control to transmit / receive data to be written to the memory card 115 or data read from the memory card 115 via the DAT line.

  In reading and writing data, the timing of transmission and reception of clock pulses and data is different as described above. For this reason, the delay element 203 delays the phase of the clock signal in accordance with the control of the main microcomputer 118 when reading data from the memory card 115, for example, and generates a timing signal for latching the data output from the memory card 115. The flip-flop 204 latches the data output from the memory card 115 in accordance with the timing signal output from the delay element 203. The signal branching unit 205 switches between the CMD line and the DAT line according to command input / output and data transmission / reception.

  Further, the internal configuration of the delay element 203 will be described with reference to FIG. The delay element 203 includes a predetermined number of delay circuits 206 and a selector 207 that selects one of the outputs from each delay circuit 206. The delay element 203 of the present embodiment will be described as having 15 delay circuits 206 and the number of delay stages being changeable to 16. Each delay circuit 206 delays the clock signal output from the clock source 201 or the clock signal output from the immediately preceding delay circuit 206 by a predetermined time. In the present embodiment, the delay amount in each delay circuit 206 is 1/16 of the clock pulse period output from the clock source 201, and the delay is performed in all the delay circuits 206, so that the clock pulse is 1 Assume that the amount of delay is equal to the period. The selector 207 outputs a clock signal output from either the clock source 201 or each delay circuit 206 as an operation clock (latch clock) of the flip-flop 204 in accordance with an instruction from the main microcomputer 118. As described above, by changing the clock signal selected by the selector 207, the delay amount of the operation clock of the flip-flop 204 can be adjusted.

  In addition, the digital camera 100 according to the present embodiment includes an operation input unit 117. The operation input unit 117 is a user interface provided in the digital camera 100. When various operation keys provided on the digital camera 100 are operated by the user, the operation input unit 117 receives a signal output by the operation and outputs a control signal corresponding to the operation to the main microcomputer 118.

<Operation overview>
Hereinafter, the outline of the operation of each block of the digital camera 100 of the present embodiment will be described first.

  When the digital camera 100 is activated in the moving image shooting mode, the main microcomputer 118 controls each block in a standby state for moving image shooting. Specifically, the main microcomputer 118 drives the imaging unit to start the imaging operation, displays the sequentially obtained image data on the liquid crystal panel 111, and sets the through display state.

  When the control signal corresponding to the shooting start instruction is received from the operation input unit 117 in the shooting standby state, the main microcomputer 118 controls the MPEG encoding unit 109 to start encoding processing of uncompressed image data. Then, the data related to the moving image data generated by the encoding process is sequentially stored in the SDRAM 116. The main microcomputer 118 monitors whether or not the amount of moving image data stored in the SDRAM 116 has reached a threshold value for starting writing to the memory card 115, and starts writing processing when it reaches.

  In response to a write instruction from the main microcomputer 118, the memory card controller 113 reads moving image data from the SDRAM 116 and writes it to the memory card 115 via the card slot 114. At this time, the host controller 202 of the memory card controller 113 repeatedly issues a write command to the memory card 115. Thereby, the moving image data is read from the SDRAM 116 by a predetermined amount and written to the memory card 115.

  In the present embodiment, it is assumed that the data rate that can be written to the memory card 115 is higher than the data rate when moving image data encoded by the MPEG encoding unit 109 is stored in the frame memory 106. In this case, when the writing process by the memory card controller 113 is started, the amount of unrecorded moving image data stored in the SDRAM 116 gradually decreases. When the main microcomputer 118 detects that the data amount of the moving image data stored in the SDRAM 116 has decreased to a predetermined value after the writing by the memory card controller 113 is started, the main microcomputer 118 stops the writing process by the memory card controller 113. . When the amount of moving image data stored in the SDRAM 116 reaches a threshold value for starting the writing process, the main microcomputer 118 causes the memory card controller 113 to start writing to the memory card 115 again.

  As described above, after an instruction to start capturing moving image data is given, the memory card controller 113 writes the moving image data to the memory card 115 intermittently.

  Further, when the control signal corresponding to the instruction to stop shooting, that is, the recording stop is received from the operation input unit 117 during shooting, the main microcomputer 118 stops the encoding process by the MPEG encoding unit 109. The main microcomputer 118 causes the memory card controller 113 to write the unrecorded moving image data remaining in the SDRAM 116 to the memory card 115 and then stops the recording process to the memory card 115.

  When the control signal corresponding to the still image recording instruction is received from the operation input unit 117 in the shooting standby state, the main microcomputer 118 causes the imaging unit to output uncompressed image data for one screen corresponding to the still image recording instruction. The main microcomputer 118 causes the JPEG encoding unit 108 to encode the uncompressed image data, and stores the obtained still image data in the SDRAM 116. The memory card controller 113 performs a process of writing still image data stored in the SDRAM 116 to the memory card 115 under the control of the main microcomputer 118.

《Tuning process》
Hereinafter, the details of the tuning process, which is the process for adjusting the number of delay stages, executed in the digital camera 100 of the present embodiment having the above-described configuration will be described with reference to the flowchart of FIG. This tuning process is performed, for example, after the memory card 115 is connected to the digital camera 100 until a recording process start instruction is issued, or after the digital camera 100 is activated until a recording process start instruction is issued. It will be described as being executed. Note that during execution of the tuning process, the main microcomputer 118 does not execute the recording process even if an instruction to start the recording process is given. In the tuning process, the main microcomputer 118 controls the memory card controller 113 to execute a process corresponding to each block of the memory card controller 113. For this reason, the main microcomputer 118 will be described as being able to refer to data and the like acquired in the processing in the memory card controller 113.

  In S301, the main microcomputer 118 causes the clock source 201 of the memory card controller 113 to start transmitting a clock signal. The main microcomputer 118 sets the number of delay stages (16 stages) of the clock signal in the delay element 203 to “1”.

  In step S302, the host controller 202 issues a test data transmission command for causing the memory card 115 to transmit test data to the memory card 115 and transmits the test data via the CMD line. The test data is a 64-byte data string having a predetermined pattern, and the memory card 115 transmits the data string in synchronization with the received clock signal.

  In S303, the flip-flop 204 latches the data received from the memory card 115 via the DAT line at the latch timing supplied by the delay element 203. The latch timing supplied by the delay element 203 is generated by the delay element 203 delaying the clock signal according to the currently set number of delay stages.

  In S304, the main microcomputer 118 determines whether or not the data string received by the flip-flop 204 matches a predetermined pattern (the pattern of the data string returned by the memory card 115). If the main microcomputer 118 determines that the received data string matches a predetermined pattern, the process proceeds to S305. If the main microcomputer 118 determines that the received data string does not match, the process proceeds to S306.

  In step S <b> 305, the main microcomputer 118 records information on successful reception in association with the current number of delay stages in the reception result table stored in the SDRAM 116, for example. On the other hand, if the main microcomputer 118 determines that the received data string does not match the predetermined pattern in S304, the main microcomputer 118 records information on reception failure in the reception result table in association with the current number of delay stages in S306.

  In S307, the main microcomputer 118 determines whether or not the number of delay stages set in the delay element 203 is the maximum number of delay stages (16 in this embodiment). When the main microcomputer 118 determines that the number of delay stages set in the delay element 203 is not the maximum number of delay stages, the main microcomputer 118 sets the number of delay stages one level higher in the delay element 203 in S308, and returns the process to S302. If the main microcomputer 118 determines that the number of delay stages set in the delay element 203 is the maximum number of delay stages, the process proceeds to S309.

  In step S309, the main microcomputer 118 refers to the reception result table stored in the SDRAM 116, determines the optimum delay stage number, sets the stage number in the delay element 203, and completes the tuning process. A reception result table as shown in FIG. 4 is obtained by the processing of S301 to S308, for example. In this step, the main microcomputer 118 determines the center of the range of the number of delay stages successfully received as the optimum number of delay stages. In the example of FIG. 4, the number of delay stages 5 to 16 and 1 after one period indicate the number of delay stages (phases) successfully received, so the median of 11 is determined as the optimum delay stage number.

  In this way, the delay stage number of the delay element 203 can be set so that the delay element 203 of the memory card controller 113 can output the optimum latch timing to the flip-flop 204 by executing the tuning process. That is, under the control of the main microcomputer 118, the host controller 202 outputs the test data output command a plurality of times with different delay stage numbers, so that the optimum data is obtained based on the output data obtained for each delay stage number. It is possible to set the number of delay stages.

《Delay check processing》
By the way, although the optimum delay stage number can be temporarily set by executing the tuning process as described above, the delay amount by the delay element varies depending on factors such as temperature as described above. That is, the set optimum number of delay stages may not be optimum due to a temperature change, or may be a stage number that may cause a data reception error. For this reason, in the digital camera 100 of the present embodiment, a delay check process for checking the validity of the latch clock is performed during the recording process of still image data or moving image data.

  Hereinafter, the delay check process executed in the digital camera 100 of the present embodiment will be described in detail using the flowchart of FIG. The delay check process will be described as being started when a data write start request to the memory card 115 is made in the upper layer program.

  In step S <b> 501, the main microcomputer 118 determines whether or not a condition for executing the validity check of the phase (delay amount) delayed by the data write start request made is satisfied. In the present embodiment, it is assumed that the check processing after S502 is executed when a data write start request is made, but the condition for executing the check is not limited to this. The conditions for executing the check are, for example, when the time elapsed since the previous check execution has reached a predetermined time, when the write start request is made a predetermined number of times, or when the amount of data to be written is a predetermined amount or more You may set about a case etc. If the main microcomputer 118 determines that the data write start request made corresponds to the condition for executing the check, the process proceeds to S502. If the main microcomputer 118 determines that the request does not correspond, the process proceeds to S506.

  In step S502, the host controller 202 issues a test data transmission command to the memory card 115 and transmits the command via the CMD line.

  In S503, the flip-flop 204 latches the data received from the memory card 115 via the DAT line at the latch timing supplied by the delay element 203. The latch timing supplied by the delay element 203 is generated by the delay element 203 delaying the clock signal in accordance with the number of delay stages set in the tuning process described above.

  In step S504, the main microcomputer 118 determines whether or not the data string received by the flip-flop 204 matches a predetermined pattern. If the main microcomputer 118 determines that the received data string matches a predetermined pattern, the process proceeds to S506. If the main microcomputer 118 determines that the received data string does not match, the process proceeds to S505.

  In step S <b> 505, the main microcomputer 118 executes the tuning process again and sets an optimal number of delay stages.

  In S506, the memory card controller 113 sends out the data write request received in S501 in accordance with the clock signal, and executes a recording process related to data writing.

  In this way, in the digital camera 100 of the present embodiment, the validity of the latch timing is checked not only when the memory card is mounted or when the digital camera 100 is activated, but also during the recording process on the memory card 115. be able to. That is, even when the delay amount of the clock signal that can be suitably latched changes due to an external factor such as a temperature change in the memory card controller 113, the delay amount can be set again.

  For example, as shown in FIG. 6, the memory card controller 113 is set to start writing to the memory card 115 when the data to be recorded stored in the SDRAM 116 exceeds 16 megabytes (MB). Think about the case.

  The main microcomputer 118 transmits a test data transmission command to the memory card controller 113 at a timing when unrecorded data stored in the SDRAM 116 exceeds 16 MB. The memory card controller 113 issues a test data transmission command to the memory card 115, receives pattern data from the memory card 115, and sends it to the main microcomputer 118. The main microcomputer 118 determines whether or not the received data string matches the test pattern. As a result of determination, when the received data string matches the test pattern, the main microcomputer 118 issues a write command to the memory card controller. In response to a write command from the main microcomputer 118, the memory card controller 113 reads unrecorded data from the SDRAM 116 and starts writing to the memory card 115. Thereafter, the data amount of data accumulated in the SDRAM 116 due to data writing gradually decreases to below 16 MB, but the unrecorded data amount starts to increase with the completion of the 16 MB data writing. Thereafter, since the data write start request is made again at the timing when the data amount exceeds 16 MB, the memory card controller 113 starts writing data again. That is, since the data write start request is intermittently made according to the data amount of unrecorded data stored in the SDRAM 116, the digital camera 100 of this embodiment can intermittently check the effectiveness of the delay amount. .

  In the present embodiment, the delay check process is performed when a data write start request to the memory card 115 is made. However, the validity of the delay amount is checked when a data read request is made. May be. That is, the delay check process may be executed when an access request to the memory card 115 is made. Note that the check execution condition may be set for the elapsed time from the previous request, the number of requests, or the read data amount in the data read, as described above for the data write. In addition, the main microcomputer 118 has a counter for accumulating the amount of access data by the access request, and checks when the access request is made for the first time after a predetermined amount of data has been accessed since the previous check by receiving the test pattern. It may be configured to execute. In addition, after the mode such as the shooting mode and the playback mode set in the digital camera 100 is switched, a check may be performed when an access request is first made. That is, by changing the conditions, it is possible to avoid excessively performing a check by receiving a test pattern when, for example, an access to repeatedly write data with a small data size continues.

  As described above, the recording / reproducing apparatus of the present embodiment can prevent performance degradation due to unnecessary tuning processing while ensuring the reliability of data read from the recording medium. Specifically, the recording / reproducing apparatus outputs the clock signal to the recording medium and acquires the data transmitted from the recording medium according to the timing signal obtained by delaying the clock signal. The recording / reproducing apparatus controls to output an output command of predetermined data having a predetermined data string to the recording medium in response to an access request to the recording medium. At this time, the recording / reproducing apparatus confirms that the data transmitted and acquired from the recording medium according to the output command of the predetermined data has a predetermined data string.

[Embodiment 2]
In the first embodiment, when the access request to the memory card 115 is made, the validity of the delay amount due to the reception of the test data is checked, and if there is a test data reception error as a result of the check, execution of retuning is decided. Explained as what to do. In the present embodiment, a method for determining whether or not to execute the tuning process after determining the reliability of the check result will be described.

  Note that the digital camera 100 of the present embodiment has the same configuration as the digital camera 100 of the first embodiment described above, and a detailed description of the functional configuration thereof is omitted. In the following description, steps that perform the same processing as the tuning processing or delay check processing of the first embodiment described above are denoted by the same reference numerals and description thereof is omitted.

《Delay check processing》
Hereinafter, the delay check process executed in the digital camera 100 of the present embodiment will be described in detail using the flowchart of FIG. The delay check process will be described as being started when a data write start request to the memory card 115 is made in the upper layer program as in the first embodiment.

  If it is determined in S501 that the data write start request corresponds to the condition for executing the check, the main microcomputer 118 substitutes 0 for a variable N indicating the number of times test data is transmitted in S701, and the process proceeds to S502.

  When the host controller 202 latches the received data in S503, the main microcomputer 118 determines in S702 whether the received data string matches a predetermined pattern. The main microcomputer 118 stores information on the determination result (reception success / failure) in the reception result determination table stored in the SDRAM 116 in association with the number of delay stages currently set in the delay element 203.

  In S703, the main microcomputer 118 increments the variable N by 1. In step S704, it is determined whether the variable N is 1. When determining that the variable N is 1, the main microcomputer 118 sets a delay stage number one step lower than the delay stage number set in the delay element 203 at the start of the delay check process in S705 to the delay element 203. To S502. If the main microcomputer 118 determines that the variable N is not 1, the process proceeds to S706.

  In step S <b> 706, the main microcomputer 118 determines whether the variable N is 2. When determining that the variable N is 2, the main microcomputer 118 sets a delay stage number one step higher than the delay stage number set in the delay element 203 at the start of the delay check process in S707 to the delay element 203. To S502. If the main microcomputer 118 determines that the variable N is not 2, the process proceeds to S708.

  As described above, in the delay check process of this embodiment, not only the number of delay stages set in the delay element 203 at the start of the delay check process but also the validity check of the delay amount by the reception of the test data for the number of stages before and after that. I do. In this embodiment, the number of delay stages of one stage before and after is set as a check target, but the implementation of the present invention is not limited to this. That is, the range of the number of delay stages set as a check target may be wider than one stage before and after. That is, the processing of S701 to S707 is processing for determining whether or not the tuning process is re-executed, and is therefore executed for a plurality of delay stages included in a narrower range than the range of delay stages (all ranges) set in the tuning process. Efficiency is achieved. In addition, the delay stage number that is continuous with the delay stage number set at the start of the delay check process may not be set as the check target. For example, even if the number of boundary value stages (in the example of FIG. 4, the number of delay stages 5 and 1) associated with the information on successful reception in the reception result table generated in the last executed tuning process is selected as the check target. Good.

  In step S708, the main microcomputer 118 refers to the reception result determination table stored in the SDRAM 116, and determines which of the patterns 1 to 8 shown in FIG. 8 corresponds to the reception results for the three types of delay stages.

  Pattern 1 is a state in which the test data can be correctly received in all of the three types of delay stages that have been checked. Therefore, data can be read out without any problem with the number of delay stages set in the delay element 203 at the start of the delay check process. It can be judged that it is possible. Therefore, the main microcomputer 118 shifts the process to S506 in a state where the delay stage number set at the start of the delay check process is set in the delay element 203, and executes a recording process related to data writing.

  On the other hand, patterns 2 and 3 or patterns 4 and 5 are states in which a test data reception error has occurred in any of the number of stages before and after the number of delay stages set at the start of the delay check process. In other words, even if the test data can be received correctly for the number of delay stages set at the start, the delay amount may become ineffective due to an external factor such as a temperature change during data writing. ing. For this reason, when the reception results for the three types of delay stages correspond to the above four patterns, the main microcomputer 118 sets the number of delay stages indicating the result of successful reception among the preceding and following stages to a new delay stage number. Specifically, when the reception result for the three types of delay stages is one of patterns 2 and 3, the main microcomputer 118 sets a stage number that is one step higher than the delay stage number set at the start of the delay check process in S709. The delay element 203 is set, and the process proceeds to S506. When the reception result is any one of patterns 4 and 5, the main microcomputer 118 sets the number of stages one step lower than the number of delay stages set at the start of the delay check process in S710 to the delay element 203, and performs the process in S506. Move to.

  Furthermore, patterns 6 to 8 indicate a state in which the reception results of the test data for the three types of delay stages are low in reliability. Specifically, in pattern 6, although a reception error has occurred with respect to the number of delay stages set at the start of the delay check process, no reception error has occurred with respect to the number of stages in the preceding and following stages. In pattern 7, although the test data can be correctly received for the number of delay stages set at the start, a reception error has occurred for the number of stages of one stage before and after. In pattern 8, reception errors occur for all three types of delay stages. If such a low-reliability result is obtained, the suitable number of delay stages cannot be easily estimated. Therefore, the main microcomputer 118 executes the tuning process again in S505 and sets the optimum number of delay stages. After that, the process proceeds to S506.

  In this way, although the processing time required for the delay amount validity check process using the test data increases, the frequency of executing the tuning process for performing the detailed validity check for all stages can be reduced. it can. In addition, since the effectiveness sampling is performed for a predetermined delay amount, a suitable delay amount can be simply estimated from the tendency.

[Other Embodiments]
The present invention can also be realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various storage media, and a computer (or CPU, MPU, or the like) of the system or apparatus reads the program. It is a process to be executed.

Claims (8)

An output means for outputting a clock signal to the recording medium;
A communication means for transmitting data to the recording medium and acquiring data transmitted from the recording medium according to a timing signal obtained by delaying the clock signal;
In response to an access request to the recording medium, the communication means is controlled to output a predetermined data output command having a predetermined data string to the recording medium, and the recording is performed in accordance with the predetermined data output command. have a control means for performing a process of confirming that the acquired data has a predetermined data sequence by said communication means is transmitted from the medium,
When the acquired data has the predetermined data string, the control means transmits a command corresponding to the access request to the recording medium without executing a phase adjustment process of the timing signal. The communication means is controlled so that when the acquired data does not have the predetermined data string, the timing signal phase adjustment processing is executed, and the timing signal phase adjustment processing is executed. After that, the recording / reproducing apparatus controls the communication means to transmit a command corresponding to the access request to the recording medium .   The control means controls the communication means to output an output command of the predetermined data to the recording medium when a predetermined condition is met when an access request to the recording medium is received, and the confirmation The recording / reproducing apparatus according to claim 1, wherein the processing is performed.   In response to the access request, the control unit transmits the predetermined data output command to the recording medium before the communication unit transmits the command corresponding to the access request to the recording medium. The recording / reproducing apparatus according to claim 1, wherein a communication unit is controlled to perform the confirmation process. In the adjustment process, the control means outputs the output command of the predetermined data a plurality of times, and transmits the data transmitted from the recording medium to each of the output commands of the plurality of times with the different delay amounts. And delaying the timing signal based on data acquired in accordance with the timing signal delayed by the different delay amount, controlling the communication means to acquire in accordance with the timing signal obtained by delaying The recording / reproducing apparatus according to claim 1 , wherein an amount is set.   The control means outputs the predetermined data output command a plurality of times in response to an access request to the recording medium, and the data transmitted from the recording medium for each of the plurality of output commands The communication means is controlled to acquire in accordance with a timing signal of delay amount and a timing signal in which the delay amount is changed before and after the current delay amount, and the acquired data is respectively the predetermined data 2. The recording / reproducing apparatus according to claim 1, wherein the recording / reproducing apparatus is confirmed to have a column. The control means determines the delay amount of the timing signal according to the timing signal of the current delay amount and the result of the confirmation process of the data acquired according to the timing signal with the delay amount varied. 6. The recording / reproducing apparatus according to claim 5 , wherein the recording / reproducing apparatus is set. The access request, the data write request to the recording medium or the recording and reproducing apparatus according to any one of claims 1 to 6, characterized in that it comprises a data read request from the recording medium. An output step of outputting a clock signal to the recording medium;
A communication step of transmitting data to the recording medium and acquiring data transmitted from the recording medium in accordance with a timing signal obtained by delaying the clock signal;
In response to an access request to the recording medium, the operation of the communication process is controlled to output a predetermined data output command having a predetermined data string to the recording medium, and according to the predetermined data output command have a control step of performing processing to verify that the data acquired in the communication process is transmitted from the recording medium has a predetermined data sequence,
In the control step, when the acquired data has the predetermined data string, an instruction corresponding to the access request is transmitted to the recording medium without executing a phase adjustment process of the timing signal. If the operation of the communication process is controlled and the acquired data does not have the predetermined data string, the timing signal phase adjustment process is executed, and the timing signal phase adjustment process is performed. the method of the after run, the operation of the communication process is controlled command corresponding to the access request to be sent to said recording medium recording and reproducing apparatus according to claim Rukoto.

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