JP2016046781A - Recording and reproducing device, control method for recording and reproducing device, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a tuning period by eliminating the need to wait test pattern reception in all latch timing.SOLUTION: A recording and reproducing device includes: communication means which transmits an instruction to a recording medium and receives data transmitted from the recording medium in response to a timing signal obtained by delaying a clock signal; and control means which controls the communication means in such a manner that a first instruction to transmit pattern data for adjusting a delay amount of the timing signal and a second instruction to transmit shorter data are transmitted to the recording medium, and adjusts the delay amount of the timing signal on the basis of whether the pattern data received by the communication means in response to the timing signal have a predetermined data stream. In the case where the communication means cannot rightly receive data transmitted from the recording medium in accordance with the second instruction, the control means controls the communication means in such a manner that the first instruction is not transmitted according to the association with the timing signal of a delay amount in that case.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a recording / reproducing apparatus, a control method for the recording / reproducing apparatus, and a program.

  Conventionally, when data is read from an SD memory card, the delay amount of data transmission from the card with respect to the clock given from the host controller to the card has been a standardized fixed value. Therefore, the host controller can perform card access without any problem by performing data latching with a predetermined amount of delay timing with respect to clock transmission.

  However, in recent years, the above-mentioned delay amount cannot be defined with a fixed value due to an increase in clock speed accompanying an increase in the access speed of the memory card. For this reason, UHS-I (Ultra High Speed-1), which is a high-speed standard for SD memory cards, stipulates that data latch timing adjustment is required when a clock with a frequency higher than a predetermined frequency is used. . This adjustment of the latch timing is called tuning and is generally performed at the time of starting the system having the host controller or at the time of card recognition.

  The SD card corresponding to UHS-I has a function of issuing a test pattern signal for tuning. Patent Document 1 discloses the tuning operation. In Patent Literature 1, when data output from a card is captured (card reading), test pattern data is captured while changing the reception timing to cover the entire range of one cycle of the card clock. The captured data is compared with the test pattern to determine whether the reception is successful or not, and the result is created as a data capture check pattern. In this check pattern, the center of the range in which the data has been successfully captured is selected as the reception timing.

JP 2010-157058 A

  However, in the above method, the reception timing is changed to cover the entire range of one cycle of the card clock, and the test pattern signal is received at each latch timing regardless of success. It is difficult to shorten the tuning time due to waiting.

  Therefore, an object of the present invention is to eliminate the need to wait for test pattern reception at all latch timings and to shorten the tuning period.

The present invention for solving the above problems is a recording / reproducing apparatus,
An output means for outputting a clock signal to the recording medium;
A communication means for transmitting data to the recording medium and receiving data transmitted from the recording medium according to a timing signal obtained by delaying the clock signal;
A first command for transmitting pattern data having a predetermined data string for adjusting the delay amount of the timing signal to the recording medium, and a first command for transmitting data shorter than the pattern data. The pattern data received by the communication unit in response to a timing signal obtained by controlling the communication unit to transmit two commands and delaying the clock signal to any one of a plurality of delay amounts Control means for adjusting the delay amount of the timing signal based on whether or not has the predetermined data string,
When the communication unit cannot correctly receive the data transmitted from the recording medium according to the second command, the control unit uses the timing signal of the delay amount set when the data cannot be received correctly. The communication means is controlled not to transmit the first command to receive pattern data.

  According to the present invention, there is no need to wait for test pattern reception at all latch timings, and the tuning period can be shortened.

The block diagram which shows the structural example of the recording / reproducing apparatus corresponding to embodiment of invention. The figure which shows the structural example of a memory card controller. The figure for demonstrating the latch timing of a memory card. The flowchart which shows operation | movement of tuning mode. The flowchart corresponding to an example of the process corresponding to Embodiment 1 of invention. The flowchart corresponding to an example of the process corresponding to Embodiment 2 of invention.

  Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the drawings. In the embodiment described below, an example in which the present invention is applied to a digital camera capable of writing / reading data to / from a connected memory card as an example of a recording / reproducing apparatus will be described. However, the present invention can be applied to any device (host device) capable of writing / reading data to / from a recording medium, and is not limited to a digital camera, for example, a personal computer, a mobile phone, a smartphone, a PDA, a digital video Cameras are also included.

<Embodiment 1>
FIG. 1 is a block diagram showing a configuration example of a recording apparatus taking a digital camera 100 corresponding to the first embodiment of the invention as an example. The main microcomputer 118 is a CPU, for example. The main microcomputer 118 controls the operation of each block included in the digital camera 100. Specifically, the main microcomputer 118 controls the operation of each block by reading a program stored in the ROM 119 for executing various sequences to be described later for each block, developing the program in the SDRAM 116, and executing the program. The main microcomputer 118 also controls display of the liquid crystal panel 111 by controlling a liquid crystal driver 112 described later. Furthermore, in the present embodiment, a signal having the same pattern as the test data stored in the memory card 115 is stored for comparison, and a test pattern success / failure determination and an optimum latch timing determination operation described later are performed. The ROM 119 is a non-volatile memory that can electrically erase and record data, for example. The ROM 119 stores not only an operation program for each block of the digital camera 100 but also information such as constants necessary for the operation of each block.

  The taking lens 101 captures the subject image, limits the amount of light to a predetermined amount by the diaphragm 102, and then forms the subject image on the image sensor 103. The image sensor 103 is, for example, a CCD or CMOS sensor, and photoelectrically converts a subject image formed on the imaging surface and outputs an analog image signal. The amount of light of the subject image formed by the photographing lens 101 is limited by controlling the opening amount of the diaphragm 102 by the main microcomputer 118. The analog image signal output from the image sensor 103 is converted into digital image data by applying A / D conversion processing by the A / D converter 104. The obtained image data is stored as uncompressed image data in the frame memory 106 after the processing relating to gamma correction, white balance correction, and noise reduction is applied in the image processing unit 105. The image generation unit (imaging unit) 10 of the digital camera 100 according to the present embodiment is configured by the photographing lens 101, the aperture 102, the image sensor 103, the A / D converter 104, the image processing unit 105, and the frame memory 106. Is done.

  In the following embodiment, a case where the image data generated by the image generation unit 10 is written to the memory card 115 as a recording medium, or a case where the written image data is read from the memory card 115 will be described. However, the target to which the present invention is applicable is not limited to image data, and may be audio data or multimedia data including moving image data and audio data. These types of data can be collectively referred to as information data. The recording / reproducing apparatus as an embodiment of the present invention can further include an audio generation unit including a microphone, an A / D converter, and an audio processing unit in addition to the image generation unit 10 in order to generate information data. .

  The JPEG codec 108 compresses and encodes uncompressed image data according to an encoding format (JPEG format) when the digital camera 100 of the present embodiment records a still image, and generates JPEG still image data. The MPEG codec 109 compresses and encodes uncompressed image data as a frame according to a moving image encoding format (MPEG format) when the digital camera 100 of the present embodiment records a moving image, and generates MPEG moving image data. Various data generated by the JPEG codec 108 and the MPEG codec 109 are temporarily written in the SDRAM 116 via the data bus 107. The SDRAM 116 is a volatile memory. The SDRAM 116 stores image data converted for display on the liquid crystal panel 111 in addition to the data generated by the JPEG codec 108 and the MPEG codec 109. The SDRAM 116 is used as a buffer memory space when writing data to the memory card 115. The SDRAM 116 also provides a working memory space of the pixel number conversion circuit 110 that generates thumbnail images to be used for index display during playback from the captured images.

  The liquid crystal panel 111 is a display device included in the digital camera 100 such as an LCD. As described above, the display control of the liquid crystal panel 111 is performed by the main microcomputer 118. Specifically, the liquid crystal driver 112 that has received a command from the main microcomputer 118 converts display image data stored in the SDRAM 116 into a liquid crystal display signal and outputs the liquid crystal display signal to the liquid crystal panel 111, thereby performing display control. Is called. The liquid crystal panel 111 functions as an electronic viewfinder by converting the non-compressed image data, which has been changed to the number of display pixels of the liquid crystal panel 111 by the pixel number conversion circuit 110, into a liquid crystal display signal and inputting it (through display). ).

  The memory card 115 is a memory card that is detachable from the camera body via the card slot / detection SW 114, for example, is composed of a NAND flash memory, and has a FAT (File Allocation Table) file having PC compatibility. Data is managed in a format compliant with the system. Communication such as data writing to the memory card 115 and data reading from the memory card 115 is performed by the memory card controller 113. The memory card controller 113 reads data for recording from the SDRAM 116 and writes the data to the memory card 115 when writing data. The memory card controller 113 reads data from the memory card 115 and stores it in the SDRAM 116 at the time of reading data.

  The card slot / detection SW 114 is a slot into which the memory card 115 is attached, and includes a detection switch (SW) that detects whether or not the memory card 115 is attached. When the detection switch detects that the memory card 115 is inserted in the card slot, the detection switch can output a detection signal to the main microcomputer 118.

  The operation input unit 117 is a user interface such as various switches that accept various operations from the user. The operation input unit 117 includes a shutter button for performing a still image shooting operation, a trigger button for instructing start and stop of shooting of a moving image, and a mode switch for switching between the camera shooting mode and the playback mode. When various operation keys provided on the digital camera 100 are operated by the user, the operation input unit 117 receives a signal corresponding to the operation and outputs a control signal corresponding to the operation to the main microcomputer 118.

  FIG. 2 is a diagram illustrating a configuration example of the memory card controller 113 corresponding to the present embodiment. The memory card controller 113 transmits and receives signals and data through the CLK line, the CMD line, and the DAT line in writing and reading data to and from the memory card 115.

  The clock source 201 gives data writing and reading timings to the memory card 115 and gives data sending and receiving timings to the host controller 202 described later. The host controller 202 outputs a command signal, which is a command related to reading and writing data, and receives a response signal for the command from the memory card 115 via the CMD line. The host controller 202 performs control to transmit / receive data to be written to the memory card 115 or data read from the memory card 115 via the DAT line. Specifically, the host controller 202 issues a command for controlling the operation of the memory card 115 and receives a command response from the memory card 115 according to an instruction from the main microcomputer 118. The delay element 203 delays the phase of the clock signal from the clock source 201 by a delay amount according to the control from the main microcomputer 118 when data is read from the memory card 115, and latches the data output from the memory card 115. Is generated. Note that the signal branching unit 205 performs switching between the CMD line and the DAT line according to command input / output and data transmission / reception according to the control of the host controller 202.

  The flip-flop 204 latches data from the memory card 115 in accordance with the timing signal from the delay element 203. The signal branching unit 205 switches between the DAT line and the CMD line for data writing and data reading under the control of the host controller 202.

  Hereinafter, one method for adjusting the delay amount of the sampling clock will be described. In this method, when the memory card controller 113 issues a first command requesting the memory card 115 to transmit test data, the memory card 115 synchronizes with a clock signal (CLK signal) supplied from the clock source 201. A 64-byte data string of a predetermined pattern is returned. Therefore, the memory card controller 113 receives the data string according to the data latch timing obtained by delaying the clock signal generated by the clock source 201 based on the delay amount set in the delay element 203. That is, the data latch timing can change the phase relationship with the clock signal by changing the number of delay stages set in the delay element 203. A plurality of latch timings can be secured by setting a plurality of delay amounts for one cycle of the clock signal. In the example of FIG. 3, a latch timing of 16 steps is secured.

  Next, with reference to FIG. 4, the tuning operation corresponding to the method of adjusting the delay amount of the sampling clock by the memory card controller 113 will be described. In the tuning operation, the main microcomputer 118 controls the memory card controller 113 to execute processing corresponding to each block. For this reason, the main microcomputer 118 will be described as being able to refer to data and the like acquired in the processing in the memory card controller 113.

  When the tuning operation is started, the main microcomputer 118 sets the number of delay stages of the delay element 203 to 1 in S401. In subsequent S <b> 402, the host controller 202 issues a first command to the memory card 115 in accordance with control by the main microcomputer 118. As the first command, for example, in the transfer mode of SDR50 or SDR104 defined by the UHS-I standard, a tuning block transmission command of CMD19 can be used. In response to the first command, the memory card 115 transmits a response signal in response to the command (for example, the response to the CMD 19 is R1) and test data of a 64-byte tuning pattern corresponding to the command. In subsequent S403, the host controller 202 receives the response and the test data transmitted from the memory card 115, and the main microcomputer 118 determines whether or not the received test data matches the predetermined pattern data in S404. To do. The main microcomputer 118 records OK (reception success) in the reception result table in S405 if all the patterns of the received data match the predetermined pattern, and NG (reception in the reception result table in S406 if they do not match. (Failure). As shown in FIG. 3, the reception result table is a table that records the relationship between the number of delay stages and whether or not test data can be received.

  Thereafter, in S407, the main microcomputer 118 confirms whether or not the delay stage number has reached the maximum value (maximum delay stage number). If not, the main microcomputer 118 increases the delay stage number by one in S408 and repeats the processing from S402. If the number of delay stages is the maximum value, the reception result table is completed. In S409, the main microcomputer 118 determines the median of the range in which reception was successful from the reception result table, and optimizes this. The latch timing is determined. In FIG. 3, since the number of delay stages 5 to 13 indicates the phase of the reception success area, the delay stage number 9 as the median value is determined as the set delay amount to be applied to the delay element 203.

  As described above, in the method shown in FIG. 4, it is necessary to receive test data of 64 bytes for all the number of delay stages. Therefore, even if the test data cannot be correctly received with the set number of delay stages, it is necessary to wait for a predetermined period necessary to receive the 64-byte test data. On the other hand, in the method of this embodiment described below, whether or not accurate reception is possible with the set number of delay stages is simply confirmed using a second command different from the first command. Keep it. Thus, unnecessary determination processing can be omitted, and the first command can be issued only for the number of delay stages that are expected to be able to be accurately received, and the reception result of the test data can be determined.

  Hereinafter, a tuning operation corresponding to the present embodiment will be described with reference to FIG. The processing from S501 to S509 in FIG. 5 is the same as S401 to S409 in FIG. Hereinafter, processing in S510 and S511 different from FIG. 4 will be described. First, in S510, the host controller 202 issues a second command different from the first command to the memory card 115 in accordance with control by the main microcomputer 118. This second command is a command that transmits only a response and does not request a return of test data, or a command for returning data having a data size smaller than 64 bytes as test data. As an example of the second command, a CMD13 command defined by the UHS-I standard can be used. This CMD13 command is a status transmission command for inquiring the current status of the card. When this status transmission command is received, no data other than the response packet is transmitted from the memory card 115. The memory card 115 can respond to the command by including status information (32 bits) such as “Busy” and “Ready for Data” in the 48-bit response packet of the response R1. Note that when the transmission of a smaller data size is requested as the second command, the minimum value can be set to 0 to set an arbitrary data size. After issuing the second command, in subsequent S511, the main microcomputer 118 determines whether or not the host controller 202 can receive a response. Specifically, the host controller 202 determines whether a response is received within a predetermined period (within 64 clocks) defined by the standard. When a response is received within a predetermined period, it is determined whether an error has occurred in the received response. The presence / absence of the error can be determined based on a 7-bit CRC code included in the response R1 packet. If it is determined that the signal can be normally received, the process proceeds to S502 where the host controller 202 issues the first command according to the control by the main microcomputer 118. On the other hand, if it is determined that reception is not possible normally, the main microcomputer 118 updates the corresponding part of the reception result table to NG in S506.

  As described above, according to this embodiment, before determining the reception result of the test pattern while changing the delay amount of the sampling clock, only the response is requested or the test data with a small data size is requested to be returned. Send a command. As a result, it is not necessary to receive the test pattern with the sampling clock of each delay amount. That is, since the test pattern success / failure determination for the first command is performed only at the latch timing setting in which the response to the second command has been successfully received, the operation for determining the optimum latch timing can be shortened.

<Embodiment 2>
Next, a second embodiment of the invention will be described. The configuration example and tuning operation of the recording apparatus corresponding to the present embodiment are the same as the configuration and operation described in FIG. 1 and FIG. In this embodiment, before issuing the first command, it is determined whether or not a response to the second command has been correctly received based on all the delay amounts of the sampling clock. Then, the delay amount of the sampling clock is selected again based on the determination result, and the test data is received with the sampling clock having the selected delay amount.

  First, the tuning operation corresponding to the present embodiment will be described with reference to FIG. The processes from S601 and S605 to S608, S610, and S611 in FIG. 6 are the same as S501, S505 to S508, S510, and S511, and thus description thereof is omitted. Hereinafter, processing in steps different from those in FIG. 5 will be described.

  In S612, the median value in the range of the number of delay stages that is OK determination (successfully received response to the second command) is determined in the created reception result table, and a predetermined number of delay stages is selected based on the median value. . In the following, a case where three delay stages are selected will be described as an example. For example, in the case of FIG. 3, 8, 9, and 10 stages are selected. It should be noted that the number of stages to be selected is not limited to three as long as it is a part of the number of delay stages for which the OK determination is obtained, and may be more or less. In S612, the minimum value among the three delay stages is set as the delay stage number of the delay element 203 as an initial value of the delay stage number.

  In subsequent S 614, the host controller 202 issues the first command to the memory card 115 under the control of the main microcomputer 118. In S615, the host controller 202 receives the 64-byte test data transmitted from the memory card 115. In subsequent S616, the main microcomputer 118 determines whether or not the received data matches the predetermined pattern data and all 64 bytes. If they do not match, the main microcomputer 118 reselects the number of delay stages by shifting the median value of the table in either the forward or backward direction, for example, one step backward or forward in S617.

  In the reselection, the delay stage number determined not to match in S616 can be shifted so as not to be included. For example, consider the case where the 8th, 9th, and 10th stages are selected, and the 8th and 9th stages have received test data that matches predetermined pattern data, but the 10th stage does not match. In this case, the number of delay stages to be reselected is not included in 10 stages, and can be shifted forward in time so as to include 7 stages, 8 stages, and 9 stages. The number of stages to be shifted is not limited to one and may be two. For example, consider the case where the 8th, 9th, and 10th stages are selected, and the 8th stage does not match the 9th stage while the received test data matches the predetermined pattern data. In this case, there is no point in reselecting the 9th stage, so it is better to shift it forward in time so that 6th stage, 7th stage, and 8th stage are included by shifting 2 stages.

  The minimum value of the number of delay stages reselected in this way is set as the initial value to the number of delay stages of the delay element 203, and the process proceeds to S614. For example, in the case of FIG. 3, three of 9, 10, and 11, or three of 7, 8, and 9 are reselected, and the minimum value of 9 or 7 is used as the initial value. Reset it. Note that the calculation may be omitted for the number of already determined delay stages.

  If the received test data matches the predetermined pattern data in S616, it is checked in S618 whether all three delay stages selected in S612 or S617 are completed. If not, the process goes to S613. Transition. In S613, the number of delay stages is changed by 1, and the process proceeds to the first command issuance process in S614. If all three delay stages have been completed, the median delay stage number of the three delay stages selected in S612 or S617 is determined as the optimum latch timing in S619.

  According to the above embodiment, the test pattern success / failure determination for the first command is performed only for the vicinity of the center of the delay stage number at which the response of the second command has been normally received, so that the determination operation of the optimum latch timing is performed. Can be shortened.

(Other examples)
The present invention can also be realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various storage media, and a computer (or CPU, MPU, or the like) of the system or apparatus reads the program. It is a process to be executed.

DESCRIPTION OF SYMBOLS 101 Shooting lens, 102 Aperture, 103 Image sensor, 104 A / D converter, 105 Image processing circuit, 106 Frame memory, 107 Data bus, 108 JPEG codec, 109 MPEG codec, 110 Pixel number conversion circuit, 111 Liquid crystal panel, 112 Liquid crystal Driver, 113 Memory card controller, 114 Card slot / detection SW, 115 Memory card, 116 SDRAM, 117 Operation key, 118 Main microcomputer, 119 ROM, 201 Clock source, 202 Host controller, 203 Delay element, 204 Flip-flop, 205 Signal Bifurcation

Claims (12)

An output means for outputting a clock signal to the recording medium;
A communication means for transmitting data to the recording medium and receiving data transmitted from the recording medium according to a timing signal obtained by delaying the clock signal;
A first command for transmitting pattern data having a predetermined data string for adjusting the delay amount of the timing signal to the recording medium, and a first command for transmitting data shorter than the pattern data. The pattern data received by the communication unit in response to a timing signal obtained by controlling the communication unit to transmit two commands and delaying the clock signal to any one of a plurality of delay amounts Control means for adjusting the delay amount of the timing signal based on whether or not has the predetermined data string,
When the communication unit cannot correctly receive the data transmitted from the recording medium according to the second command, the control unit uses the timing signal of the delay amount set when the data cannot be received correctly. A recording / reproducing apparatus for controlling the communication means so as not to transmit the first command for receiving pattern data.   2. The recording / reproducing apparatus according to claim 1, wherein the response transmitted from the recording medium in response to the second command does not include data other than a predetermined response packet.   The control means receives the pattern data based on a delay amount of the timing signal set when the communication means has correctly received the data transmitted from the recording medium in response to the second command. Determining a delay amount of the timing signal to be set, and controlling the communication means to transmit the first command in order to receive the pattern data by the timing signal of the determined delay amount. The recording / reproducing apparatus according to claim 1 or 2.   The control unit determines that the communication unit cannot correctly receive data when the communication unit cannot receive data for the second command within a predetermined period after the communication unit transmits the second command. The recording / reproducing apparatus according to claim 1.   2. The recording / reproducing according to claim 1, wherein the control unit determines that the data cannot be correctly received when the data transmitted to the second command received by the communication unit is an error. apparatus.   The control means is a part of the delay amount of the timing signal set when the communication means can correctly receive the data transmitted from the recording medium in response to the second command. 2. The recording / reproducing apparatus according to claim 1, wherein the communication means is controlled to transmit the first command in order to receive the pattern data in response to an amount of the timing signal.   The control means determines the pattern data when it is determined that any of the pattern data received by the communication means does not have the predetermined data string by the timing signal of the partial delay amount. 7. The recording / reproducing apparatus according to claim 6, wherein a delay amount of the timing signal for reception is reselected.   8. The recording / reproducing apparatus according to claim 7, wherein the control unit performs the reselection by shifting the delay amount in any direction before or after the time.   The control means sets the delay amount corresponding to the timing signal determined that any one of the pattern data received by the communication means does not have the predetermined data string in a direction in which the delay amount is shifted. 9. The recording / reproducing apparatus according to claim 8, wherein the direction is not included in the selected delay amount.   10. The recording / reproducing apparatus according to claim 6, wherein the partial delay amount is at least three delay amounts. An output means for outputting a clock signal to the recording medium;
A communication means for transmitting data to the recording medium and receiving data transmitted from the recording medium according to a timing signal obtained by delaying the clock signal;
A control method for a recording / reproducing apparatus, comprising: control means for controlling the communication means to transmit the command to the recording medium,
The control means is
A first command for transmitting pattern data having a predetermined data string for adjusting the delay amount of the timing signal to the recording medium, and a first command for transmitting data shorter than the pattern data. Controlling the communication means to transmit two instructions;
Based on whether the pattern data received by the communication unit according to a timing signal obtained by delaying the clock signal to any one of a plurality of delay amounts has the predetermined data string, Adjusting the delay amount of the timing signal;
When the communication means cannot correctly receive the data transmitted from the recording medium in response to the second command, the pattern data is received by the timing signal having a delay amount set when the data cannot be correctly received. And a step of controlling the communication means so as not to transmit the first command.   The program for functioning a computer as the said control means of the recording / reproducing apparatus of any one of Claims 1 thru | or 10.

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