JP6151581B2 - Surface treatment method for single crystal SiC substrate and method for manufacturing single crystal SiC substrate - Google Patents

Description

  The present invention mainly relates to a method for removing macrostep bunching generated on the surface of a single crystal SiC substrate.

  SiC is attracting attention as a new semiconductor material because it is superior in heat resistance, mechanical strength, and the like as compared with Si and the like. Note that crystal defects or the like may initially exist on the surface of the single crystal SiC substrate.

  Patent Document 1 discloses a surface flattening method for flattening (repairing) the surface of this single crystal SiC substrate. In this surface flattening method, a carbonized layer and a sacrificial growth layer are formed on a single crystal SiC substrate, and the sacrificial growth layer is etched to flatten the surface. Thereby, a high-quality seed substrate for epitaxial growth can be produced. Note that Patent Document 1 discloses that etching is performed under high vacuum.

  In general, the seed crystal produced as described above is subjected to processes such as epitaxial growth, ion implantation, and ion activation.

  Patent Document 2 discloses a method for suppressing sublimation of Si and SiC during ion activation by forming a carbon layer (graphene cap) on the surface of a single crystal SiC substrate and then performing the above-described ion activation. Is disclosed. Thereafter, in this method, the surface of the single crystal SiC substrate is etched in order to remove the carbon layer and remove the insufficient ion implantation portion.

JP 2008-230944 A JP 2011-233780 A

  By the way, although details are not described in Patent Document 2, macro step bunching occurs by performing heat treatment such as ion activation on a substrate having an off angle. Macro step bunching is a phenomenon in which a bundle of steps having a height of 1 nm or more is formed by a plurality of SiC layers (or a step itself formed by a plurality of SiC layers).

  When macro step bunching occurs, the device structure of the semiconductor element becomes unstable, or the performance as a semiconductor element is degraded due to local concentration of the electric field. Therefore, conventionally, heat treatment was performed in a high vacuum Si atmosphere to remove the macro step bunching.

  However, if the heat treatment is performed in a Si atmosphere in a high vacuum, the etching rate is fast, so that the substrate may be excessively removed. In particular, when removing the substrate after the ion implantation, there is a possibility that the ion implanted portion may be largely removed, so that a solution has been desired.

  The present invention has been made in view of the above circumstances, and a main object thereof is to provide a method for removing macrostep bunching formed on the surface of a single crystal SiC substrate.

Means and effects for solving the problems

  The problems to be solved by the present invention are as described above. Next, means for solving the problems and the effects thereof will be described.

According to the first aspect of the present invention, the following method is provided in the surface treatment method for removing the macro step bunching formed during the surface treatment of the single crystal SiC substrate. The surface of the single crystal SiC substrate is a plane having an off angle with respect to the (0001) plane. In this surface treatment method, the etching rate for etching the surface of the single crystal SiC substrate is adjusted to 100 nm / min by adjusting the inert gas pressure around the single crystal SiC substrate to be at least temporarily 10 Pa or less. As described above, the macro step bunching is removed by heat-treating the single crystal SiC substrate in an atmosphere of the inert gas and Si.

Thereby, since macro step bunching can be removed, the quality of a single crystal SiC substrate and a semiconductor element using the same can be improved. Further, since the etching rate can be suppressed by controlling the etching rate using the inert gas pressure, it is possible to prevent the surface of the single crystal SiC substrate from being excessively removed. Further, since the macro step bunching cannot be removed when the etching rate is about 100 nm / min or less, the macro step bunching can be surely removed by performing the above control.

  In the surface treatment method of the single crystal SiC substrate, it is preferable to adjust the inert gas pressure in consideration of the heating temperature at the time of removing the macro step bunching.

  Thereby, since the etching rate also depends on the heating temperature, by performing the above-described control, it is possible to reliably remove the macro step bunching and prevent the surface of the single crystal SiC substrate from being excessively removed.

In the surface treatment method for a single crystal SiC substrate, it is preferable that an inert gas pressure at the time of removing the macro step bunching is adjusted to be at least temporarily 10 Pa or less and 0.5 Pa or more.

  Thereby, since an etching rate can be 100 nm / min or more, macro step bunching can be removed reliably.

  In the surface treatment method of the single crystal SiC substrate, the following is preferable. That is, it includes an ion implantation step in which ions are implanted into the single crystal SiC substrate. A portion of the surface of the single crystal SiC substrate where ion implantation is insufficient and the macro step bunching are simultaneously removed.

  As a result, the ion implantation insufficient part and the macro step bunching can be removed at the same time, so that the surface treatment can be performed efficiently. In addition, since the etching rate can be suppressed in the present application, it is possible to prevent the portion into which ions are implanted from being excessively removed.

According to the 2nd viewpoint of this invention, the manufacturing method of the single crystal SiC substrate including the process of processing a substrate surface using the said surface treatment method is provided.

  Thereby, the macro step bunching is removed, and a single crystal SiC substrate whose surface is etched by a necessary amount can be produced, so that a high quality single crystal SiC substrate can be realized.

The figure explaining the outline | summary of the high temperature vacuum furnace used for the surface treatment method of this invention. The figure which shows the mode of the board | substrate in each process roughly. The graph which shows that an ion implantation insufficient part is removed by an etching. The graph which shows the relationship between heating temperature and an etching rate. The graph which shows the relationship between the pressure of an inert gas, and an etching rate for every heating temperature. The figure which shows the microscope picture and surface roughness of the surface of a board | substrate when etching is performed by changing the pressure of an inert gas. (A) The graph which shows the relationship between the etching amount with respect to processing time, and an etching rate. (B) A photomicrograph showing the surface of the substrate when etching is performed while changing the processing time.

  Next, embodiments of the present invention will be described with reference to the drawings.

  First, the high-temperature vacuum furnace 10 used in the heat treatment of the present embodiment will be described with reference to FIG. FIG. 1 is a diagram for explaining the outline of a high-temperature vacuum furnace used in the surface treatment method of the present invention.

  As shown in FIG. 1, the high-temperature vacuum furnace 10 includes a main heating chamber 21 and a preheating chamber 22. The main heating chamber 21 can heat the single crystal SiC substrate to a temperature of 1000 ° C. or higher and 2300 ° C. or lower. The preheating chamber 22 is a space for performing preheating before heating the single crystal SiC substrate in the main heating chamber 21.

  A vacuum forming valve 23, an inert gas injection valve 24, and a vacuum gauge 25 are connected to the main heating chamber 21. The degree of vacuum in the main heating chamber 21 can be adjusted by the vacuum forming valve 23. The pressure of the inert gas (for example, Ar gas) in the main heating chamber 21 can be adjusted by the inert gas injection valve 24. With the vacuum gauge 25, the degree of vacuum in the main heating chamber 21 can be measured.

  A heater 26 is provided inside the main heating chamber 21. Further, a heat reflecting metal plate (not shown) is fixed to the side wall and ceiling of the main heating chamber 21, and the heat reflecting metal plate reflects the heat of the heater 26 toward the central portion of the main heating chamber 21. It is configured. Thereby, a single-crystal SiC substrate can be heated strongly and uniformly, and can be heated up to the temperature of 1000 degreeC or more and 2300 degrees C or less. As the heater 26, for example, a resistance heating type heater or a high frequency induction heating type heater can be used.

  Further, the single crystal SiC substrate is heated while being accommodated in crucible (accommodating container) 30. The crucible 30 is placed on an appropriate support base or the like, and is configured to be movable at least from the preheating chamber to the main heating chamber by moving the support base.

  The crucible 30 includes an upper container 31 and a lower container 32 that can be fitted to each other. The crucible 30 is made of tantalum metal and is configured to expose the tantalum carbide layer to the internal space.

  When heat-treating a single crystal SiC substrate, first, as shown by a chain line in FIG. Preheat. Next, the crucible 30 is moved to the main heating chamber 21 that has been heated to a preset temperature (for example, about 1800 ° C.) in advance, and the single crystal SiC substrate is heated.

  Next, a process for manufacturing a semiconductor element from the single crystal SiC substrate 40 using the high-temperature vacuum furnace 10 will be described with reference to FIGS. FIG. 2 is a diagram schematically showing the state of the substrate in each step. FIG. 3 is a graph showing that the insufficient ion implantation portion is removed by etching. In this embodiment, a single crystal SiC substrate 40 having an off angle is used.

  First, as shown in FIG. 2A, an epitaxial layer 41 is formed on the single crystal SiC substrate 40. The method for forming the epitaxial layer is arbitrary, and a known vapor phase epitaxial method, metastable solvent epitaxial method, or the like can be used. Furthermore, when the single crystal SiC substrate 40 is an OFF substrate, a CVD method for forming an epitaxial layer by step flow control can also be used.

  Next, as shown in FIG. 2B, ion implantation is performed on the single crystal SiC substrate 40 on which the epitaxial layer 41 is formed. This ion implantation is performed using an ion doping apparatus having a function of irradiating an object with ions. Ions are selectively implanted into the entire surface or part of the surface of the epitaxial layer 41 by an ion doping apparatus. Then, a desired region of the semiconductor element is formed based on the ion implanted portion 42 into which ions are implanted.

  Further, as shown in FIG. 2C, the surface of the epitaxial layer 41 including the ion-implanted portion 42 is roughened by the ion implantation (the surface of the single crystal SiC substrate 40 is damaged and flattened). Degree gets worse).

  Next, a process for activating the implanted ions is performed. In this treatment, the single crystal SiC substrate 40 is heated in an environment of 1500 ° C. or higher and 2200 ° C. or lower, preferably 1600 ° C. or higher and 2000 ° C. or lower, under Si vapor pressure. Thereby, the implanted ions can be activated.

  In addition, since the substrate 70 used in the present embodiment has an off-angle, macro step bunching is generated by this heat treatment (see FIG. 2D). When this macro step bunching occurs, as described above, the device structure of the semiconductor element becomes unstable, or the performance as a semiconductor element deteriorates due to local concentration of the electric field. In this regard, in the present embodiment, this macro step bunching can be removed by an etching process described below.

  The macro step bunching is formed from the surface of the substrate 70 to about 100 nm depending on conditions. Further, as shown in FIG. 3, a portion where the ion concentration of the implanted ions is insufficient (ion implantation insufficient portion) appears about several tens of nanometers from the surface of the single crystal SiC substrate 40. Considering the above points, in this embodiment, it is necessary to remove the surface of the single crystal SiC substrate 40 by about 100 nm. This will be specifically described below.

  In this etching process, the single crystal SiC substrate 40 is heated under Si vapor pressure. Conventionally, since the etching rate is high, it is difficult to accurately remove only the ion implantation insufficient portion and the macro step bunching.

  In this regard, in the present embodiment, the etching rate can be accurately and easily controlled by adjusting the pressure of the inert gas. By controlling the etching rate, the etching amount can be accurately grasped, so that only the ion implantation insufficient part and the macro step bunching can be removed by etching.

  Hereinafter, the relationship between the pressure of the inert gas and the etching rate will be described with reference to FIGS.

  As conventionally known, the etching rate of the single crystal SiC substrate depends on the heating temperature. FIG. 4 is a graph showing the etching rate when the heating temperature is 1600 ° C., 1700 ° C., 1750 ° C., and 1800 ° C. in a predetermined environment. The horizontal axis of this graph is the reciprocal of temperature, and the vertical axis of this graph represents the etching rate logarithmically. As shown in FIG. 4, this graph is a straight line. Therefore, for example, the etching rate when the temperature is changed can be estimated.

  FIG. 5 is a graph showing the relationship between the inert gas pressure and the etching rate in a substrate with an off angle of 4 °. Specifically, as can be seen from this graph, since the etching rate is relatively high in a high vacuum environment where the conventional etching process has been performed, it is difficult to accurately grasp the etching amount. In this respect, in this embodiment, the etching rate can be reduced by increasing the inert gas pressure. Thereby, it is possible to accurately grasp the etching amount and remove only the ion implantation insufficient portion and the macro step bunching.

  Next, the relationship between the etching rate and the removal of macro step bunching will be described. FIG. 6 is a photomicrograph showing the surface of the substrate when etching is performed while changing the pressure of the inert gas. 7A and 7B are a graph showing the relationship between (a) the etching amount and the etching rate with respect to the processing time, and (b) a photomicrograph showing the surface of the substrate 70 when etching is performed while changing the processing time. .

  The left end of FIG. 6 shows a photomicrograph of the surface of the single crystal SiC substrate 40 before performing the etching process. This micrograph shows innumerable straight lines, which show the steps of macro step bunching. On the right side of the unprocessed micrograph, a micrograph and surface roughness of the surface of the single crystal SiC substrate 40 after heating at 1800 ° C. for 15 minutes with different inert gas pressures are shown. In addition, an enlarged view of the corresponding photomicrograph is shown below.

  As shown in these figures, when the pressure of the inert gas is 1.3 kPa, the macro step bunching remains, and when the pressure of the inert gas reaches 133 Pa, the surface roughness is remarkably reduced and the macro step bunching is reduced. It can be seen that a part of is removed. In addition, it can be seen that when the pressure of the inert gas is 13 Pa and 1.3 Pa and when the vacuum is high, the surface roughness is further reduced, and almost all macrostep bunching can be removed.

  FIG. 7 shows data when the pressure of the inert gas is 1.3 kPa and heated at 1800 ° C. for 15 minutes, 60 minutes, and 180 minutes. As shown in FIG. 7A, since the etching rate is substantially constant, the etching amount increases in proportion to the passage of time. However, as shown in FIG. 7B, the macro step bunching is not removed even after the lapse of 60 minutes and 180 minutes after the etching amount is sufficient. Therefore, it can be seen that whether or not the macro step bunching can be removed depends on the etching rate, not the etching amount.

  Here, based on these experimental results, the graph of FIG. 5, and the numerical value of the surface roughness of FIG. 6, when the etching rate is 100 nm / min or more, the decomposition of the macro step bunching is started and partly It can be seen that the macro step bunching can be almost completely removed if the etching rate is further increased.

  In addition, when the etching rate is too high, there is a possibility that the ion-implanted portion is excessively removed. Therefore, it is not preferable that the etching rate is too high. From the above, the inert gas pressure is preferably about 0.5 Pa to 10 Pa, for example. Note that the etching rate depends not only on the inert gas pressure but also on the heating temperature and the pressure of Si. Therefore, it is preferable to adjust the etching rate in consideration of them.

  Furthermore, as shown in FIG. 6, even after removing the macro step bunching, fine irregularities may remain. When this minute unevenness becomes a problem from the viewpoint of the performance of the semiconductor element, the following processing may be performed. That is, first, the macro step bunching is decomposed or removed by adjusting the pressure of the inert gas so that the etching rate is 100 nm / min or more and performing heat treatment. Thereafter, an inert gas is further added to lower the etching rate and improve the surface flatness.

  Next, an experiment comparing the etching according to the present embodiment and the etching according to the conventional method and the results thereof will be described.

Example 1
4H-SiC 4 ° -off (0001) (□ 10 mm / 4 ″), epitaxial layer n-type 1 × 10 ¹⁶ / cm ^{3 to} 10 μm single crystal SiC substrate, Al ⁺ ion multi-stage implantation is performed at a high temperature (500 ° C. ) 1 × 10 ¹⁹ atoms / cm ³ , 500 nm from the substrate surface The single crystal SiC substrate after this ion implantation was placed in the crucible with a lid having a diameter of 20 mm, and 1600 Etching was performed for 5 minutes at 1.3 ° C. in an Ar 1.3 kPa atmosphere.

(Comparative Example 1)
A conventional carbon layer was formed on the single crystal SiC substrate after ion implantation and annealed, and the electrical characteristics were compared with Example 1 above.

When the electrical characteristics of Example 1 and Comparative Example 1 were measured, after the annealing process according to Comparative Example 1, the sheet resistance was 1.35 × 10 ⁴ ohm / square and the carrier density was 3.47 × 10 ¹⁷ / cm ³ . On the other hand, after the annealing treatment in Example 1, the sheet resistance was 3.26 × 10 ⁴ ohm / square and the carrier density was 3.89 × 10 ¹⁷ / cm ³ . Therefore, it was confirmed that the activation was at a level almost inferior.

In addition, channeling measurement was performed by RBS (Rutherford backscattering) measurement on the surfaces of the single crystal SiC substrates used in Comparative Example 1 and Example 1 immediately after epitaxial growth and immediately after ion implantation, thereby measuring χ _min values. As a result, it was 2.0% immediately after epitaxial growth and 7.8% immediately after ion implantation. However, Example 1 was 2.5% and Comparative Example 1 was 2.4%. It was confirmed that it was equivalent to the case of using a conventional carbon layer.

  As described above, in this embodiment, by adjusting the inert gas pressure around the single crystal SiC substrate 40, the etching rate for etching the surface of the single crystal SiC substrate 40 is set within a predetermined range. The macro step bunching is removed by heat-treating the single crystal SiC substrate 40 in the atmosphere of the inert gas and Si.

  Thereby, since macro step bunching can be removed, the quality of the single crystal SiC substrate 40 and a semiconductor element using the same can be improved. In addition, since the etching rate can be suppressed by controlling the etching rate using the inert gas pressure, it is possible to prevent the surface of the single crystal SiC substrate 40 from being excessively removed.

  In the surface treatment method of the present embodiment, the inert gas pressure is adjusted so that the etching rate is 100 nm / min or more.

  Thereby, since the macro step bunching cannot be removed when the etching rate is about 100 nm / min or less, the macro step bunching can be surely removed by performing the above control.

  Further, in the surface treatment method of the present embodiment, the inert gas pressure is adjusted in consideration of the heating temperature when removing the macro step bunching.

  Thereby, since the etching rate also depends on the heating temperature, by performing the above control, it is possible to reliably remove the macro step bunching and to prevent the surface of the single crystal SiC substrate 40 from being excessively removed.

  Moreover, in the surface treatment method of this embodiment, the inert gas pressure at the time of macro step bunching removal is at least temporarily set to 0.5 Pa or more and 10 Pa or less.

  Thereby, since an etching rate can be 100 nm / min or more, macro step bunching can be removed reliably.

  Further, the surface treatment method of the present embodiment includes an ion implantation step in which ions are implanted into the single crystal SiC substrate 40, and the ion implantation insufficient portion on the surface of the single crystal SiC substrate 40 and the macro step bunching are simultaneously performed. Remove.

  As a result, the ion implantation insufficient part and the macro step bunching can be removed at the same time, so that the surface treatment can be performed efficiently. In addition, since the etching rate can be suppressed in the present application, it is possible to prevent the portion into which ions are implanted from being excessively removed.

  The preferred embodiment of the present invention has been described above, but the above configuration can be modified as follows, for example.

  In the above embodiment, the process of forming the carbon layer (graphene cap) is not performed, but this process may be performed. In this case, the process of removing the carbon layer, the process of activating ions, and the process of etching the single crystal SiC substrate can be performed in one step.

  The method for adjusting the inert gas is arbitrary, and an appropriate method can be used. Further, the inert gas pressure may be fixed or changed during the etching process. By changing the inert gas pressure, for example, a method can be considered in which fine adjustment is performed by initially increasing the etching rate and then decreasing the etching rate.

  The environment in which the treatment is performed and the single crystal SiC substrate used are examples, and can be applied to various environments and single crystal SiC substrates. For example, the heating temperature is not limited to the temperature mentioned above, and the etching rate can be further reduced by lowering the heating temperature. Moreover, you may use heating apparatuses other than the high temperature vacuum furnace mentioned above.

10 High-temperature vacuum furnace 21 Main heating chamber 22 Preheating chamber 30 Crucible 40 Single crystal SiC substrate 41 Epitaxial layer 42 Ion implantation portion

Claims (5)

In a surface treatment method for removing macrostep bunching formed during surface treatment of a single crystal SiC substrate,
The surface of the single crystal SiC substrate is a surface having an off angle with respect to the (0001) plane,
By adjusting the inert gas pressure around the single crystal SiC substrate to be at least temporarily 10 Pa or less, the etching rate for etching the surface of the single crystal SiC substrate is set to 100 nm / min or more , and the inert gas pressure is adjusted. A surface treatment method for a single crystal SiC substrate, wherein the macrostep bunching is removed by heat-treating the single crystal SiC substrate in an atmosphere of an active gas and Si. A surface treatment method for a single crystal SiC substrate according to claim 1 ,
A surface treatment method for a single crystal SiC substrate, wherein an inert gas pressure is adjusted in consideration of a heating temperature at the time of removing the macro step bunching. A surface treatment method for a single crystal SiC substrate according to claim 1 or 2 ,
A surface treatment method for a single crystal SiC substrate, wherein an inert gas pressure at the time of removing the macro step bunching is adjusted to be at least temporarily 10 Pa or less and 0.5 Pa or more. A surface treatment method for a single crystal SiC substrate according to any one of claims 1 to 3 ,
Including an ion implantation step in which ions are implanted into the single crystal SiC substrate;
A method for treating a surface of a single crystal SiC substrate, wherein the ion implantation insufficient portion on the surface of the single crystal SiC substrate and the macro step bunching are simultaneously removed. Method for producing a single crystal SiC substrate, which comprises the step of treating the substrate surface with a surface treatment method according to any one of claims 1 to 4.