JP6147131B2 - Arithmetic unit - Google Patents

Description

  The present invention relates to an arithmetic device.

  2. Description of the Related Art Conventionally, there is a so-called multiprocessor arithmetic device including a plurality of processors that execute arithmetic processing in accordance with a program. In such a conventional arithmetic device, each processor, while accessing each memory processing shared by a plurality of processors, each arithmetic processing according to a packet including data to be calculated input from an external block, In other words, the data used in the arithmetic processing is executed while being read from the memory or written to the memory.

  In such a conventional arithmetic device, a configuration for associating a processor with a memory is disclosed in Patent Document 1. Patent Document 1 discloses a technique for changing a memory corresponding to each processor by using a crossbar switch that switches a physical connection between the processor and the memory. With the technique disclosed in Patent Document 1, a configuration in which all memories are shared by all processors is realized.

  And in the arithmetic device to which the technique disclosed in Patent Document 1 is applied, configuration information representing the configuration of the memory that can be used when each processor executes arithmetic processing is set in advance. , For each processor, access to some memories is permitted in advance. In other words, the memory that can be accessed for each processor is limited in advance to some memories that are predetermined by the configuration information. Thereby, in the conventional arithmetic device, in each arithmetic processing, it is avoided that different processors access the same memory, that is, access to the same memory competes.

Japanese Patent No. 4288421

  However, even when the technique disclosed in Patent Document 1 is applied, if the number of processors permitted to access a specific memory increases, the frequency of accessing the same memory, that is, the same memory The frequency of access contention increases. For this reason, for example, it is necessary to take measures to prevent access to the same memory from a plurality of processors from competing, for example, by reducing the number of memories that allow access to each processor. As long as this processor is allowed, access contention to the same memory will occur. In other words, unless there is a one-to-one correspondence between the processor and the memory, there is a considerable contention for access to the same memory from a plurality of processors.

  Further, in the technique disclosed in Patent Document 1, it is necessary to change the setting of the memory that permits access in advance, for example, rewriting configuration information according to the number of processors provided in the arithmetic device. is there. Further, for example, when changing the memory that permits access to each processor, the configuration information needs to be rewritten.

  The present invention has been made on the basis of the above-mentioned problem recognition. In an arithmetic unit that shares a plurality of memories with a plurality of processors, each of the plurality of processors can access the same memory without causing contention. An object of the present invention is to provide an arithmetic device capable of easily sharing a memory between processors.

  In order to solve the above-described problems, the arithmetic device of the present invention is an arithmetic device that receives a plurality of packets including information indicating the content of requested arithmetic processing and executes arithmetic processing on the input packets. A plurality of processing operations having a processing function for performing an arithmetic processing according to the content of the arithmetic processing requested in the packet, and outputting a packet after the arithmetic processing including information indicating the content of the arithmetic processing to be executed next And the processing calculation unit that stores calculation target data to be subjected to calculation processing on the packet, or data obtained as a result of execution of calculation processing on the packet. A plurality of data storage units and a packet queue for sequentially storing the packets, and each of the packets stored in the packet queue is A packet management unit that grants the right to use the data storage unit and outputs it to any one of the processing operation units, and the packet based on the information on the right to use the data storage unit assigned to the packet. And a connection switching unit that switches a connection between the processing operation unit that executes the operation process for the packet and the data storage unit that is used when the operation process for the packet is executed.

  According to the present invention, in a computing device in which a plurality of processors share a plurality of memories, it is possible to easily share the memories between the processors without causing contention of access to the same memory from the plurality of processors. The effect that the computing device which can be provided can be provided is acquired.

It is the block diagram which showed an example of schematic structure of the arithmetic unit in the 1st Embodiment of this invention. It is the flowchart which showed the process sequence of the arithmetic processing in the arithmetic unit of the 1st embodiment. It is the flowchart which showed the process sequence in which the queue control part with which the arithmetic unit of the 1st embodiment was equipped stores a packet. It is the flowchart which showed the process sequence which the queue control part with which the arithmetic unit of the 1st embodiment was provided gives the right to use work memory. It is the flowchart which showed the process sequence which the queue control part with which the arithmetic unit of the 1st embodiment was equipped manages the output of the packet stored in the queue. It is the flowchart which showed the process sequence in which the processor with which the arithmetic unit of the 1st embodiment was provided performs a calculation process. It is the flowchart which showed the process sequence in which the reentry determination part with which the arithmetic unit of the 1st embodiment was equipped stores a packet again. It is the figure which showed an example of the state of the queue in each process step in the operation | movement of the arithmetic unit of this 1st Embodiment, and the packet in a work memory. It is the figure which showed an example of the state of the packet in a queue and a work memory in each process step in operation | movement of the arithmetic unit of the 2nd Embodiment of this invention. It is the figure which showed an example of the state of the queue in each process step in the operation | movement of the arithmetic unit of the 3rd Embodiment of this invention, and the work memory. It is the block diagram which showed an example of schematic structure of the arithmetic unit in the 4th Embodiment of this invention. It is the block diagram which showed an example of schematic structure of the arithmetic unit in the 5th Embodiment of this invention. It is the flowchart which showed the process sequence which the queue control part with which the arithmetic unit of the 5th Embodiment was provided gives the right to use a work memory. It is the flowchart which showed the process sequence which the queue control part with which the arithmetic unit of the 5th Embodiment was equipped manages the output of the packet stored in the queue. It is the flowchart which showed the process sequence in which the processor with which the arithmetic unit of the 5th Embodiment was provided performs a calculation process. It is the flowchart which showed the process sequence in which the reentry determination part with which the arithmetic unit of the 5th Embodiment was equipped stores a packet again. It is the figure which showed an example of the state of the queue in each process step in the operation | movement of the arithmetic unit of this 5th Embodiment, and the packet in a work memory. It is the figure which showed an example of the state of the packet in a queue and a work memory in each process step in operation | movement of the arithmetic unit of the 6th Embodiment of this invention. It is the figure which showed an example of the state of the packet in a queue and a work memory in each process step when priority differs in operation | movement of the arithmetic unit of this 6th Embodiment.

<First Embodiment>
A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an example of a schematic configuration of the arithmetic device according to the first embodiment. 1 includes a packet management unit 20, three processors 31 to 33, three local memories 311 to 331, a connection switching unit 40, and a work memory 50. Yes. FIG. 1 also shows an external block 100 connected to the arithmetic device 10.

  In the following description, when each of the three processors 31 to 33 is expressed without distinction, it is referred to as “processor 30”. Further, in the following description, when each of the three local memories 311 to 331 is expressed without being distinguished, it is referred to as “local memory 300”.

  The external block 100 outputs a packet representing the content of the arithmetic processing requested to the arithmetic device 10 to the arithmetic device 10. The packet output from the external block 100 to the arithmetic unit 10 includes “calculation target data” that is a target of arithmetic processing by the processor 30, “processor number” that defines the processor 30 that performs arithmetic processing on the packet, and the processor 30. The “work memory number” that defines the storage area (hereinafter referred to as “work area”) in the work memory 50 used in the above arithmetic processing, the behavior in each arithmetic processing, and the processing code held in the local memory 300 This information includes a “processing number” associated with one to one. Further, the packet includes “packet state information” used to represent the state of the arithmetic processing for the packet in the arithmetic unit 10. The packet status information includes “unprocessed” indicating that the processor 30 has not been subjected to the arithmetic processing once, “process continuation” indicating that the packet is to be taken over by the next processor 30, Alternatively, it is information indicating one of the states of “processing completed” indicating that the arithmetic processing for the packet is completed by the processor 30, that is, indicating that the packet has been subjected to a series of arithmetic processing by the arithmetic device 10. The processing code describes the calculation contents for the calculation target data, the packet status information, and the update contents of the processor number. Each processor 30 included in the calculation device 10 calculates the calculation target data according to the processing code. In addition, the packet status information and the processor number are updated.

  The arithmetic device 10 is a distributed parallel processing type arithmetic device that executes arithmetic processing of a plurality of packets output from the external block 100 in a shared manner by the three processors 31 to 33.

  The packet management unit 20 temporarily stores each of the plurality of packets input from the external block 100 and assigns each stored packet to any one of the processors 30. Thereby, the arithmetic unit 10 can execute a plurality of arithmetic processes requested from the external block 100 in parallel. The packet management unit 20 assigns each packet to the processor 30 defined by the processor number based on the processor number included in each stored packet. At this time, when the packet management unit 20 assigns each stored packet to any one of the processors 30, the situation as to whether or not the work area defined by the work memory number included in each packet can be used; It is confirmed whether or not the processor 30 defined by the processor number included in the packet is executing another calculation process. That is, the packet management unit 20 checks the usage status of each work area in the work memory 50 and the usage status of the processor 30. Then, the packet management unit 20 gives the right to use the work area to the packet in which the processor 30 can use the work area, and the processor 30 can accept the packet. Output to 30.

  Each of the processors 31 to 33 is assigned to the packet management unit 20, that is, the arithmetic processing for the operation target data included in the packet input from the packet management unit 20 is stored in the corresponding local memory 300. It is a processing operation part to be executed based on the code. When each processor 30 executes an arithmetic process on a packet, first, a work area in the work memory 50 defined by a work memory number included in the input packet, that is, a usage right is given. The connection switching unit 40 switches the connection between the work area and itself. Then, after the work area to which the right of use is given is connected, the work area is used to perform arithmetic processing on the operation target data.

  Then, each of the processors 30 outputs, to the packet management unit 20, a packet for which the arithmetic processing on the operation target data of the packet input this time has been completed. At this time, each of the processors 30 outputs a packet in which information indicating “processing complete” is set in the packet status information when outputting a packet for which a series of arithmetic processing by the arithmetic device 10 has been completed to the packet management unit 20. Output to the packet management unit 20.

  In addition, when each processor 30 outputs a packet that causes another processor 30 or itself to execute the next calculation process to the packet management unit 20 after the execution of the calculation process, the processor 30 includes “processing”. A packet in which information indicating “continuation” is set is output to the packet management unit 20 as the next packet. At this time, the next packet output from the processor 30 to the packet management unit 20 includes “operation target data”, “processor number”, “work memory” in the same manner as the packet output from the external block 100 to the arithmetic unit 10. “Number” and “processing number” are included. In the following description, the next packet output from the processor 30 to the packet management unit 20 is also referred to as a packet.

  In addition, each of the processors 30 continues to another processor 30 or itself after the next processor 30 or another processor 30 or the processor 30 itself that has been subjected to the previous computation process is executed. When outputting a packet for executing the next arithmetic processing to the packet management unit 20, a packet in which information indicating “process continuation” is set in the packet status information is output again to the packet management unit 20 as the next packet. .

  The arithmetic processing for the packet in each processor 30 is completed by outputting to the packet management unit 20 a packet whose packet status information includes “processing complete” or “processing continuation”. That is, the processor 30 that has output the packet to the packet management unit is ready to receive the next packet.

  Each of the local memory 311 to the local memory 331 holds a processing code that defines the behavior of the corresponding processor 30. The local memory 300 reads the processing code corresponding to the processing number included in the packet for each processing when the corresponding processor 30 executes the arithmetic processing on the calculation target data included in the packet. 1, the local memory 311 corresponds to the processor 31, the local memory 321 corresponds to the processor 32, and the local memory 331 corresponds to the processor 33, respectively.

  The connection switching unit 40 is configured so that each processor 30 and the work area in the work memory 50 used when each of the processors 30 executes calculation processing on the calculation target data have a one-to-one correspondence. The connection between and the work area. Further, the connection switching unit 40 switches between the address of the work area accessed by the processor 30 and the address actually accessed. As a result, each processor 30 executes the arithmetic processing without considering (addressing) the address of the work area, regardless of which work area is used to execute the arithmetic processing on the calculation target data. be able to.

  The work memory 50 includes a plurality of work areas for temporarily storing calculation target data included in each packet, data generated while each of the processors 30 is executing calculation processing on the calculation target data, and the like. Further, for example, a memory such as SRAM (Static Random Access Memory), a so-called cache memory. The configuration of the arithmetic device 10 shown in FIG. 1 shows a work memory 50 having five work areas (work area 501 to work area 505). In the following description, when each of the five work areas 501 to 505 is expressed without being distinguished, it is referred to as a “work area 500”.

  With such a configuration, the arithmetic device 10 executes a series of arithmetic processing for a plurality of packets input from the external block 100 in a shared manner by the respective processors 30. Here, the configuration of the arithmetic device 10, in particular, the packet management unit 20 and the connection switching unit 40 will be described in more detail.

  First, the packet management unit 20 will be described in more detail. As described above, the packet management unit 20 temporarily stores each of the plurality of packets input from the external block 100 and assigns each stored packet to any one processor 30. The packet management unit 20 includes a packet queue 210, a queue control unit 220, a reentry determination unit 230, a work memory usage status management register 240, and a processor usage status management register 250.

  The packet queue 210 sequentially stores a plurality of packets input from the external block 100 and a packet that is subsequently input from the re-entry determination unit 230 and that is subjected to arithmetic processing in accordance with control from the queue control unit 220. Packet queue memory. Each packet input from the external block 100 and the reentry determination unit 230 is sequentially stored in the packet queue 210 in the input order. Further, the packet queue 210 outputs the stored packet to any one of the processors 30 in accordance with control from the queue control unit 220. The packets stored in the packet queue 210 are basically output in the order in which they are stored. In the arithmetic device 10, the queue control unit 220 outputs the packets stored in the packet queue 210. To control.

  FIG. 1 shows a configuration of a packet queue 210 having five storage areas (storage areas 211 to 215) for storing packets. In FIG. 1, the numbers following “# (sharp)” shown in the respective storage areas in the packet queue 210 indicate the order in which packets are stored in the packet queue 210. In FIG. 1, the packet # 1 that is first input to the packet queue 210, that is, the top packet is stored in the storage area 211, and each time a packet is input to the packet queue 210, the storage area 212 is stored. A state is shown in which the packet # 5 that is sequentially stored in the area 213 and the storage area 214 and is finally input to the packet queue 210, that is, the last packet is stored in the storage area 215.

  The queue control unit 220 receives a calculation processing request from the external block 100 and controls the storage (entry) of a packet corresponding to the received calculation processing request in the packet queue 210. When a packet output permission request is input from the external block 100, that is, when a signal requesting arithmetic processing is input from the external block 100, the queue control unit 220 stores the five storage areas included in the packet queue 210. The availability status is confirmed, and when the storage area in the packet queue 210 is available, a permission signal notifying that the output of the packet is permitted is output to the external block 100. Further, the queue control unit 220 outputs a non-permission signal notifying that the output of the packet cannot be permitted to the external block 100 when the storage area in the packet queue 210 is not empty. As a result, the external block 100 outputs a packet corresponding to the permitted arithmetic processing request to the packet queue 210.

  Further, the queue control unit 220 controls the output of the packets stored in the packet queue 210 to the processor 30 according to the usage status of the processor 30 and the work memory 50. At this time, the queue control unit 220 sequentially confirms the work memory number included in each packet stored in the packet queue 210, and determines each packet according to the usage status of each work area 500 in the work memory 50. Is given the right to use the work area 500. In addition, the queue control unit 220 sequentially checks the processor number included in each packet to which the right to use the work area 500 is granted, and outputs the processor number to the processor 30 according to the usage status of the processor 30 that performs arithmetic processing on the packet. Select the packet to be used. Then, the queue control unit 220 causes the packet 30 selected from the packet queue 210 to output the selected packet as the packet to be output to the processor 30.

  More specifically, first, the queue control unit 220 determines the use status of the work area 500 in the work memory 50 defined by the work memory number included in each packet stored in the packet queue 210 as the work memory use. Confirmation is made from information in the work memory management register in the status management register 240. As a result of checking the information of the work memory management register, when the work area 500 defined by the work memory number can be used, that is, when the information of the work memory management register is “unused”, The queue control unit 220 grants the right to use the work area 500. Then, the queue control unit 220 changes the information in the work memory management register 240 in the work memory use status management register 240 corresponding to the work memory number included in the packet to which the work area 500 is granted the right to use to “in use”. .

  When the queue control unit 220 grants the right to use the work area 500 to the packet, the packet near the head of the packets to which the right to use the work area 500 stored in the packet queue 210 is not granted. (In FIG. 1, for example, packet # 1), work memory numbers are confirmed in order, and the right to use the work area 500 is given.

  Subsequently, the queue control unit 220 displays the usage status of the processor 30 determined by the processor number included in each packet to which the usage right of the work area 500 is given, as a corresponding processor management in the processor usage status management register 250. Check from the register information. As a result of checking the information of the processor management register, when the processor 30 determined by the processor number can accept a packet, that is, when the information of the processor management register is “unused”, the queue control unit 220 determines that this packet is a packet that can be output to the processor 30, and selects this packet as a packet to be output to the processor 30 next. Then, the queue control unit 220 changes the information “in use” in the processor management register in the processor usage status management register 250 corresponding to the processor 30 defined by the processor number included in the selected packet.

  When the queue control unit 220 selects a packet to be output to the processor 30 next, a packet near the top of the packets to which the right to use the work area 500 stored in the packet queue 210 is granted (see FIG. 1, for example, processor numbers are confirmed in order from packet # 1), and the corresponding processor 30 selects a packet that is not being executed for another packet.

  Thereafter, the queue control unit 220 instructs the packet queue 210 to output a packet to the processor 30 defined by the processor number included in the selected packet. As a result, the packet queue 210 outputs the instructed packet to the corresponding processor 30, and the processor 30 executes a calculation process on the calculation target data of the input packet.

  The reentry determination unit 230 controls the output destination of the packet after the arithmetic processing input from the processor 30. At this time, the re-entry determination unit 230 switches the output destination of the packet after the arithmetic processing based on the packet state information of the packet after the arithmetic processing input from the processor 30. Then, the re-entry determination unit 230 changes the information of the processor management register in the processor usage status management register 250 and the information of the work memory management register in the work memory usage status management register 240 corresponding to the packet after the arithmetic processing. To do.

  More specifically, when the packet status information of the packet after the arithmetic processing input from the processor 30 indicates “processing completed”, the reentry determination unit 230 sets the packet after the arithmetic processing to the external block 100. Output to. Then, the re-entry determination unit 230 changes the information of the processor management register in the processor usage status management register 250 corresponding to the post-computation packet output to the external block 100 to “unused”, and further to this packet. The information of the work memory management register in the corresponding work memory use status management register 240 is changed to “unused”. As a result, the queue control unit 220 can allocate the next packet stored in the packet queue 210 to the processor 30, that is, perform packet distribution.

  In addition, when the packet status information of the packet after the arithmetic processing input from the processor 30 indicates “processing continuation”, the re-entry determination unit 230 stores the packet after the arithmetic processing in the packet queue 210 again ( Entry). Then, the re-entry determination unit 230 changes the information in the processor management register in the processor usage status management register 250 corresponding to the packet after the arithmetic processing stored (entry) again in the packet queue 210 to “unused”. As a result, the queue control unit 220 can again allocate the post-computation packet stored in the packet queue 210 to the processor 30 and continue the computation process on the post-computation packet.

  The work memory usage status management register 240 corresponds to each of the work areas 501 to 505 in the work memory 50 provided in the arithmetic device 10 and holds information indicating the usage status of the corresponding work area 500. The configuration of the arithmetic unit 10 shown in FIG. 1 includes five work memory management registers (work memory management registers 241 to 245) corresponding to five work areas (work areas 501 to 505). A work memory use status management register 240 is shown.

  More specifically, the work memory management register 241 holds information indicating the usage status of the work area 501. Also, the work memory management register 242 holds information indicating the usage status of the work area 502, the work memory management register 243 holds information indicating the usage status of the work area 503, and the work memory management register 244 stores the information indicating the usage status of the work area 504. Information indicating the usage status is held, and the work memory management register 245 holds information indicating the usage status of the work area 505. Each work memory management register holds information indicating that the corresponding work area 500 is “unused” when the corresponding work area 500 is not used by any processor 30. Information indicating that the processor 30 is “in use”.

  The queue control unit 220 and the re-entry determination unit 230 constantly check the respective work memory management registers in the work memory use status management register 240, so that each work area 500 in the work memory 50 provided in the arithmetic device 10 is obtained. Always monitor the usage status. Each work memory management register in the work memory usage status management register 240 can be read and written by the queue control unit 220 and the re-entry determination unit 230. More specifically, the queue control unit 220 corresponds to the work area 500 that gives the use right to the packet when the use right of the work area 500 is given to each packet stored in the packet queue 210. Change the information in the work memory management register to “in use”. In addition, when the reentry determination unit 230 releases the use right of the work area 500 given to the packet after the arithmetic processing input from the processor 30, the work corresponding to the work area 500 that releases the use right of the packet. Change the information in the memory management register to “unused”.

  In each work memory management register, a value representing the processor 30 that executes arithmetic processing on a packet is written to indicate “in use”. For example, when the processor 32 grants the right to use the work area 504 to a packet for executing arithmetic processing, a value representing the processor 32 is written in the work memory management register 244 corresponding to the work area 504. Thus, the work memory management register 244 can indicate that the work area 504 is “in use” by the processor 32. In addition, a value that does not represent any processor 30 (for example, “0”) is written in each work memory management register to indicate “unused”.

  The processor usage status management register 250 corresponds to each of the processors 30 included in the arithmetic device 10 and holds information indicating the usage status of the corresponding processor 30. In the configuration of the arithmetic unit 10 shown in FIG. 1, a processor usage status management register including three processor management registers (processor management register 251 to processor management register 253) corresponding to three processors 30 (processor 31 to processor 33). 250 is shown.

  More specifically, the processor management register 251 holds information indicating the usage status of the processor 31. The processor management register 252 holds information indicating the usage status of the processor 32, and the processor management register 253 holds information indicating the usage status of the processor 33. Each processor management register holds information indicating that the corresponding processor 30 is “unused” when the corresponding processor 30 is not performing arithmetic processing on any packet. When the arithmetic processing for is performed, information indicating “in use” is held.

  The queue control unit 220 and the re-entry determination unit 230 constantly monitor the usage status of each processor 30 included in the arithmetic device 10 by constantly checking the respective processor management registers in the processor usage status management register 250. Each processor management register in the processor usage status management register 250 can be read and written by the queue control unit 220 and the re-entry determination unit 230. More specifically, when the queue control unit 220 instructs the packet queue 210 to output the selected packet to the processor 30, the processor management corresponding to the processor 30 defined by the processor number included in the packet to be output. Change the register information to “In Use”. In addition, when a post-computation packet is input from the processor 30, the re-entry determination unit 230 changes the information in the processor management register corresponding to the processor 30 that has performed the computation process on the packet to “unused”.

  Note that the processor management register may include information representing the work area 500 used when the processor 30 executes arithmetic processing. For example, when the work area 504 is used when the processor 32 executes arithmetic processing, a value representing the work area 504 is written in the processor management register 252 corresponding to the processor 32. Accordingly, the processor management register 252 can indicate that the processor 32 is “in use” in order to execute the arithmetic processing using the work area 504.

  With such a configuration, the packet management unit 20 outputs a plurality of packets input from the external block 100 and a packet after arithmetic processing input from the processor 30 to the processor 30 or output to the external block 100. The management is performed according to two states of “in use” or “not in use” of all the processors 30 and all the work memories 50.

  Next, the connection switching unit 40 will be described in more detail. As described above, the connection switching unit 40 has a one-to-one correspondence between each processor 30 and the work area 500 in the work memory 50 used when each of the processors 30 executes a calculation process on the calculation target data. Thus, the connection between the processor 30 and the work area 500 is switched. The connection switching unit 40 includes an address conversion unit 401 to an address conversion unit 403 and a crossbar switch 450.

  Each of the address conversion unit 401 to the address conversion unit 403 corresponds to each of the three processors 31 to 33 provided in the calculation device 10, and the corresponding processor 30 executes calculation processing on the calculation target data included in the packet. The address that designates the work area 500 to be used at the time and the address of the work area 500 in the work memory 50 that is actually used are associated one-to-one. In the following description, when each of the three address conversion units 401 to 403 is expressed without distinction, it is referred to as an “address conversion unit 400”.

  More specifically, each address conversion unit 400 includes a table in which a work memory number and a work area 500 in the work memory 50 are associated with each other on a one-to-one basis. Each address conversion unit 400 refers to a table corresponding to a work memory number included in a packet for which the corresponding processor 30 executes arithmetic processing, and specifies a work area 500 used by the corresponding processor 30. Furthermore, each address conversion unit 400 actually accesses the work area 500 in the work memory 50 using the logical address when the corresponding processor 30 accesses the work area 500 based on the information of the specified work area 500. Is converted to a physical address. Thereby, each processor 30 is the same regardless of which work area 500 is used without considering (without being aware of) the physical address of the work area 500 used when performing arithmetic processing on a packet. Arithmetic processing can be executed. That is, each processor 30 can access with the same logical address regardless of which work area 500 is used.

  For example, in the configuration of the arithmetic unit 10 shown in FIG. 1, the physical address 0x1000-0x1FFF is in the work area 501 in the work memory 50, the physical address 0x2000-0x2FFF is in the work area 502, and the physical address 0x3000-0x3FFF is in the work area 503. However, a case is considered where physical addresses 0x4000 to 0x4FFF are assigned to the work area 504 and physical addresses 0x5000 to 0x5FFF are assigned to the work area 505, respectively. At this time, for example, the address conversion unit 401 converts the logical address 0x0000 to 0x0FFF when the processor 31 accesses the work area 500 into the physical address 0x2000 to 0x2FFF of the work area 502, so that the processor 31 50 can actually access the work area 502 within the.

  In this way, each address conversion unit 400 converts the logical address when the corresponding processor 30 accesses the work area 500 into the physical address of the actual work area 500, so that each processor 30 Even when the work area 500 is accessed, the same logical address 0x0000 to 0x0FFF can be accessed.

  Each address conversion unit 400 includes a table in which control values of the crossbar switch 450 for connecting the corresponding processor 30 and the work area 500 in the work memory 50 in a one-to-one relationship. Then, each address conversion unit 400 determines the control value of the crossbar switch 450 by referring to a table that summarizes the control values based on the work memory number included in the packet for which the corresponding processor 30 executes the arithmetic processing. The determined control value is output to the crossbar switch 450.

  The crossbar switch 450 is a signal line used when each of the three processors 31 to 33 provided in the arithmetic device 10 accesses the work area 500, and when each of the processors 31 to 33 performs arithmetic processing on a packet. It is a switch that connects the signal lines of the five work areas 501 to 505 in the work memory 50 to be used in a one-to-one relationship. The crossbar switch 450 switches the connection between the signal line of each processor 30 and the signal line of each work area 500 according to the control value input from each of the address conversion units 400.

  With this configuration, the connection switching unit 40 has a one-to-one correspondence between each processor 30 and the work area 500 in the work memory 50 that is used when each processor 30 executes a calculation process on the calculation target data. Make it correspond.

  Next, a processing procedure of arithmetic processing by the arithmetic device 10 will be described. FIG. 2 is a flowchart illustrating the processing procedure of the arithmetic processing in the arithmetic device 10 according to the first embodiment. FIG. 2 shows an overall processing procedure of the arithmetic device 10. In the description of FIG. 2, the overall processing flow of the arithmetic processing executed by the arithmetic device 10 will be described, and detailed processing procedures of each will be described later.

  When a packet output permission request is input from the external block 100, that is, when an arithmetic processing request is input from the external block 100, the arithmetic device 10 performs arithmetic processing on a packet corresponding to the input arithmetic processing request. To start. First, in step S1, the queue control unit 220 in the packet management unit 20 receives a calculation processing request from the external block 100 and temporarily stores (entries) a packet corresponding to the calculation processing request in the packet queue 210. The first entry processing is performed.

  Subsequently, in step S <b> 2, the queue control unit 220 performs usage right grant processing for granting the right to use the work area 500 in the work memory 50 to the packets stored in the packet queue 210. Subsequently, in step S <b> 3, the queue control unit 220 performs a queue management process for outputting a packet to which the right to use the work area 500 stored in the packet queue 210 is granted to the corresponding processor 30.

  Subsequently, in step S4, the processor 30 to which the packet is input from the packet management unit 20 executes arithmetic processing on the input packet. Subsequently, in step S <b> 5, the reentry determination unit 230 in the packet management unit 20 performs reentry determination processing for determining an output destination according to the packet state information of the packet after the arithmetic processing input from the processor 30.

  Subsequently, in step S <b> 6, the queue control unit 220 confirms whether the arithmetic processing for all the packets input from the external block 100 has been completed. If the calculation processing for all the packets is not completed by the confirmation in step S6 (“NO” in step S6), the processing returns to step S2 and the processing for other packets is continued. Further, when the calculation processing for all the packets is completed by the confirmation in step S6 (“YES” in step S6), the processing in the calculation device 10 is completed.

  In the flowchart of the overall processing flow in the arithmetic device 10 shown in FIG. 2, each processing is shown to be performed sequentially, but each component provided in the arithmetic device 10 is different from each other. Always going. That is, each process in the arithmetic unit 10 shown in the flowchart of FIG. 2 is a process performed in parallel.

  Next, a processing procedure of the first entry process (step S1 shown in FIG. 2) by the queue control unit 220 in the packet management unit 20 provided in the arithmetic device 10 will be described. FIG. 3 is a flowchart showing the processing procedure of the first entry process in which the queue control unit 220 included in the arithmetic device 10 according to the first embodiment stores a packet.

  When starting the first entry process, the queue control unit 220 first determines in step S11 whether there is a packet output permission request from the external block 100, that is, whether there is a calculation processing request from the external block 100. Confirm. In step S11, when there is no packet output permission request from the external block 100 (“NO” in step S11), the queue control unit 220 completes the first entry process.

  If there is a packet output permission request from the external block 100 in step S11 (“YES” in step S11), the queue control unit 220 in step S12 determines the number of packets already stored in the packet queue 210. It is checked whether or not the number of packets (hereinafter referred to as “number of packets already entered”) is smaller than a predetermined maximum number of packets that can be stored in the packet queue 210 (hereinafter referred to as “maximum number of entries”). The maximum number of entries is a value determined in advance based on the number of storage areas in the packet queue 210 provided in the arithmetic device 10 and the number of processors 30 provided in the arithmetic device 10.

  In step S12, when the number of entered packets is equal to or greater than the maximum number of entries (number of entered packets ≧ maximum number of entries) (“NO” in step S12), in step S13, the queue control unit 220 outputs the packet. Is output to the external block 100, and the first entry process is completed.

  In step S12, when the number of packets that have been entered is smaller than the maximum number of entries (number of packets that have been entered <maximum number of entries) (“YES” in step S12), in step S14, the queue control unit 220 Is output to the external block 100, and a packet from the external block 100 is received. Then, the queue control unit 220 sets information indicating “unprocessed” in the packet status information of the packet input this time from the external block 100.

  Subsequently, in step S15, the queue control unit 220 sets the information indicating “unprocessed” in the packet status information, and the packet input this time from the external block 100 is already stored in the packet queue 210. Storage (entry) in the storage area next to the current storage area, that is, the current storage area at the tail end, and the first entry process is completed.

  Through such processing, the queue control unit 220 temporarily stores (entries) each of the plurality of packets input from the external block 100 in the packet queue 210. The queue control unit 220 always performs the initial entry process. That is, the queue control unit 220 always monitors the output permission request of the packet output from the external block 100 and performs the initial entry process while the arithmetic device 10 is operating. For this reason, for example, in step S12, when the number of entered packets <the maximum number of entries (“YES” in step S12), the queue control unit 220 sends a permission signal to notify that the packet output is permitted. It can also be configured to output to the external block 100.

  Next, the processing procedure of the right to use the work area 500 in the work memory 50 (step S2 shown in FIG. 2) by the queue control unit 220 in the packet management unit 20 provided in the arithmetic device 10 will be described. FIG. 4 is a flowchart illustrating a processing procedure of a usage right granting process in which the queue control unit 220 included in the arithmetic device 10 according to the first embodiment grants the usage right of the work area 500 in the work memory 50.

  When the queue control unit 220 starts the usage right granting process, first, in step S21, among the work areas 500 in the work memory 50, the work area 500 that can be used for packet calculation processing, that is, the unprocessed area is not yet stored. It is confirmed whether or not there is a work area 500 to be used. More specifically, the queue control unit 220 confirms information on each work memory management register in the work memory use status management register 240, and creates a work area 500 in which the information on the work memory management register is “unused”. Search for. In step S21, when there is no unused work area 500 (“NO” in step S21), the queue control unit 220 completes the usage right granting process.

  If there is an unused work area 500 in step S21 (“YES” in step S21), in step S22, the queue control unit 220 uses the work area 500 in a packet already stored in the packet queue 210. Check if there is a packet to which no right is granted. In step S22, when there is no packet to which the use right of the work area 500 is not granted (“NO” in step S22), the queue control unit 220 completes the use right grant process.

  If there is a packet to which the right to use the work area 500 is not granted in step S22 (“YES” in step S22), in step S23, the queue control unit 220 checks the work area 500 confirmed in step S22. The right to use the work area 500 is granted to the packet closest to the head of the packet queue 210 among the packets to which no right to use is assigned. In addition, the queue control unit 220 updates the information in the work memory management register 240 in the work memory use status management register 240 corresponding to the work area 500 to which the usage right is given to the packet to information indicating “in use”. Complete the authorization process.

  Through such processing, the queue control unit 220 confirms the unused work area 500 from the information in the work memory management register in the work memory usage status management register 240, and a packet to which the right to use the work area 500 is not granted. The right to use the work area 500 is granted. Note that the queue control unit 220 always performs use right grant processing. In other words, the queue control unit 220 always searches for an unused work area 500 and performs a usage right granting process while packets are stored in the packet queue 210. Thereby, the queue control unit 220 grants the right to use the work area 500 to other packets at an early timing after any work area 500 in the work memory 50 can be used. Can do.

  Next, a processing procedure of queue management processing (step S3 shown in FIG. 2) by the queue control unit 220 in the packet management unit 20 provided in the arithmetic device 10 will be described. FIG. 5 is a flowchart illustrating a processing procedure of a queue management process in which the queue control unit 220 included in the arithmetic device 10 according to the first embodiment manages the output of the packets stored in the packet queue 210 to the processor 30. It is.

  When the queue control unit 220 starts the queue management process, first, in step S31, the processor 30 that can execute the packet calculation process among the processors 30 included in the calculation apparatus 10, that is, an unused one. It is confirmed whether or not there is a processor 30. More specifically, the queue control unit 220 confirms information of each processor management register in the processor usage status management register 250 and searches for a processor 30 whose information in the processor management register is “unused”. In step S31, when there is no unused processor 30 (“NO” in step S31), the queue control unit 220 completes the queue management process.

  If there is an unused processor 30 in step S31 (“YES” in step S31), the queue control unit 220 grants the right to use the work area 500 stored in the packet queue 210 in step S32. It is confirmed whether or not there is a packet in which the unused processor 30 searched in step S31 is determined as the processor 30 that executes the arithmetic processing among the packets that have been searched. More specifically, the queue control unit 220 determines the processor number included in the packet to which the right to use the work area 500 is granted, thereby determining that the unused processor 30 executes the arithmetic processing. Search for packets that have been sent. In step S32, when there is no packet defined as the processor 30 that causes the unused processor 30 to execute the arithmetic processing (“NO” in step S32), the queue control unit 220 completes the queue management process.

  In step S32, when there is a packet defined as the processor 30 that causes the unused processor 30 to execute arithmetic processing (“YES” in step S32), in step S33, the queue control unit 220 performs step Among the packets determined as the processor 30 that the unused processor 30 confirmed in S32 executes the arithmetic processing, the packet closest to the head of the packet queue 210 is output to the corresponding processor 30. In addition, the queue control unit 220 updates the processor management register information in the processor usage status management register 250 corresponding to the packet output to the processor 30 to information indicating “in use”, and completes the queue management process.

  By such processing, the queue control unit 220 confirms the unused processor 30 from the information of the processor management register in the processor usage status management register 250, and determines that the unused processor 30 executes the arithmetic processing. The received packet is output to the corresponding processor 30. The queue control unit 220 always performs queue management processing. In other words, the queue control unit 220 always searches for unused processors 30 and performs queue management processing while packets are stored in the packet queue 210. Accordingly, the queue control unit 220 can output the corresponding packet at an early timing after any of the processors 30 included in the arithmetic device 10 can accept the packet.

  Next, the processing procedure of the arithmetic processing (step S4 shown in FIG. 2) by the processor 30 provided in the arithmetic device 10 will be described. FIG. 6 is a flowchart illustrating a processing procedure in which the processor 30 included in the arithmetic device 10 according to the first embodiment executes arithmetic processing.

  When a corresponding packet is input from the packet queue 210 in the packet management unit 20, the processor 30 starts arithmetic processing. First, in step S41, the processor 30 acquires a work memory number included in the input packet. That is, information on the work area 500 that is used when performing arithmetic processing on the input packet is acquired.

  Subsequently, in step S <b> 42, the processor 30 outputs the acquired work memory number to the corresponding address conversion unit 400 in the connection switching unit 40. As a result, the corresponding address conversion unit 400 uses the processor 30 by referring to the table in which the work memory number and the work area 500 corresponding to the work memory number input from the processor 30 are associated with each other. The work area 500 to be specified is specified. Further, the corresponding address conversion unit 400 refers to a table that summarizes the control values of the crossbar switch 450 that connects the processor 30 and the work area 500 in the work memory 50 in a one-to-one relationship, and determines the control value of the crossbar switch 450. The determined control value is output to the crossbar switch 450. As a result, the crossbar switch 450 switches the connection between the signal line of the processor 30 and the signal line of the work area 500 according to the control value input from the address conversion unit 400, and the processor 30 and the work area 500 are paired. Connect to 1. The address conversion unit 400 notifies the corresponding processor 30 of a notification indicating that the connection of the work area 500 is completed after the switching of the connection between the processor 30 and the work area 500 by the crossbar switch 450 is completed.

  Subsequently, in step S43, the processor 30 transfers the entire input packet to the corresponding work area 500 via the corresponding address conversion unit 400 and the crossbar switch 450.

  Subsequently, in step S44, the processor 30 reads the processing code corresponding to the processing number included in the packet transferred to the work area 500 from the local memory connected to the processor 30, and executes the arithmetic processing on the operation target data. To do.

  Then, after completing the calculation process on the calculation target data, in step S45, the processor 30 updates the packet state information and the processor number of the packet after the calculation process. More specifically, when the packet after the arithmetic processing is a packet that takes over the arithmetic processing, the packet status information of the packet after the arithmetic processing is updated to “continue processing”, and the processor number is continuously calculated. The processor number of the next processor 30 (another processor 30 or itself) to be executed is updated. If the packet after the arithmetic processing is a packet that is output to the external block 100 when the arithmetic processing is completed, the packet status information of the packet after the arithmetic processing is updated to “processing complete”.

  In the processing code, the calculation contents for the calculation target data, the packet status information, and the update contents of the processor number are described by logical addresses. When the address conversion unit 400 accesses the work area 500, the processor 30 accesses the work area 500. The logical address is converted into a physical address when the corresponding work area 500 is accessed. Thereby, the processor 30 can implement | achieve the calculation process with respect to the calculation object data of step S44, and the update of the packet status information and processor number of step S45.

  Subsequently, when the calculation process for the calculation target data (step S44) and the update of the packet state information and the processor number (step S45) are completed, in step S46, the processor 30 has a packet after the calculation process to be output. Is sent to the re-entry determination unit 230 in the packet management unit 20. The re-entry determination unit 230 outputs a notification indicating that the packet is accepted to the processor 30 when the packet after the arithmetic processing can be acquired.

  When the processor 30 receives from the re-entry determination unit 230 a notification indicating that the packet after the arithmetic processing is accepted, in step S47, the packet status information of the post-computation packet output to the re-entry determination unit 230 is “ It is confirmed whether it is “Continue processing”.

  In step S47, when the packet status information of the post-computation packet output to the re-entry determination unit 230 is not “processing continuation” (“NO” in step S47), that is, the packet status information is “processing complete”, If the packet is to be output to the external block 100, in step S48, the processor 30 outputs the entire packet after the arithmetic processing to the reentry determination unit 230 via the crossbar switch 450 and the corresponding address conversion unit 400. , The arithmetic processing is completed.

  In step S47, when the packet status information of the packet after the calculation process output to the re-entry determination unit 230 is “processing continuation” (“YES” in step S47), that is, the packet after the calculation process is calculated. In step S49, the processor 30 sends a packet other than the next calculation target data finally stored in the work area 500 via the crossbar switch 450 and the corresponding address conversion unit 400. Is output to the re-entry determination unit 230 to complete the arithmetic processing.

  By such processing, the processor 30 executes a calculation process on the calculation target data using the work area 500 corresponding to the input packet. Then, the processor 30 updates the packet state information of the packet after the arithmetic processing and outputs it to the re-entry determination unit 230. At this time, the processor 30 changes the configuration of the packet output to the reentry determination unit 230 according to the packet state information of the packet after the arithmetic processing. More specifically, when the packet status information of the packet after the arithmetic processing is “processing completed”, the entire packet after the arithmetic processing is output to the re-entry determination unit 230, and the packet status of the packet after the arithmetic processing is When the information is “process continuation”, the packet after the calculation process other than the calculation target data is output to the re-entry determination unit 230. As a result, when the packet after the calculation process is a packet that takes over the calculation process, the calculation target data to be subjected to the next calculation process is stored (remaining) in the work area 500, and this calculation target The processor 30 that performs the next arithmetic processing on the data can reduce the time required to transfer the entire packet to the work area 500 in step S43.

  Next, the procedure of the reentry determination process (step S5 shown in FIG. 2) by the reentry determination unit 230 in the packet management unit 20 provided in the arithmetic device 10 will be described. FIG. 7 is a flowchart illustrating a processing procedure of reentry determination processing in which the reentry determination unit 230 included in the arithmetic device 10 according to the first embodiment stores the packet again.

  When the re-entry determination unit 230 starts the re-entry determination process, first, in step S51, the processor 30 determines whether or not there is a notification indicating that there is a packet after the arithmetic processing, that is, after the arithmetic processing from the processor 30. Check whether there is a request for permission to output other packets. In step S51, when there is no output permission request for the packet after the arithmetic processing from the processor 30 (“NO” in step S51), the reentry determination unit 230 completes the reentry determination process.

  In step S51, when there is an output permission request for the packet after the arithmetic processing from the processor 30 (“YES” in step S51), the reentry determination unit 230 acquires the packet after the arithmetic processing from the processor 30. Then, the information of the processor management register in the processor usage status management register 250 corresponding to the acquired packet after the arithmetic processing is updated to information indicating “unused”. In step S <b> 52, the reentry determination unit 230 confirms whether or not the packet state information of the post-computation packet input from the processor 30 is “processing continuation”.

  In step S52, when the packet status information of the packet after the arithmetic processing input from the processor 30 is “processing continuation” (“YES” in step S52), that is, the packet after the arithmetic processing is a packet that takes over the arithmetic processing. If there is, in step S53, the re-entry determination unit 230 uses the storage area next to the storage area in which the packet has already been stored in the packet queue 210, as a result of the computation process input from the processor 30 this time. That is, the current entry is stored (entry) in the last storage area, and the re-entry determination process is completed. That is, the re-entry determination unit 230 stores (entries) the packet in the packet queue 210 again while giving the right to use the work area 500 to the packet after the arithmetic processing input this time.

  In step S52, when the packet status information of the packet after the arithmetic processing input from the processor 30 is not “processing continuation” (“NO” in step S52), that is, the packet status information is “processing completed”. If the packet is to be output to the external block 100, in step S54, the re-entry determination unit 230 releases the right to use the work area 500 given to the input packet after the arithmetic processing. More specifically, the usage right of the work area 500 is updated by updating the information in the work memory management register corresponding to the packet after the arithmetic processing in the work memory usage management register 240 to information indicating “unused”. Is released.

  Subsequently, in step S55, the re-entry determination unit 230 outputs the entire packet after the arithmetic processing that releases the right to use the work area 500 to the external block 100, and completes the re-entry determination process.

  By such processing, the re-entry determination unit 230 switches the output destination of the packet after the arithmetic processing according to the packet state information of the packet after the arithmetic processing input from the processor 30. The reentry determination unit 230 always performs reentry determination processing. That is, the re-entry determination unit 230 performs a re-entry determination process by monitoring an output permission request for a packet after a calculation process that is always output from the processor 30 while the calculation device 10 is operating. In the re-entry determination process, the packet after the arithmetic process whose packet state information is “process continuation” is stored (entry) in the packet queue 210 again. For this reason, the re-entry determination unit 230 compares the number of already entered packets with the maximum number of entries, for example, similarly to step S12 in the initial entry process executed by the queue control unit 220, and determines the processor according to the comparison result. It is also possible to adopt a configuration for receiving (acquiring) packets after arithmetic processing from 30. Further, when storing (entry) the packet after the arithmetic processing in the packet queue 210 again, as in the external block 100, an output permission request for the packet after the arithmetic processing is output to the queue controller 220, and the queue controller 220 It is also possible to store (entry) the acquired packet after the arithmetic processing in the packet queue 210 after the permission signal notifying that the output of the packet is permitted is input.

  As described above, the arithmetic device 10 requests the external block 100 by constantly performing a series of arithmetic processing on a plurality of packets input from the external block 100 for each packet stored in the packet queue 210. A plurality of arithmetic processes can be executed in parallel.

<First operation>
Here, an example of the operation in the arithmetic unit 10 will be described. The operation of the arithmetic unit 10 will be described by paying attention to the packets in the packet queue 210 and the work memory 50. FIG. 8 is a diagram illustrating an example of the state of packets in the packet queue 210 and the work memory 50 at each processing stage in the operation of the arithmetic device 10 according to the first embodiment.

  FIG. 8 shows “calculation target data” and “processor number” included in each packet as the state of the packet in the work memory 50. Further, FIG. 8 shows “calculation target data”, “processor number”, “work memory number”, and “packet state information” included in each packet as the state of the packet in the packet queue 210. . In the state of each packet shown in FIG. 8, the “processor number” includes a processor 30 that executes arithmetic processing on “operation target data” included in the packet, under the symbol of each processor 30. It is indicated by a single digit. The “work memory number” includes a work area 500 used when each processor 30 executes a computation process on “calculation target data” included in the packet, under the sign of each work area 500. It is indicated by a single digit.

  In the respective states of the packet queue 210 and the packet in the work memory 50 shown in FIG. 8, the order in which the packets are stored in the packet queue 210 is included in the “packet number” item for easy explanation. Show. The packet numbers are assigned in the order in which the packets are stored in the packet queue 210, and are not changed until the arithmetic processing is completed and output to the external block 100. Further, in the state of the packet in the work memory 50, the processor 30 executing the arithmetic processing on the packet stored in each work area 500 is shown in the item “Processing Processor”.

  First, in the operation of the arithmetic unit 10, as shown in FIG. 8A, three packets are stored in the work memory 50, three packets are stored in the packet queue 210, and in the packet queue 210. The subsequent operation will be described with the state in which the use right of the work area 500 has already been given by the queue control unit 220 to the two packets near the head of the stored packets as the initial state of the arithmetic device 10. .

  More specifically, the initial state of the work memory 50 is stored in the work area 501 as a packet # 1 that is first input to the packet queue 210 and for which the processor 31 performs calculation processing on the calculation target data A. It is in a state. Also, the work area 502 stores packet # 2 for which the processor 32 executes the arithmetic process on the operation target data B, which is input secondly into the packet queue 210, and the work area 503 stores 3 in the packet queue 210. This is a state in which packet # 3 is stored in which processor 33 performs arithmetic processing on operation target data C that is input second.

  In the initial state of the packet queue 210, the right to use the work area 504 is given to the storage area 211, in which the processor 31 executes arithmetic processing on the operation target data D that is input fourth in the packet queue 210. In this state, the received packet # 4 is stored. Also, in the storage area 212, packet # 5, which has been given the right to use the work area 505, is stored in the storage area 212. In the storage area 213, packet # 6, which is the sixth input to the packet queue 210 and for which the processor 31 executes arithmetic processing on the operation target data F and is not granted the right to use the work area 500, is stored. It is in a state.

  From this initial state, the processor 31 completes the arithmetic processing for the operation target data A included in the packet # 1, sets the processor number to “2” to take over the next arithmetic processing to the processor 32, and sets the packet status information to “ Consider a case where packet # 1 after the arithmetic processing updated to “continue processing” is output to the re-entry determination unit 230. Since the packet state information of the packet # 1 after the arithmetic processing is “processing continuation”, as described above, the processor 31 determines that the next calculation target data (hereinafter referred to as the following calculation target data) that is finally stored in the work area 501. Packet # 1 other than “calculation target data A2” is output to the reentry determination unit 230 (see step S49 in FIG. 6).

  The re-entry determination unit 230 that has acquired the packet # 1 after the arithmetic processing updates the information in the processor management register 251 in the processor usage status management register 250 corresponding to the processor 31 to information indicating “unused” (FIG. 7 step S51). Then, the re-entry determination unit 230 stores (entries) the acquired packet # 1 after the arithmetic processing again in the last storage area in the packet queue 210 (see step S53 in FIG. 7). Since the packet state information of packet # 1 after the arithmetic processing is “processing continuation”, as described above, the re-entry determination unit 230 uses the right to use the work area 501 given to the packet # 1 after the arithmetic processing. Is stored, that is, stored (entry) in the packet queue 210 again with the use right of the work area 501 being given to the packet # 1 after the arithmetic processing.

  In addition, the queue control unit 220 indicates that the information in the processor management register 251 corresponding to the processor 31 has become “unused” by the re-entry determination unit 230, that is, the processor 31 can execute the packet calculation process. Accordingly, the packet # 4 closest to the head of the packet queue 210 with the processor number = 1 among the packets to which the right to use the work area 500 stored in the packet queue 210 is granted 31 to output. Further, the queue control unit 220 updates the information in the processor management register 251 in the processor usage status management register 250 corresponding to the processor 31 to information indicating “in use” (see step S33 in FIG. 5).

  Thereafter, the processor 31 outputs the work memory number included in the input packet # 4 to the corresponding address conversion unit 401, and after the processor 31 and the work area 504 are connected one-to-one (step in FIG. 6). The calculation target data D included in the packet # 4 is transferred to the work area 504 (see step S43 in FIG. 6), and the calculation process for the calculation target data D is executed (see step S44 in FIG. 6).

  FIG. 8B shows the state of the packets in the packet queue 210 and the work memory 50 at this time. More specifically, the work memory 50 is stored in the work area 501 with calculation target data A2 as a result of the processor 31 executing calculation processing on the calculation target data A of packet # 1 (remaining). The work area 504 stores a packet # 4 that is input from the packet queue 210 and that is executed by the processor 31 on the calculation target data D. The work area 502 and the work area 503 in the work memory 50 are an arithmetic process for the calculation target data B included in the packet # 2 by the processor 32 and an arithmetic process for the calculation target data C included in the packet # 3 by the processor 33. This is the same as in the initial state.

  The packet queue 210 is in a state where the packet # 4 stored in the storage area 211 is output to the processor 31 and the packet # 5 is stored in the storage area 211. Packet # 6 is stored, and the final storage area 213 in the packet queue 210 is in a state where the post-computation packet # 1 stored again (entry) by the re-entry determination unit 230 is stored. As described above, the post-computation packet # 1 stored in the storage area 213 is a packet whose packet status information is “continue processing”, that is, the computation target data A2 is stored in the work area 501. Since it is a packet that remains (remains), the calculation target data A2 is not included, and the right to use the work area 501 remains granted.

  From this state, the processor 32 completes the operation processing for the operation target data B included in the packet # 2, sets the processor number to “3” to take over the next operation processing to the processor 33, and sets the packet state information to “processing”. Consider a case where the packet # 2 after the arithmetic processing updated to “continue” is output to the re-entry determination unit 230. Similar to the processor 31, the processor 32 uses the re-entry determination unit for the packet # 2 other than the next calculation target data (hereinafter referred to as “calculation target data B 2”) finally stored in the work area 502. 230 (see step S49 in FIG. 6).

  The re-entry determination unit 230 that has acquired the packet # 2 after the arithmetic processing updates the information in the processor management register 252 in the processor usage status management register 250 corresponding to the processor 32 to information indicating “unused” (FIG. 7 step S51). Then, the re-entry determination unit 230 stores (entries) the acquired packet # 2 after the arithmetic processing again in the last storage area in the packet queue 210 (see step S53 in FIG. 7). Note that the re-entry determination unit 230 gives the right to use the work area 502 to the packet # 2 after the arithmetic processing in the same manner as when the packet # 1 after the arithmetic processing is stored (entry) again in the packet queue 210. Then, it is stored (entry) in the packet queue 210 again.

  Also, the queue control unit 220 is in a state where the information in the processor management register 252 corresponding to the processor 32 becomes “unused” by the re-entry determination unit 230 and the processor 32 can execute the packet calculation process. Accordingly, among the packets to which the right to use the work area 500 stored in the packet queue 210 is granted, the processor number = 2 and the packet # 1 after the arithmetic processing closest to the head of the packet queue 210, that is, Then, the processor 32 is caused to output the packet # 1 after being stored in the packet queue 210 again and the processor 32 taking over the operation process. Further, the queue control unit 220 updates the information in the processor management register 252 in the processor usage status management register 250 corresponding to the processor 32 to information indicating “in use” (see step S33 in FIG. 5).

  Thereafter, the processor 32 outputs the work memory number included in the input packet # 1 after the arithmetic processing to the corresponding address conversion unit 401, and the processor 32 and the operation target data A2 are stored (remaining). After the work area 501 is connected in a one-to-one relationship (see step S42 in FIG. 6), the calculation process is performed on the calculation target data A2 without transferring the calculation target data to the work area 501 (step in FIG. 6). (See S44).

  FIG. 8C shows the state of packets in the packet queue 210 and the work memory 50 at this time. More specifically, the state of the work memory 50 is stored in the work area 502 as the calculation target data B2 as a result of the processor 32 executing the calculation processing on the calculation target data B of the packet # 2 (remaining). ) State. The work area 501 in the work memory 50 stores (remains) the calculation target data A2 as a result of the processor 31 executing the calculation processing on the calculation target data A of the packet # 1. Calculation processing is performed on the calculation target data A <b> 2 inherited from 31. In addition, the work area 503 and the work area 504 in the work memory 50 are calculated by the processor 33 for the calculation target data C included in the packet # 3, and the calculation process for the calculation target data D included in the packet # 4 by the processor 31. This is the same as the state shown in FIG.

  Further, the state of the packet queue 210 is re-stated in the last storage area 213 in the packet queue 210 because the packet # 1 after the arithmetic processing stored in the previous storage area 213 is output to the processor 32. The packet # 2 after the arithmetic processing stored again (entry) by the entry determination unit 230 is stored. As described above, the post-computation packet # 2 stored in the storage area 213 is a packet whose packet status information is “continue processing”, and the computation target data B2 is stored in the work area 502 ( Since the packet is a remaining packet, the calculation target data B2 is not included and the right to use the work area 502 is still given. The storage area 211 and the storage area 212 in the packet queue 210 are the same as the state shown in FIG. 8B because the respective packets are not output to the processor 30.

  From this state, the processor 33 completes the arithmetic processing for the operation target data C included in the packet # 3, whereby a series of arithmetic processing by the arithmetic device 10 is completed, and the packet state information is updated to “processing complete”. Consider a case where the packet # 3 after the arithmetic processing is output to the reentry determination unit 230. Since the packet status information of the packet # 3 after the arithmetic processing is “processing completed”, the processor 33 includes the arithmetic target data C finally stored in the work area 503 as described above. The entire processed packet # 3 is output to the reentry determination unit 230 (see step S48 in FIG. 6).

  The re-entry determination unit 230 that acquired the packet # 3 after the arithmetic processing updates the information in the processor management register 253 in the processor usage status management register 250 corresponding to the processor 33 to information indicating “unused” (FIG. 7 step S51). Further, since the packet status information of the packet # 3 after the arithmetic processing is “processing completed”, the re-entry determining unit 230 has the information in the work memory management register 243 in the work memory usage status management register 240 as described above. Is updated to information indicating “unused” to release the right to use the work area 503 given to the packet # 3 after the arithmetic processing (see step S54 in FIG. 7). Then, the re-entry determination unit 230 outputs the acquired packet # 3 after the arithmetic processing to the external block 100 (see step S55 in FIG. 7).

  Also, the queue control unit 220 is in a state where the information in the processor management register 253 corresponding to the processor 33 becomes “unused” by the re-entry determination unit 230, and the processor 33 can execute the packet calculation process. Accordingly, among the packets to which the right to use the work area 500 stored in the packet queue 210 is granted, the processor number = 3 and the packet # 2 after the arithmetic processing closest to the head of the packet queue 210, that is, Then, the processor 33 outputs the packet # 2 after being stored in the packet queue 210 again, and the processor 33 takes over the operation process. Further, the queue control unit 220 updates the information in the processor management register 253 in the processor usage status management register 250 corresponding to the processor 33 to information indicating “in use” (see step S33 in FIG. 5).

  Thereafter, the processor 33 outputs the work memory number included in the input packet # 2 after the arithmetic processing to the corresponding address conversion unit 402, and the processor 33 and the operation target data B2 are stored (remaining). After the work area 502 is connected to the work area 502 in a one-to-one relationship (see step S42 in FIG. 6), the calculation process is performed on the calculation target data B2 without transferring the calculation target data to the work area 502 (step in FIG. 6). (See S44).

  In addition, the queue control unit 220 causes the re-entry determination unit 230 to change the information in the work memory management register 243 in the work memory usage status management register 240 corresponding to the work area 503 to “unused”, so that the right to use the work area 503 is obtained. The packet after the arithmetic processing closest to the head of the packet queue 210 among the packets to which the right to use the work area 500 already stored in the packet queue 210 is not granted. The right to use the work area 503 is granted to # 6 (see step S23 in FIG. 4).

  FIG. 8D shows the state of the packets in the packet queue 210 and the work memory 50 at this time. More specifically, the work memory 50 is in a state where no packet is stored in the work area 503. The work area 502 in the work memory 50 stores the calculation target data B2 as a result of the processor 32 executing the calculation process on the calculation target data B of the packet # 2, and the processor 33 is stored in the processor 33. The calculation process is performed on the calculation target data B <b> 2 inherited from 32. Further, the work area 501 and the work area 504 in the work memory 50 are used for the calculation process on the calculation target data A2 of the packet # 1 after the calculation process by the processor 32 and the calculation target data D included in the packet # 4 by the processor 31. Since the arithmetic processing has not been completed, the state is the same as that shown in FIG.

  The state of the packet queue 210 is a state in which the right to use the work area 503 is granted to the packet # 6 stored in the storage area 213. The storage area 211 in the packet queue 210 is the same as the state shown in FIG. 8C because the packet # 5 is not output to the processor 31. At this time, for example, when the predetermined maximum number of entries is set to the maximum number of entries = 3, the queue control unit 220 can confirm that the number of already entered packets <the maximum number of entries (step S12 in FIG. 3). Therefore, a permission signal notifying that the packet output is permitted can be output to the external block 100.

  In this way, the arithmetic device 10 constantly monitors and monitors the usage status of each work area 500 in the work memory 50 provided in the arithmetic device 10 and the usage status of each processor 30 provided in the arithmetic device 10. Depending on the situation, each packet is assigned to the corresponding processor 30. At this time, since the processor 30 and the work area 500 have a one-to-one correspondence, when each processor 30 executes an arithmetic process on the assigned packet, a conflict of the work area 500 occurs in each processor 30. The work area 500 is shared without any problem, and the arithmetic device 10 can execute a plurality of arithmetic processes requested from the external block 100 in parallel.

  In addition, in the arithmetic device 10, when the arithmetic processing is taken over by another processor 30, the operation target data is stored (leaved) in the work area 500 and a packet that takes over the arithmetic processing is output to the reentry determination unit 230. To do. For this reason, in the arithmetic unit 10, calculation target data can be shared between the processors 30.

  In the example of the operation of the arithmetic device 10 illustrated in FIG. 8, each processor 30 uses one work area 500 in the work memory 50 to execute arithmetic processing on the operation target data included in the packet. Explained. However, the number of work areas 500 used when each processor 30 executes arithmetic processing is not necessarily one. For example, a packet that performs arithmetic processing using two work areas 500 may be assigned to the processor 30.

<Second Embodiment>
Next, a second embodiment of the present invention will be described. The arithmetic device according to the second embodiment is an arithmetic device to which the concept when each processor provided in the arithmetic device executes arithmetic processing using a plurality of work areas is applied. For this reason, the arithmetic device of the second embodiment includes the “calculation target data”, the “processor number”, the “work memory number”, the “processing number” described in the arithmetic device 10 of the first embodiment, and In addition to the “packet status information”, a packet that contains information on the “number of used memory” that determines the number of work areas in the work memory used when performing arithmetic processing on the packet is input from an external block The

  In the arithmetic device according to the second embodiment, the configuration and processing procedure of the arithmetic device are the same except that a function for executing arithmetic processing using a plurality of work areas is added to the queue control unit and the address conversion unit. This is the same as the arithmetic device 10 of the first embodiment. Therefore, in the following description, the arithmetic device according to the second embodiment is the arithmetic device 10, and only functions added to the respective components provided in the arithmetic device 10 will be described.

  The queue control unit 220 has a function of confirming the number of used memories included in each packet stored in the packet queue 210 and giving the right to use the work area 500 of the number determined by the number of used memories to the packet. Join.

  More specifically, first, the queue control unit 220 checks the number of work areas 500 in the work memory 50 that are determined by the number of used memories included in each packet stored in the packet queue 210. Then, the queue control unit 220 indicates the usage status of the work area 500 in the work memory 50 determined by the work memory number included in the packet for which the usage count of the work area 500 is confirmed, in the work memory usage status management register 240. Check from the information in the work memory management register. As a result of confirming the use number of the work area 500 and the information of the work memory management register, the work area 500 is determined by the number of used memory and can be used by the work memory number. When the information in the memory management register is “unused” by the number determined by the number of used memories, the queue control unit 220 grants the right to use the plurality of work areas 500. Then, the queue control unit 220 stores the number of work memory management registers corresponding to the number of used memories in the work memory use state management register 240 corresponding to the work memory number included in the packet to which the right to use the work area 500 is granted. Change the information to “in use”.

  Each of the address conversion unit 401 to the address conversion unit 403 is actually used with an address that specifies the work area 500 used when the corresponding processor 30 executes the calculation process on the calculation target data included in the packet. A function for continuously associating the addresses of the plurality of work areas 500 in the work memory 50 with one to one is added. That is, the address conversion unit 400 converts the logical address when the corresponding processor 30 accesses the plurality of work areas 500 into a continuous physical address when actually accessing the plurality of work areas 500 in the work memory 50. To do. As a result, each processor 30 can select any work area without considering (without being aware of) the delimiter (physically separated structure) of the work area 500 used when executing the arithmetic processing on the packet. Even when 500 is used, the arithmetic processing can be executed in the same manner. That is, each processor 30 can access as one work area 500 having a large storage area regardless of which work area 500 is used.

  For example, in the configuration of the arithmetic unit 10 of the second embodiment (see FIG. 1), the work area 501 in the work memory 50 has a physical address 0x1000-0x1FFF, the work area 502 has a physical address 0x2000-0x2FFF, and the work area 503. Assume that physical addresses 0x3000 to 0x3FFF are assigned to the work area 504, physical addresses 0x4000 to 0x4FFF are assigned to the work area 505, and physical addresses 0x5000 to 0x5FFF are assigned to the work area 505, respectively. At this time, for example, the address conversion unit 401 uses the logical address 0x0000 to 0x1FFF when the processor 31 accesses the work area 500, the physical address 0x1000 to 0x1FFF of the work area 501, and the physical address 0x2000 to 0x2FFF of the work area 502 as Are converted to be continuous. As a result, the processor 31 can continuously access the two work areas 500 of the work area 501 and the work area 502 in the work memory 50. Further, for example, the address conversion unit 401 includes logical addresses 0x0000 to 0x1FFF when the processor 31 accesses the work area 500, physical addresses 0x2000 to 0x2FFF of the work area 502, and physical addresses 0x5000 to 0x5FFF of the work area 505. Convert to be continuous. As a result, the processor 31 can continuously access the two work areas 500 of the work area 502 and the work area 505 in the work memory 50. Further, for example, the address conversion unit 401 includes logical addresses 0x0000 to 0x1FFF when the processor 31 accesses the work area 500, physical addresses 0x1000 to 0x1FFF of the work area 501, and physical addresses 0x4000 to 0x4FFF of the work area 504. Convert to be continuous. Thereby, the processor 31 can continuously access the two work areas 500 of the work area 501 and the work area 504 in the work memory 50.

<Second operation>
Here, in the arithmetic device 10 of the second embodiment, an example of an operation when the processor 30 executes arithmetic processing using a plurality of work areas 500 will be described. Also in the description of the second operation, the operation of the arithmetic unit 10 will be described by paying attention to the packets in the packet queue 210 and the work memory 50. FIG. 9 is a diagram illustrating an example of packet states in the packet queue 210 and the work memory 50 at each processing stage in the operation of the arithmetic device 10 according to the second embodiment. The second operation is the operation of the arithmetic device 10 when the packet stored in the packet queue 210 includes a packet for performing arithmetic processing using the two work areas 500.

  FIG. 9 shows, as an example of the state of the packet in the work memory 50 in the operation of the arithmetic unit 10 of the first embodiment shown in FIG. “Calculation target data” and “processor number” included are shown. FIG. 9 shows the state of the packet in the packet queue 210 as an example of the state of the packet in the packet queue 210 in the operation of the arithmetic device 10 of the first embodiment shown in FIG. “Calculation target data”, “processor number”, “work memory number”, and “packet state information” included are shown. Further, the state of the packet in the packet queue 210 further indicates “number of used memories”.

  The “processor number” and “work memory number” in each packet state shown in FIG. 9 include the packet queue 210 and the work memory 50 in the operation of the arithmetic unit 10 of the first embodiment shown in FIG. Similarly to the example of the state of the packet, the last digit of the sign of each processor 30 and the last digit of the sign of each work area 500 are shown. Also, in the state of each packet shown in FIG. 9, for ease of explanation, the packet queue 210 and the packet in the work memory 50 in the operation of the arithmetic unit 10 of the first embodiment shown in FIG. Similarly to the example of the state, an item “packet number” and an item “processor in process” are shown.

  First, in the operation of the arithmetic unit 10 of the second embodiment, as shown in FIG. 9A, three packets are stored in the work memory 50, and three packets are stored in the packet queue 210. The computing device 10 according to the second embodiment shows a state in which the right to use the work area 500 has already been given to one of the packets stored in the packet queue 210 by the queue control unit 220. The following operations will be described as the initial state. Here, it is assumed that the second packet from the top is a packet that uses two work areas 500.

  More specifically, the initial state of the work memory 50 is stored in the work area 501 as a packet # 1 that is first input to the packet queue 210 and for which the processor 31 performs calculation processing on the calculation target data A. It is in a state. Also, the work area 502 stores packet # 2 for which the processor 32 executes the arithmetic process on the operation target data B, which is input secondly into the packet queue 210, and the work area 503 stores 3 in the packet queue 210. This is a state in which packet # 3 is stored in which processor 33 performs arithmetic processing on operation target data C that is input second.

  In the initial state of the packet queue 210, the right to use the work area 504 is given to the storage area 211, in which the processor 31 executes arithmetic processing on the operation target data D that is input fourth in the packet queue 210. In this state, the received packet # 4 is stored. In addition, in the storage area 212, two work areas 500 in which the processor 32 executes arithmetic processing on the calculation target data E that is input fifth in the packet queue 210 are used, and the right to use the work area 500 is granted. The packet # 5 that has not been granted is stored, and the storage area 213 has the right to use the work area 500 in which the processor 31 executes the arithmetic processing on the calculation target data F that is input sixth in the packet queue 210. This is a state where unassigned packet # 6 is stored.

  As can be seen from FIG. 9A, two work areas 500 (work area 504 and work area 505) are in an “unused” state in the work memory 50. However, the right to use the work area 500 is not given to the packet # 5 that performs arithmetic processing using the two work areas 500. This is because packet # 5 is stored in the second storage area 212 of the packet queue 210, and packet # 4 stored in the top storage area 211 of the packet queue 210 already has the right to use the work area 504. This is because the work area 500 that is in an “unused” state is only the work area 505 due to the assignment. That is, in the initial state of the work memory 50, there is only one work area 500 in the “unused” state, and the number of work areas 500 necessary for the arithmetic processing of packet # 5 cannot be secured. is there.

  From this initial state, the processor 31 completes the arithmetic processing for the operation target data A included in the packet # 1, sets the processor number to “2” to take over the next arithmetic processing to the processor 32, and sets the packet status information to “ Consider a case where packet # 1 after the arithmetic processing updated to “continue processing” is output to the re-entry determination unit 230. At this time, the processor 31 outputs the packet # 1 other than the next calculation target data A2 finally stored in the work area 501 to the reentry determination unit 230 (see step S49 in FIG. 6).

  The re-entry determination unit 230 that has acquired the packet # 1 after the arithmetic processing updates the information in the processor management register 251 in the processor usage status management register 250 corresponding to the processor 31 to information indicating “unused” (FIG. 7 step S51). Then, the re-entry determination unit 230 stores (entries) the acquired packet # 1 after the arithmetic processing again in the last storage area in the packet queue 210 (see step S53 in FIG. 7). The re-entry determination unit 230 stores (entries) the packet in the packet queue 210 again without releasing the right to use the work area 501 given to the packet # 1 after the arithmetic processing.

  Also, the queue control unit 220 is in a state where the information in the processor management register 251 corresponding to the processor 31 becomes “unused” by the re-entry determination unit 230 and the processor 31 can execute the packet calculation process. Accordingly, among the packets to which the right to use the work area 500 stored in the packet queue 210 is granted, the packet # 4 closest to the head of the packet queue 210 with the processor number = 1 is output to the processor 31. Let Further, the queue control unit 220 updates the information in the processor management register 251 in the processor usage status management register 250 corresponding to the processor 31 to information indicating “in use” (see step S33 in FIG. 5).

  Thereafter, the processor 31 outputs the work memory number included in the input packet # 4 to the corresponding address conversion unit 401, and after the processor 31 and the work area 504 are connected one-to-one (step in FIG. 6). The calculation target data D included in the packet # 4 is transferred to the work area 504 (see step S43 in FIG. 6), and the calculation process for the calculation target data D is executed (see step S44 in FIG. 6).

  FIG. 9B shows the state of packets in the packet queue 210 and the work memory 50 at this time. More specifically, the work memory 50 is stored in the work area 501 with calculation target data A2 as a result of the processor 31 executing calculation processing on the calculation target data A of packet # 1 (remaining). The work area 504 stores a packet # 4 that is input from the packet queue 210 and that is executed by the processor 31 on the calculation target data D. The work area 502 and the work area 503 in the work memory 50 are an arithmetic process for the calculation target data B included in the packet # 2 by the processor 32 and an arithmetic process for the calculation target data C included in the packet # 3 by the processor 33. This is the same as in the initial state.

  The packet queue 210 is in a state where the packet # 4 stored in the storage area 211 is output to the processor 31 and the packet # 5 is stored in the storage area 211. Packet # 6 is stored, and the final storage area 213 in the packet queue 210 is in a state where the post-computation packet # 1 stored again (entry) by the re-entry determination unit 230 is stored. Note that, as described above, the post-computation packet # 1 stored in the storage area 213 does not include the computation target data A2 because the packet status information is a “process continuation” packet, and the work area In this state, the usage right 501 is still given.

  As can be seen from FIG. 9B, the right to use the work area 500 is not given to the packet # 5 that performs arithmetic processing using the two work areas 500. This is because the work area 500 in the “unused” state is only the work area 505 even when the packet # 5 is stored in the top storage area 211 of the packet queue 210, and is necessary for the calculation process of the packet # 5. This is because a large number of work areas 500 cannot be secured.

  From this state, when the processor 32 has completed the arithmetic processing on the operation target data B included in the packet # 2, a series of arithmetic processing by the arithmetic device 10 is completed, and the packet state information is updated to “processing complete”. Consider a case where the packet # 2 after the arithmetic processing is output to the reentry determination unit 230. The processor 32 outputs the entire packet # 2 after the calculation process including the calculation target data B finally stored in the work area 502 to the reentry determination unit 230 (see step S48 in FIG. 6). .

  The re-entry determination unit 230 that has acquired the packet # 2 after the arithmetic processing updates the information in the processor management register 252 in the processor usage status management register 250 corresponding to the processor 32 to information indicating “unused” (FIG. 7 step S51). In addition, the re-entry determination unit 230 updates the information in the work memory management register 242 in the work memory usage status management register 240 to information indicating “unused”, thereby giving the re-entry determination unit 230 to the packet # 2 after the arithmetic processing. The right to use the work area 502 is released (see step S54 in FIG. 7). Then, the reentry determination unit 230 outputs the acquired packet # 2 after the arithmetic processing to the external block 100 (see step S55 in FIG. 7).

  In addition, the queue control unit 220 causes the re-entry determination unit 230 to change the information in the work memory management register 242 in the work memory usage status management register 240 corresponding to the work area 502 to “unused”, and the right to use the work area 502. The two work areas that are closest to the top of the packet queue 210 among the packets to which the right to use the work area 500 stored in the packet queue 210 is not granted. It is confirmed that the number of work areas 500 necessary for the arithmetic processing of packet # 5 that performs arithmetic processing using 500 can be secured (see step S21 in FIG. 4). Thereby, the queue control unit 220 grants the right to use the work area 502 and the work area 505 to the packet # 5 (see step S23 in FIG. 4).

  The queue control unit 220 is in a state in which the information in the processor management register 252 corresponding to the processor 32 becomes “unused” by the re-entry determination unit 230 and the processor 32 can execute the packet calculation process. Accordingly, the packet # 5 after the arithmetic processing closest to the head of the packet queue 210 with the processor number = 2 among the packets to which the right to use the work area 500 stored in the packet queue 210 is granted, The data is output to the processor 32. Further, the queue control unit 220 updates the information in the processor management register 252 in the processor usage status management register 250 corresponding to the processor 32 to information indicating “in use” (see step S33 in FIG. 5).

  Thereafter, the processor 32 outputs the work memory number included in the input packet # 5 to the corresponding address conversion unit 402. The address conversion unit 402 configures a logical address so that the work area 502 and the work area 505 are one continuous work area. More specifically, one continuous work area is formed by adding the logical address when the processor 32 allocated to the physical address of the work area 502 accesses the work area as an offset to the logical address of the work area 505. To do. Thereby, for example, half of the calculation target data E can be stored in the work area 502 and the other half of the calculation target data E can be stored in the work area 505.

  Then, after the processor 32 and the work area composed of the work area 502 and the work area 505 are connected one-to-one (see step S42 in FIG. 6), the processor 32 calculates the calculation target included in the packet # 5. Data E is transferred to one continuous work area (work area 502 and work area 505) (see step S43 in FIG. 6), and calculation processing is performed on calculation target data E (see step S44 in FIG. 6). At this time, the processor 32 can execute a calculation process on the calculation target data E without considering (not aware of) the physical separation of the work area 500.

  FIG. 9C shows the state of packets in the packet queue 210 and the work memory 50 at this time. More specifically, the state of the work memory 50 is stored in the work area 502 and the work area 505 as a packet # 5 that is input from the packet queue 210 by the processor 32 and performs arithmetic processing on the operation target data E. It is in a state that has been. Here, in FIG. 9C, the upper half of the calculation target data E is stored in the work area 502 and the lower half of the calculation target data E is stored in the work area 505 separately. It shows the state being done. The work area 501 in the work memory 50 stores the calculation target data A2 as a result of the processor 31 executing the calculation process on the calculation target data A of the packet # 1 (remains). In the area 504, the calculation processing for the calculation target data C included in the packet # 3 by the processor 33 and the calculation processing for the calculation target data D included in the packet # 4 by the processor 31 have not been completed. It is the same as the state shown in.

  Further, the state of the packet queue 210 is that the packet # 5 stored in the storage area 211 is output to the processor 32, so that the packet # 6 is stored in the storage area 211. In the last storage area 212, the packet # 1 after the arithmetic processing stored again (entry) by the re-entry determination unit 230 is stored.

  As can be seen from FIG. 9C, the right to use the work area 500 is not given to the packet # 6. This is because all the work areas 500 in the work memory 50 are in use, that is, all the information in the work memory management register in the work memory use status management register 240 is “in use”. This is because the number of work areas 500 necessary for the arithmetic processing cannot be secured.

  As described above, also in the arithmetic device 10 of the second embodiment, as in the arithmetic device 10 of the first embodiment, the usage status of each work area 500 in the work memory 50 provided in the arithmetic device 10 is constantly monitored. Then, according to the monitored usage status of the work area 500, the right to use the work areas 500 as many as necessary when performing the arithmetic processing on the packet is granted. As a result, even in the arithmetic device 10 of the second embodiment, as in the arithmetic device 10 of the first embodiment, each processor 30 is input from the external block 100 without causing a conflict of the work area 500. A series of arithmetic processing for a plurality of packets can be shared by each processor 30 and executed in parallel.

  Further, in the arithmetic device 10 of the second embodiment, the processor 30 includes a single work area 500 including a plurality of work areas 500 necessary for each processor 30 to execute arithmetic processing on a packet. One-to-one correspondence. That is, in the arithmetic device 10 according to the second embodiment, the work area 500 having a size of a storage area required when each processor 30 executes arithmetic processing is associated. Thus, in the arithmetic device 10 of the second embodiment, each processor 30 executes arithmetic processing for a packet even when a work area having a large storage area is used when executing arithmetic processing for the packet. The computing device 10 can execute a plurality of computing processes requested from the external block 100 in parallel without causing conflicts in the work area 500 at the time.

  In the example of the operation of the arithmetic device 10 shown in FIGS. 8 and 9, the work areas in the work memory 50 are in the order in which the packets are stored in the packet queue 210 except for the packet that takes over the arithmetic processing to the next processor 30. The case where 500 usage rights are granted has been described. However, the packets that each processor 30 executes arithmetic processing are not necessarily distributed and stored in the packet queue 210, and packets that the same processor 30 (for example, the processor 31) executes arithmetic processing are consecutive. May be stored in the packet queue 210.

<Third Embodiment>
Next, a third embodiment of the present invention will be described. The arithmetic device according to the third embodiment sets the right to use the work area in the queue so that the number of packets processed by the same processor to which the right to use the work area is processed does not exceed a predetermined threshold. This is an arithmetic device to which the concept of controlling the order of giving is applied. In other words, the arithmetic device according to the third embodiment controls the right to use a work area so that a specific processor does not bias the right to use the work area given to a processor that performs arithmetic processing on a packet. It is the arithmetic unit of the structure which prevents having occupied.

  In the arithmetic device according to the third embodiment, the configuration and processing procedure of the arithmetic device are the same except that a function for controlling the order of granting the right to use the work memory 50 is added to the queue control unit and the re-entry determination unit. Is the same as that of the arithmetic unit 10 of the first or second embodiment. Therefore, in the following description, the arithmetic device of the third embodiment is the arithmetic device 10, and only functions added to the respective components provided in the arithmetic device 10 will be described.

  In the queue control unit 220, the number of packets to be processed by the same processor 30 to which the use right of the work area 500 is given is set in the packet queue 210 (hereinafter referred to as “the number of used right packets”). In order not to become the above, a function for controlling the right to use the work area 500 to be assigned to each packet is added. Note that the number of use right packets can be set for each processor 30.

  More specifically, the queue control unit 220 first confirms the processor number included in each packet stored in the packet queue 210. Then, the queue control unit 220 has the same processor number included in the packet that has already been given the right to use the work area 500 and the processor number included in the packet that has not been given the right to use the work area 500. Check whether or not. As a result of this confirmation, if there are more packets than the predetermined threshold in the packet queue 210 that contain the same processor number to which the right to use the work area 500 has been assigned, the work memory usage status management register 240 Even when there is “unused” information in the work memory management register, the right to use the work area 500 is not granted to a packet that does not have the right to use the work area 500 including the same processor number.

  The re-entry determination unit 230 assigns each packet to the packet queue 210 so that the number of packets processed by the same processor 30 to which the usage right of the work area 500 is granted does not exceed the number of usage right packets. A function for controlling the release of the right to use the assigned work area 500 is added.

  More specifically, first, the re-entry determination unit 230 checks the processor number included in each packet stored in the packet queue 210. Then, the re-entry determination unit 230 has the same processor number included in the packet to which the right to use the work area 500 is already assigned and the processor number included in the packet stored (entry) in the packet queue 210 again. Check whether or not. As a result of this confirmation, if there are more packets in the packet queue 210 that have the same processor number to which the right to use the work area 500 has been assigned, the packet queue 210 stores the packet again (entry ), Even when the packet status information of the packet to be processed is “continuation of processing”, the right to use the work area 500 given to the packet stored (entry) in the packet queue 210 again is released.

  Note that if the right to use the work area 500 given to a packet stored (entry) again in the packet queue 210 is released, the calculation target data stored (remaining) in the work area 500 is rewritten. Become. For this reason, the re-entry determination unit 230, although the packet status information is “processing continuation”, the result of executing the arithmetic processing to the processor 30 that outputs the packet after the arithmetic processing for releasing the right to use the work area 500 is obtained. An instruction is given to output the calculation target data, that is, the entire packet after the calculation process including the calculation target data to be taken over by the next processor 30.

<Third operation>
Here, in the arithmetic device 10 of the third embodiment, the number of packets in the packet queue 210 processed by the same processor 30 to which the usage right of the work area 500 is granted does not exceed the number of the usage right packets. An example of an operation when controlling the granting of the right to use the work area 500 will be described. Also in the description of the third operation, the operation of the arithmetic unit 10 will be described by paying attention to the packets in the packet queue 210 and the work memory 50. In the third operation, the same value is applied to all processor numbers for the number of right-of-use packets, that is, the same number of right-of-use packets is assigned to all the processors 30 in the arithmetic unit 10. Shall apply. The number of usage right packets is assumed to be the number of usage right packets = 1. That is, it is assumed that there is only one packet in the packet queue 210 to which the right to use the work area 500 in which the same processor 30 executes arithmetic processing is assigned. FIG. 10 is a diagram illustrating an example of packet states in the packet queue 210 and the work memory 50 at each processing stage in the operation of the arithmetic device 10 according to the third embodiment.

  FIG. 10 shows, as an example of the state of the packet in the work memory 50 in the operation of the arithmetic device 10 of the first embodiment shown in FIG. “Calculation target data” and “processor number” included are shown. In addition, FIG. 10 shows the packet status in the packet queue 210 as an example of the status of the packet in the packet queue 210 in the operation of the arithmetic device 10 of the first embodiment shown in FIG. “Calculation target data”, “processor number”, “work memory number”, and “packet state information” included in the packet are shown. Further, the state of the packet in the packet queue 210 includes “number of used memories” as in the example of the state of the packet in the packet queue 210 in the operation of the arithmetic device 10 of the second embodiment shown in FIG. Is also shown. However, the number of used memories is only used memory number = 1.

  The “processor number” and “work memory number” in the state of each packet shown in FIG. 10 are the same as those of the arithmetic unit 10 of the first embodiment and the second embodiment shown in FIGS. Similarly to the example of the state of the packet in the packet queue 210 and the work memory 50 in the operation, the last digit of the sign of each processor 30 and the last digit of the sign of each work area 500 are shown. . Also, in the state of each packet shown in FIG. 10, in order to facilitate the explanation, the packet queue in the operation of the arithmetic unit 10 of the first embodiment and the second embodiment shown in FIGS. Similarly to the example of the state of the packet in 210 and the work memory 50, the item of “packet number” and the item of “processing processor” are shown.

  First, in the operation of the arithmetic unit 10 of the third embodiment, as shown in FIG. 10A, three packets are stored in the work memory 50, and three packets are stored in the packet queue 210. The state in which the right to use the work area 500 is already granted to the first packet and the third packet among the packets stored in the packet queue 210 by the queue control unit 220 in the third embodiment. The following operations will be described as an initial state of the arithmetic unit 10.

  More specifically, the initial state of the work memory 50 is stored in the work area 501 as a packet # 1 that is first input to the packet queue 210 and for which the processor 31 performs calculation processing on the calculation target data A. It is in a state. Also, the work area 502 stores packet # 2 for which the processor 32 executes the arithmetic process on the operation target data B, which is input secondly into the packet queue 210, and the work area 503 stores 3 in the packet queue 210. This is a state in which packet # 3 is stored in which processor 33 performs arithmetic processing on operation target data C that is input second.

  In the initial state of the packet queue 210, the right to use the work area 504 is given to the storage area 211, in which the processor 31 executes arithmetic processing on the operation target data D that is input fourth in the packet queue 210. In this state, the received packet # 4 is stored. Also, in the storage area 212, packet # 5, which is the fifth input to the packet queue 210 and for which the processor 31 performs arithmetic processing on the operation target data E and is not granted the right to use the work area 500, is stored. In the storage area 213, the packet # 6, which is the sixth input to the packet queue 210 and for which the processor 32 executes the arithmetic process on the operation target data F and is granted the right to use the work area 505, is stored. It is in a state.

  As can be seen from FIG. 10A, the packet # 5 stored in the second storage area 212 of the packet queue 210 is the packet # 6 stored in the third storage area 213 of the packet queue 210. The right to use the work area 500 is not granted even though the packet is closer to the beginning. In this packet # 5, since the work area 505 is in an “unused” state in the work memory 50 before the use right of the work area 500 is given to the packet # 6, the right to use the work area 505 is given. Should be granted. However, the right to use the work area 505 is not granted at this stage because the same processor number = 1 is included and one or more packets to which the right to use the work area 500 has already been assigned (usage right packet This is because there are more than a few). More specifically, in the third operation, since the number of right-of-use packets is 1, the same processor 31 executes arithmetic processing, and packet # 4 to which the right to use work area 504 has already been granted is the first. Therefore, the right to use the work area 505 is not given to the packet # 5 in which the same processor 31 as that of the packet # 4 executes the arithmetic processing. Then, the use right of the work area 505 is given to the packet # 6 in which the packet for which the processor 32 performs the arithmetic processing by the same processor 32 to which the use right of the work area 500 has already been given does not exist in the packet queue 210. It was done.

  From this initial state, the processor 31 completes the arithmetic processing for the operation target data A included in the packet # 1, sets the processor number to “2” to take over the next arithmetic processing to the processor 32, and sets the packet status information to “ Consider a case where packet # 1 after the arithmetic processing updated to “continue processing” is output to the re-entry determination unit 230. At this time, the processor 31 uses the packet # 1 other than the next calculation target data A2 finally stored in the work area 501, that is, the packet # 1 after the calculation process including only the processor number and the packet state information. Is output to the re-entry determination unit 230 (see step S49 in FIG. 6).

  The re-entry determination unit 230 that acquired the processed packet # 1 including only the processor number and the packet status information from the processor 31 first stores the acquired processed packet # 1 stored in the packet queue 210. The number of packets having the same processor number as that included in 1 and already granted the right to use the work area 500 is confirmed. More specifically, the re-entry determination unit 230 stores each work memory in the work memory use status management register 240 in which the same processor number = 2 as the processor number included in the packet # 1 after the arithmetic processing is written. Check the number of management registers. In the third operation, since the value representing the processor 32 is written in the work memory management register 245, the re-entry determination unit 230 has already given the right to use the work area 500 (see FIG. 10 ( It is determined that at least one packet # 6 shown in a) corresponds to the packet queue 210 (the number of used right packets).

  When the processor management register in the processor usage status management register 250 includes information indicating the work area 500 used when the corresponding processor 30 executes the arithmetic processing, the re-entry determination unit 230 The same confirmation can be made by checking the respective processor management registers.

  The re-entry determining unit 230 that has confirmed that there are more packets than the number of use right packets in the packet queue 210 outputs the entire packet # 1 after the arithmetic processing including the arithmetic target data A2 so as to output the processor 31. To instruct. This is because the packet status information included in the packet # 1 after the arithmetic processing is “processing continuation”, but the calculation target data A2 to be taken over by the processor 32 may be rewritten by another processor 30. This is to save the data A2 to be inherited.

  The processor 31 that has received an instruction to output the entire packet # 1 after the arithmetic processing from the re-entry determination unit 230, after the arithmetic processing including the next arithmetic target data A2 that is finally stored in the work area 501 The entire packet # 1 is output again to the re-entry determination unit 230 (see step S48 in FIG. 6).

  The re-entry determination unit 230 that acquired the entire packet # 1 after the arithmetic processing from the processor 31 converts the information in the processor management register 251 in the processor usage status management register 250 corresponding to the processor 31 into information indicating “unused”. Update (see step S51 in FIG. 7). Then, the re-entry determination unit 230 determines that the packet state information included in the acquired packet # 1 after the arithmetic processing is “processing continuation”, but the entire packet # 1 after the arithmetic processing acquired this time is stored in the packet queue 210. Is stored (entry) again in the last storage area (see step S53 in FIG. 7). The re-entry determination unit 230 also sets the information of the work memory management register 241 in the work memory usage status management register 240, although the packet status information included in the acquired packet # 1 after the arithmetic processing is “processing continuation”. By updating to information indicating “unused”, the right to use the work area 501 assigned to the packet # 1 after the arithmetic processing is released (see step S54 in FIG. 7).

  Also, the queue control unit 220 is in a state where the information in the processor management register 251 corresponding to the processor 31 becomes “unused” by the re-entry determination unit 230 and the processor 31 can execute the packet calculation process. Accordingly, among the packets to which the right to use the work area 500 stored in the packet queue 210 is granted, the packet # 4 closest to the head of the packet queue 210 with the processor number = 1 is output to the processor 31. Let Further, the queue control unit 220 updates the information in the processor management register 251 in the processor usage status management register 250 corresponding to the processor 31 to information indicating “in use” (see step S33 in FIG. 5).

  Thereafter, the processor 31 outputs the work memory number included in the input packet # 4 to the corresponding address conversion unit 401, and after the processor 31 and the work area 504 are connected one-to-one (step in FIG. 6). The calculation target data D included in the packet # 4 is transferred to the work area 504 (see step S43 in FIG. 6), and the calculation process for the calculation target data D is executed (see step S44 in FIG. 6).

  In addition, the queue control unit 220 causes the re-entry determination unit 230 to change the information in the work memory management register 241 in the work memory usage status management register 240 corresponding to the work area 501 to “unused”, so that the right to use the work area 501 To the packet # 5 closest to the head of the packet queue 210 among the packets to which the right to use the work area 500 stored in the packet queue 210 is not granted. The right to use the work area 501 is granted (see step S23 in FIG. 4). This is because the packet # 4 stored in the storage area 211 is output to the processor 31, so that a packet that includes the same processor number = 1 and has already been granted the right to use the work area 500 is transferred to the packet queue. This is because one or more (more than the number of use right packets) does not exist in 210, that is, “0”.

  FIG. 10B shows the state of packets in the packet queue 210 and the work memory 50 at this time. More specifically, the work memory 50 is in a state in which no packet is stored in the work area 501 because the entire packet # 1 after processing is output by the processor 31. Further, the work area 504 stores a packet # 4 that is input from the packet queue 210 and for which the processor 31 performs arithmetic processing on the operation target data D. The work area 502 and the work area 503 in the work memory 50 are an arithmetic process for the calculation target data B included in the packet # 2 by the processor 32 and an arithmetic process for the calculation target data C included in the packet # 3 by the processor 33. This is the same as in the initial state.

  The packet queue 210 is in a state where the packet # 4 stored in the storage area 211 is output to the processor 31 and the packet # 5 to which the right to use the work area 501 is stored is stored in the storage area 211. Similarly, the storage area 212 stores the packet # 6 to which the use right of the work area 505 has already been granted, and the re-entry determination unit 230 stores the packet # 6 again in the last storage area 213 in the packet queue 210 ( The packet # 1 after the arithmetic processing entered is stored.

  Note that, as described above, the post-computation packet # 1 stored in the storage area 213 is a packet whose packet state information is “continue processing”, but the processor 31 responds to an instruction from the reentry determination unit 230. Is outputting the entire packet # 1 after the arithmetic processing, so that the arithmetic target data A2 is stored. In addition, although the packet # 1 after the arithmetic processing stored in the storage area 213 is a packet whose packet status information is “processing continuation”, the work given to the packet # 1 after the arithmetic processing by the re-entry determination unit 230 Since the right to use the area 501 is released, the right to use the work area 500 is not granted. This is because the packet # 6 to which the right to use the work area 505 has already been stored is stored in the storage area 212 before the storage area 213 in which the packet # 1 after the arithmetic processing is stored. This is because the right to use the work area 500 is not given to the packet # 1 after the arithmetic processing in which the same processor 32 as that of FIG.

  As described above, also in the arithmetic device 10 of the third embodiment, each work area 500 in the work memory 50 provided in the arithmetic device 10 is the same as the arithmetic device 10 of the first embodiment and the second embodiment. The usage rights of the number of work areas 500 necessary to execute the arithmetic processing on the packet are given according to the monitored usage status of the work areas 500. As a result, even in the arithmetic device 10 of the second embodiment, as in the arithmetic device 10 of the first and second embodiments, the competition of the work area 500 does not occur in each processor 30, and external A series of arithmetic processing for a plurality of packets input from the block 100 can be shared by the respective processors 30 and executed in parallel.

  In the arithmetic device 10 of the third embodiment, the right to use the work area 500 stored in the packet queue 210 is determined based on the usage status of each work area 500 in the work memory 50 provided in the arithmetic device 10. Check the number of packets attached. In the arithmetic device 10 of the third embodiment, the work area is set so that the number of packets processed by the same processor 30 to which the right to use the work area 500 is processed does not exceed the predetermined number of use right packets. Controls the granting of 500 usage rights. Thereby, in the arithmetic device 10 of 3rd Embodiment, it can prevent that the packet which the specific processor 30 performs arithmetic processing occupies the right to use the work area 500 in the work memory 50. . Thus, in the arithmetic device 10 according to the third embodiment, it is possible to improve the operation rate of each processor 30 without causing competition of the work area 500 by each processor 30. Note that the usage rights of the work area 500 are set so that the number of packets processed by the same processor 30 to which the usage right of the work area 500 in the third embodiment is granted does not exceed a predetermined number of usage right packets. The idea of controlling the assignment can be applied to any of the arithmetic devices 10 of the first and second embodiments.

  In the example of the operation of the arithmetic device 10 shown in FIGS. 8 to 10, each processor 30 corresponds to the work memory number included in the packet for executing the input arithmetic processing in the connection switching unit 40. After output to the address conversion unit 400 and the corresponding address conversion unit 400 connects the processor 30 and the work area 500 in a one-to-one relationship, the calculation target data is transferred to the work area 500 to perform calculation processing on the calculation target data. The case of executing was described. However, the output of the work memory number to the address conversion unit 400 for connecting the processor 30 and the work area 500 on a one-to-one basis is not performed by each processor 30, but by the packet management unit 20. You can also.

<Fourth Embodiment>
Next, a fourth embodiment of the present invention will be described. The arithmetic device according to the fourth embodiment is an arithmetic device to which the idea that the packet management unit controls connection switching between the processor 30 and the work area is applied. FIG. 11 is a block diagram illustrating an example of a schematic configuration of an arithmetic device according to the fourth embodiment. The arithmetic device 11 illustrated in FIG. 11 includes a packet management unit 21, three processors 31 to 33, three local memories 311 to 331, a connection switching unit 41, and a work memory 50. Yes. FIG. 11 also shows the external block 100 connected to the arithmetic unit 11.

  Note that in the arithmetic device 11 of the fourth embodiment, the packet management unit 20 and the connection switching unit 40 of the arithmetic device 10 of the first to third embodiments shown in FIG. And the connection switching unit 41, and other components are the same as those of the arithmetic device 10 of the first to third embodiments. In the following description, only the operation of components that are different from the arithmetic device 10 of the first to third embodiments will be described, and the same components as those of the arithmetic device 10 of the first to third embodiments are the same. The detailed description is abbreviate | omitted.

  The packet management unit 21 temporarily stores each of a plurality of packets input from the external block 100 in the same manner as the packet management unit 20 provided in the arithmetic device 10 of the first to third embodiments. The packet is assigned to any one processor 30. The packet management unit 21 includes a packet queue 260, a queue control unit 221, a reentry determination unit 230, a work memory usage status management register 240, and a processor usage status management register 250.

  The packet management unit 21 includes a packet queue 210 and a queue control unit 221 in the packet queue 210 and the queue control unit 220 in the packet management unit 20 provided in the arithmetic device 10 of the first to third embodiments. The other components are the same as the components of the packet management unit 20 included in the arithmetic device 10 of the first to third embodiments. In the following description, only the operation of components different from the packet management unit 20 provided in the arithmetic device 10 of the first to third embodiments will be described, and the arithmetic device 10 of the first to third embodiments will be provided. The same components as those of the packet management unit 20 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The queue control unit 221 stores (entries) each packet input from the external block 100 in the packet queue 260, similarly to the queue control unit 220 provided in the arithmetic device 10 of the first to third embodiments. The output of the packet stored in the packet queue 260 to the processor 30 according to the usage status of the processor 30 and the work memory 50 is controlled.

  However, unlike the queue control unit 220 provided in the arithmetic device 10 of the first to third embodiments, the queue control unit 221 first selects a packet to be output to the processor 30 and then selects the packet queue 260. The work memory number included in the packet is output to the address conversion unit corresponding to the processor number included in the selected packet. Thereafter, after receiving a notification indicating that the switching of the connection between the processor 30 and the work area 500 is completed from the corresponding address conversion unit, the calculation target data included in the packet selected as the packet to be output to the processor 30 is The packet 30 is output from the packet queue 260 to the corresponding processor 30.

  The packet queue 260 continues to be input from the plurality of packets input from the external block 100 and the re-entry determination unit 230, similarly to the packet queue 210 provided in the arithmetic device 10 of the first to third embodiments. Packets that execute arithmetic processing are sequentially stored. However, the packet queue 260 is different from the packet queue 210 provided in the arithmetic device 10 of the first to third embodiments, and the work memory number included in the stored packet is any one corresponding to the processor number. The operation target data included in the packet stored in one address conversion unit is output to any one of the processors 30 corresponding to the processor number. Note that the order of outputting the information of each packet stored in the packet queue 260 is controlled by the queue control unit 221 that operates in the same manner as the queue control unit 220 included in the arithmetic device 10 of the first to third embodiments. Is done.

  FIG. 11 shows a configuration of a packet queue 260 having five storage areas (storage areas 261 to 265) for storing packets. In FIG. 11, the numbers following “# (sharp)” shown in the respective storage areas in the packet queue 260 are the same as those in the packet queue 210 provided in the arithmetic device 10 of the first to third embodiments. The order in which packets are stored in the packet queue 260 is shown.

  In the connection switching unit 41, each processor 30 and each work area 500 in the work memory 50 are in a one-to-one relationship, similarly to the connection switching unit 40 provided in the arithmetic device 10 of the first to third embodiments. The connection and address between the processor 30 and the work area are switched so as to correspond. The connection switching unit 41 includes an address conversion unit 411 to an address conversion unit 413 and a crossbar switch 450.

  The connection switching unit 41 includes an address conversion unit 411 to an address conversion unit, each of the address conversion unit 401 to the address conversion unit 403 in the connection switching unit 40 included in the arithmetic device 10 of the first to third embodiments. The crossbar switch 450 is the same as the connection switching unit 40 provided in the arithmetic device 10 of the first to third embodiments. In the following description, only the operations of the address conversion unit 411 to the address conversion unit 413, which are different from the connection switching unit 40 provided in the arithmetic device 10 of the first to third embodiments, will be described, and the first to third implementations will be described. The crossbar switch 450 that is the same as the connection switching unit 40 included in the computing device 10 of the embodiment is given the same reference numeral, and detailed description thereof is omitted.

  Each of the address conversion unit 411 to the address conversion unit 413 is similar to each of the address conversion unit 401 to the address conversion unit 403 included in the arithmetic device 10 of the first to third embodiments. Corresponding to each of the three processors 31 to 33, the corresponding processor 30 and the work area 500 in the work memory 50 used when the corresponding processor 30 executes arithmetic processing are associated with each other in a one-to-one relationship. In the following description, when each of the three address conversion units 411 to 413 is expressed without distinction, it is referred to as an “address conversion unit 410”.

  In addition, each address conversion unit 410 controls the crossbar switch 450, and after the switching of the connection between the corresponding processor 30 and the work area 500 is completed, a notification indicating that the connection of the work area 500 is completed, This is notified to the queue control unit 221 in the packet management unit 21.

<Fourth operation>
The operation in the computing device 11 is such that the output source of the work memory number for switching the connection and address between the processor 30 and the work area so that each processor 30 and each work area 500 correspond one-to-one. Only the packet management unit 21 is replaced from each processor 30, and the operation can be considered in the same manner as the operation in the arithmetic device 10 of the first to third embodiments. Therefore, the detailed description regarding operation | movement of the arithmetic unit 11 is abbreviate | omitted.

  As described above, also in the arithmetic device 11 of the fourth embodiment, the processor 30 and the work area 500 are made to correspond one-to-one as in the arithmetic device 10 of the first to third embodiments. As a result, in the arithmetic device 11 of the fourth embodiment, as in the arithmetic devices 10 of the first to third embodiments, the content of the work area 500 does not occur in each processor 30, and the external block 100 can A series of arithmetic processing for a plurality of input packets can be shared by each processor 30 and executed in parallel.

  In the arithmetic device 11 of the fourth embodiment, the connection between the processor 30 and the work area 500 is switched by a packet management unit 21 that is different from the processor 30 that performs arithmetic processing on a packet. Thereby, in the arithmetic unit 11 of the fourth embodiment, the processing load for the processor 30 to switch the connection between the processor 30 and the work area 500 is reduced, and the connection between the processor 30 and the work area 500 is reduced. It is possible to reduce the time from the completion of the switching until the start of the transfer of the calculation target data to the work area 500, that is, the overhead time in the processor 30. Note that the idea that the packet management unit in the fourth embodiment controls the connection switching between the processor 30 and the work area can be applied to any of the arithmetic devices 10 in the first to third embodiments. .

  In addition, in the arithmetic device 10 of the first to third embodiments and the arithmetic device 11 of the fourth embodiment, each packet includes operation target data to be subjected to arithmetic processing, and the corresponding processor 30 is The configuration for transferring the calculation target data for executing the calculation processing to the corresponding work area 500 has been described. However, the arithmetic device is not limited to a configuration that performs arithmetic processing on a packet including calculation target data. For example, an arithmetic device in which the external block 100 stores arithmetic target data to be subject to arithmetic processing in the memory and executes arithmetic processing on the arithmetic target data stored in the external memory is also conceivable.

<Fifth Embodiment>
Next, a fifth embodiment of the present invention will be described. The arithmetic device according to the fifth embodiment is an arithmetic device configured to acquire operation target data from another component different from a packet and to execute a requested operation process on the acquired operation target data. FIG. 12 is a block diagram illustrating an example of a schematic configuration of an arithmetic device according to the fifth embodiment. The arithmetic device 12 shown in FIG. 12 includes a packet management unit 22, three processors 31 to 33, three local memories 311 to 331, a connection switching unit 40, and a work memory 52. Yes. In FIG. 12, as a system configuration including the arithmetic device 12 of the fifth embodiment, an external block 100 connected to the arithmetic device 12, a DMA (Direct Memory Access) control unit 60, and the arithmetic device 12. Also shown is a DRAM (Dynamic Random Access Memory) 200 connected to a bus 700 to which is connected.

  The DRAM 200 is an external memory arranged outside the arithmetic device 12 in which arithmetic target data on which the arithmetic device 12 performs arithmetic processing is stored. The DMA control unit 60 is a transfer control unit for calculation target data that performs DMA transfer between the DRAM 200 and the work memory 52 provided in the calculation device 12 via the bus 700 in accordance with control from the calculation device 12.

  The concept in the fifth embodiment, that is, the configuration for obtaining the computation target data from another component (DRAM 200 in FIG. 12) different from the packet and executing the requested computation process is shown in FIG. The present invention can be applied to any configuration of the arithmetic device 10 of the first to third embodiments shown and the arithmetic device 11 of the fourth embodiment shown in FIG. The configuration of the arithmetic device 12 shown in FIG. 12 is a configuration applied to the arithmetic device 10 of the first to third embodiments shown in FIG.

  In the system including the arithmetic device 12 of the fifth embodiment shown in FIG. 12, the operation target data is transferred between the DRAM 200 and the work memory 52 by the DMA transfer by the DMA control unit 60. For this reason, the calculation device 12 of the fifth embodiment stores calculation target data that is a target of calculation processing in a packet, instead of the “calculation target data” described in the calculation device 10 of the first embodiment. A packet including information on a “start address” that determines the start address of the storage area in the DRAM 200 and a “data size” that determines the size of the calculation target data is input from the external block.

  The arithmetic device 11 of the fifth embodiment has a configuration in which the packet management unit 20 and the work memory 50 of the arithmetic device 10 shown in FIG. 1 are replaced with the packet management unit 22 and the work memory 52, respectively. The other components are the same as those of the arithmetic unit 10 shown in FIG. In the following description, only the operation of components that are different from the arithmetic device 10 will be described, and the same components as those of the arithmetic device 10 will be assigned the same reference numerals, and detailed description thereof will be omitted.

  The work memory 52 temporarily stores calculation target data in each packet, data generated while each of the processors 30 is executing calculation processing on the calculation target data, and the like shown in FIG. 10 is a memory having the same configuration as the work memory 50 included in the memory 10. However, the work memory 52 has a function of performing DMA transfer of the operation target data via the bus 700. The configuration of the arithmetic unit 12 shown in FIG. 12 shows a work memory 52 having six work areas (work area 521 to work area 526). In the following description, when each of the six work areas 521 to 526 is expressed without being distinguished, it is referred to as a “work area 520”.

  In FIG. 12, corresponding to each of the six work areas 521 to 526, the work memory management register of the work memory use status management register 240 also includes six work memory management registers (work memory management register 241 to work memory. Management register 246).

  The packet management unit 22 temporarily stores each of a plurality of packets input from the external block 100, as in the packet management unit 20 provided in the arithmetic device 10 illustrated in FIG. Assigned to one processor 30. Further, the packet management unit 22 controls the DMA transfer of the operation target data between the DRAM 200 and the work memory 52 by the DMA control unit 60. The packet management unit 22 includes a packet queue 210, a queue control unit 222, a reentry determination unit 232, a work memory usage status management register 240, and a processor usage status management register 250.

  The packet management unit 22 includes a queue control unit 220 and a reentry determination unit 230 in the packet management unit 20 included in the arithmetic device 10, and a queue control unit 222 and a reentry determination unit 232, respectively. This is an alternative configuration, and the other components are the same as those of the packet management unit 20 provided in the arithmetic device 10 of the first to third embodiments. In the following description, only the operation of components different from the packet management unit 20 provided in the arithmetic device 10 of the first to third embodiments will be described, and the arithmetic device 10 of the first to third embodiments will be provided. The same components as those of the packet management unit 20 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The queue control unit 222 stores (entries) each packet input from the external block 100 in the packet queue 210, similarly to the queue control unit 220 included in the arithmetic device 10 of the first to third embodiments. The output of the packet stored in the packet queue 210 to the processor 30 according to the usage status of the processor 30 and the work memory 52 is controlled.

  In addition, the queue control unit 222 has a function of the queue control unit 220 included in the arithmetic device 10 of the first to third embodiments, based on the information on the start address and the data size included in the packet, and the DMA control unit 60. And a function for DMA transfer of the operation target data from the DRAM 200 to the work memory 52 is added.

  More specifically, first, the queue control unit 222 confirms a storage area in the DRAM 200 defined by the head address and the data size included in each packet stored in the packet queue 210. Then, the queue control unit 222 indicates the usage status of the work area 520 in the work memory 52 determined by the work memory number included in the packet confirming the storage area in the DRAM 200, as the work status in the work memory usage status management register 240. Check from the information in the memory management register. As a result of confirming the information of the storage area and the work memory management register in the DRAM 200, when the corresponding work area 520 can be used, that is, the work memory management register information has a data size determined size. If the calculation target data is “unused” for storing the calculation target data, the queue control unit 222 grants the right to use the work area. Then, the queue control unit 222 instructs the DMA control unit 60 to perform DMA transfer of the calculation target data corresponding to the data size from the head address to the corresponding work area 520.

  The DMA control unit 60, to which the DMA transfer instruction is input from the queue control unit 222, DMA-transfers the operation target data corresponding to the data size from the head address designated by the queue control unit 222 to the designated work area 520. .

  In addition, the queue control unit 222 displays the information of the work memory management register of the corresponding work area 520 in the work memory use state management register 240 corresponding to the work memory number included in the packet to which the work area use right is granted. Change to “In Use”. Thereafter, after the DMA transfer of the operation target data from the DRAM 200 to the work area 520 by the DMA control unit 60 is completed by the DMA control unit 60, the queue control unit 222 performs a packet for executing the operation process on the operation target data for which the DMA transfer is completed. The packet queue 210 outputs to the corresponding processor 30.

  The processor 30 to which the packet is input from the packet queue 210 acquires the work memory number included in the input packet, outputs it to the corresponding address conversion unit 400, and is connected to the corresponding work area 520 on a one-to-one basis. Thereafter, a calculation process is performed on the calculation target data transferred from the DRAM 200 to the corresponding work area 520.

  Similar to the reentry determination unit 230 provided in the arithmetic device 10 of the first to third embodiments, the reentry determination unit 232 outputs each packet input from each processor 30 to the external block 100 or The storage (entry) for the second time in the packet queue 210 and the release of the right to use the work area 520 assigned to each packet are controlled.

  In addition, the re-entry determination unit 232 performs DMA control on the basis of information on the start address and data size included in the packet, in addition to the function of the re-entry determination unit 230 provided in the arithmetic device 10 of the first to third embodiments. The function of transferring the calculation target data from the work memory 52 to the DRAM 200 before controlling the unit 60 and releasing the right to use the work area 520 is added.

  More specifically, first, when the packet status information of the packet after the arithmetic processing input from the processor 30 indicates “processing completed”, the reentry determination unit 232 externally transmits the packet after the arithmetic processing. It is determined that the data is output to the block 100, and the storage area in the DRAM 200 defined by the head address and the data size included in the packet after the arithmetic processing output to the external block 100 is confirmed. Then, the re-entry determination unit 232 confirms the work memory number included in the packet after the arithmetic processing, and the data size from the top address of the DRAM 200 of the arithmetic processing target data stored in the corresponding work area 520 after the arithmetic processing. The DMA control unit 60 is instructed to perform DMA transfer for the number of minutes.

  Subsequently, after the DMA transfer of the operation target data after the operation processing from the work area 520 to the DRAM 200 by the DMA control unit 60 is completed by the DMA control unit 60, the re-entry determination unit 232 stores information on the processor management register in the processor usage status management register 250. Is changed to “unused”, and the information of the work memory management register 240 in the work memory usage status management register 240 corresponding to the packet after the arithmetic processing is changed to “unused”, and the packet after the arithmetic processing The right to use the work area 520 given to the user is released. Then, the reentry determination unit 232 outputs the packet after the arithmetic processing to the external block 100.

  Further, the re-entry determination unit 232 stores the packet after the arithmetic processing in the packet queue 210 again when the packet state information of the packet after the arithmetic processing input from the processor 30 indicates “processing continuation” ( It is determined whether or not it is necessary to release the right to use the work area 520 given to the packet after the arithmetic processing. As a result of this confirmation, if it is necessary to release the right to use the work area 520, the DRAM 200 in the DRAM 200 defined by the start address and data size included in the packet after the arithmetic processing to be stored (entry) in the packet queue 210 again. Check the storage area. Further, the re-entry determination unit 232 confirms the work memory number included in the packet after the arithmetic processing to be stored (entry) in the packet queue 210 again, and the arithmetic target after the arithmetic processing stored in the corresponding work area 520 The DMA control unit 60 is instructed to perform DMA transfer of data corresponding to the data size from the start address of the DRAM 200.

  The DMA control unit 60 to which the DMA transfer instruction is input from the re-entry determination unit 232 also specifies the calculation target data after the calculation process stored in the work area 520 specified by the re-entry determination unit 232. DMA transfer is performed to the DRAM 200 by the data size from the head address.

  Subsequently, after the DMA transfer of the operation target data after the operation processing from the work area 520 to the DRAM 200 by the DMA control unit 60 is completed by the DMA control unit 60, the re-entry determination unit 232 stores information on the processor management register in the processor usage status management register 250. Is changed to “unused”, and the information of the work memory management register 240 in the work memory usage status management register 240 corresponding to the packet after the arithmetic processing is changed to “unused”, and the packet after the arithmetic processing The right to use the work area 520 given to the user is released. Then, the reentry determination unit 232 stores (entries) the packet after the arithmetic processing in the packet queue 210 again.

  With such a configuration, the packet management unit 22 outputs a plurality of packets input from the external block 100 and a packet after arithmetic processing input from the processor 30 to the processor 30 or output to the external block 100. At this time, the DMA control unit 60 controls the DMA transfer of the calculation target data between the DRAM 200 and the work memory 52.

  In the arithmetic device 12 shown in FIG. 12, the configuration in which the DMA control unit 60 is provided outside the arithmetic device 12 is shown. It is not limited to the position shown in. For example, the DMA control unit 60 may be configured to be included in the arithmetic device 12, that is, the DMA control unit 60 may be a component of the arithmetic device 12.

  Next, a processing procedure of arithmetic processing by the arithmetic device 12 will be described. The overall processing flow of the arithmetic processing executed by the arithmetic device 12 is the same as the overall processing flow of the arithmetic processing in the arithmetic device 10 of the first to third embodiments shown in FIG. Detailed description is omitted. In the following description, processing procedures of processing different from the processing of the arithmetic device 10 in the processing of the arithmetic device 12 will be described.

  First, the processing procedure of the right-of-use grant processing (step S2 shown in FIG. 2) of the work area 520 in the work memory 52 by the queue control unit 222 in the packet management unit 22 provided in the arithmetic device 12 will be described. FIG. 13 is a flowchart illustrating a processing procedure of a usage right granting process in which the queue control unit 222 provided in the arithmetic device 12 according to the fifth embodiment grants the usage right of the work area 520 in the work memory 52.

  When the queue control unit 222 starts the usage right granting process, first, in step S221, among the work areas 520 in the work memory 52, a work area 520 that can be used for packet calculation processing, that is, an unprocessed area. It is confirmed whether there is a work area 520 to be used. More specifically, the queue control unit 222 confirms information on each work memory management register in the work memory use status management register 240, and creates a work area 520 in which the work memory management register information is “unused”. Search for. In step S221, when there is no unused work area 520 (“NO” in step S221), the queue control unit 222 completes the usage right granting process.

  If there is an unused work area 520 in step S221 (“YES” in step S221), in step S222, the queue control unit 222 causes the processor included in each packet stored in the packet queue 210. The number is confirmed, and it is confirmed whether or not the number of packets to be processed by the same processor 30 to which the right to use the work area 520 is already assigned is equal to or larger than the number of used right packets. In step S222, when the number of packets processed by the same processor 30 to which the usage right of the work area 520 has already been given is equal to or larger than the number of usage right packets (“YES” in step S222), the queue control unit 222 Completes the usage right granting process.

  In step S222, if the number of packets processed by the same processor 30 to which the usage right of the work area 520 has already been granted is not equal to or greater than the number of usage right packets (“NO” in step S222), step S223 is performed. Then, the queue control unit 222 confirms whether there is a packet to which the right to use the work area 520 is not given in the packets already stored in the packet queue 210. In step S223, when there is no packet to which the usage right of the work area 520 is not granted (“NO” in step S223), the queue control unit 222 completes the usage right granting process.

  If there is a packet to which the right to use the work area 520 is not granted in step S223 (“YES” in step S223), in step S224, the queue control unit 222 checks the work area 520 confirmed in step S223. The right to use the work area 520 is given to the packet closest to the head of the packet queue 210 among the packets to which no right to use is assigned. In addition, the queue control unit 222 updates the information in the work memory management register 240 in the work memory use status management register 240 corresponding to the work area 520 to which the use right is given to the packet, to information indicating “in use”.

  Subsequently, in step S225, the queue control unit 222 confirms the head address and data size included in the packet closest to the head of the packet queue 210 to which the right to use the work area 520 is granted, and data from the confirmed head address. The DMA control unit 60 is instructed to perform DMA transfer of the calculation target data for the size from the DRAM 200 to the corresponding work area 520, and the usage right granting process is completed.

  By such processing, the queue control unit 222 confirms the unused work area 520 from the information of the work memory management register in the work memory usage status management register 240, and the packet to which the right to use the work area 520 is not granted. The right to use the work area 520 is granted. Then, the DMA control unit 60 is instructed to perform DMA transfer of operation target data corresponding to a packet to which the right to use the work area 520 is not granted. Note that the queue control unit 222 always performs use right grant processing. In other words, the queue control unit 222 always searches for an unused work area 520 and performs usage right grant processing while packets are stored in the packet queue 210. As a result, the queue control unit 222 performs an arithmetic operation used when executing arithmetic processing on another packet at an early timing after any work area 520 in the work memory 52 can be used. The target data is prepared in the corresponding work area 520, and the right to use the work area 520 can be given to this packet.

  Next, a processing procedure of queue management processing (step S3 shown in FIG. 2) by the queue control unit 222 in the packet management unit 22 provided in the arithmetic device 12 will be described. FIG. 14 is a flowchart illustrating a processing procedure of queue management processing in which the queue control unit 222 included in the arithmetic device 12 according to the fifth embodiment manages the output of the packets stored in the packet queue 210 to the processor 30. It is.

  When the queue control unit 222 starts the queue management process, first, in step S321, among the processors 30 included in the arithmetic unit 12, the processor 30 that can execute the packet arithmetic process, that is, an unused one. It is confirmed whether or not there is a processor 30. More specifically, the queue control unit 222 confirms information of each processor management register in the processor usage status management register 250 and searches for a processor 30 whose information in the processor management register is “unused”. In step S321, when there is no unused processor 30 (“NO” in step S321), the queue control unit 222 completes the queue management process.

  If there is an unused processor 30 in step S321 (“YES” in step S321), the queue control unit 222 grants the right to use the work area 520 stored in the packet queue 210 in step S322. It is confirmed whether or not there is a packet in which the unused processor 30 searched in step S321 is determined as the processor 30 that executes the arithmetic processing among the packets that have been searched. More specifically, the queue control unit 222 confirms the processor number included in the packet to which the right to use the work area 520 is granted, thereby defining the processor 30 that causes the unused processor 30 to execute arithmetic processing. Search for packets that have been sent. In step S322, when there is no packet defined as the processor 30 that causes the unused processor 30 to execute the arithmetic processing (“NO” in step S322), the queue control unit 222 completes the queue management process.

  In step S322, when there is a packet defined as a processor 30 that causes the unused processor 30 to execute arithmetic processing (“YES” in step S322), in step S323, the queue control unit 222 determines that the DMA It is confirmed whether or not the DMA transfer from the DRAM 200 to the corresponding work area 520 of the operation target data corresponding to the packet closest to the head of the packet queue 210 instructed to the control unit 60 is completed. As a result of the confirmation in step S323, if the DMA transfer of the operation target data from the DRAM 200 to the corresponding work area 520 is not completed ("NO" in step S323), step S322 is repeated to calculate the DMA of the operation target data. Wait for the transfer to complete.

  Further, as a result of the confirmation in step S323, when the DMA transfer of the operation target data from the DRAM 200 to the corresponding work area 520 is completed (“YES” in step S323), in step S324, the queue control unit 222 In step S322, the packet corresponding to the work area 520 for which the DMA transfer of the calculation target data has been completed is output to the processor 30 that executes the calculation process. Further, the queue control unit 222 updates the processor management register information in the processor usage status management register 250 corresponding to the packet output to the processor 30 to information indicating “in use”, and completes the queue management process.

  By such processing, the queue control unit 222 confirms the unused processor 30 from the information of the processor management register in the processor usage status management register 250, and defines it as a processor 30 that causes the unused processor 30 to execute arithmetic processing. After the DMA transfer of the operation target data of the received packet is completed, this packet is output to the corresponding processor 30. The queue control unit 222 always performs queue management processing. That is, the queue control unit 222 always searches for an unused processor 30 and performs queue management processing while packets are stored in the packet queue 210. Accordingly, the queue control unit 222 outputs the corresponding packet at an early timing when the DMA transfer of the operation target data is completed after any of the processors 30 included in the arithmetic device 12 can accept the packet. can do.

  Next, the processing procedure of the arithmetic processing (step S4 shown in FIG. 2) by the processor 30 provided in the arithmetic device 12 will be described. FIG. 15 is a flowchart illustrating a processing procedure in which the processor 30 included in the arithmetic device 12 according to the fifth embodiment executes arithmetic processing.

  When the corresponding packet is input from the packet queue 210 in the packet management unit 22, the processor 30 starts arithmetic processing. First, in step S421, the processor 30 acquires a work memory number included in the input packet. That is, information on the work area 520 used when executing arithmetic processing on the input packet is acquired.

  Subsequently, in step S422, the processor 30 outputs the acquired work memory number to the corresponding address conversion unit 400 in the connection switching unit 40. As a result, the corresponding address conversion unit 400 uses the processor 30 by referring to the table in which the work memory number and the work area 520 corresponding to the work memory number input from the processor 30 are associated one-to-one. The work area 520 to be specified is specified. Further, the corresponding address conversion unit 400 refers to a table that summarizes the control values of the crossbar switch 450 that connects the processor 30 and the work area 520 in the work memory 52 on a one-to-one basis. The determined control value is output to the crossbar switch 450. Thereby, the crossbar switch 450 switches the connection between the signal line of the processor 30 and the signal line of the work area 520 in accordance with the control value input from the address conversion unit 400, and makes a pair of the processor 30 and the work area 520. Connect to 1. The address conversion unit 400 notifies the corresponding processor 30 of a notification indicating that the connection of the work area 520 is completed after the switching of the connection between the processor 30 and the work area 520 by the crossbar switch 450 is completed.

  Subsequently, in step S423, the processor 30 transfers the processing number included in the input packet to the corresponding work area 520 via the corresponding address conversion unit 400 and the crossbar switch 450.

  Subsequently, in step S424, the processor 30 reads the processing code corresponding to the processing number included in the packet transferred to the work area 520 from the local memory connected to the processor 30, and executes the arithmetic processing on the operation target data. To do.

  Then, after completing the calculation process on the calculation target data, in step S425, the processor 30 updates the packet state information and the processor number of the packet after the calculation process. More specifically, when the packet after the arithmetic processing is a packet that takes over the arithmetic processing, the packet status information of the packet after the arithmetic processing is updated to “continue processing”, and the processor number is continuously calculated. The processor number of the next processor 30 (another processor 30 or itself) to be executed is updated. If the packet after the arithmetic processing is a packet that is output to the external block 100 when the arithmetic processing is completed, the packet status information of the packet after the arithmetic processing is updated to “processing complete”.

  Subsequently, when the calculation process for the calculation target data (step S424) and the update of the packet state information and the processor number (step S425) are completed, in step S426, the processor 30 has a packet after the calculation process to be output. To the re-entry determination unit 232 in the packet management unit 22. The re-entry determination unit 232 outputs a notification indicating that the packet is accepted to the processor 30 when the packet after the arithmetic processing can be acquired.

  When the processor 30 receives a notification indicating that the packet after the arithmetic processing is accepted from the re-entry determination unit 232, the processor 30 converts the packet after the arithmetic processing into the crossbar switch 450 and the corresponding address conversion in step S427. The data is output to the re-entry determination unit 232 via the unit 400, and the arithmetic processing is completed. It should be noted that the post-computation packet output to the re-entry determination unit 232 here does not matter whether or not the packet state information is “continue processing”, that is, even if the packet state information is “continue processing”. Even if the packet status information is “processing complete”, the packet is other than the calculation target data finally stored in the work area 520.

  By such processing, the processor 30 executes arithmetic processing on the calculation target data using the work area 520 corresponding to the input packet and in which the calculation target data is already stored. Then, the processor 30 updates the packet state information of the packet after the arithmetic processing and outputs it to the re-entry determination unit 232. At this time, the processor 30 outputs the post-computation packet other than the computation target data to the re-entry determination unit 232 regardless of the packet state information of the post-computation packet. As a result, the re-entry determination unit 232 determines whether or not to perform the DMA transfer of the operation target data stored in the work area 520 to the DRAM 200, and performs DMA transfer to the DMA control unit 60 according to the determination result. And unnecessary DMA transfer can be avoided. That is, the calculation target data used for the calculation processing can be stored (remaining) in the work area 520 without performing the DMA transfer to the DRAM 200, and the DMA transfer can be efficiently performed. Can do.

  Next, the procedure of the reentry determination process (step S5 shown in FIG. 2) by the reentry determination unit 232 in the packet management unit 22 provided in the arithmetic device 12 will be described. FIG. 16 is a flowchart illustrating a processing procedure of reentry determination processing in which the reentry determination unit 232 included in the arithmetic device 12 according to the fifth embodiment stores a packet again.

  When the re-entry determination unit 232 starts the re-entry determination process, first, in step S521, the processor 30 determines whether or not there is a notification indicating that there is a packet after the calculation process, that is, after the calculation process from the processor 30. Check whether there is a request for permission to output other packets. In step S521, when there is no output permission request for the packet after the arithmetic processing from the processor 30 (“NO” in step S521), the reentry determination unit 232 completes the reentry determination process.

  In step S521, when there is an output permission request for the packet after the arithmetic processing from the processor 30 ("YES" in step S521), the reentry determination unit 232 acquires the packet after the arithmetic processing from the processor 30. Then, the information of the processor management register in the processor usage status management register 250 corresponding to the acquired packet after the arithmetic processing is updated to information indicating “unused”. In step S <b> 522, the re-entry determination unit 232 confirms whether the packet state information of the post-calculation packet input from the processor 30 is “continue processing”.

  In step S522, when the packet status information of the packet after the arithmetic processing input from the processor 30 is “processing continuation” (“YES” in step S522), that is, the packet after the arithmetic processing is a packet that takes over the arithmetic processing. If there is, in step S523, the re-entry determination unit 232 stores the post-computation packet input this time from the processor 30 in the storage area next to the storage area in which the packet is already stored in the packet queue 210. That is, the current entry is stored (entry) in the last storage area, and the re-entry determination process is completed. In other words, the re-entry determination unit 232 stores (entries) the packet in the packet queue 210 again while giving the right to use the work area 520 to the packet after the arithmetic processing input this time.

  In step S522, when the packet status information of the packet after the arithmetic processing input from the processor 30 is not “processing continuation” (“NO” in step S522), that is, the packet status information is “processing completed”. If the packet is to be output to the external block 100, in step S524, the re-entry determination unit 232 checks the start address and data size included in the acquired packet after the arithmetic processing, and stores it in the corresponding work area 520. The DMA control unit 60 is instructed to perform DMA transfer corresponding to the data size from the start address confirmed by the DRAM 200 of the operation target data after the operation processing.

  Subsequently, in step S525, the re-entry determination unit 232 confirms whether the DMA transfer from the work area 520 of the operation target data after the operation processing, which is instructed to the DMA control unit 60, to the DRAM 200 is completed. As a result of the confirmation in step S525, if the DMA transfer of the operation target data from the work area 520 to the DRAM 200 is not completed (“NO” in step S525), step S525 is repeated to perform the DMA transfer of the operation target data. Wait for completion.

  As a result of the confirmation in step S525, when the DMA transfer of the operation target data from the work area 520 to the DRAM 200 is completed (“YES” in step S525), in step S526, the reentry determination unit 232 The right to use the work area 520 given to the input packet after the arithmetic processing is released. More specifically, the right to use the work area 520 is updated by updating the information in the work memory management register corresponding to the packet after the arithmetic processing in the work memory use status management register 240 to information indicating “unused”. Is released.

  Subsequently, in step S527, the re-entry determination unit 232 outputs the packet after the arithmetic processing that releases the right to use the work area 520 to the external block 100, and completes the re-entry determination process. Note that the post-computation packet output to the external block 100 here is a packet other than the computation target data finally stored in the work area 520, although the packet status information is “processing complete”.

  By such processing, the re-entry determination unit 232 switches the output destination of the packet after the arithmetic processing according to the packet state information of the packet after the arithmetic processing input from the processor 30. The reentry determination unit 232 always performs reentry determination processing. That is, the re-entry determination unit 232 always monitors the output permission request for the post-computation packet output from the processor 30 while the arithmetic device 12 is operating, and performs the re-entry determination process. In the re-entry determination process, the packet after the arithmetic processing whose packet state information is “processing continuation” is stored (entry) in the packet queue 210 again, and the packet after the arithmetic processing whose packet state information is “processing complete” Is output to the external block 100. At this time, the post-computation packet output to the external block 100 by the re-entry determination unit 232 indicates that the post-computation packet other than the computation target data is sent to the external block 100 even if the packet status information is “processing complete” Output. For this reason, the external block 100 can acquire post-arithmetic operation target data from the DRAM 200 as necessary when a post-arithmetic packet whose packet state information is “processing complete” is input.

  As described above, the arithmetic device 12 requests the external block 100 by constantly performing a series of arithmetic processing on a plurality of packets input from the external block 100 for each packet stored in the packet queue 210. A plurality of arithmetic processes can be executed in parallel. At this time, a packet including information other than the calculation target data is input from the external block 100 to the arithmetic device 12. Then, in accordance with the execution of the arithmetic processing, the arithmetic device 12 transfers the operation target data stored in the DRAM 200 to the work memory 52 by DMA transfer, and the operation target data after the operation processing is transferred to the DRAM 200 by DMA transfer. Forward. As a result, the size of the packet input to the arithmetic unit 12 can be reduced, and each processor 30 does not need to transfer the operation target data to the work memory 52. Therefore, the packet in the processor 30 is transferred to the work memory 52. The time required for the transfer can be reduced. Further, since the calculation target data can be stored in the work memory 52 in advance by DMA transfer, execution of calculation processing on the calculation target data is started after the switching of the connection between the processor 30 and the work area 500 is completed. It is possible to reduce the time to wait, that is, the overhead time that is waited until the processor 30 executes the arithmetic processing.

<Fifth operation>
Here, an example of the operation in the arithmetic unit 12 will be described. The operation of the arithmetic device 12 will be described by paying attention to the packets in the packet queue 210 and the work memory 52, as in the description of the operation in the arithmetic device 10 of the first to third embodiments. FIG. 17 is a diagram illustrating an example of packet states in the packet queue 210 and the work memory 52 at each processing stage in the operation of the arithmetic device 12 according to the fifth embodiment.

  FIG. 17 shows the correspondence between the address of the DRAM 200 and the calculation target data stored in the DRAM 200, that is, the arrangement of the calculation target data in the DRAM 200. FIG. 17 shows “calculation target data” and “processor number” corresponding to each packet as the state of the packet in the work memory 52. FIG. 17 also shows the state of the packet in the packet queue 210 as “start address”, “processor number”, “work memory” indicating the storage area of the DRAM 200 in which the calculation target data corresponding to each packet is stored. “Number” and “packet state information”. The packet status in the packet queue 210 also indicates “number of used memories”. This number of used memories corresponds to a “data size” that determines the size of the calculation target data stored in the DRAM 200. For example, when the number of used memories = 1, it indicates that the calculation target data corresponding to one work area 520 is stored in the DRAM 200. In the following description, it is assumed that the number of used memories is only the number of used memories = 1.

  The “processor number” and “work memory number” in the state of each packet shown in FIG. 17 include the packet in the operation of the arithmetic device 10 of the first to third embodiments shown in FIGS. Similarly to the example of the state of the packet in the queue 210 and the work memory 50, the last one digit of the sign of each processor 30 and the last one digit of the sign of each work area 520 are shown. Also, in order to facilitate the explanation in the state of each packet shown in FIG. 17, the packet queue 210 and the work in the operation of the arithmetic unit 10 of the first to third embodiments shown in FIGS. Similarly to the example of the state of the packet in the memory 50, an item “packet number” and an item “processor in process” are shown. Further, in the state of the packet in the packet queue 210 shown in FIG. 17, for easy explanation, the corresponding calculation target is indicated in “(): parentheses” following the head address in the “head address” item. Data are shown.

  First, calculation target data stored in the DRAM 200 shown in FIG. 17A will be described. Calculation target data to be subjected to calculation processing in each packet is stored for a data size corresponding to one work area 520 from each head address of the DRAM 200. More specifically, for example, consider a case where the size (size) of each work area 520 in the work memory 52 is 0x1000 in the configuration of the arithmetic unit 12 shown in FIG. In this case, the state shown in FIG. 17A represents that the calculation target data A is stored in the physical addresses 0x1000 to 0x1FFF of the DRAM 200. Similarly, in the state shown in FIG. 17A, the calculation target data B is stored in the physical address 0x2000-0x2FFF of the DRAM 200, and the calculation target data C is stored in the physical address 0x3000-0x3FFF of the DRAM 200. ing. Similarly, in the state shown in FIG. 17A, the operation target data D is the physical address 0x4000 to 0x4FFF of the DRAM 200, the operation target data E is the physical address 0x5000 to 0x5FFF of the DRAM 200, and the operation target data F is the DRAM 200. This indicates that the physical address 0x6000 to 0x6FFF and the calculation target data G are stored in the physical address 0x7000 to 0x7FFF of the DRAM 200, respectively.

  Next, the operation of the arithmetic device 12 will be described. It is assumed that the number of usage right packets in the fifth operation is the number of usage right packets = 1. First, in the operation of the arithmetic unit 12, as shown in FIG. 17B, three packets are stored in the work memory 52, four packets are stored in the packet queue 210, and in the packet queue 210. Among the stored packets, the right to use the work area 520 has already been given by the queue control unit 222 to the two packets close to the head and the last packet. When the queue control unit 222 grants the right to use the work area 520 to each packet, the queue control unit 222 responds to the DMA control unit 60 with the calculation target data corresponding to the data size from the start address of the DRAM 200 included in the packet to which the usage right is given. The DMA transfer to the work area 520 to be performed is instructed. As a result, the DMA transfer of the calculation target data corresponding to the packet to which the right to use the work area 520 has already been granted by the DMA control unit 60 is completed in the work memory 52. The subsequent operation will be described with the state of the packets in the packet queue 210 and the work memory 52 as the initial state of the arithmetic unit 12.

  More specifically, the initial state of the work memory 52 is that the processor 31 performs arithmetic processing on the operation target data A stored in the start address 0x1000 of the DRAM 200 that is first input to the work area 521 in the packet queue 210. Is stored in the packet # 1. Also, in the work area 522, packet # 2 is stored in which the processor 32 performs arithmetic processing on the operation target data B stored in the leading address 0x2000 of the DRAM 200, which is input second in the packet queue 210, In the area 523, a packet # 3 is stored in which the processor 33 executes arithmetic processing on the operation target data C stored in the leading address 0x3000 of the DRAM 200, which is input third in the packet queue 210. .

  In the initial state of the packet queue 210, the processor 31 performs an arithmetic process on the operation target data D stored in the start address 0x4000 of the DRAM 200, which is input fourth in the packet queue 210 in the storage area 211. In this state, packet # 4 to which the right to use the work area 524 is granted is stored. In the storage area 212, the right to use the work area 525, in which the processor 32 executes arithmetic processing on the operation target data E stored in the leading address 0x5000 of the DRAM 200, which is input fifth in the packet queue 210, is used. In this state, the assigned packet # 5 is stored. In the storage area 213, the right to use the work area 520, in which the processor 31 executes the arithmetic process on the operation target data F stored in the start address 0x6000 of the DRAM 200, which is input sixth in the packet queue 210, is used. This is a state where unassigned packet # 6 is stored. Note that the use right of the work area 520 is not given to the packet # 6 because the number of use right packets = 1, so that the work area 521 is already included in the packet # 4 in which the same processor 31 executes the arithmetic processing. This is because usage rights are granted. In the storage area 214, the right to use the work area 526, in which the processor 33 executes arithmetic processing on the operation target data G stored in the leading address 0x7000 of the DRAM 200, which is input seventh in the packet queue 210, is used. In this state, the assigned packet # 7 is stored.

  The initial state of the work memory 52 is that the operation target data D corresponding to the packet # 4 to which the work area 524 is already granted the right to use the work area 524 is already stored in the work area 525 and the work area 525 is already used. The calculation target data E corresponding to packet # 5 to which is assigned is stored in the work area 526, and the calculation target data G corresponding to packet # 7 to which the right to use the work area 526 is already stored is stored. It is.

  From this initial state, when the processor 31 has completed the arithmetic processing for the operation target data A corresponding to the packet # 1, a series of arithmetic processing by the arithmetic device 12 is completed, and the packet state information is updated to “processing complete”. Consider a case where the packet # 1 after the above arithmetic processing is output to the re-entry determination unit 232. Although the packet status information of packet # 1 after the arithmetic processing is “processing completed”, as described above, the processor 31 performs arithmetic processing other than the arithmetic target data A finally stored in the work area 521. The subsequent packet # 1 is output to the re-entry determination unit 232 (see step S427 in FIG. 15).

  The re-entry determination unit 232 that has acquired the packet # 1 after the arithmetic processing updates the information in the processor management register 251 in the processor usage status management register 250 corresponding to the processor 31 to information indicating “unused” (FIG. 16 step S521). Then, the re-entry determination unit 232 confirms the start address (= 0x4000) and the number of used memories (data size) included in the packet # 1 after the arithmetic processing, and after the arithmetic processing stored in the corresponding work area 521 The DMA control unit 60 is instructed to perform DMA transfer of the calculation target data A (hereinafter referred to as “calculation target data A2”) (see step S524 in FIG. 16).

  Subsequently, the re-entry determination unit 232 instructs the DMA control unit 60 whether the DMA transfer for the data size has been completed from the start address (= 0x4000) of the DRAM 200 of the calculation target data A2 after the calculation process. After confirming (see step S525 in FIG. 16) and completing the DMA transfer, the information in the work memory management register 241 in the work memory use status management register 240 is updated to information indicating “unused”. Then, the re-entry determination unit 232 releases the right to use the work area 521 given to the packet # 1 after the arithmetic processing (see step S526 in FIG. 16). Then, the reentry determination unit 232 outputs the acquired packet # 1 after the arithmetic processing to the external block 100 (see step S527 in FIG. 16).

  In addition, the queue control unit 222 indicates that the information in the processor management register 251 corresponding to the processor 31 has become “unused” by the re-entry determination unit 232, that is, the processor 31 can execute the packet calculation process. As a result, among the packets to which the right to use the work area 520 stored in the packet queue 210 is granted, the processor number = 1 corresponds to the packet # 4 closest to the head of the packet queue 210. It is confirmed whether or not the DMA transfer of the operation target data D from the DRAM 200 to the work area 524 is completed (see step S323 in FIG. 14). Then, the queue control unit 222 causes the packet queue 210 to output the packet # 4 to the processor 31 after the DMA transfer of the calculation target data D to the work area 524 is completed. Further, the queue control unit 222 updates the information in the processor management register 251 in the processor usage status management register 250 corresponding to the processor 31 to information indicating “in use” (see step S324 in FIG. 14).

  Thereafter, the processor 31 outputs the work memory number included in the input packet # 4 to the corresponding address conversion unit 401, and after the processor 31 and the work area 524 are connected one-to-one (step in FIG. 15). (Refer to S422), the calculation process is performed on the calculation target data D corresponding to the packet # 4 (see Step S424 in FIG. 15).

  In addition, the queue control unit 222 uses the re-entry determination unit 232 to change the information in the work memory management register 241 in the work memory usage status management register 240 corresponding to the work area 521 to “unused”, so that the right to use the work area 521 In the packet queue 210 that is not granted the right to use the work area 520 stored in the packet queue 210, the processor number = 1 and the packet queue 210 at the top of the packet queue 210. The right to use the work area 521 is given to the near packet # 6 (see step S224 in FIG. 13). This is because the packet # 4 stored in the storage area 211 is output to the processor 31, so that a packet that includes the same processor number = 1 and is already granted the right to use the work area 520 is transferred to the packet queue. This is because one or more (more than the number of use right packets) does not exist in 210, that is, “0”.

  Subsequently, the queue control unit 222 confirms the start address and the data size included in the packet # 6 to which the right to use the work area 521 is granted, and the calculation target data F corresponding to the data size from the confirmed start address is received from the DRAM 200. The DMA control unit 60 is instructed to perform DMA transfer to the corresponding work area 521 (see step S225 in FIG. 13).

  FIG. 17C shows the state of packets in the packet queue 210 and the work memory 52 at this time. More specifically, the work memory 52 is in a state where the calculation target data F corresponding to the packet # 6 DMA-transferred by the DMA control unit 60 is stored in the work area 521, and the work area 524 is stored in the packet queue 210. A packet # 4 is stored in which the processor 31 executes arithmetic processing on the input operation target data D. The work area 522 and the work area 523 in the work memory 52 are calculated by the processor 32 for the calculation target data B corresponding to the packet # 2, and the processor 33 performs the calculation process for the calculation target data C corresponding to the packet # 3. This is the same as in the initial state. Also, the work area 525 and the work area 526 in the work memory 52 are not used for execution of arithmetic processing by the processor 32 and the processor 33, and thus are the same as in the initial state.

  The packet queue 210 is in a state where the packet # 4 stored in the storage area 211 is output to the processor 31 and the packet # 5 is stored in the storage area 211. The packet # 6 to which the right to use the work area 521 is granted is stored, and the packet # 7 is stored in the storage area 213.

  In this way, the arithmetic device 12 constantly monitors and monitors the usage status of each work area 520 in the work memory 52 provided in the arithmetic device 12 and the usage status of each processor 30 provided in the arithmetic device 12. Depending on the situation, the operation target data corresponding to each packet is DMA-transferred between the DRAM 200 and the work memory 52. And the arithmetic device 12 allocates each packet to the corresponding processor 30, and performs arithmetic processing similarly to the arithmetic device 10 of the 1st-3rd embodiment. At this time, since the processor 30 and the work area 520 have a one-to-one correspondence, similarly to the arithmetic device 10 of the first to third embodiments, each processor 30 does not compete with the work area 520. A series of arithmetic processing for a plurality of packets input from the external block 100 can be shared by the processors 30 and executed in parallel.

  In the arithmetic unit 12, the DMA control unit 60 DMA-transfers the operation target data that is the target of the operation processing of each packet. As a result, the arithmetic device 12 can reduce the size of the packet input from the external block 100 and reduce the time required for the processor 30 to transfer the operation target data to the work memory 52.

  In the arithmetic unit 12, the calculation target data is stored in advance in the corresponding work area 520 in the work memory 52 by the DMA control unit 60. As a result, the processor 30 can start execution of the arithmetic processing at an earlier timing after the corresponding packet is input, and the overhead time generated by each processor 30 transferring the operation target data is reduced. can do.

  Note that each packet for which the arithmetic device executes arithmetic processing may have a priority order when the arithmetic processing is executed. For this reason, the queue control unit needs to give the right to use the work area in the work memory according to the priority of each packet, and to control the output of the packet stored in the queue to the processor.

<Sixth Embodiment>
Next, a sixth embodiment of the present invention will be described. The arithmetic device of the sixth embodiment is configured to control the order in which work area usage rights are granted based on the priority of each input packet. The concept in the sixth embodiment is shown in the arithmetic device 10 of the first to third embodiments shown in FIG. 1, the arithmetic device 11 of the fourth embodiment shown in FIG. 11, and FIG. In addition, the present invention can be applied to any configuration of the arithmetic device 12 of the fifth embodiment. In the following description, a case will be described in which the idea of the sixth embodiment is applied to the arithmetic device 12 of the fifth embodiment shown in FIG.

  In the sixth embodiment, as described above, the order of granting the right to use the work area is controlled based on the priority of each input packet. For this reason, “priority” information that determines the priority for executing the arithmetic processing on the packet is added to the packet input to the arithmetic device 12 of the sixth embodiment. The priority is set for each packet by the external block 100 or each processor 30.

  In the arithmetic device 12 of the sixth embodiment, a function for controlling the order of granting the right to use the work memory 52 according to the priority is added to the queue control unit 222 and the reentry determination unit 232. The configuration and processing procedure of the arithmetic device 12 of the sixth embodiment are the same as those of the arithmetic device 12 of the fifth embodiment. Therefore, in the following description, the arithmetic device of the sixth embodiment is the arithmetic device 12, and only functions added to the respective components provided in the arithmetic device 12 will be described.

  The queue control unit 222 has a function of controlling the right to use the work area 520 assigned to each packet according to the priority of each packet stored in the packet queue 210. The queue control unit 222 grants the right to use the work area 520 in order from the packet with the highest priority in the packets processed by the same processor 30, and outputs them to the corresponding processor 30. If a plurality of packets with the same priority processed by the same processor 30 are stored in the packet queue 210, the right to use the work area 520 is assigned in order from the packet closer to the head, and the corresponding processor 30 is assigned. Output to.

  More specifically, first, the queue control unit 222 confirms the processor number included in each packet stored in the packet queue 210. Then, the queue control unit 222 checks the priority included in each packet among packets including the same processor number. Then, the queue control unit 222 grants the right to use the work area 520 according to the confirmed priority. Note that the right to use the work area 520 may be reassigned when the state of the packet stored in the packet queue 210 changes.

  For example, as a result of confirming the processor number and the priority included in each packet stored in the packet queue 210, the priority of the packet including the same processor number to which the right to use the work area 520 has already been assigned is If the usage right of the work area 520 stored later in the packet queue 210 is higher than the packet to which the use right of the work area 520 is not granted, the use right of the work area 520 that has already been granted is granted and stored in the packet queue 210 later. The packet is output to the corresponding processor 30 prior to the low priority packet. Further, for example, the priority of a packet including the same processor number to which the right to use the work area 520 is already assigned is higher than that of the packet to which the right to use the work area 520 stored in the packet queue 210 is not granted later. If it is lower, the right to use the work area 520 that has already been granted is released, and the right to use the work area 520 is reassigned to a packet having a high priority stored in the packet queue 210 later. Then, after the right to use the work area 520 is reassigned, the packet stored in the packet queue 210 later is output to the processor 30 corresponding to the previous one. Further, for example, the priority of a packet including the same processor number to which the right to use the work area 520 is already assigned, and the packet to which the right to use the work area 520 stored in the packet queue 210 is not granted later. If the priorities are the same, they are output to the corresponding processor 30 in the order stored in the packet queue 210.

  In the re-entry determination unit 232, when a packet whose packet status information is “process continuation” is acquired from each processor 30, each re-entry determination unit 232 depends on the priority of each packet stored in the packet queue 210. A function for controlling the release of the right to use the work area 520 given to the packet is added. The re-entry determination unit 232 releases the right to use the work area 520 of the low-priority packet in the packet processed by the same processor 30 even when the packet status information is “process continuation”, and then sets the packet queue Store (entry) in 210 again. Note that even when a plurality of packets with the same priority processed by the same processor 30 are stored in the packet queue 210, the right to use the work area 520 is released and stored again in the packet queue 210 (entry). To do.

  More specifically, first, the reentry determination unit 232 confirms the processor number included in each packet stored in the packet queue 210. The re-entry determination unit 232 includes each packet including the same processor number and a packet whose packet state information to be stored (entry) in the packet queue 210 is “process continuation”. Check the priority. Then, the re-entry determination unit 232 releases the right to use the work area 520 according to the confirmed priority. Note that the right to use the work area 520 is released after the operation target data to be transferred corresponding to the packet to be stored (entry) again in the packet queue 210 is saved in the DRAM 200, that is, the DMA control unit 60 takes over. This is performed after the completion of the DMA transfer of the operation target data to be performed to the DRAM 200. Further, the re-entry determination unit 232 is given the right to use the work area 520 when the number of usage right packets to be processed by the same processor 30 to which the right to use the work area 520 is assigned is set. Release the right of use of the work area 520 assigned to each packet according to the number of use right packets and priority so that the number of packets processed by the same processor 30 does not exceed the number of use right packets. To control.

  For example, when a packet whose packet status information is “processing continuation” is acquired from the processor 30, the re-entry determination unit 232 first checks the processor number and priority included in each packet stored in the packet queue 210. To do. Then, the re-entry determination unit 232 has the same processor number included in the packet to which the right to use the work area 520 is already assigned and the processor number included in the packet stored (entry) in the packet queue 210 again. It is confirmed whether or not there are more packets in the packet queue 210 than the number of use right packets. As a result of this confirmation, when there are more packets in the packet queue 210 that have the same processor number to which the right to use the work area 520 has been assigned, the highest priority is given to these packets. The priority of the packet that is the lowest and closest to the tail in the packet queue 210 is compared with the packet whose packet status information to be stored (entry) in the packet queue 210 is “continue processing”.

  As a result of this comparison, when the packet status information to be stored (entry) again in the packet queue 210 is lower in priority of the packet whose processing status is “continuation of processing”, even when the packet status information is “processing continues”, The operation target data corresponding to the packet to be stored (entry) again is saved in the DRAM 200, and the right to use the work area 520 given to the packet is released, and then stored (entry) in the packet queue 210. As a result of comparison, if the priority of a packet whose packet state information stored (entry) in the packet queue 210 is “continuation of processing” is higher, the same processor number is included and the priority is lowest. The operation target data corresponding to the packet closest to the tail in the packet queue 210 is saved in the DRAM 200, and the right to use the work area 520 given to this packet is released. When the same processor number that releases the right to use the work area 520 is included, the lowest priority, and the packet status information of the packet closest to the tail in the packet queue 210 is “continue processing” Then, after the operation target data to be used when the operation processing is continued in the packet is saved in the DRAM 200, the right to use the work area 520 is released.

<Sixth operation>
Here, an example of the operation in the case of controlling the order of assigning the right to use work areas based on the priority of packets in the arithmetic device 12 according to the sixth embodiment will be described. Also in the description of the sixth operation, the operation of the arithmetic unit 10 will be described by paying attention to the packets in the packet queue 210 and the work memory 50. In the sixth operation as well, the number of use right packets is assumed to be the number of use right packets = 1. FIG. 18 is a diagram illustrating an example of the state of packets in the packet queue 210 and the work memory 52 at each processing stage in the operation of the arithmetic device 12 according to the sixth embodiment.

  FIG. 18 shows the address of the DRAM 200 and the operation target stored in the DRAM 200, as in the example of the arrangement of the operation target data in the DRAM 200 in the operation of the arithmetic device 12 of the fifth embodiment shown in FIG. The correspondence with the data is shown. In addition, FIG. 18 shows, as an example of the state of the packet in the work memory 52 in the operation of the arithmetic unit 12 of the fifth embodiment shown in FIG. “Calculation target data” and “processor number” corresponding to the packet are shown. In addition, FIG. 18 shows, as an example of the state of the packet in the packet queue 210 in the operation of the arithmetic device 12 of the fifth embodiment shown in FIG. The “number of used memories”, “start address”, “processor number”, “work memory number”, and “packet state information” included in the packet are shown. The packet status in the packet queue 210 also indicates “priority”. Here, it is assumed that priority = 1 is the highest priority and priority = 3 is the lowest priority.

  The “processor number” and “work memory number” in the state of each packet shown in FIG. 18 include the packet queue 210 and the work memory 52 in the operation of the arithmetic unit 12 of the fifth embodiment shown in FIG. Similarly to the example of the state of the packet, the last digit of the sign of each processor 30 and the last digit of the sign of each work area 520 are shown. Also, in the state of each packet shown in FIG. 18, in order to facilitate the explanation, the packet queue 210 and the packet in the work memory 52 in the operation of the arithmetic unit 12 of the fifth embodiment shown in FIG. Similarly to the example of the state, an item “packet number” and an item “processor in process” are shown. Also, in order to facilitate the description of the state of the packet in the packet queue 210 shown in FIG. 18, the state of the packet in the packet queue 210 in the operation of the arithmetic device 12 of the fifth embodiment shown in FIG. Similarly to the example, the corresponding calculation target data is shown in “(): parentheses” following the head address in the item “head address”. Note that the arithmetic device 12 of the sixth embodiment will be described assuming that the packet queue 210 includes eight storage areas (storage areas 211 to 218).

  First, calculation target data stored in the DRAM 200 shown in FIG. Calculation target data to be subjected to calculation processing in each packet is stored for a data size corresponding to one work area 520 from each head address of the DRAM 200. More specifically, for example, considering the case where the size (size) of each work area 520 in the work memory 52 is 0x1000, in the state shown in FIG. Stored in physical addresses 0x1000 to 0x1FFF. Similarly, in the state shown in FIG. 18A, the calculation target data B is stored in the physical address 0x2000-0x2FFF of the DRAM 200, and the calculation target data C is stored in the physical address 0x3000-0x3FFF of the DRAM 200. ing. Similarly, in the state shown in FIG. 18A, the operation target data D is the physical address 0x4000 to 0x4FFF of the DRAM 200, the operation target data E is the physical address 0x5000 to 0x5FFF of the DRAM 200, and the operation target data F is the DRAM 200. This indicates that the physical address 0x6000 to 0x6FFF and the calculation target data G are stored in the physical address 0x7000 to 0x7FFF of the DRAM 200, respectively. Similarly, in the state shown in FIG. 18A, the operation target data H is stored in the physical address 0x8000 to 0x8FFF of the DRAM 200, and the operation target data I is stored in the physical address 0x9000 to 0x9FFF of the DRAM 200. Represents.

  Next, the operation of the arithmetic device 12 will be described. Note that the number of usage right packets in the sixth operation is the number of usage right packets = 1. First, in the operation of the arithmetic unit 12, as shown in FIG. 18B, three packets are stored in the work memory 52, six packets are stored in the packet queue 210, and in the packet queue 210. Of the stored packets, the right to use the work area 520 has already been given by the queue control unit 222 to the two packets near the head and the fourth packet. As a result, the DMA transfer of the operation target data corresponding to the packet to which the use right of the work area 520 has already been granted by the DMA control unit 60 instructed by the queue control unit 222 to the DMA transfer is completed. ing. The subsequent operation will be described with the state of the packets in the packet queue 210 and the work memory 52 as the initial state of the arithmetic unit 12.

  More specifically, the initial state of the work memory 52 is that the processor 31 performs arithmetic processing on the operation target data A stored in the start address 0x1000 of the DRAM 200 that is first input to the work area 521 in the packet queue 210. Is stored in the packet # 1. Also, in the work area 522, packet # 2 is stored in which the processor 32 performs arithmetic processing on the operation target data B stored in the leading address 0x2000 of the DRAM 200, which is input second in the packet queue 210, In the area 523, a packet # 3 is stored in which the processor 33 executes arithmetic processing on the operation target data C stored in the leading address 0x3000 of the DRAM 200, which is input third in the packet queue 210. .

  In the initial state of the packet queue 210, the processor 31 performs an arithmetic process on the operation target data D stored in the start address 0x4000 of the DRAM 200, which is input fourth in the packet queue 210 in the storage area 211. In this state, packet # 4 to which the right to use the work area 524 is granted is stored. In the storage area 212, the right to use the work area 525, in which the processor 32 executes arithmetic processing on the operation target data E stored in the leading address 0x5000 of the DRAM 200, which is input fifth in the packet queue 210, is used. In this state, the assigned packet # 5 is stored. In the storage area 213, the right to use the work area 520, in which the processor 33 executes arithmetic processing on the arithmetic target data F stored in the leading address 0x6000 of the DRAM 200, which is input sixth in the packet queue 210, is used. This is a state where unassigned packet # 6 is stored. In the storage area 214, the right to use the work area 526, in which the processor 33 executes arithmetic processing on the operation target data G stored in the leading address 0x7000 of the DRAM 200, which is input seventh in the packet queue 210, is used. In this state, the assigned packet # 7 is stored. Note that the use right of the work area 520 is not granted to the packet # 6 because the number of use right packets = 1, so that the same processor 33 has already assigned the high-priority packet # 7 for executing the arithmetic processing. This is because the right to use the work area 526 is given. In the storage area 215, the right to use the work area 520, in which the processor 32 executes the arithmetic process on the operation target data H stored in the first address 0x8000 of the DRAM 200, which is input eighth in the packet queue 210, is used. This is a state where unassigned packet # 8 is stored. In the storage area 216, the right to use the work area 520, in which the processor 31 performs arithmetic processing on the operation target data I stored in the leading address 0x9000 of the DRAM 200, which is input ninth in the packet queue 210, is used. This is a state where unassigned packet # 9 is stored.

  The initial state of the work memory 52 is that the operation target data D corresponding to the packet # 4 to which the work area 524 is already granted the right to use the work area 524 is already stored in the work area 525 and the work area 525 is already used. The calculation target data E corresponding to packet # 5 to which is assigned is stored in the work area 526, and the calculation target data G corresponding to packet # 7 to which the right to use the work area 526 is already stored is stored. It is.

  From this initial state, the processor 31 completes the arithmetic processing for the operation target data A corresponding to the packet # 1, sets the processor number to “3” in order to take over the next arithmetic processing to the processor 33, and sets the packet state information to “ Consider a case where the packet # 1 after the arithmetic processing with the priority “1” updated to “continue processing” is output to the re-entry determination unit 232. Since the packet state information of the packet # 1 after the arithmetic processing is “processing continuation”, as described above, the processor 31 determines that the next calculation target data (hereinafter referred to as the following calculation target data) that is finally stored in the work area 521. Packet # 1 after calculation processing other than “calculation target data A2” is output to the re-entry determination unit 232 (see step S427 in FIG. 15).

  The re-entry determination unit 232 that has acquired the packet # 1 after the arithmetic processing updates the information in the processor management register 251 in the processor usage status management register 250 corresponding to the processor 31 to information indicating “unused” (FIG. 16 step S521). Then, the re-entry determination unit 232 stores a packet in which the use right of the work area 520 is already granted with the same processor number as the processor number included in the packet # 1 after the arithmetic processing stored in the packet queue 210. Check the number of In the sixth operation, the packet # 7 stored in the storage area 214 is confirmed, and the re-entry determination unit 232 determines that there is one or more (more than the number of used right packets) in the packet queue 210. Then, the re-entry determination unit 232 has the lowest priority in the packet in the packet queue 210, the priority included in the packet # 7 closest to the tail in the packet queue 210, and the packet # 1 after the arithmetic processing. Compare the included priorities. In the sixth operation, since the priority of the packet # 7 stored in the storage area 214 is lower than the priority of the packet # 1 after the arithmetic processing, the re-entry determination unit 232 sets the packet # 7 to the packet # 7. The use right of the assigned work area 526 is released, and it is stored (entry) again in the packet queue 210 while the use right of the work area 521 is given to the packet # 1 after the arithmetic processing (see step S523 in FIG. 16). . The packet # 7 stored in the storage area 214 is given the right to use the work area 526 and then the right to use the work area 526 is released. Since it is “unprocessed”, the re-entry determination unit 232 causes the DMA control unit 60 to perform DMA transfer of the operation target data G when the right to use the work area 526 is released, that is, save the operation target data G. Do not instruct.

  In addition, the queue control unit 222 indicates that the information in the processor management register 251 corresponding to the processor 31 has become “unused” by the re-entry determination unit 232, that is, the processor 31 can execute the packet calculation process. As a result, among the packets to which the right to use the work area 520 stored in the packet queue 210 is granted, the processor number = 1 corresponds to the packet # 4 closest to the head of the packet queue 210. It is confirmed whether or not the DMA transfer of the operation target data D from the DRAM 200 to the work area 524 is completed (see step S323 in FIG. 14). Then, the queue control unit 222 causes the packet queue 210 to output the packet # 4 to the processor 31 after the DMA transfer of the calculation target data D to the work area 524 is completed. Further, the queue control unit 222 updates the information in the processor management register 251 in the processor usage status management register 250 corresponding to the processor 31 to information indicating “in use” (see step S324 in FIG. 14).

  Thereafter, the processor 31 outputs the work memory number included in the input packet # 4 to the corresponding address conversion unit 401, and after the processor 31 and the work area 524 are connected one-to-one (step in FIG. 15). (Refer to S422), the calculation process is performed on the calculation target data D corresponding to the packet # 4 (see Step S424 in FIG. 15).

  In addition, the queue control unit 222 causes the re-entry determination unit 232 to change the information in the work memory management register 246 in the work memory usage status management register 240 corresponding to the work area 526 to “unused”, and the right to use the work area 526 In the packet queue 210 that is not granted the right to use the work area 520 stored in the packet queue 210, the processor number = 1 and the packet queue 210 at the top of the packet queue 210. The right to use the work area 526 is granted to the near packet # 9 (see step S224 in FIG. 13). This is because the packet # 4 stored in the storage area 211 is output to the processor 31, so that a packet that includes the same processor number = 1 and is already granted the right to use the work area 520 is transferred to the packet queue. This is because one or more (more than the number of use right packets) does not exist in 210, that is, “0”.

  Subsequently, the queue control unit 222 confirms the start address and the data size included in the packet # 9 to which the right to use the work area 526 is granted, and the calculation target data I corresponding to the data size from the confirmed start address from the DRAM 200. The DMA control unit 60 is instructed to perform DMA transfer to the corresponding work area 526 (see step S225 in FIG. 13).

  FIG. 18C shows the state of packets in the packet queue 210 and the work memory 52 at this time. More specifically, the state of the work memory 52 is stored in the work area 521 as operation target data A2 as a result of the processor 31 executing operation processing on the operation target data A of packet # 1 (remaining). The work area 524 stores a packet # 4 input from the packet queue 210 and executed by the processor 31 on the operation target data D. The packet transferred to the work area 526 by the DMA control unit 60 is DMA-transferred. The calculation target data I corresponding to # 9 is stored. The work area 522 and the work area 523 in the work memory 52 are calculated by the processor 32 for the calculation target data B corresponding to the packet # 2, and the processor 33 performs the calculation process for the calculation target data C corresponding to the packet # 3. This is the same as in the initial state. Further, the work area 525 in the work memory 52 is not used for the execution of the arithmetic processing by the processor 32, and thus is similar to the initial state.

  The packet queue 210 is in a state where the packet # 4 stored in the storage area 211 is output to the processor 31 and the packet # 5 is stored in the storage area 211. Packet # 6 is stored, and packet # 7 in which the right to use work area 526 is released is stored in storage area 213. The storage area 214 stores packet # 8, the storage area 215 stores packet # 9 to which the right to use the work area 526 is stored, and the last storage area 216 in the packet queue 210 stores The packet # 1 after the arithmetic processing stored again (entry) by the re-entry determining unit 232 is stored.

  Here, from the initial state shown in FIG. 18B, the processor 31 completes the arithmetic processing for the operation target data A corresponding to the packet # 1, and sets the processor number to take over the next arithmetic processing to the processor 33. An example of the case where the priority of packet # 1 after the arithmetic processing is different in the case where packet # 1 after the arithmetic processing whose packet state information is updated to “continue processing” is output to the re-entry determination unit 232. Will be described. FIG. 19 is a diagram illustrating an example of the state of the packet in the packet queue 210 and the work memory 52 at each processing stage when the priorities are different in the operation of the arithmetic unit 12 of the sixth embodiment. In FIG. 19A, when the priority is “2”, FIG. 19B shows each packet queue 210 corresponding to FIG. 18C when the priority is “3”. An example of the state of a packet in the work memory 52 is shown.

  First, from the initial state shown in FIG. 18B, the processor 31 completes the calculation process for the calculation target data A corresponding to the packet # 1, and the processor number “ 3, and a case where the packet # 1 after the arithmetic processing with the priority “2” updated to “continue processing” in the packet state information is output to the re-entry determination unit 232 will be described.

  The re-entry determination unit 232 that acquired the packet # 1 after the arithmetic processing with the priority = 2 performs the packet stored in the storage area 214 in the same manner as when the packet # 1 after the arithmetic processing with the priority = 1 is acquired. Confirm # 7 as a packet to be compared with the priority. The re-entry determination unit 232 compares the priority included in the packet # 7 and the priority included in the packet # 1 after the calculation process of priority = 2, and as a result, the priority of each packet is the same. Therefore, the right to use the work area 526 given to the packet # 7 is not released, and the DMA transfer of the computation target data A2 after the computation processing corresponding to the packet # 1 after the computation processing with the priority = 2, that is, Instruct to save the calculation target data A2 to the DRAM 200. This means that if the right of use of the work area 521 is given to the packet # 1 after the calculation process with the priority = 2, the processor number stored in the packet queue 210 = 3 when the packet is stored again (entry) in the packet queue 210. This is because the number of packets to which the right to use the work area 520 has already been granted is one or more (more than the number of used right packets). After that, the re-entry determination unit 232 completes the DMA transfer of the calculation target data A2 stored in the work area 521 to the DRAM 200, and then the work area 521 given to the packet # 1 after the calculation process with priority = 2. The right to use is released.

  In addition, the queue control unit 222 uses the re-entry determination unit 232 to change the information in the work memory management register 241 in the work memory usage status management register 240 corresponding to the work area 521 to “unused”, so that the right to use the work area 521 In the packet queue 210 that is not granted the right to use the work area 520 stored in the packet queue 210, the processor number = 1 and the packet queue 210 at the top of the packet queue 210. The right to use the work area 521 is given to the near packet # 9 (see step S224 in FIG. 13). This is because the packet # 4 stored in the storage area 211 is output to the processor 31, so that a packet that includes the same processor number = 1 and is already granted the right to use the work area 520 is transferred to the packet queue. This is because one or more (more than the number of use right packets) does not exist in 210, that is, “0”.

  Subsequently, the queue control unit 222 confirms the head address and the data size included in the packet # 9 to which the right to use the work area 521 is granted, and the calculation target data I corresponding to the data size from the confirmed head address is read from the DRAM 200. The DMA control unit 60 is instructed to perform DMA transfer to the corresponding work area 521 (see step S225 in FIG. 13).

  Thereby, the state of the packet in the packet queue 210 and the work memory 52 becomes the state shown in FIG. More specifically, the work memory 52 is stored in the work area 521 in which the calculation target data I corresponding to the packet # 9 DMA-transferred by the DMA control unit 60 is stored, and in the work area 524 from the packet queue 210. A packet # 4 is stored in which the processor 31 executes arithmetic processing on the input operation target data D. The work area 522 and the work area 523 in the work memory 52 are calculated by the processor 32 for the calculation target data B corresponding to the packet # 2, and the processor 33 performs the calculation process for the calculation target data C corresponding to the packet # 3. This is the same as in the initial state. Also, the work area 525 and the work area 526 in the work memory 52 are not used for execution of arithmetic processing by the processor 32 and the processor 33, and thus are the same as in the initial state.

  The packet queue 210 is in a state where the packet # 4 stored in the storage area 211 is output to the processor 31 and the packet # 5 is stored in the storage area 211. The packet # 6 is stored, and the storage area 213 stores the packet # 7 with the right to use the work area 526 still stored. The storage area 214 stores packet # 8, the storage area 215 stores packet # 9 to which the right to use the work area 521 is stored, and the last storage area 216 in the packet queue 210 stores The packet # 1 after the arithmetic processing in which the right to use the work area 521 is released and stored (entry) again by the re-entry determination unit 232 is stored.

  In the above description, a case has been described in which the re-entry determination unit 232 releases the right to use the work area 521 when the packet # 7 having the same priority is confirmed. However, the right to use the work area 521 that has been released has been described. It is considered that the work area 520 is also released when the calculation processing of each packet stored in the work area 520 prior to the storage area 215 in which the packet # 9 to which the packet # 9 is stored is completed. Therefore, the re-entry determination unit 232 immediately considers that the packet state information of the packet # 1 after the arithmetic processing for releasing the use right of the work area 521 is “processing continuation”, and immediately uses the work area 521. For example, based on a predetermined condition such as the order in which the packet # 9 is output to the processor 30, the packet # 1 after the arithmetic processing is assigned to the packet queue 210 with the right to use the work area 521 being granted. It may be configured to store (entry) again.

  Next, from the initial state shown in FIG. 18B, the processor 31 completes the arithmetic processing for the operation target data A corresponding to the packet # 1, and sets the processor number to take over the next arithmetic processing to the processor 33. A case will be described in which “3” is output and packet # 1 after the arithmetic processing with the priority “3” updated to “continue processing” in the packet state information is output to the re-entry determination unit 232.

  The re-entry determination unit 232 that acquired the packet # 1 after the arithmetic processing with the priority = 3 receives the packet stored in the storage area 214 in the same manner as when the packet # 1 after the arithmetic processing with the priority = 1 is acquired. Confirm # 7 as a packet to be compared with the priority. Then, the re-entry determination unit 232 compares the priority included in the packet # 7 and the priority included in the packet # 1 after the arithmetic processing with the priority = 3, and as a result, the re-entry determining unit 232 Since the priority is lower than the priority of the packet # 7, the right to use the work area 526 given to the packet # 7 is not released, and it corresponds to the packet # 1 after the arithmetic processing of the priority = 3. An instruction to save the calculation target data A2 after the calculation processing to the DRAM 200 is given. After that, the re-entry determination unit 232 completes the DMA transfer of the calculation target data A2 stored in the work area 521 to the DRAM 200, and then the work area 521 given to the packet # 1 after the calculation process with the priority = 3. The right to use is released.

  Further, in response to the fact that the right to use the work area 521 can be granted, the queue control unit 222 receives the packet # 1 after the arithmetic processing of the priority = 2, The right to use the work area 521 is given to # 9 (see step S224 in FIG. 13). Subsequently, the queue control unit 222 performs DMA control on the DMA transfer of the calculation target data I from the DRAM 200 to the corresponding work area 521 in the same manner as when the packet # 1 after the calculation process with the priority = 2 is acquired. The unit 60 is instructed (see step S225 in FIG. 13).

  As a result, the state of the packet in the packet queue 210 and the work memory 52 becomes the state shown in FIG. Note that the state of the packet in the packet queue 210 and the work memory 52 shown in FIG. 19B is when the priority shown in FIG. 19A is 2 except for the priority of the packet after the arithmetic processing. The packet queue 210 and the state of the packet in the work memory 52 are the same as those in FIG.

  In the subsequent operation, in the packet for which the same processor 33 executes the arithmetic processing, the work area is set to the packet # 6 having the same priority and close to the head of the packet queue 210 before the packet # 1 after the arithmetic processing. 520 usage rights are granted.

  As described above, in the arithmetic device 12 of the sixth embodiment, as in the arithmetic device 12 of the fifth embodiment, the usage status of each work area 520 in the work memory 52 provided in the arithmetic device 12 and the arithmetic The usage status of each processor 30 provided in the apparatus 12 is constantly monitored, and the calculation target data corresponding to each packet is DMA-transferred between the DRAM 200 and the work memory 52 according to the monitored status. Then, similarly to the arithmetic device 12 of the fifth embodiment, the arithmetic device 12 assigns each packet to the corresponding processor 30 to execute arithmetic processing. At this time, since the processor 30 and the work area 520 have a one-to-one correspondence, as in the arithmetic device 12 of the fifth embodiment, the content of the work area 520 does not occur in each processor 30, and the external block A series of arithmetic processing on a plurality of packets input from 100 can be shared by each processor 30 and executed in parallel.

  Further, the arithmetic unit 12 controls the right to use the work area to be assigned to each packet based on the priority of each packet. Even if the packets stored in the packet queue 210 are late in order, the right to use the work area 520 is granted to the packets with high priority at an early timing. That is, priority is given to the packet priority over the order stored in the packet queue 210 (packet priority> order stored in the packet queue 210), and the order in which the right to use the work area 520 is given is controlled. . Thereby, in the arithmetic device 12 of the sixth embodiment, the right to use the work area 520 corresponding to a packet having a high priority is preferentially given, the frequency of saving the operation target data is reduced, and the operation target data is transferred. By doing so, the overhead time generated can be reduced. As a result, the arithmetic device 12 of the sixth embodiment can complete a series of arithmetic processing for a packet with high priority at an early timing. Note that the concept of controlling the order in which work area usage rights are granted based on the priority of packets in the sixth embodiment is the same as that in any of the arithmetic devices 10 of the first to third embodiments. The present invention can also be applied to the arithmetic device 11 of the fourth embodiment.

  As described above, according to the embodiment for carrying out the present invention, the content of requested arithmetic processing in the arithmetic device that shares a plurality of data storage units (work areas) with a plurality of processing arithmetic units (processors). When executing arithmetic processing for a plurality of packets representing the data in parallel, the usage status of each data storage unit and the usage status of each processing arithmetic unit are constantly monitored, and the calculation for each packet is performed according to the monitored status. A process is assigned to each processing operation unit. At this time, in the form for implementing this invention, the data storage part provided to each packet so that a process calculating part and the data storage part used when performing a calculation process may correspond to 1 to 1 Change usage rights dynamically. Thereby, in the form for implementing this invention, when each process calculating part performs the calculation process with respect to a corresponding packet, the access with respect to the same data storage part between process calculating parts does not compete, A plurality of requested arithmetic processes can be executed in parallel. That is, each processing operation unit can exclusively use the data storage unit to which the usage right is given.

  Moreover, according to the form for implementing this invention, the use right of a data storage part is not provided to the several packet more than the predetermined threshold value which the same process calculating part performs arithmetic processing. That is, in the embodiment for carrying out the present invention, the right to use the data storage unit is used so that the number of packets processed by the same processing operation unit to which the right to use the data storage unit is given does not exceed a predetermined threshold. Control the grant of At this time, in the embodiment for carrying out the present invention, the priority of the arithmetic processing in each packet is also taken into consideration. Thereby, in the form for implementing this invention, it can prevent that the packet which a specific process calculating part performs a calculation process occupies the usage right of a data storage part. Thereby, in the form for implementing this invention, the operation rate of each process calculating part can be improved, without the competition of the data storage part by each process calculating part generating.

  Moreover, according to the form for implementing this invention, the address at the time of a process calculating part accessing a data storage part is converted into the address of a data storage part. Thereby, in the form for implementing this invention, each process calculating part does not consider the address of the data storage part used when performing the calculation process with respect to a packet (without being conscious), Even when the data storage unit is used, the arithmetic processing can be executed in the same manner.

  Note that, in the present embodiment, for example, the configuration in which the queue control unit 220 outputs each packet stored in the packet queue 210 to the corresponding processor 30 has been described, but the operation when outputting the packet to the processor 30 is described. Is not limited to the operation of the embodiment for carrying out the present invention. For example, the queue control unit 220 notifies the corresponding processor 30 that a packet that can be output exists in the packet queue 210, and the processor 30 that has received this notification acquires the packet from the packet queue 210. That is, a configuration for reading a packet may be used.

  In the present embodiment, for example, after the processor 30 outputs (after entering) the post-computation packet output to the re-entry determination unit 230 in the packet queue 210, the queue control unit 220 stores the packet in the packet queue 210. In this order, the packets are output to the corresponding processor 30. However, as described above, each component included in the arithmetic device 10 always performs each process in parallel. Therefore, the timing at which the packet is stored (entry) again in the packet queue 210 and the timing at which the packet is output from the packet queue 210 to the processor 30 are not limited to the operation of the mode for carrying out the present invention. For example, after the queue control unit 220 outputs the packet stored in the packet queue 210 to the corresponding processor 30, the operation-processed packet output by the processor 30 to the re-entry determination unit 230 is stored again in the packet queue 210 (entry ).

  In the present embodiment, the configuration in which the work memory is provided in the arithmetic device has been described. However, the position at which the work memory is provided is not limited to the operation of the embodiment for carrying out the present invention. Can be provided outside the arithmetic unit. Further, the number of work areas in the work memory is not limited to the operation of the mode for carrying out the present invention. In this case, the number of work memory management registers in the work memory usage status management register 240 is appropriately changed according to the number of work areas in the work memory. Similarly, the number of storage areas in the queue is not limited to the operation of the embodiment for carrying out the present invention.

  In this embodiment, an example of an arithmetic device including three processors 31 to 33 has been described. However, the number of processors included in the arithmetic device is limited to the operation of the embodiment for carrying out the present invention. The concept of the present invention can be similarly applied to a configuration in which more processors than two or three are mounted in the arithmetic device. In this case, the number of processor management registers in the processor usage status management register 250, the local memory 300, the address conversion unit 400, or the address conversion unit 410 is appropriately changed according to the number of processors provided in the arithmetic device.

  In the present embodiment, the processing function of each processor 30 is not described. For example, when the arithmetic device 10 is provided in an imaging system such as an imaging device, each processor 30 It can be considered that the imaging system has a processing function for performing image processing.

  Further, in the present embodiment, the processing functions possessed by the respective processors 30 included in the arithmetic device 10 are not described. However, for example, when the arithmetic device 10 is an image processing device provided in an imaging system such as an imaging device, the processing functions of the respective processors 30 are YC conversion processing, noise removal processing, distortion correction processing, and scratch correction. It is considered that this is a processing function capable of performing various image processing in the imaging system such as processing and image compression processing. Further, for example, when the arithmetic device 10 is a part of image processing in the imaging system, such as an image recognition unit in an image processing device provided in an imaging system such as an imaging device, each processor 30 The processing function is considered to be a processing function for performing various processes in some processing units in the image processing apparatus.

  The embodiment of the present invention has been described above with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes various modifications within the scope of the present invention. It is.

10, 11, 12 ... arithmetic devices 20, 21, 22 ... packet management units 210, 260 ... packet queues 211, 212, 213, 214, 215, 261, 262, 263, 264, 265,. -Storage area (packet queue)
220, 221, 222 ... Queue control unit (packet management unit, queue control unit)
230, 232 ... Re-entry control unit (packet management unit, re-entry determination unit)
240... Work memory usage status management register (packet management unit)
241, 242, 243, 244, 245, 246 ... Work memory management register (packet management unit)
250... Processor usage status management register (packet management unit)
251, 252, 253... Processor management register (packet management unit)
30, 31, 32, 33... Processor (processing operation unit)
300, 311, 321, 331... Local memory (processing operation unit)
40, 41 ... connection switching unit 400, 401, 402, 403, 410, 411, 412, 413 ... address conversion unit (connection switching unit)
450 ... Crossbar switch (connection switching part)
50, 52 ... Work memory (data storage unit)
500, 501, 502, 503, 504, 505, 520, 521, 522, 523, 524, 525, 526... Work area (data storage unit)
60: DMA controller (transfer controller)
100: External block 200: DRAM (external memory)
700 ... Bus

Claims (9)

A computing device that receives a plurality of packets including information indicating the content of requested computation processing, and performs computation processing on the input packet.
A plurality of processing arithmetic units having a processing function for performing arithmetic processing according to the content of the arithmetic processing requested in the packet, and outputting a packet after arithmetic processing including information indicating the content of arithmetic processing to be executed next; ,
The processing operation unit stores operation target data to be subjected to operation processing on the packet, or data obtained as a result of execution of operation processing on the packet, and is shared by each of the processing operation units. A data storage unit;
A packet that includes a packet queue that sequentially stores the packets, grants the right to use the data storage unit to each of the packets stored in the packet queue, and outputs the packet to any one of the processing arithmetic units The management department,
Based on the information on the right to use the data storage unit assigned to the packet, the processing operation unit that performs operation processing on the packet, and the data storage unit used when executing operation processing on the packet; A connection switching unit for switching the connection of
An arithmetic device comprising: The packet management unit
Based on the usage status of each of the processing operation units and the usage status of each of the data storage units, one or more usage rights of the data storage units are granted to the packet, and the use of the data storage units A queue control unit that causes the packet to which the right is granted to be output from the packet queue to any one of the processing arithmetic units that performs arithmetic processing on the packet;
A re-entry determining unit that determines an output destination of the packet after the arithmetic processing based on information in the packet after the arithmetic processing output from each of the processing arithmetic units;
With
The connection switching unit
The data storage unit and the processing operation unit are connected so that the data storage unit to which the usage right is given to the packet and the processing operation unit that executes the operation processing on the packet are connected one-to-one. A crossbar switch to
Based on information on the right to use the data storage unit attached to the packet, the switching of the connection between the data storage unit and the processing operation unit by the crossbar switch is controlled. An address conversion unit that converts a logical address when the processing operation unit accesses the data storage unit into a physical address of the data storage unit to which a right to use is granted;
The arithmetic unit according to claim 1, further comprising: The queue control unit
The same processing operation unit to which the right to use the data storage unit is not given is subjected to the processing, and the packets stored in the packet queue are sequentially stored in the packet queue in order from the first packet stored in the packet queue. Grant usage rights,
The same processing operation unit to which the right to use the data storage unit is given outputs the packets to be executed to the corresponding processing operation unit in order from the packets stored in the packet queue in order from the earlier And
The re-entry determination unit
Based on the information in the packet after the arithmetic processing, determine whether the packet after the arithmetic processing is a packet output from the arithmetic device or a packet requesting the next arithmetic processing,
When the packet after the arithmetic processing is a packet output from the arithmetic device, the right to use the data storage unit attached to the packet after the arithmetic processing is released and output,
If the packet after the arithmetic processing is a packet requesting the next arithmetic processing, the packet after the arithmetic processing is stored again in the packet queue.
The arithmetic unit according to claim 2. The queue control unit
Based on the information in the packet that grants the right to use the data storage unit, the usage right to the data storage unit is granted to the packet,
The address conversion unit
The processing arithmetic unit that executes arithmetic processing on the packet to which a plurality of data storage unit usage rights are granted continuously accesses each of the data storage units to which usage rights have been granted. Translate addresses so that you can,
The arithmetic unit according to claim 3. The queue control unit
The data is set so that the number of the packets for which the same processing operation unit to which the right to use the data storage unit is given executes the arithmetic processing does not exist in the packet queue more than a predetermined number of packets. The same processing operation unit to which the right to use the storage unit is not granted controls the grant of the right to use the data storage unit to the packet for executing the arithmetic processing,
The re-entry determination unit
When the packet after the arithmetic processing is stored again in the packet queue, the same processing arithmetic unit as the processing arithmetic unit that performs the arithmetic processing on the packet after the arithmetic processing executes the arithmetic processing, The number of the packets to which the right to use the data storage unit is given is given to the packet after the arithmetic processing to be stored again in the packet queue so that it does not exist in the packet queue more than the threshold of the number of packets Controlling the release of the right to use the data storage unit;
The arithmetic unit according to claim 3 or 4, characterized by the above. The queue control unit
The same processing operation unit to which the right to use the data storage unit is not assigned has a high priority when performing the operation processing, and the order in which the packets are stored in the packet queue. In order starting from the earlier packet, the right to use the data storage unit is granted,
The same processing operation unit to which the right to use the data storage unit is assigned has a higher priority when performing the operation processing, and the order in which the packets are stored in the packet queue is higher. In order from the packet, output to the corresponding processing operation unit,
The re-entry determination unit
When the packet after the arithmetic processing is stored again in the packet queue, the processing arithmetic unit that performs the arithmetic processing on the packet after the arithmetic processing performs the arithmetic processing by the same processing arithmetic unit. In the packet to which the right to use the storage unit is given, and the packet after the calculation process, the priority when executing the calculation process is high, and the packets stored in the packet queue are in order from the packet stored in the earlier order. Controls the release of the right to use the data storage unit assigned to the packet stored in the packet queue or the packet after the arithmetic processing to be stored again in the packet queue so as to have the right to use the data storage unit To
The arithmetic unit according to any one of claims 3 to 5, wherein the arithmetic unit is any one of the above. The calculation target data is
Included in each said packet,
The processing operation unit is
After the crossbar switch is connected to the data storage unit to which the right to use the packet for executing the arithmetic processing is connected, the arithmetic target data included in the packet for executing the arithmetic processing is transferred to the data storage unit And performing a calculation process on the transferred calculation target data,
The arithmetic unit according to any one of claims 3 to 6, wherein the arithmetic unit is any one of the above. The calculation target data is
Stored in an external memory arranged outside the arithmetic unit,
The arithmetic unit is
A transfer control unit for controlling transfer of the operation target data between the external memory and the data storage unit;
Further comprising
The queue control unit
Before outputting the packet to which the right to use the data storage unit is assigned to the corresponding processing operation unit, the operation target data corresponding to the packet is transferred from the external memory to the data storage unit to which the right to use is assigned. Instructing the transfer control unit to transfer,
After the transfer of the operation target data to the data storage unit is completed under the control of the transfer control unit, the packet to which the right to use the data storage unit is output is output to the corresponding processing operation unit,
The re-entry determination unit
Before releasing the right to use the data storage unit attached to the packet or the packet after the arithmetic processing, transferring the operation target data corresponding to the packet from the data storage unit to the external memory, Instruct the transfer control unit,
After the transfer of the operation target data to the external memory is completed under the control of the transfer control unit, the right to use the data storage unit attached to the packet is released.
The arithmetic unit according to any one of claims 3 to 6, wherein the arithmetic unit is any one of the above. The queue control unit
Information on the right to use the data storage unit attached to the packet is output to the address conversion unit,
After the crossbar switch connects the processing arithmetic unit that executes arithmetic processing on the packet and the corresponding data storage unit, the packet is output to the processing arithmetic unit;
The arithmetic unit according to claim 3, wherein the arithmetic unit is any one of claims 3 to 8.

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