JP6144376B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachislot machine.

  Conventionally, multiple reels with multiple symbols on each surface, game medals, coins, etc. are inserted, the start lever is operated by the player, and the start of rotation of multiple reels is requested A stop switch that detects that the player has pressed a stop button provided corresponding to each of the plurality of reels, and outputs a signal requesting the rotation of the corresponding reel to stop, A stepping motor is provided corresponding to each of the reels, and the operation of the stepping motor is controlled based on the signals output from the start switch and the stop switch that transmit the respective driving forces to the reels. A reel control unit that rotates and stops the rotation, and when it detects that the start lever has been operated, This is called so-called pachislot, in which the reel rotation is stopped based on the result of the lottery (hereinafter referred to as “internal winning combination”) and the timing at which the stop button is detected to be operated. Are known.

  This type of gaming machine has a main control circuit that controls the progression of a series of games such as determination of internal winning combination and reel rotation control, and determination and execution of effect data based on various commands output from this main control circuit. And a sub-control circuit that performs various processes such as the above.

  In recent years, an act of illegally operating a gaming machine by analyzing a command transmitted from a main control circuit to a sub-control circuit has been discovered. Therefore, a technique has been proposed in which an encrypted command is sent from the main control circuit to the sub control circuit and decrypted by the sub control circuit (see, for example, Patent Documents 1 and 2).

Japanese Patent Laid-Open No. 2005-21660 JP 2006-204324 A

  However, the conventional ones described in Patent Documents 1 and 2 are those in which a command encrypted by the main control circuit is simply decrypted by the sub control circuit, and it is found that the decrypted command is not a regular command. However, that information was not registered as error information. For this reason, the conventional one has a problem that it cannot effectively use error information generated by fraud. As a result, the conventional product cannot display the error information to the staff of the store where the gaming machine is installed, and cannot reflect the error information in the development of the next model by analyzing the error information.

  The present invention has been made in view of the above-described circumstances, and an object thereof is to provide a gaming machine capable of effectively using error information generated by an illegal act.

The gaming machine according to the present invention is connected to the first control unit that executes processing related to the progress of the game, the second control unit that controls the presentation according to the progress of the game, and various information connected to the second control unit. Display means for displaying, wherein the first control unit includes: encryption means for encrypting transmission data; and data transmission means for transmitting the encrypted transmission data to the second control unit. The second control unit includes: a data receiving unit that receives the encrypted transmission data as received data; a decrypting unit that decrypts the received data received by the data receiving unit; and the decrypting unit And determining whether the received data is normal based on the received data decoded by the step, and determining that the received data is not normal, and between the first control unit and the second control unit When a communication error occurs And error information registration means for registering the error information about the communication error on the condition that the communication error again within a predetermined time occurs, displays the error information registered by said error information registration unit on the display unit Error information display means, wherein the transmission data and the reception data are composed of a plurality of bytes of data arranged in a predetermined order, and the encryption means is the plurality of data constituting the transmission data. The transmission data is encrypted by replacing byte data with a predetermined encryption procedure, and the decryption means decrypts the encrypted reception data by replacing with a predetermined decryption procedure. The second control unit controls an effect based on the received data decoded by the decoding means. And features.

  According to this gaming machine, it is possible to effectively use error information generated by an illegal act.

  The present invention can provide a gaming machine having an effect that it is possible to effectively use error information generated by an illegal act.

It is an external view of the gaming machine in the present embodiment. It is a figure which shows the symbol display area and winning line of the game machine in this Embodiment. It is a figure which shows the symbol arrangement | positioning table of the game machine in this Embodiment. It is a figure which shows the front upper part of the game machine in this Embodiment. (A) is a figure which shows the left decoration panel and left infrared sensor of the game machine in this Embodiment. (B) is a figure which shows the left infrared sensor of the game machine in this Embodiment. It is a figure which shows the structure of the main control circuit of the game machine in this Embodiment. It is a figure which shows the structure of the sub control circuit of the game machine in this Embodiment. It is a figure which shows the area | region image in the sub ROM of the sub control circuit in this Embodiment. It is a figure which shows the area | region image in the sub-RAM of the sub-control circuit in this Embodiment. It is a figure which shows the area | region image in the backup RAM of the sub control circuit in this Embodiment. It is a figure which shows an example of the structure of the error information log | history storage area in the sub RAM of the sub control circuit in this Embodiment. It is a figure which shows an example of the content of the data stored in the error information log | history storage area in the sub RAM of the sub control circuit in this Embodiment. It is explanatory drawing which shows the ring buffer area | region for communication log collection in the sub RAM of the sub control circuit in this Embodiment. It is explanatory drawing which shows the communication error preservation | save area | region in sub RAM of the sub control circuit in this Embodiment. It is explanatory drawing of the encryption process at the time of using the data replacement pattern A in the game machine in this Embodiment. It is explanatory drawing of the encryption process at the time of using the data replacement pattern B in the game machine in this Embodiment. It is explanatory drawing of an encryption process and a decoding process at the time of using the calculation pattern A in the game machine in this Embodiment. It is explanatory drawing of the encryption process at the time of using the calculation pattern B in the game machine in this Embodiment. It is a figure which shows the example of a transition of the game state of the game machine in this Embodiment. It is a figure which shows the example of the internal lottery table determination table of the game machine in this Embodiment. It is a figure which shows the example of the internal lottery table of the game machine in this Embodiment. It is a figure which shows the example of the internal lottery table for RB1 gaming states of the game machine in this Embodiment. It is a figure which shows the example of the internal lottery table for RB2 game states of the game machine in this Embodiment. It is a figure which shows the example of RT transition table of the game machine in this Embodiment. It is a figure which shows the example of the internal winning combination determination table for bonus of the gaming machine in this Embodiment. It is a figure which shows the example of the internal winning combination determination table for a small combination and replay of the game machine in this Embodiment. It is a figure which shows the example of the symbol combination table of the game machine in this Embodiment. It is a figure which shows the example of the table at the time of the bonus action | operation of the game machine in this Embodiment. It is a figure which shows the example of the drawing-in priority order table A of the gaming machine in this Embodiment. It is a figure which shows the example of the drawing-in priority order table B of the gaming machine in this Embodiment. It is a figure which shows the example of the stop table of the game machine in this Embodiment. It is a figure which shows the example of the internal winning combination storing area | region of the game machine in this Embodiment. It is a figure which shows the example of the display combination storage area | region of the game machine in this Embodiment. It is a figure which shows the example of the carryover combination storage area | region of the game machine of this Embodiment. It is a figure which shows the example of the game state flag storage area | region of the gaming machine of this Embodiment. It is a figure which shows the example of storage of the symbol storage area A of the game machine in this Embodiment. It is a figure which shows the example of storage of the symbol storage area B of the game machine in this Embodiment. It is a figure which shows the flowchart of the reset interruption process by the main CPU performed by the main control circuit in this Embodiment. It is a figure which shows the flowchart of the bonus action | operation monitoring process performed with the main control circuit in this Embodiment. It is a figure which shows the flowchart of the internal lottery process performed with the main control circuit in this Embodiment. It is a figure which shows the flowchart of the internal lottery process performed with the main control circuit in this Embodiment. It is a figure which shows the flowchart of the reel stop control process performed with the main control circuit in this Embodiment. It is a figure which shows the flowchart of the display combination search process performed in the main control circuit in this Embodiment. It is a figure which shows the flowchart of RT control processing performed with the main control circuit in this Embodiment. It is a figure which shows the flowchart of the bonus completion | finish check process performed in the main control circuit in this Embodiment. It is a figure which shows the flowchart of the bonus operation | movement check process performed with the main control circuit in this Embodiment. It is a figure which shows the flowchart of the communication data storage process performed by main CPU of the main control circuit in embodiment of this invention. It is a figure which shows the flowchart of the encryption data creation process performed by main CPU of the main control circuit in this Embodiment. It is a figure which shows the flowchart of the interruption process (1.1173 ms) by the main CPU performed by the main control circuit in this Embodiment. It is a figure which shows the flowchart of the communication data transmission process performed by main CPU of the main control circuit in embodiment of this invention. It is the schematic which shows the whole management system of the game machine in this Embodiment. It is the schematic which shows the menu screen of the game machine in this Embodiment. It is the schematic which shows the error information log | history screen of the game machine in this Embodiment. It is explanatory drawing which shows the content of the information of the two-dimensional code used for the management system of the game machine in this Embodiment. It is explanatory drawing which shows the code number of the reception command used for the game machine in this Embodiment, a classification | category, and a parameter. It is explanatory drawing which shows the recording image of the information of the two-dimensional code when a COM error occurs in the gaming machine in the present embodiment, (a) is an accidental occurrence during a normal game, (b) When the setting is changed due to the goto action, (c) shows the case where the lever continuous transmission is performed. In the gaming machine in the present embodiment, when there is a RAM destruction, it is a diagram showing an example of notifying the liquid crystal display area of it. It is a figure which shows the flowchart for demonstrating the process at the time of power activation of the sub CPU of the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the mother task which performs the various task starting request | requirement performed by the sub CPU of the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the power interruption interruption process of the sub CPU of the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the main board | substrate communication reception interruption process by sub CPU performed by the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the effect registration process performed with the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the effect content determination process performed with the sub control circuit in this Embodiment. It is a figure which shows the detailed flowchart of the main board | substrate communication task performed with the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the reception data decoding process performed with the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the main board | substrate reception data BCC check process performed with the sub control circuit of this Embodiment. It is a figure which shows the flowchart of the main board | substrate communication reception data log preservation | save process performed with the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the main board | substrate communication reception data log temporary area | region preservation | save process performed by the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the main board | substrate communication error log | history data preservation | save process performed with the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the main board | substrate reception command check process performed with the sub control circuit in embodiment of this invention. It is a figure which shows the flowchart of the COM error check process performed with the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the RTC control task performed by the sub CPU of the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the sub RAM management process performed by the sub CPU of the sub control circuit in this Embodiment. FIG. 74 is a diagram showing a flowchart of a backup creation process in the sub RAM management process shown in FIG. 73. It is a perspective view which shows the external appearance of the game machine in other embodiment of this invention. It is a front view which shows the structure of the outline of the game board of the game machine in other embodiment of this invention. It is a block diagram which shows the structure of the main control circuit and sub control circuit of the game machine in other embodiment of this invention.

[Configuration of pachislot machines]
The gaming machine of the present invention will be specifically described below with reference to the drawings. In the following embodiment, as a gaming machine of the present invention, a gaming machine having three rotating reels that variably display symbols, in addition to coins, medals or tokens, etc. A description will be given using a game machine capable of playing using a game value such as a card, a so-called pachislot machine. In the following embodiments, a pachislot gaming machine will be described as an example. However, the gaming machine of the present invention is not limited, and a pachinko machine or a slot machine may be used. An example of a pachinko machine will be described later.

  First, an overview of the pachislot machine according to the present embodiment will be described with reference to FIG. FIG. 1 is a perspective view of the gaming machine 1 according to the present embodiment.

  As shown in FIG. 1, the gaming machine 1 includes a housing 1a that houses reels 3L, 3C, and 3R, a main control circuit 60 (see FIG. 6), which will be described later, and the like. The housing 1a includes a front door 1b that can be opened and closed. Furthermore, the gaming machine 1 includes a lock mechanism that switches the front door 1b to a locked state or an unlocked state with the front door 1b closed. This lock mechanism is operated by inserting the door key 2 into the door key hole 1 c and rotating the door key 2.

  When the door key 2 is inserted into the door key hole 1c and rotated to the right, for example, the front door 1b can be opened and closed, and when rotated to the left, the main control circuit 60 and the like are electrically reset. Yes. That is, the door key 2 has a reset function for electrically resetting the gaming machine 1 in addition to the operation of the lock mechanism.

  A symbol display region 4L, 4C, 4R as a substantially vertical surface and a liquid crystal display region 23 are formed in front of the central portion of the front door 1b. Three reels 3L, 3C, 3R are rotatably provided in a horizontal row inside the front of the central portion of the cabinet 1a. On the three reels 3L, 3C, 3R, a symbol row composed of a plurality of types of symbols is drawn on each outer peripheral surface.

  The symbols of the reels 3L, 3C, 3R can be seen through the symbol display areas 4L, 4C, 4R. Each reel 3L, 3C, 3R is controlled by a later-described main control circuit 60 (see FIG. 6) so as to rotate at a constant speed (for example, 80 revolutions / minute), and within the symbol display areas 4L, 4C, 4R. The symbols drawn on the displayed reels 3L, 3C, 3R vary as the reels rotate.

  A substantially horizontal base 10 is formed below the liquid crystal display area 23. On the left side of the pedestal 10, a C / P button 14 that switches between credit (Credit) / payout (Pay) of medals acquired by the player and bet the credited medals by operating a push button. The maximum BET button 13 is provided.

  The payout mode or the credit mode is switched by the player's operation on the C / P button 14. In the credit mode, when a winning is established, medals for the number of payouts corresponding to the winning are credited.

  Further, in the payout mode, when a winning is established, medals corresponding to the payout are paid out from the medal payout exit 15 at the lower front, and the medals paid out from the medal payout exit 15 are sent to the medal receiving unit 16. Can be stored.

  Note that winning means that a combination of symbols relating to a small combination is stopped on the active line. The small role is a role in which medals are paid out when established.

  Further, by the player's operation on the maximum BET button 13, among the credited medals, the maximum number of medals that can be inserted at that time is inserted. By operating the maximum BET button 13, a winning line described later is activated.

  On the right side of the pedestal portion 10, a medal slot 22 is provided. In accordance with the medal inserted into the medal slot 22, a pay line described later is activated.

  On the left side of the medal slot 22, a selection button 24 and a determination button 25 are provided. The player can input to the menu screen displayed in the liquid crystal display area 23 using the selection button 24 and the determination button 25.

  Speakers 21 </ b> L and 21 </ b> R are provided on the left and right above the medal receiving portion 16. The speakers 21L and 21R output game sounds such as performance sounds and notification sounds according to the game situation.

  A start lever 6 is provided on the left side of the front surface of the pedestal 10. The start lever 6 rotates the reels 3L, 3C, and 3R by the player's start operation, and starts changing the symbols displayed in the symbol display areas 4L, 4C, and 4R.

  Three stop buttons 7L for stopping the rotation of the three reels 3L, 3C, and 3R by the player's pressing operation (stopping operation) are provided on the right side of the start lever 6 at the center of the front surface portion of the base 10. , 7C, 7R are provided.

  Here, when the three reels 3L, 3C, and 3R are rotating, the first stop of the rotation of the reels is referred to as a first stop, which is performed after the first stop and the two reels are rotated. The second stop of the rotation of the reel that is performed when the operation is performed is referred to as the second stop, which is performed after the second stop, and is performed last when the rotation of the remaining one reel is performed. Stopping the rotation of the reel is referred to as a third stop.

  The stop operation for the player to stop for the first time is referred to as a first stop operation. Similarly, a stop operation for the player to stop the second stop is referred to as a second stop operation, and a stop operation for the third stop is referred to as a third stop operation.

  A light transmissive upper panel 101 is provided on the upper portion of the front door 1b, and an upper panel LED (Light Emitting Diode) (not shown) is provided on the inner side. In addition, it is good also as using another light-emitting body instead of LED. The upper panel 101 emits light according to the contents of effects described later.

  The liquid crystal display area 23 is disposed on the front side of the reels 3L, 3C, and 3R when viewed from the front side, displays an image, and is drawn on the reels 3L, 3C, and 3R in the symbol display areas 4L, 4C, and 4R. The displayed design is displayed transparently. The transmittance in the symbol display areas 4L, 4C, 4R can be changed.

  The liquid crystal display area 23 displays the number of medals stored (credited) or displays the number of medals paid out when winning is established. In addition, the liquid crystal display area 23 displays a frame image having a predetermined shape so as to surround the symbol display areas 4L, 4C, and 4R, and a predetermined image corresponding to the contents of effects described later.

  A lower panel 102 is provided below the liquid crystal display area 23 and above the pedestal 10, and an LED for the lower panel 102 (other light emitters may be used in place of the LEDs). Is good). The lower panel 102 emits light according to the contents of effects described later.

  A light-transmitting waist panel 103 is provided below the pedestal 10, and an LED for the waist panel 103 (other light emitters may be used in place of the LEDs) is provided on the inside thereof. Yes. The lower back panel 103 emits light according to the contents of effects described later.

  One symbol is displayed in each of the upper, middle, and lower regions in each of the vertically long rectangular symbol display areas 4L, 4C, and 4R. Each symbol display area 4L, 4C, and 4R has a corresponding reel peripheral surface. Three symbols of the arranged symbols are displayed. That is, the symbol display areas 4L, 4C, and 4R have a function as a so-called display window.

  Next, the winning line will be described with reference to FIG. In the symbol display areas 4L, 4C, 4R, five winning lines (center line 8c, bottom line 8d, cross) connecting any one of the upper, middle, and lower stages in each of the symbol display areas 4L, 4C, 4R described above. An up line 8a, a cross down line 8e, and an RB middle special line 8f) are provided.

  When the rotation of the reels 3L, 3C, 3R is stopped, the gaming machine 1 determines whether the winning combination is established or not based on the combination of symbols displayed on the activated winning line. Hereinafter, the activated winning line is referred to as an activated line, and the activated winning line is referred to as an inactivated line.

  As shown in FIG. 2, the center line 8c is a line formed by connecting the left / middle stage region D, the middle / middle stage region E, and the right / middle stage region F, respectively. The bottom line 8d is a line formed by connecting the left / lower region G, the middle / lower region H, and the right / lower region I, respectively.

  The cross-up line 8a is a line formed by connecting the left / lower region G, the middle / middle region E, and the right / upper region C, respectively. The cross-down line 8e is a line formed by connecting the left / upper region A, the middle / middle region E, and the right / lower region I, respectively. The RB middle special line 8f is a line formed by connecting the left / middle stage area D, the middle / lower stage area H, and the right / upper stage area C, respectively.

  In the present embodiment, in the BB gaming state (RB gaming state), only the special line 8f during RB becomes an effective line by inserting two medals. On the other hand, in a game state other than the BB game state (RB game state), four winning lines including the center line 8c, the bottom line 8d, the cross-up line 8a, and the cross-down line 8e are activated as three medals are inserted. Become.

  In some cases, the BB1 gaming state to the BB4 gaming state are collectively referred to as the BB gaming state. In addition, the RB1 gaming state to the RB2 gaming state may be collectively referred to as an RB gaming state.

  Next, the symbol sequence arranged on the reels 3L, 3C, 3R will be described with reference to the symbol arrangement table shown in FIG. FIG. 3 is a diagram showing an arrangement of symbols drawn on the outer peripheral surface of the reels 3L, 3C, 3R of the gaming machine 1 according to the present embodiment.

  On the outer peripheral surfaces of the reels 3L, 3C, 3R, a symbol row in which 21 types of symbols are arranged is drawn. Specifically, a symbol sequence consisting of 7 red symbols, 1 don symbol, 2 don symbols, BAR symbol, wave symbol, 1 bell symbol, 2 bell symbols, 1 cherry symbol, 2 cherry symbols, and a replay symbol is drawn. ing.

  The symbol arrangement table is stored in the main ROM 32 of the main control circuit 60 described later. As shown in FIG. 3, in the symbol arrangement table, the reels 3L, 3C, and 3R are rotated 1/21 times in order to associate the rotation positions of the reels 3L, 3C, and 3R with the symbols drawn on the outer peripheral surface of the reel. Symbol positions from “0” to “20” that are sequentially assigned to each are defined.

  Next, the upper part of the gaming machine will be described with reference to FIG. FIG. 4 is a view showing the upper front of the gaming machine 1.

  As shown in FIG. 4, a display panel unit 110 is provided in the upper center of the liquid crystal display area 23, and a left selection panel 151L and a right selection panel 151R are provided on the left and right sides of the display panel unit 110.

  A left decorative panel 121L and a right decorative panel 121R are provided on the upper left and right of the display panel unit 110.

  The display panel unit 110 includes a plurality of display panels having high light transmittance and excellent light guiding properties, and a plurality of LEDs.

  As shown in FIG. 5A, a left infrared sensor 120L is provided in the back of the left decorative panel 121L. Although not shown, the right infrared sensor 120R is also provided behind the right decorative panel 121R.

  The infrared sensors 120L and 120R are so-called reflective infrared sensors, and can detect whether an object (for example, a player's hand) is present or approached in the direction in which the infrared beam is output.

  As shown in FIG. 5B, the left infrared sensor 120L outputs an infrared beam in the direction of the arrow AR, and receives the reflected infrared beam, thereby bringing the player's hand or the like closer to the left selection panel 151L. Detect that. Similarly, the right infrared sensor 120R detects whether the player's hand or the like has approached the right selection panel 151R.

  Note that the infrared sensors 120L and 120R do not always operate, but operate when a specific effect is executed.

  In this embodiment, a reflective infrared sensor is used. However, other sensors that can detect that a player's hand or the like has come close to the left selection panel 151L and the right selection panel 151R are used. It is good. The left selection panel 151L and the right selection panel 151R themselves may be so-called touch sensors.

[Circuit configuration of gaming machine]
Next, with reference to FIG. 6, a circuit configuration of the gaming machine 1 including a main control circuit 60, a sub control circuit 70, a peripheral device and the like electrically connected to the main control circuit 60 or the sub control circuit 70 will be described. FIG. 6 is a diagram showing a circuit configuration of the gaming machine 1.

  The main control circuit 60 controls the progress of a series of games such as determination of an internal winning combination and reel rotation control. The main control circuit 60 includes a microcomputer 30 disposed on a circuit board as a main component, and is added to a circuit for random number sampling. The microcomputer 30 includes a main CPU 31, a main ROM 32 and a main RAM 33. The main control circuit 60 constitutes a main control unit according to the present invention.

  The main CPU 31 includes key code creation means 31a, main sum value calculation means 31b, main key code added sum value calculation means 31c, command encryption means 31d, and command transmission means 31e.

  The key code creation means 31a creates a key code for each predetermined condition for a command transmitted to the sub-control circuit 70. The key code here is a 1-byte random value acquired from the refresh register at the time of activation. However, the key code may be a random value, and may be set based on a random value using means other than the refresh register. Further, as a predetermined condition for generating the key code, the gaming machine 1 is turned on or reset.

  The main sum value calculation means 31b calculates the sum value from the command by exclusive OR (hereinafter referred to as “XOR logical operation”) to obtain the main sum value. Here, as an example of the main sum value, there is BCC (Block Check Character) data which is error check information for confirming the presence or absence of a communication error between the main control circuit 60 and the sub control circuit 70.

  The main key code added sum value calculation means 31c performs an XOR logical operation using the main sum value and the key code, and calculates a main key code added sum value.

  The command encryption unit 31d encrypts a command (including a main key code added sum value) generated by the main CPU 31 based on encryption information (described later) stored in the main ROM 32. The command transmission unit 31e transmits the encrypted command to the sub control circuit 70.

  As commands generated by the main CPU 31, for example, as shown in FIG. 55, there are 16 types “01H” to “10H” described in the received command column. This command data consists of eight data each consisting of 1 byte, for example, command type, five parameters P1 to P5, a gaming state flag (gaming state information) indicating a gaming state, and a main key code added sum value data. Composed. Each of these data can be identified by the bit pattern according to the command type. The command data constitutes one packet by these eight data (8-byte data).

  The BCC data corresponds to the error check information according to the present invention. Further, the command data may be data each consisting of a plurality of bytes. The command data is not limited to 8-byte data.

  The main CPU 31 is connected to a clock pulse generation circuit 34, a frequency divider 35, a random number generator 36, and a sampling circuit 37.

  The main CPU 31 determines an internal winning combination based on the random number value and the internal lottery table, and stops the rotation of the reels 3L, 3C, 3R based on the internal winning combination and the timing when the stop operation is detected.

  Further, when the main CPU 31 stops the rotation of the reels 3L, 3C, and 3R, it determines whether or not a winning combination has been established based on the combination of symbols displayed in the symbol display areas 4L, 4C, and 4R. If established, the player is given a profit such as paying out medals according to the established combination.

  The clock pulse generation circuit 34 and the frequency divider 35 generate a reference clock pulse. The random number generator 36 generates a random number in the range of “0” to “65535”. The sampling circuit 37 extracts (samples) one random number value from the random number generated by the random number generator 36.

  In the gaming machine 1, the extracted random number value is stored in a random value storage area of the main RAM 33 described later. The internal winning combination is determined in the internal lottery process based on the random value stored in the random value storage area of the main RAM 33 for each game.

  In addition, as a means for random number sampling, you may make it the structure which performs random number sampling within the microcomputer 30, ie, on the operation program of the main CPU31. In that case, the random number generator 36 and the sampling circuit 37 can be omitted, or can be left as a backup for the random number sampling operation.

  The main ROM 32 of the microcomputer 30 stores programs related to the processing of the main CPU 31, various tables, encryption information, and the like. Here, the encryption information includes unique data predetermined for each model (for each title) (hereinafter referred to as model ID) and data of an encryption method code indicating a predetermined encryption method. Instead of the model ID, for example, unique data for identifying the gaming machine in hardware may be used.

  Various information obtained by processing of the main CPU 31 is set in the main RAM 33. For example, information for identifying the extracted random number value, gaming state, internal winning combination, number of payouts, bonus carryover status, setting value, etc., various counters and flags are set. Some of these pieces of information are transmitted to the sub-control circuit 70 by the above-described command.

  Examples of main peripheral devices whose operation is controlled by a control signal from the microcomputer 30 include a hopper 40 and stepping motors 49L, 49C, 49R. The exchange of signals between these actuators and the main CPU 31 is performed via the I / O port 38.

  In addition, the output unit of the microcomputer 30 is connected to each circuit for receiving the control signal output from the main CPU 31 and controlling the operation of each peripheral device described above. Each circuit includes a motor drive circuit 39 and a hopper drive circuit 41.

  The hopper drive circuit 41 drives and controls the hopper 40. Thereby, the medal accommodated in the hopper 40 is paid out.

  The motor drive circuit 39 drives and controls the stepping motors 49L, 49C, 49R. As a result, the reels 3L, 3C, and 3R are rotated and stopped.

  In addition, each switch and each circuit for generating an input signal that triggers the output of a control signal to each circuit and each peripheral device are connected to the input unit of the microcomputer 30. As each switch and each circuit, a start switch 6S, stop switches 7LS, 7CS, 7RS, maximum BET switch 13S, C / P switch 14S, setting key SW20S, medal sensor 22S, reel position detection circuit 50, payout completion signal circuit 51 There is. Note that the stop switches 7LS, 7CS, and 7RS are collectively referred to as the stop switch 7S.

  The start switch 6S detects a player's start operation on the start lever 6 and outputs a start signal instructing the start of the game to the microcomputer 30.

  The stop switches 7LS, 7CS, and 7RS detect the player's stop operation on the stop buttons 7L, 7C, and 7R, respectively, and stop the rotation of the reels 3L, 3C, and 3R corresponding to the detected stop buttons 7L, 7C, and 7R. A stop signal to be commanded is output to the microcomputer 30.

  The maximum BET switch 13 </ b> S detects a player's insertion operation (pressing operation) on the maximum BET button 13 and outputs a signal for instructing insertion of a medal from a credited medal to the microcomputer 30.

  The C / P switch 14S detects a player's switching operation on the C / P button 14, and outputs a signal for switching the credit mode or the payout mode to the microcomputer 30. When the credit mode is switched to the payout mode, a signal for instructing the payout of medals credited to the gaming machine 1 is output to the microcomputer 30.

  The setting key switch 20S detects that a setting key for operating the setting value of the gaming machine 1 has been operated, and outputs a detection signal to the microcomputer 30.

  The medal sensor 22S detects medals inserted into the medal insertion slot 22 by the player's insertion operation, and outputs a signal indicating that a medal has been inserted to the microcomputer 30.

  The reel position detection circuit 50 detects a pulse signal from the reel rotation sensor and generates a signal for detecting the position of the symbol on each reel 3L, 3C, 3R.

  The payout completion signal circuit 51 indicates that the medal payout has been completed when the number of medals detected by the medal detection unit 40S (that is, the number of medals paid out from the hopper 40) reaches the designated number. Generate a signal to indicate.

  The sub control circuit 70 performs various processes such as determination and execution of effect data based on various commands output from the main control circuit 60 such as a start command described later. The sub control circuit 70 does not input commands, information, or the like to the main control circuit 60, and communication is performed in one direction from the main control circuit 60 to the sub control circuit 70. The sub control circuit 70 constitutes a sub control unit according to the present invention.

  As main peripheral devices whose operation is controlled by a control signal from the sub control circuit 70, the liquid crystal display device 5 as a display unit for displaying an image on the liquid crystal display region 23, speakers 21L and 21R, various operation panels 101 to 101, and the like. 103, a display panel unit 110, and infrared sensors 120L and 120R. The liquid crystal display device 5 constitutes error information display means according to the present invention.

  The sub control circuit 70 determines and displays an image displayed on the liquid crystal display device 5 based on the determined effect data, determines and outputs the light emission patterns of the various operation panels 101 to 103 and the display panel unit 110, and an infrared sensor. Controls such as determination and output of effect sound and effect sound output from the speakers 21L and 21R, such as determination of operation timing of 120L and 120R.

  Details of the configuration of the sub control circuit 70 in the present embodiment will be described later.

  In the gaming machine 1, when a signal for starting a game is output from the start switch 6S by a player's operation on the start lever 6 on condition that a medal is inserted, a control signal is output to the motor drive circuit 39, and the stepping motor The rotation of the reels 3L, 3C, and 3R is started by the drive control of 49L, 49C, and 49R (for example, excitation to each phase).

  At this time, the number of pulses output to the stepping motors 49L, 49C, 49R is counted, and the counted value is set as a pulse counter in a predetermined area of the main RAM 33.

  In the gaming machine 1, when the “16” pulse is output, the reels 3L, 3C, and 3R move by one symbol. The number of symbols moved is counted, and the counted value is set in a predetermined area of the main RAM 33 as a symbol counter. That is, every time the pulse counter counts “16”, the symbol counter is updated by “1”.

  In addition, the symbol (refer FIG. 3) of the symbol position which the value of a symbol counter shows corresponds to the symbol located on the center line 8c. For example, when the symbol counter of the left reel 3L is “0”, the red 7 at the symbol position “0” in the symbol arrangement table shown in FIG. 3 is located on the center line 8c.

  A reel index is obtained from the reels 3L, 3C, and 3R for each rotation and is output to the main CPU 31 via the reel position detection circuit 50. By the output of the reel index, the pulse counter and the symbol counter set in the main RAM 33 are cleared to “0”.

  In this way, the symbol position within one rotation range is specified for each reel 3L, 3C, 3R. The distance that each symbol moves by one symbol by the rotation of the reel is called one frame. That is, moving the symbol by one frame corresponds to updating the symbol counter by “1”.

  In order to associate the rotational positions of the reels 3L, 3C, and 3R with the symbols drawn on the outer peripheral surface of the reel, a symbol arrangement table is stored in the main ROM 32. This symbol arrangement table includes code numbers from “0” to “20” that are sequentially given at fixed rotation pitches of the reels 3L, 3C, and 3R with reference to the position where the reel index is output. A symbol code for identifying the type of symbol provided corresponding to each code number is associated with each other.

  When a start signal is output from the start switch 6S, a random number value is extracted by the random number generator 36 and the sampling circuit 37. In the gaming machine 1, when the random value is extracted, it is stored in the random value storage area of the main RAM 33. Then, an internal winning combination is determined based on the random value stored in the random value storage area.

  After the reels 3L, 3C, 3R have reached constant speed rotation, when a stop signal is output from the stop switches 7LS, 7CS, 7RS by a stop operation, based on the output stop signal and the determined internal winning combination, A control signal for stopping and controlling the reels 3L, 3C, 3R is output to the motor drive circuit 39. The motor drive circuit 39 drives and controls the stepping motors 49L, 49C, 49R, and stops the rotation of the reels 3L, 3C, 3R.

  The gaming machine 1 stops the rotation of the reel 3 by drawing in the symbols related to the establishment of the internal winning combination for the maximum number of sliding frames, that is, four frames from the time when the stop operation is performed. Specifically, the gaming machine 1 determines whether or not there is a symbol related to the establishment of an internal winning combination within 4 frames after the stop operation is detected by the stop switches 7LS, 7CS, and 7RS. When there is a symbol related to the establishment of an internal winning combination within four frames, the number of sliding symbols is determined so that the symbol is stopped and displayed on the active line, and the corresponding reel is stopped.

  In addition, in the case where a plurality of winning combinations are determined as internal winning combinations, the gaming machine 1 relates to an internal winning combination having a higher priority when there are a plurality of symbols related to establishment of the internal winning combination within 4 frames. The number of sliding symbols is determined so that the symbols are stopped and displayed on the active line.

  Basically, the first priority (highest priority) is a symbol combination related to replay, and the second priority is a symbol combination related to a small role. Next, the third highest priority is a combination of symbols related to the bonus.

  When the stop operation is detected by the stop switches 7LS, 7CS, 7RS, the symbol position corresponding to the symbol counter of the corresponding reel 3, that is, the symbol position at which the rotation of the reel 3 is stopped is set as “stop start position”. The symbol position obtained by adding the determined number of sliding symbols (numerical range “0” to “4”) to the stop start position, that is, the symbol position at which the rotation of the reel 3 is stopped is referred to as “scheduled stop position”. The number of sliding symbols is the amount of rotation of the reel 3 until the corresponding reel 3 stops rotating after the stop operation is detected by the stop switches 7LS, 7CS, 7RS. 4 ”.

  When the rotation of all the reels 3L, 3C, and 3R is stopped, the display combination retrieval process, that is, the determination process of the formation / non-establishment of the combination is performed based on the combination of symbols displayed on the effective line. The search for the display combination is performed based on a later-described symbol combination table stored in the main ROM 32. In this symbol combination table, a symbol combination related to a display combination and a corresponding payout are set.

  When it is determined by the display combination search that a combination of symbols related to winning is displayed, a control signal is output to the hopper driving circuit 41 and the hopper 40 is driven to pay out medals.

  At this time, the medal detection unit 40S counts the number of medals to be paid out from the hopper 40, and when the count value reaches the designated number, the payout completion signal circuit 51 outputs a signal indicating the completion of the medal payout. . Thereby, a control signal is output to the hopper drive circuit 41, and the drive of the hopper 40 is stopped.

  When the credit mode is switched by the C / P switch 14S, if it is determined that the symbol combination related to winning is displayed, the payout amount corresponding to the symbol combination related to winning is displayed in the main RAM 33. Add to credit counter.

  Further, the number of medals paid out is transmitted to the sub-control circuit 70, and based on this, the number of medals paid out and the updated number of credits are displayed in the liquid crystal display area 23. Here, there is a case where a medal payout or a credit performed when a symbol combination related to winning is displayed is simply referred to as “payout”.

  Next, the circuit configuration of the sub control circuit 70 will be described with reference to FIG. FIG. 7 is a diagram showing a circuit configuration of the sub control circuit 70 of the gaming machine 1.

  The sub-control circuit 70 performs control for performing effects related to games using video, sound, light, and the like. The sub control circuit 70 determines effect data and performs various effect processes based on various commands transmitted from the main control circuit 60 and input information from the selection switch 24S and the determination switch 25S.

  The sub control circuit 70 includes a sub CPU 71 as processing means, a sub ROM 72 functioning as processing information storage means, a DRAM 73-1 functioning as control information storage means (also referred to as “sub RAM 73-1”), an SRAM 73-2, a GPU 74, A VRAM 75 and a digital amplifier 78 are provided.

  The selection switch 24S detects a player's operation on the selection button 24 and moves, for example, a display (for example, an icon) indicating which of the items to be selected displayed on the menu screen or the like is in a selected state. Is output to the sub CPU 71.

  In addition, the determination switch 25S detects the player's operation on the determination button 25, and outputs, for example, a signal indicating that the player has selected an item in the selected state to the sub CPU 71. That is, the player can select an item on the menu screen or the like by pressing the selection button 24 until the item to be selected is selected, and then pressing the enter button.

  The sub CPU 71 performs display control of the liquid crystal display device 5, output control of the speakers 21L and 21R, various operation panels 101 to 103, light emission control of the display panel unit 110, and the like based on a program stored in the sub ROM 72. Specifically, the sub CPU 71 receives various commands and the like from the main control circuit 60 and stores various information included in the commands in the sub RAM 73-1.

  The sub CPU 71 is connected to an SRAM 73-2 (also referred to as “backup RAM 73-2”) described later. The backup RAM 73-2 is backed up with data copied to the sub RAM 73-1 when the power is turned on.

  All information in the main control circuit 60 is transmitted by a command, and the sub control circuit 70 can determine the state of the main control circuit 60 step by step. The sub CPU 71 executes the program while referring to the game state information, the internal winning combination information, etc. stored in the DRAM 73-1, so that the liquid crystal display device 5, the speakers 21L and 21R, the various operation panels 101 to 103, the display The content of the effect to be performed by the effect device such as the panel unit 110 is determined.

  In addition, the sub CPU 71 controls the liquid crystal display device 5 via the GPU 74 based on the determined effect data, and also outputs sounds output from the speakers 21L and 21R, the various operation panels 101 to 103, and the display panel unit 110. Control light emission.

  The upper panel 101, the waist panel 102, and the lower panel 103 are each actually provided with a plurality of LEDs, and these are controlled by input / output processing of ports (not shown) provided individually. Therefore, light emission can be individually controlled by each port.

  Further, the sub CPU 71 executes a random number acquisition program stored in the sub ROM 72, thereby acquiring a random value used when determining effect data and the like. However, when a random number generator and a sampling circuit are provided in the sub-control circuit 70 as in the main control circuit 60, this processing is not necessary.

  As shown in FIG. 8, the sub ROM 72 has an OS area 72a for storing an operating system, a sub control program storage area 72b for storing a program executed by the sub CPU 71, a game data initialization setting data area 72c, and a staff operation. Initial setting data area 72d, various program table areas 72e for storing various tables, a program management data area 72f, an image data (still image / moving image) area 72g, a sound data area 72h, and an accessory movable data area 72i and a decryption information area 72j.

  The sub-control program storage area 72b has various operations based on the device driver, inter-board communication processing for controlling communication with the main control circuit 60, effect registration processing for determining the contents of the effect, and the registered LED data. LED control task for controlling light output by panels 101 to 103 and display panel unit 110, voice control task for controlling sound output by speakers 21L and 21R based on registered sound data, registered A drawing control task and the like for controlling display of an image by the liquid crystal display device 5 based on the animation data are stored.

  The various program table area 72e stores an effect lottery table, an error code table of the sub control circuit shown in FIG.

  The program management data area 72f stores a magic code, a program version, and the like. The image data (still image / moving image) area 72g stores animation data such as character object data. The sound data area 72h stores sound data such as BGM and sound effects. Further, the accessory movable data area 72i stores, for example, LED control data for performing a light lighting pattern or the like. The decryption information area 72j is information corresponding to the encryption information stored in the main ROM 32 of the microcomputer 30, and stores a model ID and data of a decryption method code indicating a predetermined decryption method. .

  As shown in FIG. 9, the sub RAM 73-1 has a game data area 73a-1, a game data sum value area 73b-1, a work area 73c-1, and a staff operation setting data area 73g as a game data storage area. -1, an error information history storage area 73d-1, a communication log collection ring buffer area 73e-1, and a communication error storage buffer area 73f-1. The clerk operation setting data registered in the clerk operation setting data area 73g-1 is data in which setting items on the menu screen are stored.

  The game data area 73a-1 stores data stored in the sub RAM 73-1 among information including game data relating to the progress of the game. The game data sum value area 73b-1 stores the checksum sum value for the game data stored in the game data area 73a-1. The work area 73c-1 stores data in various processes.

  The game data area 73a-1 and the work area 73c-1 are used as work temporary storage means when the sub CPU 71 executes each program. The game data area 73a-1 includes, for example, commands transmitted from the main control circuit 60, effect data information, game state information, internal winning combination information, display combination information, various counters, and any arbitrary byte from 4 bytes to 8 bytes. Information such as a magic code and various flags is stored.

  The error information history storage area 73d-1 stores an error code (see FIG. 12) indicating all error information detected by a communication error detecting means 71b, a procedure detecting means 71c, a data destruction detecting means 71d, and the like which will be described later. It has become. In the error information history storage area 73d-1, an error information history is created by sequentially storing error codes.

  In the error information history storage area 73d-1, the error detected by the communication error detecting means 71b is stored as a COM error, and the error detected by the procedure detecting means 71c is stored as a procedure abnormal error. Further, the error detected by the data destruction detection means 71d is stored as a data destruction error.

  As shown in FIG. 10, the backup RAM 73-2 has a backup data 1 area 73a-2, a backup data 1 sum value area 73b-2, and a backup data 2 area 73c- which is a mirroring of the backup data 1 area 73a-2. 2, backup data 2 sum value area 73 d-2, clerk backup data area 73 e-2, error information history storage area 73 f-2, and clerk backup data sum value area 73 g-2.

  In this embodiment, the backup data 1 area 73a-2 and the backup data 2 area 73c-2 are configured in a single backup RAM 73-2. In this specification, “mirroring” is used to mean copying data, and is not limited to the meaning of copying data to another storage.

  The backup data 1 area 73a-2 and the backup data 2 area 73c-2 each include an arbitrary magic code of 4 to 8 bytes.

  As shown in FIG. 11, the error information history storage area 73d-1 of the sub RAM 73-1 includes an error code (ERROR CODE in the figure), an error occurrence time ("occurrence" in the figure), and an error release time ( In the drawing, “cancel”) can be stored as one set, and 128 sets can be stored.

  The error code is 1-byte data. The error code related to the sub-control circuit includes a communication error ("COM error" in the figure) and a procedure error ("procedure error" in the figure) as shown in FIG. ”), Data destruction errors (“ Sum Abnormal ”in the figure), and other errors.

  In the error information history storage area 73d-1, the error occurrence time and the error release time are both a 2-byte data year, a 1-byte data month, a 1-byte data day, a 1-byte data time, and a 1-byte data minute. It consists of seconds of 1-byte data.

  As shown in FIG. 13, the communication log collection ring buffer area 73e-1 stores an appropriate number of data groups including 256 command and parameter data sets and one corresponding buffer index. It functions as a buffer.

  As shown in FIG. 14, the communication error storage buffer area 73f-1 stores 1024 data groups including 256 command and parameter data sets and one corresponding buffer index. The communication error storage buffer area 73f-1 is provided with one buffer selection index indicating which buffer index is selected from among the 1024 buffer indexes.

  In the communication log collection ring buffer area 73e-1 shown in FIG. 13 and the communication error storage buffer area 73f-1 shown in FIG. 14, the command is made up of one character data and the parameter is made up of two character data. .

  Further, as shown in FIG. 7, the sub CPU 71 includes a command decryption unit 71a, a communication error detection unit 71b, a procedure detection unit 71c, a data destruction detection unit 71d, an error information registration unit 71e, and a received data log. Storage means 71f, error information history display means 71g, two-dimensional code conversion means 71h, key code acquisition means 71i, sub-sum value calculation means 71j, sub-key code added sum value calculation means 71k, sum value determination Means 71m.

  The command decryption means 71a decrypts the encrypted command from the main control circuit 60 based on the model ID and the encryption method code stored in the decryption information area 72j of the sub ROM 72. .

  The communication error detection means 71b detects that a communication error has occurred between the main control circuit 60 and the sub control circuit 70 by executing a COM error check process shown in FIG. .

  The procedure detecting means 71c detects the progress of the game in a procedure different from the normal game procedure, that is, an abnormal procedure by executing a main board received command check process shown in FIG. ing.

  The data destruction detection unit 71d performs a data check of the game data area 73a-1 (see FIG. 9) of the sub RAM 73-1 by performing a sum check process of the sub control game data storage area shown in FIG. Further, it is possible to detect data destruction related to information received from the main control circuit 60, such as effect data information, game state information, internal winning combination information, display combination information, various counters and various flags.

  The error information registration unit 71e stores the error code of the detected error in the error information history storage area 73d-1 of the sub RAM 73-1, when the occurrence of an error is detected by the error detection unit. Yes. The error information registration unit 71e constitutes an error information registration unit according to the present invention.

  Specifically, the error information registration unit 71e stores a COM error error code (COM ERR ALM) in the error information history storage area 73d-1 when the occurrence of a communication error is detected by the communication error detection unit 71b. It is supposed to be.

  When the procedure detection unit 71c detects the occurrence of a procedure abnormality error, the error information registration unit 71e stores a procedure abnormality error code (for example, BLS123PE) in the error information history storage area 73d-1. Yes.

  The error information registration unit 71e stores the error code (MEM ERR ALM) of the sum abnormality in the error information history storage area 73d-1 when the occurrence of the sum abnormality error is detected by the data destruction detection unit 71d. ing.

  In the error information history storage area 73d-1, an error information history is created by sequentially storing error codes.

  The reception data log storage unit 71f collects information about a reception log (hereinafter also referred to as a communication log) by executing a main board communication reception data log storage process shown in FIG. By executing the main board communication reception data log temporary area saving process shown, only one communication log is temporarily stored in the communication log collection ring buffer area 73e-1.

  Further, the received data log storage unit 71f executes a main board communication error history data storage process shown in FIG. 69 to be described later, and when the occurrence of a communication error is detected by the communication error detection unit 71b, a communication error storage is performed. Up to 1024 communication logs related to communication errors (hereinafter referred to as communication error logs) are stored in the buffer area 73f-1.

  The error information history display means 71g displays the error information history stored in the error information history storage area 73d-1 on the liquid crystal display device 5 when the door key 2 is operated in a predetermined manner. This error information history display means 71g constitutes an error information display means according to the present invention.

  The two-dimensional code conversion means 71h, when the occurrence of a communication error is detected by the communication error detection means 71b, the communication error log related to the communication error stored in the communication error storage buffer area 73f-1 and the data management as the transmission destination The domain of the server 500 is converted into two-dimensional code 300 as transmission information and transmitted to the error information history display means 71g.

  Then, as shown in FIG. 53, the error information history display means 71g displays the “COM error alarm” item 23b when the “COM error alarm” item 23b is selected in the liquid crystal display area 23 where the error information history is displayed. A two-dimensional code 300 corresponding to the communication error is displayed on the right side.

  Here, as shown in FIG. 54, the transmission information included in the two-dimensional code 300 created by the two-dimensional code conversion means 71h consists of 192 bytes. The transmission information has a general-purpose configuration so that error information recorded in not only the gaming machine 1 of the model described in the present embodiment but also other types of gaming machines can be transmitted. Alternatively, a player's game record may be included in the transmission information. Hereinafter, items included in the transmission information will be described.

  Data indicating the domain of the data management server 500 and a request to the data management server 500 is set in the 0th to 28th bytes of the transmission information. A case-specific code for identifying the gaming machine 1 is set in the 29th to 39th bytes of the transmission information.

  The 40th to 61st bytes of the transmission information are reserved areas. The transmission information generation time is set in the 62nd to 67th bytes of the transmission information. A model code indicating the type of the gaming machine 1 is set in the 68th to 71st bytes of the transmission information.

  A type number is set in the 72nd to 73rd bytes of the transmission information. Here, both the 72nd byte and the 73rd byte are set to 3FH.

  The error type is set in the 74th to 75th bytes of the transmission information. Error information is set in the 76th to 188th bytes of the transmission information. A checksum is set from the 189th byte to the 191st byte of the transmission information.

  The error information set in the 76th to 188th bytes of the transmission information has a command type consisting of one character (6 bits). If the command type is accompanied by a parameter, it is also provided with a parameter consisting of two characters (12 bits) after the one-character command type. FIG. 55 shows examples of command types and parameters.

  The sub sum value calculating means 71j calculates the sum value by performing an XOR logical operation on the received command, and sets it as the sub sum value. The sub key code added sum value calculating means 71k calculates the sub key code added sum value by performing an XOR logical operation using the sub sum value and the key code.

  The key code acquisition unit 71i acquires a key code when the sub CPU 71 as a command reception unit receives a command for the first time. In the present embodiment, the key code acquisition means 71i calculates the initial sum value from the command received for the first time by the sub sum value calculation means 71j, and the sub key code added sum value calculation means 71k and the initial sum value and the main sum value. A key code is calculated by performing an XOR logical operation with the key code added sum value.

  The sum value determining means 71m determines whether or not the sum value is normal by comparing the main key code added sum value and the sub key code added sum value.

  In the present embodiment, a door key switch 2S is connected to the sub CPU 71. The door key switch 2S detects that the door key 2 has been rotated in the left direction and outputs it to the sub CPU 71.

  Here, the error of the gaming machine 1 is reset when the door key 2 is rotated leftward.

  When the occurrence of a communication error is detected by the communication error detection means 71b, the error information registration means 71e stores the error code of the communication error in the error information history storage area 73d-1 of the sub RAM 73-1. The received data log storage unit 71f stores the communication log in the communication log collection ring buffer area 73e-1, and stores the communication error log in the communication error storage buffer area 73f-1.

  If the occurrence of an error other than a communication error is detected by the procedure detection means 71c other than the communication error detection means 71b, the data destruction detection means 71d, or other error detection means, the error information registration means 71e The code is stored in the error information history storage area 73d-1 of the sub RAM 73-1. The received data log storage unit 71f stores the communication log in the communication log collection ring buffer area 73e-1, but does not store the communication error storage buffer area 73f-1.

  Then, when the door key 2 is operated in a predetermined manner, the error information history display means 71g causes the liquid crystal display device 5 to display the error information history stored in the error information history storage area 73d-1. In this case, as shown in FIG. 53, when the “COM error alarm” item 23b is selected in the liquid crystal display area 23, the error information history display means 71g displays the communication on the right side of the “COM error alarm” item 23b. A two-dimensional code 300 corresponding to the error is displayed.

  In the present embodiment, in order to display the error information history shown in FIG. 53 on the liquid crystal display device 5, two kinds of operation methods of normal operation and simple operation by an attendant are adopted.

  In the normal operation, the clerk turns the door key 2 to the right to release the lock mechanism of the front door 1b, turns on the setting key to turn on the setting key switch 20S, and the liquid crystal display area 23 is shown in FIG. The menu screen is displayed. Then, when the clerk operates the operation key and selects the “error information history” item 23 a, the error information history screen shown in FIG. 53 is displayed in the liquid crystal display area 23.

  On the other hand, in the simple operation, the clerk turns the door key 2 counterclockwise to reset the error, and holds the state for a predetermined time, for example, 5 seconds or more, so that the error information history screen shown in FIG. It is displayed.

  Further, the sub CPU 71 has a built-in RTC 70a with a dedicated clocking circuit. An external RTC 70c is connected to the sub CPU 71 for backup of the built-in RTC 70a. A battery 70b is connected to the external RTC 70c and the SRAM 73-2. The internal RTC 70a and the external RTC 70c are processed by an RTC control task shown in FIG.

  The GPU 74 performs a process for displaying an image on the liquid crystal display device 5 based on an image display command received from the sub CPU 71. Data necessary for processing performed by the GPU 74 is expanded in the VRAM 75 at the time of activation. The GPU 74 superimposes the image data developed in the VRAM 75 in order from the background image located at the rear to the image located at the front to generate image data, and supplies the image data to the liquid crystal display device 5.

  As a result, an image corresponding to the effect data determined by the sub CPU 71 is displayed on the liquid crystal display area 23 by the liquid crystal display device 5.

  The VRAM 75 has two frame buffers, a writing image data area and a display image data area. The writing image data area stores image data generated by the GPU 74, and the display image data area includes Image data to be displayed on the liquid crystal display device 5 is stored.

  The GPU 74 causes the liquid crystal display device 5 to sequentially display image data by alternately switching these frame buffers (that is, switching banks).

  The digital amplifier 78 amplifies the digital sound data selected by the sub CPU 71 based on the effect data based on the volume adjusted by a volume adjusting knob (not shown) provided in the gaming machine 1, and the analog amplifier Is transmitted to the speakers 21L and 21R. As a result, sounds corresponding to the effect data determined by the sub CPU 71 are output from the speakers 21L and 21R.

[Encryption processing, decryption processing]
Next, an encryption process performed by the main CPU 31 of the main control circuit 60 and a decryption process performed by the sub CPU 71 of the sub control circuit 70 will be described with reference to FIGS. In the present embodiment, four encryption processes and decryption processes of data replacement patterns A and B and operation patterns A and B will be described.

(Data replacement pattern A)
The data replacement pattern A will be described with reference to FIG. FIG. 15A shows the structure of 8-byte data included in one packet before encryption processing. In FIG. 15A, B0 to B7 indicate 0-bit to 7-bit data when each 8-byte data is represented by a binary number. For example, “1-B7” represents 7-bit data when the first byte data is represented in binary.

  In the configuration shown in FIG. 15A, the main CPU 31 takes out one byte at a time, maintains the bit string arrangement order, and starts with the eighth byte from the first byte data based on the predetermined data arrangement order. The arrangement of the data up to this point is exchanged to generate 8-byte data as shown in FIG. 15B, thereby performing encryption processing.

  Specifically, the main CPU 31 sets the first byte data to the eighth byte, the second byte data to the seventh byte,..., The eighth byte data to the first byte, and so on. The encryption process is performed by replacing the data while maintaining the arrangement order of the bit strings of the data.

  In the configuration shown in FIG. 15 (b), the sub CPU 71 takes out one byte at a time and maintains the bit string arrangement order, and the eighth byte from the first byte data based on a predetermined data arrangement order. Decoding processing is performed by replacing the arrangement of the data up to and generating 8-byte data as shown in FIG. That is, the decryption process is the reverse of the encryption process.

  The sub CPU 71 arranges the bit string of each data so that the eighth byte data is the first byte, the seventh byte data is the second byte,... The first byte data is the eighth byte. Decoding processing is performed by exchanging data while maintaining the order.

  More specifically, as shown on the right side of FIG. 15A, the structure of 1 to 8 bytes of data before encryption processing is 01H, 03H, 05H, 07H, 09H, 0BH, 0DH, and 0FH. In this case, when the main CPU 31 performs the encryption process, as shown on the right side of FIG. 15B, the configuration of 1 to 8 bytes of the data after the encryption process is 0FH, 0DH, 0BH, 09H, 07H, 05H. , 03H and 01H.

  In the above description, the data included in one packet is 8 bytes, but the present invention is not limited to this. If the data included in one packet is n bytes, the main CPU 31 sets the first byte data to the nth byte, the second byte data to the (n-1) byte, the third byte data to (n -2) As in the byte, the data is exchanged while the bit position of each data is held, and the encryption process is performed. In this case, the sub CPU 71 sets the nth byte data to the first byte, the (n-1) th byte data to the second byte, the (n-2) th byte data to the third byte, and so on. The data is exchanged while the bit position of each data is held, and the decoding process is performed.

  For example, the main CPU 31 may be configured to replace adjacent data. Specifically, the main CPU 31 may perform encryption processing by exchanging the first byte and the second byte,..., (N−1) th byte and the nth byte. .

(Data replacement pattern B)
The data replacement pattern B will be described with reference to FIG. FIG. 16A shows the configuration of 8-byte data included in one packet, similar to FIG. 15A described above.

  In the configuration shown in FIG. 16A, the main CPU 31 extracts one byte at a time and maintains the data arrangement order from the 0th bit (B0) data based on the predetermined bit string arrangement order. The arrangement order of the bit string up to the seventh bit (B7) is changed, and the 8-byte data as shown in FIG. 16B is generated to perform the encryption process.

  Specifically, the main CPU 31 converts the 0th bit data into the 7th bit data, the 1st bit data into the 6th bit data,..., The 7th bit data into the 0th bit data. As described above, while maintaining the data arrangement order, the bit string arrangement order is changed and encryption processing is performed.

  In the configuration shown in FIG. 16B, the sub CPU 71 extracts one byte at a time and maintains the data arrangement order from the 0th bit (B0) data based on the predetermined bit string arrangement order. Decoding processing is performed by changing the arrangement order of the bit strings up to the seventh bit (B7) and generating 8-byte data as shown in FIG. That is, the decryption process is the reverse of the encryption process.

  The sub CPU 71 sets the 7th bit data to the 0th bit data, the 6th bit data to the 1st bit data,..., The 0th bit data to the 7th bit data, and so on. The encryption processing is performed by changing the arrangement order of the bit strings while maintaining the arrangement order.

  More specifically, as shown on the right side of FIG. 16A, the configuration of 1 to 8 bytes of data before encryption processing is 01H, 03H, 05H, 07H, 09H, 0BH, 0DH, and 0FH. In this case, when the main CPU 31 performs the encryption process, as shown on the right side of FIG. 16B, the configuration of 1 to 8 bytes of the data after the encryption process is 80H, C0H, A0H, E0H, 90H, 50H. , B0H, F0H.

  In the above description, the data included in one packet is 8 bytes, but the present invention is not limited to this. Further, for example, the main CPU 31 may replace data at bit positions adjacent to each other. Specifically, the main CPU 31 may perform the encryption process such that the 0th bit and the 1st bit are exchanged, and the 2nd bit and the 3rd bit are exchanged.

  Further, the data replacement pattern A and the data replacement pattern B described above may be combined to perform encryption processing and decryption processing.

(Calculation pattern A)
The calculation pattern A will be described with reference to FIG. FIG. 17A shows the structure of 8-byte data included in one packet before encryption processing. As shown in FIG. 17A, the first byte data is 01H, the second byte data is 03H,..., And the eighth byte data is 0FH. The data indicating the model ID is 5AH.

  In the configuration shown in FIG. 17A, the main CPU 31 performs an XOR logic operation on each data from the 1st byte to the 8th byte and 5AH that is data indicating the model ID, and FIG. By generating 8-byte data as shown in (2), encryption processing is performed while maintaining the data arrangement order.

  Specifically, for example, the main CPU 31 obtains 5BH from the XOR logical operation of 01H and 5AH in the first byte. For example, the main CPU 31 obtains 55H from the XOR logic operation of 0FH and 5AH in the eighth byte. As a result of this XOR logic operation, the main CPU 31 encrypts that the first byte data is 5BH, the second byte data is 59H,..., And the eighth byte data is 55H, as shown in FIG. Data that has been processed is generated.

  In the configuration shown in FIG. 17B, the sub CPU 71 performs an XOR logic operation on each data from the 1st byte to the 8th byte and 5AH which is data indicating the model ID, and then performs the operation shown in FIG. 8) data is generated, the decoding process is performed while maintaining the data arrangement order.

  Specifically, for example, the sub CPU 71 obtains 01H from the XOR logic operation of 5BH and 5AH in the first byte. For example, the sub CPU 71 obtains 0FH from the XOR logic operation of 55H and 5AH in the eighth byte. As a result of this XOR logic operation, the sub CPU 71 decodes 01H for the first byte data, 03H for the second byte data,..., 0FH for the eighth byte data, as shown in FIG. Data that has been processed is generated.

  In the above description, the data included in one packet is 8 bytes, but the present invention is not limited to this. Further, the encryption process and the decryption process are described by the XOR logic operation with the model ID data, but the present invention is not limited to this, and the encryption process is performed by the XOR logic operation with predetermined data other than the model ID. Alternatively, a decoding process may be performed.

(Calculation pattern B)
The calculation pattern B will be described with reference to FIG. FIG. 18A shows the configuration of 8-byte data included in one packet before encryption processing, and is the same as FIG. 17A described above.

  In the configuration shown in FIG. 18A, the main CPU 31 performs an addition operation with 5AH, which is data indicating the model ID, for each data from the first byte to the eighth byte, and FIG. By generating the 8-byte data as shown in FIG. 6, the encryption process is performed while maintaining the data arrangement order.

  Specifically, for example, the main CPU 31 adds 5AH to 01H of the first byte to obtain 5BH. For example, the main CPU 31 adds 69 AH to 0FH of the eighth byte to obtain 69H. As a result of this addition operation, the main CPU 31 encrypts the first byte of data as 5BH, the second byte of data as 5DH,..., The eighth byte of data as 69H, as shown in FIG. Generate processed data.

  In the configuration shown in FIG. 18B, the sub CPU 71 performs a subtraction operation with respect to each data from the 1st byte to the 8th byte with 5AH which is data indicating the model ID. By generating the 8-byte data as shown in FIG. 8, the decoding process is performed while maintaining the data arrangement order.

  Specifically, for example, the sub CPU 71 subtracts 5AH from 5BH of the first byte to obtain 01H. Further, for example, the sub CPU 71 subtracts 5AH from 69H of the 8th byte to obtain 0FH. As a result of this subtraction operation, the sub CPU 71 decodes the first byte data as 01H, the second byte data as 03H,..., And the eighth byte data as 0FH as shown in FIG. Generate processed data.

  In the above description, the data included in one packet is 8 bytes, but the present invention is not limited to this. In addition, although the encryption process is performed by the addition operation with the model ID data and the decryption process is performed by the subtraction operation with the model ID data, the present invention is not limited to this, and the predetermined process other than the model ID is performed. An encryption process and a decryption process may be performed by addition and subtraction operations with data.

[Game state]
Next, with reference to FIG. 19, the transition of the gaming state will be described. The main gaming state managed by the main control circuit 60 includes a general gaming state, an RT1 gaming state, an RT2 gaming state, an RT3 gaming state, an RT4 gaming state, and a BB gaming state (a general term of BB1 gaming state to BB4 gaming state). Although not shown, there is an SB gaming state in which only one game coexists with other gaming states, an RB1 gaming state that operates in the BB1 gaming state to the BB3 gaming state, and an RB2 gaming state that operates in the BB4 gaming state.

  First, in the general gaming state, the SB spilled eyes (SB spilled eyes 1 to SB spilled eyes 12) are displayed on the active line, thereby transitioning to the RT1 gaming state. Next, in the RT1 gaming state, the raised one-step lip 1 is displayed on the active line, thereby transitioning to the RT2 gaming state. Next, in the RT2 gaming state, the two-step up lip (up two-step lip 1, up two-step lip 2) and the second up (up two to one up two) are displayed on the active line, so that RT3 Transition to the gaming state.

  Further, in the RT2 gaming state or the RT3 gaming state, the SB spilling eyes (SB spilling eyes 1 to SB spilling eyes 12) are displayed on the active line, thereby transitioning to the RT1 gaming state. In the RT1 gaming state to the RT3 gaming state, the push order bell failure (push order bell failure 1 to push order bell failure 4) is displayed on the active line, thereby transitioning to the general gaming state.

  In the general gaming state, the RT1 gaming state to the RT3 gaming state, the BB (BB1 to BB4) is determined as the internal winning combination, thereby transitioning to the RT4 gaming state. In the RT4 gaming state, BB (BB1 to BB4) is displayed, thereby transitioning to the BB gaming state. When a predetermined number (270 or 60) of medals are paid out in the BB gaming state, a transition is made to the general gaming state.

  Next, an internal lottery table determination table stored in the main ROM 32 of the main control circuit 60 will be described with reference to FIG. FIG. 20 is a diagram illustrating an example of an internal lottery table determination table of the gaming machine 1 in the present embodiment.

  In the internal lottery table determination table, an internal lottery table used for determining an internal winning combination in an internal lottery process described later corresponding to a gaming state (on / off of each game state flag described later), and the number of lotteries Is stipulated. Thereby, for example, when only the SB gaming state flag and the RT1 gaming state flag are “1 (ON)”, “the internal lottery table for RT1 gaming state during SB” is selected as the number of lotteries. “49” is selected.

  Next, an internal lottery table stored in the main ROM 32 of the main control circuit 60 will be described with reference to FIGS. FIG. 21 is a diagram in which examples of a general gaming state internal lottery table, an RT1 gaming state internal lottery table to an RT4 gaming state internal lottery table of the gaming machine 1 according to the present embodiment are grouped into one.

  FIG. 22 is a diagram illustrating an example of the internal lottery table for the RB1 gaming state of the gaming machine 1 according to the present embodiment.

  FIG. 23 is a diagram illustrating an example of the RB2 gaming state internal lottery table of the gaming machine 1 according to the present embodiment. It should be noted that the lottery value corresponding to the winning number “1” in FIG. 21 is “1000” in the internal lottery table for the general gaming state during SB and the internal lottery table for the RT1 gaming state during SB to the internal lottery table for the RT4 gaming state during SB. The difference is only “1001”, not “”.

  The internal lottery table is a table used when performing internal lottery in an internal lottery process described later, that is, when determining an internal winning combination. In the internal lottery table, lottery values and data pointers are defined for each winning number. The lottery value is a numerical value used to determine the data pointer. There are two types of data pointers, a small combination / replay data pointer and a bonus data pointer, which correspond to one or more internal winning combinations.

  In the internal lottery tables shown in FIGS. 21 to 23, the abbreviated names of the internal winning combinations corresponding to the data pointers are shown in the right column of the winning numbers. Also, on the right side of each internal lottery table shown in FIG. 22 and FIG. 23, symbols that can be stopped and displayed on the line connecting the upper stage, the line connecting the middle stage, or the line connecting the lower stage corresponding to the data pointer. The stop form is shown.

  For example, in the RB1 gaming state, when “25” is determined as the small role / replay data pointer, a stop operation is performed at a timing at which a don symbol can be stopped and displayed on the lower stage of the left reel 3L and the lower stage of the middle reel 3C. If it is performed, the don symbol is stopped and displayed on the lower stage of the left reel 3L and the lower stage of the middle reel 3C, but the stop operation was performed at a timing at which the don symbol can be stopped and displayed on the lower stage of the right reel 3R. Even in this case, the don symbol is not stopped and displayed in the lower stage of the right reel 3R.

  On the other hand, if “28” is determined as the small role / replay data pointer, the stop operation is performed at a timing at which a don symbol can be stopped and displayed on the lower stage of the left reel 3L, the lower stage of the middle reel 3C, and the lower stage of the right reel 3R. As a result, the don symbol is stopped and displayed on the line connecting the lower stages of the reels.

  In the stop form of the symbols aligned on the winning line in FIG. 22, “tempered losing” means that even if the stop operation is performed at a timing at which the don symbol can be stopped and displayed on the corresponding line, "Don symbol-Don symbol-Don symbol" means a stop type that is not stopped and displayed on a line connecting the upper stage of each reel, a line connecting the middle stage, and a line connecting the lower stage.

  On the other hand, “per tempering” is a line in which “Don symbol-Don symbol-Don symbol” connects the upper stages of each reel by performing a stop operation on the corresponding line at a timing at which the Don symbol can be stopped and displayed. , Means a stop form that is stopped and displayed on a line connecting the middle stages or a line connecting the lower stages.

  Next, a method for determining a data pointer using a lottery value, that is, an internal lottery method will be described. In the internal lottery, first, a random number value is extracted from a predetermined numerical range “0 to 65535”, and a lottery value corresponding to each winning number is sequentially subtracted from the extracted random number value and a digit is performed. This is done by determining whether or not. Digit is performed when the numerical value to be subtracted is smaller, in other words, when the result of subtraction is negative.

  For example, when the internal lottery table for the general gaming state is determined to be the internal lottery table, when the extracted random number value is “1500”, the main CPU 31 first corresponds to the winning number “1” from “1500”. The lottery value “1000” to be subtracted is subtracted. The subtraction result is “1500−1000 = 500”, which is positive.

  Next, the main CPU 31 subtracts the lottery value “2100” corresponding to the winning number “2” from the subtracted value “500”. The subtraction result is “500-2100 = −1600”, which is negative. Therefore, the main CPU 31 determines the winning number “2” as the internal winning combination, that is, “13” as the small combination / replay data pointer and “0” as the bonus data pointer.

  According to this internal lottery method, the larger the numerical value defined as the lottery value, the higher the possibility that the data pointer of the corresponding winning number will be determined. The winning probability of each winning number is “the lottery value corresponding to each winning number / the number of all random values that may be extracted (“ 65536 ”)”.

  Note that various types of lottery performed using lottery values, which will be described later, are the same as those for determining the data pointer. That is, lottery values are defined in the various lottery tables in association with items (for example, winning numbers) that may be selected by lottery. Hereinafter, the various lottery methods based on the lottery value are the same as the internal lottery method, and thus description thereof is omitted.

  Next, the RT transition table will be described with reference to FIG. The RT transition table is a table used when a gaming state flag is updated in an RT control process to be described later. As shown in FIG. 24, in the RT transition table, the display combination and the control contents for the game state flag are defined correspondingly.

  Specifically, when the combination of symbols related to any one of push order bell failure 1 to push order bell failure 4 is stopped and displayed on the active line, all the game state flags are turned off. That is, the general gaming state is activated. In addition, when the combination of symbols related to any one of the SB spilled eyes 1 to 12 is stopped and displayed on the active line, the RT1 gaming state flag is turned on. In addition, when the combination of symbols related to the raising 1-step lip 1 is stopped and displayed on the active line, the RT2 gaming state flag is turned on. In addition, when the combination of symbols related to any one of the raising 2 stage lip 1, the raising 2 stage lip 2, and the second raising 1 to the second raising 3 is stopped on the active line, the RT3 gaming state flag is turned on. To do.

  In addition, push order bell failure 1-push order bell failure 4, SB spilled eyes 1-SB spilled eyes 12, raised 1 stage lip 1, raised 2 stage lip 1, raised 2 stage lip 2, raised 2 stage 1-raised 2nd stage 3 is a case where a predetermined combination is determined as an internal winning combination, and when a stop operation is performed according to a predetermined stop operation sequence, the stop operation is stopped in a stop operation sequence different from the predetermined stop operation sequence. This is a display combination that may be stopped and displayed on the active line when an operation is performed or when a stop operation is not performed at an appropriate timing, which will be described in detail later.

  Next, with reference to FIGS. 25 and 26, the bonus internal winning combination determining table and the small winning combination / replay internal winning combination determining table stored in the main ROM 32 of the main control circuit 60 will be described. FIG. 25 is a diagram showing an example of a bonus internal winning combination determination table for the gaming machine 1 in the present embodiment. FIG. 26 is a diagram showing an example of a small winning combination / replay internal winning combination determining table of the gaming machine 1 according to the present embodiment. Hereinafter, the bonus internal winning combination determination table and the small winning combination / replay internal winning combination determination table are collectively referred to as an internal winning combination determination table.

  The internal winning combination determination table is a table used when determining an internal winning combination based on a data pointer in an internal lottery process described later. Each winning combination determined as an internal winning combination corresponding to the data pointer is defined in the internal winning combination determination table. Each combination corresponds to each bit stored in an internal winning combination storage area described later. Therefore, it is possible to identify which combination is an internal winning combination by determining which bit in the internal winning combination storing area is “1”.

  In the bonus internal winning combination determination table shown in FIG. 25, internal winning combinations corresponding to bonus data pointers “1” to “5” are defined. When “5” is determined as the bonus data pointer, the combination of symbols related to SB is stopped and displayed on the active line depending on whether or not the stop operation is performed in a predetermined stop order, or The combination of symbols related to any of the SB spilled eyes 1 to SB spilled eyes 12 is stopped and displayed on the effective line.

  In the small winning combination / replay internal winning combination determining table shown in FIG. 26, internal winning combinations corresponding to the small winning combination / replay data pointers “1” to “31” are defined. For example, when “1” is determined as the small combination / replay data pointer, the normal lip 1 and the raised one-stage lip 1 become the internal winning combination.

  When “2” is determined as the small role / replay data pointer, the first stop operation is performed on the left reel 3L, the second stop operation is performed on the middle reel 3C, and the second stop operation is performed on the right reel 3R. Only when the 3 stop operation is performed, the combination of symbols related to the raised 1-step lip 1 is stopped and displayed on the active line. On the other hand, when the stop operation is performed in the other stop operation order, the symbol combination related to the normal lip 1 is stopped and displayed on the active line.

  Also for the small role / replay data pointers “3” to “6”, a stop operation sequence in which the combination of symbols related to the raised 1-step lip 1 is stopped and displayed on the active line is determined in advance. When the stop operation is performed in a stop operation order other than the above, the symbol combination related to the normal lip 1 is stopped and displayed on the active line.

  In addition, when “7” is determined as the small role / replay data pointer, only when the first stop operation is performed on the left reel 3L, the raised two-step lip 1, the raised two-step lip 2, The combination of symbols relating to any one of the raised second eye 1, the raised second eye 2, and the raised second eye 3 is stopped and displayed on the active line.

  In addition, when the raised second 1, raised second 2, and raised second 3 are stopped and displayed on the effective line, the normal lip 1 or the raised one-step lip 1 is simultaneously stopped and displayed on the effective line. On the other hand, when the stop operation is performed in the other stop operation order, the symbol combination related to the normal lip 1 is stopped and displayed on the active line.

  For the data pointers “8” to “11” for the small role / replay, the combination of the symbols related to the two-step-up lip 1, the two-step lip-up 2, the second-up 1, the second-up 2, and the second-up 3 is effective. The stop operation order to be stopped and displayed on the line is determined in advance, and when the stop operation is performed in a stop operation order other than this stop operation order, the combination of symbols related to the normal Lip 1 is on the active line. Stopped display.

  When “12” is determined as the small role / replay data pointer, the symbol related to the bell is stopped and displayed in the middle of the middle reel 3C regardless of the stop operation order.

  When “13” is determined as the small role / replay data pointer, the first stop operation is performed on the left reel 3L, the second stop operation is performed on the middle reel 3C, and the third stop is performed on the right reel 3R. Only when the operation is performed, the symbol related to the bell is stopped and displayed on the middle stage of the middle reel 3C.

  On the other hand, when the stop operation is performed in the other stop operation order, the combination of symbols related to any one of the push order bell failure 1 to the push order bell failure 4 is stopped and displayed on the active line. When the symbol related to the bell is stopped and displayed on the middle stage of the middle reel 3C, any one of the center line 8c, the cross-up line 8a, and the cross-down line 8e indicates "Bell 1 symbol (Bell 2 symbol)-Bell 1 symbol-" "Bell 1 symbol" is stopped and displayed.

  Further, when the combination of symbols relating to any one of the push order bell failure 1 to the push order bell failure 4 is stopped and displayed on the active line, the lower stage of the left reel 3L, the lower stage of the middle reel 3C, and the lower stage of the right reel 3R. "Bell 1 symbol (Bell 2 symbol)-Bell 1 symbol-Bell 1 symbol" is stopped and displayed.

  As for the small role / replay data pointers “14” to “17”, a stop operation order in which symbols related to the bell are stopped and displayed in the middle stage of the middle reel 3C is determined in advance, and stop operations other than this stop operation order are performed. When the stop operation is performed in order, the combination of symbols related to any one of the push order bell failure 1 to the push order bell failure 4 is stopped and displayed on the active line.

  In addition, in the internal lottery table, when the small role / replay pointer that indicates the stop operation order (push order) for the reel is determined, the suggested push order is the so-called correct push order, When the stop operation is performed in the pushing order, each reel 3 is stopped so that the player is advantageous.

  For example, when the small role / replay pointer “2” (abbreviation “left middle right bell”) is determined, the first stop operation is performed on the left reel 3L, the second stop operation is performed on the middle reel 3C, Only when the third stop operation is performed on the right reel 3R, the symbol related to the bell is stopped and displayed on the middle stage of the middle reel 3C (payout number: 4 sheets × 3 lines = 12 sheets). If it is, the symbol related to the bell is stopped and displayed on the lower stage of the middle reel 3C (paid-out number: 4 sheets × 1 line = 4 sheets). Note that the small role / replay pointers whose abbreviations indicate the stop operation order (pushing order) for the reels are “2” to “11” and “13” to “17”.

  Next, the symbol combination table stored in the main ROM 32 of the main control circuit 60 will be described with reference to FIG. FIG. 27 is a diagram showing an example of the symbol combination table of the gaming machine 1 in the present embodiment.

  In the symbol combination table, a combination of symbols related to the privilege display displayed on the active line, or a combination of symbols related to the transition of the gaming state, data indicating a display combination corresponding to the symbol combination, and a storage area type , And the number of payouts. The data indicating the display combination is any one of a display combination storage area 1 to a display combination storage area 7 each of which will be described later (display combination storage area 1 to display combination storage area 7 are collectively referred to as a display combination storage area). Is stored in the data. Further, in which display combination storage area the data is stored is defined by the storage area type.

  In the symbol combination table, BB1 to BB4, SB, normal lip 1, raised 1 stage lip 1, raised 2 stage lip 1, raised 2 stage lip 2, control lip 1 to control lip 3, bell, ice 1 Cherry 1-Cherry 12, Control role 1-Control role 3, BB middle role 1-BB middle role 5, Raise 2-1, Raise 2, Push order bell failure 1-Push order bell failure 4, SB Spilled eyes 1 to SB spilled eyes 12 are defined.

  For example, the normal lip 1 is established by displaying “replay symbol-replay symbol-replay symbol” on the active line. When any of the various replays (normal lip 1, raising 1-step lip 1, raising 2-step lip 1, raising 2-step lip 2, control lip 1 to control lip 3) is established, re-playing is performed in the next game. Is called. That is, the same number of medals as the number inserted in the game in which any of the various replays is established is automatically inserted in the next game without being based on the player's input operation.

  Thereby, the player can play the next game without consuming medals. Here, the above-mentioned medal payout and re-game are examples of giving game value. The bell is established by displaying “ANY symbol-Bell 1 symbol-ANY symbol” on the active line. “ANY” represents that any symbol may be used.

  Next, with reference to FIG. 28, the bonus operation time table stored in the main ROM 32 of the main control circuit 60 will be described. FIG. 28 is a diagram showing an example of the bonus operation time table of the gaming machine 1 in the present embodiment.

  The bonus operating time table is a table used when setting conditions for ending the BB gaming state and the RB gaming state. In the bonus operation time table, end conditions relating to the BB1 gaming state to the BB4 gaming state, the RB1 gaming state, and the RB2 gaming state are defined. Specifically, in the bonus operation time table, “270” is defined for the value of the bonus end number counter as the end condition of the BB1 gaming state to the BB3 gaming state.

  Further, “60” is defined for the value of the bonus end number counter as an end condition of the BB4 gaming state. In the BB1 gaming state to the BB3 gaming state, the RB1 gaming state operates, and in the BB4 gaming state, the RB2 gaming state operates. Further, in the bonus operation time table, “12” and “8” are defined for the values of the number of possible games and the number of possible winnings, respectively, as termination conditions for the RB1 gaming state and the RB2 gaming state.

  Next, the pull-in priority order table stored in the main ROM 32 of the main control circuit 60 will be described with reference to FIGS. 29 and 30. FIG. FIG. 29 is a diagram illustrating an example of the pull-in priority table A of the gaming machine 1 in the present embodiment, and FIG. 30 illustrates an example of the pull-in priority table B of the gaming machine 1 in the present embodiment. FIG. Hereinafter, the pull-in priority table A and the pull-in priority table B are collectively referred to as a pull-in priority table.

  When multiple winning combinations are determined as internal winning combinations, when the multiple winning combinations can be drawn on the active line, the drawing priority order table gives priority to the symbol related to any combination on the active line. Specifies whether to stop. As described above, basically, replay from the highest priority order, small role (the higher the payout number, the higher the priority order. In the case of JAC1 (seven in BB), priority is given), and bonus order It has become.

  However, in the present embodiment, there are a plurality of types of replays, and the priority order of each replay differs depending on the conditions. Therefore, a pull-in priority table A and a pull-in priority table B are provided for each condition.

  The pull-in priority table A is a table that is used during normal times (including during BB) or so-called correct push order, and the priority of each replay is raised two-step Lip 1, raised two-step Lip 2> up one-step Lip 1 > Normal Lip 1> Control Lip 1-Control Lip 3

  On the other hand, the pull-in priority table B is a table used at the time of so-called incorrect push order, and the priority of each replay is normal lip 1> up 2 step lip 1, up 2 step lip 2, up 1 step lip 1> control. Lip 1-control Lip 3 is in this order.

  Although not shown, when two or more combinations related to the transition of the RT gaming state simultaneously become display combinations, it is determined in advance which one is to be prioritized. In the present embodiment, in the order of higher priority, the two-step raising lip 1, the two-step raising lip 2, the second raising 1-the second raising 3> the first raising lip 1> SB spilling 1-SB spilling Eye 12> Pushing order bell failure 1-pushing order bell failure 4

  Next, the stop table stored in the main ROM 32 of the main control circuit 60 will be described with reference to FIG. FIG. 31 shows an example of a stop table for the first stop of the middle reel when the small role / replay data pointer “15” is won. The stop table defines line data and stop data corresponding to symbol positions “0” to “20”. The symbol position is a symbol position located in the middle of the symbol display area when a stop operation is detected, and is a symbol position at which rotation of the reel starts to be stopped.

  Although not shown, the main ROM 32 of the main control circuit 60 stores a small role / replay data pointer and a plurality of stop tables corresponding to the stop operation order of the player. For example, when “5” is determined as the bonus data pointer, the first stop operation is performed on the right reel 3R, the second stop operation is performed on the left reel 3L, and the third stop operation is performed on the middle reel 3C. Only when the operation is performed, a stop table in which the number of sliding frames is defined so that none of the SB spilled eyes 1 to SB spilled eyes 12 is stopped and displayed on the active line is selected.

  On the other hand, when the stop operation is performed in a stop operation order other than the stop operation order, when the stop operation is performed on each reel at a timing at which the combination of symbols relating to SB is not stopped and displayed, SB spill 1 A stop table in which the number of sliding frames is defined so that the combination of symbols relating to any one of the SB spilled eyes 12 is stopped and displayed on the active line is selected.

  Next, an internal winning combination storing area, a display combination storing area and a carryover combination storing area allocated to the main RAM 33 of the main control circuit 60 will be described with reference to FIGS. FIG. 32 is a diagram showing an example of the internal winning combination storing area of the gaming machine 1 in the present embodiment. FIG. 33 is a diagram showing an example of the display combination storing area of the gaming machine 1 in the present embodiment. FIG. 34 is a diagram showing an example of the carryover combination storage area of the gaming machine 1 in the present embodiment.

  As shown in FIG. 32, the internal winning combination storing area is composed of an internal winning combination storing area 1 to an internal winning combination storing area 5. The internal winning combination storing area 1 to the internal winning combination storing area 5 are 8-bit data areas allocated on the main RAM 33, and store internal winning combination information. Each internal winning combination storing area indicates which combination is an internal winning combination by storing data of “0” or “1” in the area of bits “0” to “7”.

  As shown in FIG. 33, the display combination storage area is composed of a display combination storage area 1 to a display combination storage area 7. The display combination storage area 1 to the display combination storage area 7 are 8-bit data areas allocated on the main RAM 33 and store display combination information. Each display combination storage area indicates which combination is a display combination by storing data of “0” or “1” in an area of bits “0” to “7”.

  As shown in FIG. 34, the carryover combination storage area is an 8-bit data area allocated on the main RAM 33 and stores carryover combination information. The carryover combination storage area indicates which combination is a carryover combination by storing data of “0” or “1” in an area of bits “0” to “3”.

  Next, with reference to FIG. 35, the gaming state flag storage area allocated to the main RAM 33 of the main control circuit 60 will be described. FIG. 35 is a diagram showing an example of the game state flag storage area of the gaming machine 1 in the present embodiment.

  As shown in FIG. 35, the gaming state flag storage area is composed of a gaming state flag storage area 1 and a gaming state flag storage area 2. The gaming state flag storage area is an 8-bit data area allocated on the main RAM 33, and indicates whether each gaming state flag is on or off. Further, when all the data in each area of the game state flag storage area is “0”, it indicates that the game state is a general game state.

  Next, the symbol storage area in the main RAM 33 of the main control circuit 60 will be described with reference to FIGS. FIG. 36 is a diagram showing a storage example (when the symbol position data of each reel is “0”) in the symbol storage area A (non-RB) of the gaming machine 1 in the present embodiment. FIG. 37 shows a storage example of the symbol storage area B (in RB) of the gaming machine 1 in the present embodiment (when the symbol position data of each reel is “9”, “8”, “9” from the left reel). ).

  The symbol storage area is an area for storing a corresponding symbol code in the symbol display areas 4L, 4C, and 4R constituting each effective line, and is provided for each effective line. For example, when the gaming state is a gaming state other than the RB gaming state, it corresponds to each of the middle stage of the left symbol display area 4L, the middle stage of the middle symbol display area 4C, and the middle stage of the right symbol display area 4R constituting the center line 8c. Stores the symbol code.

  Such symbol storage areas are also provided for the other effective lines (cross down line 8e, bottom line 8d, cross up line 8a). When the gaming state is the RB gaming state, the effective line is only one line (RB special line 8f), and the RB special line 8f is configured in the symbol storage area corresponding to the RB special line 8f. The symbol codes corresponding to the middle part of the left symbol display area 4L, the lower part of the middle symbol display area 4C, and the upper part of the right symbol display area 4R are stored.

  The symbol storage area shown in FIG. 36 indicates the symbol storage area when the symbol code is stored when the symbol position data of each reel is “0”. The case where the symbol position data is “0” means that the symbol position “0” of each reel 3L, 3C, 3R (red 7 symbol for left reel 3L, red 7 symbol for middle reel 3C, red for right reel 3R) 7 symbols) are displayed in the middle of the left symbol display area 4L, the middle of the middle symbol display area 4C, and the middle of the right symbol display area 4R, respectively.

  Therefore, in this case, the symbol storage area corresponding to the upper symbol display area 4L has a symbol position “1” (wave symbol), and the symbol storage area corresponding to the lower symbol display area 4L has a symbol position “ The symbol code indicating the symbol “20” (replay symbol) is stored. The symbol storage area corresponding to the upper part of the middle symbol display area 4C has a symbol position “1” (replay symbol), and the symbol storage area corresponding to the lower part of the middle symbol display area 4C has symbol position “20”. A symbol code indicating a symbol (cherry 1 symbol) is stored.

  Furthermore, in the symbol storage area corresponding to the upper part of the right symbol display area 4R, the symbol at the symbol position “1” (cherry 1 symbol), and in the symbol storage area corresponding to the lower part of the right symbol display area 4R, the symbol position “20”. The symbol code indicating the symbol (bell 1 symbol) is stored.

[Control operation of main control circuit]
Next, the control operation of the main CPU 31 of the main control circuit 60 will be described with reference to the flowcharts shown in FIGS.

  First, with reference to FIG. 38, the reset interrupt process by the main CPU 31 of the main control circuit 60 will be described. FIG. 38 is a diagram showing a flowchart of reset interrupt processing by the main CPU 31 performed by the main control circuit 60 of the present embodiment. Further, the main CPU 31 generates a reset interrupt when power is turned on and a voltage is applied to the reset terminal, and the reset interrupt process stored in the main ROM 32 is sequentially performed based on the occurrence of the interrupt. Configured to do.

  First, the key code creating means 31a of the main CPU 31 sets a key code (step S0). In the present embodiment, the key code is a 1-byte random value acquired from the refresh register when the gaming machine 1 is powered on. Subsequently, the main CPU 31 clears the designated storage area (step S1). Specifically, the main CPU 31 clears the designated storage area of the main RAM 33 at the end of the previous game. More specifically, the main CPU 31 erases data in the writable area in the main RAM 33 used in the previous game, writes parameters necessary for the current game in the writable area in the main RAM 33, Specify the start address to the sequence program.

  Next, the main CPU 31 performs a bonus operation monitoring process (step S2).

  Next, the main CPU 31 performs medal acceptance / start check processing (step S3). In the medal acceptance / start check process, the insertion number counter is updated by checking the medal sensor 22S, the maximum BET switch 13S, and the like, and the input of the start switch 6S is checked. The main CPU 31 validates the winning line through the medal acceptance / start check process.

  Next, the main CPU 31 performs a process of extracting a random value and storing it in the random value storage area (step S4). Specifically, the main CPU 31 extracts a random value from the range of “0” to “65535” by the random number generator 36 and the sampling circuit 37 and stores the extracted random value in the random value storage area of the main RAM 33.

  Next, the main CPU 31 performs an internal lottery process (step S5). Specifically, the main CPU 31 refers to the internal lottery table determination table (see FIG. 20), the internal lottery table (see FIGS. 21 to 23), and the internal winning combination determination table (see FIGS. 25 and 26). To determine the internal winning role.

  Next, the main CPU 31 transmits start command data to the sub-control circuit 70 (step S6). The start command includes information such as game state information, internal winning combination information (data pointer for small role / replay, bonus data pointer and internal winning combination storage area), and carryover state information indicating whether or not a bonus carryover state exists. It is included.

  Specifically, the main CPU 31 assigns communication data to be transmitted to the main RAM 33 by setting parameters such as a flag and a counter, setting a start command, and performing communication data storage processing described later. To be registered in the communication data storage area. The following command data is also transmitted to the sub control circuit 70 in the same manner.

  Next, the main CPU 31 requests rotation start of all reels (step S7). When the start of rotation of all reels is requested, rotation start processing and acceleration control processing of the reels 3L, 3C, and 3R are performed.

  Next, the main CPU 31 waits for a constant speed for reel rotation (step S8).

  Next, the main CPU 31 performs a reel stop control process (step S9). In the reel stop control process, the main CPU 31 stops the rotation of the reels 3L, 3C, 3R based on a stop signal transmitted from the stop switches 7LS, 7CS, 7RS by the stop operation of the player.

  Next, the main CPU 31 performs a display combination search process (step S10). In this display combination search process, the main CPU 31 determines the display combination and the number of payouts based on the combination of symbols displayed on the effective line as a result of stopping the rotation of all the reels 3L, 3C, 3R.

  Next, the main CPU 31 performs an RT control process (step S11).

  Next, the main CPU 31 transmits display command data (step S12). The display command includes information such as display combination information indicating a display combination and payout number information indicating a payout number.

  As a specific process, for example, the main CPU 31 sets an RT operation combination display flag in P1, and sets a winning number counter in P2. The main CPU 31 sets a display command and performs communication data storage processing described later, thereby registering communication data to be transmitted in the communication data storage area.

  Next, the main CPU 31 performs medal payout processing (step S13). Specifically, in the payout mode, the main CPU 31 drives and controls the hopper 40 by the hopper drive circuit 41 based on the payout number, and pays out medals. In the credit mode, the main CPU 31 performs main control based on the payout number. The credit counter set in the RAM 33 is updated.

  Next, it is determined whether or not the bonus is being operated (step S14). Specifically, it is determined whether or not the BB1 gaming state to the BB4 gaming state or the SB gaming state. At this time, if the main CPU 31 determines that the bonus is being operated, it performs a bonus end check process (step S15), and proceeds to the process of step S16. On the other hand, when the main CPU 31 determines that the bonus operation is not being performed, or after finishing the processing of step S15, the main CPU 31 then performs a bonus operation check processing (step S16). The process proceeds to S1.

  In this way, the main CPU 31 executes the processing from step S1 to step S16 as processing in one game (one game), and when the processing in step S16 ends, the processing in step S1 is executed to execute processing in the next game. Migrate to Therefore, during one reset interrupt process, the key code is set only once, and even if the game process is performed a plurality of times, the same key code is used every time.

  Next, the bonus operation monitoring process will be described with reference to FIG. FIG. 39 is a view showing a flowchart of the bonus operation monitoring process performed in the main control circuit 60 of the present embodiment.

  First, the main CPU 31 determines whether or not the BB gaming state is set (step S31). At this time, when the main CPU 31 determines that it is in the BB gaming state, it proceeds to the processing of step S32. On the other hand, when determining that the main CPU 31 is not in the BB gaming state, the main CPU 31 ends the bonus operation monitoring process.

  When the main CPU 31 determines in the process of step S31 that it is in the BB gaming state, it then determines whether or not it is in the RB gaming state (step S32). At this time, when determining that the main CPU 31 is in the RB gaming state, the bonus operation monitoring process is terminated.

  On the other hand, when the main CPU 31 determines that it is not in the RB gaming state, the main CPU 31 performs RB operation processing according to the type of BB based on the bonus operation table (see FIG. 28) (step S33), and performs bonus operation monitoring processing. Terminate. Specifically, the RB1 gaming state is activated in the BB1 gaming state to the BB3 gaming state, and the RB2 gaming state is activated in the BB4 gaming state.

  Next, with reference to FIGS. 40 and 41, the internal lottery process will be described. 40 and 41 are diagrams showing a flowchart of an internal lottery process performed by the main control circuit 60 of the present embodiment.

  First, the main CPU 31 refers to the internal lottery table determination table (see FIG. 20) and determines the type of the internal lottery table and the number of lotteries based on the gaming state flag (step S61). Next, the main CPU 31 acquires a random value from the random value storage area and sets it as a random number for determination (step S62). Next, the main CPU 31 sets “1” as the initial value of the winning number (step S63).

  Next, the main CPU 31 refers to the internal lottery table and acquires a lottery value based on the winning number (step S64). Next, the main CPU 31 subtracts the lottery value from the determination random number value, and sets the subtraction result as the determination random number value (step S65). Specifically, the main CPU 31 subtracts the lottery value acquired in the process of step S64 from the random number value for determination stored in the random number value storage area for determination, and updates the random number value storage area for determination with the subtraction result. .

  Next, the main CPU 31 determines whether or not a digit has been performed in the subtraction process of step S65, that is, whether or not the subtraction result has become a negative value (step S66). At this time, when the main CPU 31 determines that a digit has been made, the main CPU 31 obtains the small role / replay data pointer and the bonus data pointer based on the winning number (step S70), and proceeds to the processing of step S71.

  On the other hand, when the main CPU 31 determines that no digit has been placed, it then subtracts “1” from the number of lotteries and adds “1” to the winning number (step S67). Next, the main CPU 31 determines whether or not the number of lotteries is “0” (step S68).

  When determining that the number of lotteries is “0” in the process of step S68, the main CPU 31 determines the small role / replay data pointer and the bonus data pointer to be “0” (step S69). Transition to processing. On the other hand, when determining that the number of lotteries is not “0”, the main CPU 31 proceeds to the process of step S64. Thereafter, the main CPU 31 repeats the processing from step S64 to step S68 until the number of lotteries becomes “0” or a digit is made.

  After completing the process of step S69 or step S70, the main CPU 31 then refers to the internal winning combination determination table for small roles / replay (see FIG. 26) and determines the internal winnings based on the small role / replay data pointer. A combination is acquired (step S71). Next, the main CPU 31 updates the internal winning combination storing area according to the internal winning combination storing area (step S72).

  Next, the main CPU 31 determines whether or not the carryover combination storage area is “00000000” (step S73). At this time, when the main CPU 31 determines that the carryover combination storage area is not “00000000”, the main CPU 31 proceeds to the process of step S80. On the other hand, when the main CPU 31 determines that the carryover combination storage area is “00000000”, the main CPU 31 refers to the bonus internal winning combination determination table (FIG. 25) and acquires the internal winning combination based on the bonus data pointer ( Step S74).

  Next, the main CPU 31 determines whether or not SB is an internal winning combination (step S75). At this time, when the main CPU 31 determines that the SB is an internal winning combination, the main CPU 31 updates the internal winning combination storing area according to the SB (step S76), and proceeds to the processing of step S80. On the other hand, when determining that SB is not an internal winning combination, the main CPU 31 determines whether or not BB is an internal winning combination (step S77).

  When the main CPU 31 determines in step S77 that BB is not an internal winning combination, the main CPU 31 proceeds to step S80. On the other hand, when determining that BB is an internal winning combination, the main CPU 31 updates the carryover combination storing area according to BB (step S78), turns on the RT4 gaming state flag (step S79), and performs the process of step S80. Migrate to

  When the main CPU 31 determines that the carryover combination storage area is not “00000000” in the process of step S73, and determines that BB is not the internal winning combination in the process of step S77, the process of steps S76 and S79. Then, the logical OR of the carryover combination storage area and the internal winning combination storage area 1 is taken, and the result is stored in the internal winning combination storage area 1 (step S80).

  The main CPU 31 performs lottery of an internal winning combination by repeatedly executing the processes of steps S64 to S68 in the internal lottery process. Specifically, the main CPU 31 sequentially subtracts the lottery value from the extracted random number value, thereby obtaining the small role / replay data pointer and the bonus data pointer corresponding to the winning number when the digit is placed. The internal winning combination is determined based on the determined data pointers and the internal winning combination determination table.

  Next, the reel stop control process will be described with reference to FIG. FIG. 42 is a flowchart of the reel stop control process performed by the main control circuit 60 of the present embodiment.

  First, the main CPU 31 sets “3” in the stop button non-operation counter (step S101), and then acquires a stop table corresponding to the internal winning combination (step S102).

  Next, the main CPU 31 determines whether or not a valid stop button has been pressed (step S103). An effective stop button is a stop button that has not been stopped. At this time, if the main CPU 31 determines that a valid stop button has been pressed, the main CPU 31 proceeds to the processing of step S104. On the other hand, when the main CPU 31 determines that a valid stop button has not been pressed, the main CPU 31 executes the process of step S103 again. That is, the main CPU 31 repeats the process of step S103 until a stop operation corresponding to a valid stop button is detected.

  When the main CPU 31 determines in the process of step S103 that an effective stop button has been pressed, the main CPU 31 invalidates the operation of the corresponding stop button (step S104). Next, the stop table is reselected according to the operation stop button (stop order) (step S105).

  Next, the main CPU 31 sets “5” as the number of checks (step S106). Next, the main CPU 31 refers to the drawing priority table (see FIGS. 29 and 30), and based on the internal winning combination, the symbol having the highest priority within the range of the number of checks from the symbol position corresponding to the symbol counter. The position is searched (step S107).

  Next, the main CPU 31 determines the number of sliding symbols based on the stop table, the symbol position corresponding to the symbol counter, and the search result, and sets the planned stop position (step S108). Next, the main CPU 31 transmits a reel stop command (step S109). The reel stop command includes information such as stop reel type information indicating which reel has stopped, stop start position information indicating the stop start position, and slip frame number information indicating the number of slide frames.

  Next, the main CPU 31 refers to the symbol arrangement table (see FIG. 3), acquires a symbol code based on the stop reel, the planned stop position, and the gaming state, and stores it in the symbol storage area (step S110).

  Finally, the main CPU 31 determines whether or not there is a stop button whose operation is valid (step S111). At this time, when the main CPU 31 determines that there is no stop button for which the operation is effective, the main CPU 31 ends the reel stop control process. On the other hand, when the main CPU 31 determines that there is a stop button whose operation is valid, the main CPU 31 proceeds to the process of step S103. Thereafter, the main CPU 31 repeats the processing from step S103 to step S111 until it is determined that there is no stop button for which the operation is valid.

  Next, the display combination search process will be described with reference to FIG. FIG. 43 is a diagram showing a flowchart of the display combination search process performed in the main control circuit 60 of the present embodiment.

  First, the main CPU 31 clears the display combination storing area (step S121).

  Next, the main CPU 31 designates the top address of the symbol storage area (step S122). Specifically, the main CPU 31 designates an address corresponding to the center line 8c as the head address when the gaming state is a gaming state other than the RB gaming state, and RB when the gaming state is the RB gaming state. The address corresponding to the middle special line 8f is designated as the head address.

  Next, the main CPU 31 designates the head address of the symbol combination table (see FIG. 27) (step S123). Specifically, the main CPU 31 designates an address corresponding to BB1 as the head address.

  Next, the main CPU 31 compares the symbol combination defined in the symbol combination table with the symbol combination stored in the symbol storage area (step S124).

  Next, as a result of the comparison in the process of step S124, the main CPU 31 determines whether or not the symbol combination specified in the symbol combination table matches the symbol combination stored in the symbol storage area ( Step S125). At this time, when the main CPU 31 determines that the symbol combination defined in the symbol combination table does not match the symbol combination stored in the symbol storage area, the main CPU 31 proceeds to the process of step S129, When it is determined that they match, data indicating the storage area type and the display combination is acquired from the symbol combination table (step S126).

  Next, the main CPU 31 stores the logical combination of the display combination storage area corresponding to the acquired storage area type and the data indicating the acquired display combination in the display combination storage area (step S127).

  Next, the main CPU 31 acquires the number of payouts from the symbol combination table and adds it to the payout number counter (step S128).

  When the main CPU 31 determines in the process of step S125 that the symbol combination specified in the symbol combination table does not match the symbol combination stored in the symbol storage area, or ends the process of step S128. Then, an address corresponding to the next combination in the symbol combination table is designated (step S129).

  Next, the main CPU 31 determines whether or not an end code is stored at the address designated in the process of step S129 (step S130). At this time, when the main CPU 31 determines that the end code is not stored, the main CPU 31 proceeds to the process of step S124. On the other hand, when determining that the end code is stored, the main CPU 31 then searches for all the effective lines, that is, whether or not the processes of steps S124 to S130 have been performed for all the effective lines. A determination is made (step S131).

  When the main CPU determines that all the effective lines have been searched in the process of step S131, the main CPU ends the display combination search process. On the other hand, when the main CPU determines that all the effective lines are not searched, the main CPU then designates an address corresponding to the next effective line in the symbol storage area (step S132), and the process proceeds to step S123.

  Next, the RT control process will be described with reference to FIG. FIG. 44 is a diagram showing a flowchart of the RT control process performed in the main control circuit 60 of the present embodiment.

  First, the main CPU 31 determines whether or not it is BB carryover (RT4 gaming state) (step S161). At this time, if the main CPU 31 determines that the BB is being carried over, it terminates the RT control process. On the other hand, when determining that the BB is not being carried over, the main CPU 31 determines whether or not the BB is being carried out (step S162). Specifically, it is determined whether any BB gaming state flag is on.

  When the main CPU 31 determines in step S162 that the BB is being performed, the main CPU 31 ends the RT control process. On the other hand, when determining that the BB is not in progress, the main CPU 31 refers to the RT transition table (see FIG. 24), and updates it when it is necessary to update the gaming state flag based on the display combination (step S163). ), The RT control process is terminated.

  Next, with reference to FIG. 45, the bonus end check process will be described. FIG. 45 is a flowchart of the bonus end check process performed in the main control circuit 60 of the present embodiment.

  First, the main CPU 31 determines whether or not BB is in progress (step S141). At this time, when the main CPU 31 determines that the BB is not in progress, the main CPU 31 turns off the SB gaming state flag (step S142) and ends the bonus end check process. On the other hand, when determining that the BB is in progress, the main CPU 31 determines whether or not the value of the bonus end number counter is “0” (step S143).

  When determining that the value of the bonus end number counter is “0”, the main CPU 31 performs a bonus end time process (step S144). Specifically, the BB gaming state flag and the RB gaming state flag that are on are turned off. Next, the main CPU 31 transmits a bonus end command (step S145), and ends the bonus end check process.

  On the other hand, when determining that the value of the bonus end number counter is not “0”, the main CPU 31 subtracts “1” from the value of the possible game number counter (step S146), and whether or not the display combination is a small combination Is determined (step S147). At this time, when the main CPU 31 determines that the display combination is not a small combination, the main CPU 31 proceeds to the process of step S149. On the other hand, when determining that the display combination is a small combination, the main CPU 31 subtracts “1” from the value of the winning possible number counter (step S148), and proceeds to the processing of step S149.

  Next, the main CPU 31 determines whether or not the value of the winning possible number counter or the value of the possible gaming number counter is “0” (step S149). At this time, when the main CPU 31 determines that neither the value of the winning possible number counter or the value of the possible gaming number counter is “0”, the main CPU 31 ends the bonus end check process. On the other hand, when the main CPU 31 determines that the value of the winning possible number counter or the value of the possible gaming number counter is “0”, the main CPU 31 then performs RB end time processing (step S150) and ends the bonus end check processing. . In the RB end process, a process such as turning off an RB gaming state flag that is turned on is performed.

  Next, with reference to FIG. 46, the bonus operation check process will be described. FIG. 46 is a view showing a flowchart of the bonus operation check process performed in the main control circuit 60 of the present embodiment.

  First, the main CPU 31 determines whether or not the display combination is BB (any one of BB1 to BB4) (step S171). At this time, when the main CPU 31 determines that the display combination is not BB, the main CPU 31 proceeds to the process of step S174. On the other hand, when the main CPU 31 determines that the display combination is BB, the main CPU 31 performs a bonus operation process (step S172). In this bonus operation time process, the bonus operation time table (FIG. 28) is referred to, the game state flag is turned on and a value is set in the bonus end number counter according to the game state to be operated. Next, the main CPU 31 turns off the RT4 gaming state flag, clears the carryover combination storage area (step S173), transmits a bonus start command (step S176), and ends the bonus operation check process. The bonus start command includes information indicating the type of bonus to be started.

  When the main CPU 31 determines in the process of step S171 that the display combination is not BB, the main CPU 31 then determines whether or not the display combination is SB (step S174). At this time, when the main CPU 31 determines that the display combination is not SB, the main CPU 31 proceeds to the process of step S177. On the other hand, when the main CPU 31 determines that the display combination is SB, it performs a bonus operation process (step S175). In this bonus operation time process, the bonus operation time table (FIG. 28) is referred to and the SB game state flag is turned on. Next, the main CPU 31 transmits a bonus start command (step S176), and ends the bonus operation check process.

  When the main CPU 31 determines in the process of step S174 that the display combination is not SB, it next determines whether or not the display combination is replay (step S177). At this time, when determining that the display combination is not replay, the main CPU 31 ends the bonus operation check process. On the other hand, when determining that the display combination is replay, the main CPU 31 copies the value of the insertion number counter to the automatic insertion number counter (step S178), and ends the bonus operation check process. When a value is set in the automatic insertion number counter, in the process of step S3 in the next game, the number of medals corresponding to the value is automatically inserted (the player's medal is not reduced).

  Next, communication data storage processing will be described with reference to FIG. FIG. 47 is a diagram showing a flowchart of the communication data storage process performed in the main control circuit 60 of the present embodiment. In addition, the illustrated P1 to P5 data indicate parameters of each command.

  The main CPU 31 stores the transmission command in the 0th byte of the communication temporary storage area (step S1291). The main CPU 31 stores the P1 data in the first byte of the communication temporary storage area allocated to the main RAM 33 (step S1292). The main CPU 31 stores the P2 data in the second byte of the communication temporary storage area (step S1293). The main CPU 31 stores the P3 data in the third byte of the communication temporary storage area (step S1294). The main CPU 31 stores the P4 data in the fourth byte of the communication temporary storage area (step S1295). The main CPU 31 stores the P5 data in the fifth byte of the temporary communication storage area (step S1296). The main CPU 31 stores the gaming state flag in the sixth byte of the temporary communication storage area (step S1297).

  Then, the main CPU 31 calculates the 0th to 6th bytes of data in the temporary communication storage area by XOR logic operation, and creates BCC data that is the main sum value (step S1298). Further, the main CPU 31 calculates the BCC data and the key code by the XOR logical operation, and creates the main key code added BCC data which is the main key code added sum value (step S1299).

  The main CPU 31 stores the main key code-added BCC data in the seventh byte of the temporary communication storage area (step S1300). As a result, in one packet consisting of 8-byte data, the main key code added BCC data is included in addition to the command.

  Subsequently, the main CPU 31 performs encrypted data creation processing described later (step S1301).

  Next, the main CPU 31 obtains the storage address of the communication data storage area from the communication data storage setting information (step S1302). Here, the main CPU 31 determines whether or not there is an empty communication data storage area (step S1303). When the main CPU 31 determines that there is no free space in the communication data storage area, the communication data storage process is terminated.

  When the main CPU 31 determines that there is an empty communication data storage area, the data stored in the communication temporary storage area is stored in the communication data storage area (step S1304). Further, the main CPU 31 updates the communication data storage setting information (step S1305), and ends the communication data storage process.

  Next, encrypted data creation processing will be described with reference to FIG. FIG. 48 is a diagram showing a flowchart of encrypted data creation processing executed by the main CPU 31 of the present embodiment.

  The main CPU 31 refers to the encryption information stored in the main ROM 32, and determines whether or not the encryption sequence for performing the encryption process is data replacement (step S1311). If the main CPU 31 does not determine that the data is to be replaced, the process proceeds to step S1325 described later.

  When the main CPU 31 determines that the data is to be replaced, it is determined whether or not the data replacement pattern is A (step S1312). When determining that the data replacement pattern is A, the main CPU 31 encrypts the transmission data in the temporary communication storage area with the data replacement pattern A shown in FIG. 15 (step S1313), and performs the processing of the main routine (see FIG. 47). Return.

  When the main CPU 31 does not determine that the data replacement pattern is A, the transmission data in the temporary communication storage area is encrypted with the data replacement pattern B (see FIG. 16) (step S1314), and the process returns to the main routine.

  In step S1311, when the main CPU 31 does not determine data replacement, the main CPU 31 determines whether or not the calculation pattern is A (step S1315). When determining that the calculation pattern is A, the main CPU 31 encrypts the transmission data in the temporary communication storage area with the calculation pattern A shown in FIG. 17 (step S1316), and returns to the processing of the main routine.

  When the main CPU 31 does not determine that the calculation pattern is A, the transmission data in the temporary communication storage area is encrypted with the calculation pattern B shown in FIG. 18 (step S1317), and the process returns to the main routine.

  Next, with reference to FIG. 49, an interrupt process by the control of the main CPU 31 will be described. FIG. 49 is a diagram showing a flowchart of an interrupt process under the control of the main CPU 31 performed by the main control circuit 60 of the present embodiment. The interrupt process under the control of the main CPU 31 is an interrupt process that occurs every predetermined period (1.1173 milliseconds in this embodiment).

  First, the main CPU 31 interrupts the program being executed before calling the interrupt process under the control of the main CPU 31, and saves the address indicating the interrupted position and the values of various registers in a predetermined area of the main RAM 33. (Step S181). This is because when the interrupt process under the control of the main CPU 31 ends, the address indicating the interrupted position of the saved program and the values of various registers are restored, and the program is continuously executed from the point of interruption. It is.

  Next, the main CPU 31 performs input port check processing (step S182). Specifically, the main CPU 31 checks a signal from each switch such as the maximum BET switch 13S.

  Next, the main CPU 31 performs a reel control process (step S183). Specifically, the main CPU 31 starts rotation of the reels 3L, 3C, and 3R and rotates them at a constant speed when there is a reel rotation start request in the reset interrupt process (see FIG. 38). Take control. Further, when the planned stop position is determined by determining the number of sliding frames in the reel stop control process (see FIG. 42), the main CPU 31 determines the value of the symbol counter of the corresponding reel to indicate the planned stop position. When the value becomes the same as the value, control is performed to stop the reel. For example, when the value indicating the planned stop position is “4”, the main CPU 31 performs control for stopping the corresponding reel when the value of the symbol counter becomes “4”.

  Next, the main CPU 31 performs communication data transmission processing to be described later (step S184). Further, the main CPU 31 performs a lamp drive control process (step S185). Next, the main CPU 31 refers to the value saved in the main RAM 33 in the process of step S181 and restores the register (step S186). When this process ends, the interrupt process under the control of the main CPU is ended, and the program interrupted by the occurrence of the interrupt process under the control of the main CPU is continuously executed.

  Next, communication data transmission processing will be described with reference to FIG. FIG. 50 is a flowchart of communication data transmission processing performed by the main control circuit 60 of the present embodiment. This communication data transmission process is mainly executed by the command transmission unit 31b of the main CPU 31.

  First, the main CPU 31 sets the address of the current communication data storage area based on the communication data storage setting information (step S1341). Then, the main CPU 31 determines whether or not communication data (transmission data) to be transmitted to the sub control circuit 70 is stored at the set address of the communication data storage area (step S1342).

  When the main CPU 31 determines that transmission data is not stored at the set address in the communication data storage area, it sets a no-operation command (step S1343) and performs the communication data storage process described above (step S1344). .

  After completion of the communication data storage process here, or when the main CPU 31 determines that transmission data is stored at the set address of the communication data storage area, the main CPU 31 transmits the main control circuit 60. It is determined whether or not there is an available port (step S1345). When the main CPU 31 determines that the transmission port of the main control circuit 60 is not empty, the main CPU 31 ends the communication data transmission process.

  When the main CPU 31 determines that there is an empty transmission port of the main control circuit 60, the number of data for one packet (8 in this embodiment) is set (step S1346). Then, the main CPU 31 sets the leading number of the packet transmission data setting output port (step S1347). Further, the main CPU 31 sets the data in the communication data storage area to the output port (step S1348).

  The main CPU 31 adds 1 to the address of the communication data storage area and updates it (step S1349). Next, the main CPU 31 adds 1 to the output port number and updates it (step S1350). Further, the main CPU 31 subtracts 1 from the data number counter (step S1351).

  Next, the main CPU 31 determines whether or not the data number counter is 0 (step S1352). If the main CPU 31 determines that the data number counter is not 0, it determines that data that has not yet been set in the output port remains in the communication data storage area, and again outputs the data in the communication data storage area to the output port. (Step 1348).

  If the main CPU 31 determines that the data number counter is 0, it determines that one packet of data has been stored in the output port, and sets a transmission activation request in the communication register port (step S1353). As a result, a packet including the command and the main key code-added BCC data is transmitted.

  The main CPU 31 sets the transmitted data in the communication data storage area (step S1354). Further, the main CPU 31 updates the communication data storage setting information, sets the address of the next communication data storage area (step S1355), and ends the communication data transmission process.

[Game machine management system]
Next, an error information history transmission system using the gaming machine 1 of the present embodiment will be described. The error information history transmission system is a system that stores various errors generated in the gaming machine 1 as error information, transmits the error information history to a remote server by using a mobile terminal, and analyzes the cause of the error. .

  As shown in FIG. 51, the error information history transmission system includes a gaming machine 1, a mobile communication terminal with a camera 400 (hereinafter referred to as “mobile terminal”) as a mobile terminal held by a staff member, and a data management server as a server. 500 and an analysis PC 600 as analysis means. In the example of FIG. 51, for convenience of explanation, one mobile terminal 400 is shown, but in reality, the data management server 500 can be accessed from many mobile terminals 400.

  For example, the data management server 500 manages not only error information but also information related to game records. The portable terminal 400 and the data management server 500 can exchange data with each other using, for example, TCP / IP as a communication protocol via the network NW. The network NW is constructed by, for example, the Internet, a dedicated communication line (for example, a CATV (Community Antenna Television) line), a mobile communication network (including a base station, etc.), a gateway, and the like. Note that the gaming machine 1 is not connected to the network NW.

  Note that the portable terminal 400, the data management server 500, and the analysis PC 600 are each provided with a control unit, a storage unit, a display unit, a communication unit, and the like, although not particularly illustrated. Further, the data management server 500 and the analysis PC 600 are preferably installed in an area 700 separated from the installation location of the gaming machine 1 such as a manufacturer of the gaming machine 1 or a system management company.

  The sub CPU 71 of the gaming machine 1 displays the two-dimensional code 300 on the liquid crystal display area 23 so that the staff (portable terminal 400) accesses the data management server 500 when providing the service by the error information history transmission system. Specifically, as shown in FIG. 53, the clerk displays the error information history in the liquid crystal display area 23 and selects, for example, a predetermined item such as a COM error alarm (COM ERR ALM) 23b which is a communication error alarm. As a result, the two-dimensional code 300 is displayed.

  The control unit of the portable terminal 400 reads the displayed two-dimensional code 300 with the camera 401 of the portable terminal 400, analyzes the two-dimensional code 300 with the dedicated software of the portable terminal 400, for example, the domain in the code, the communication error log, etc. And the data management server 500 is accessed according to the domain included in the two-dimensional code 300, and the information included in the two-dimensional code 300 is transmitted as output transmission data.

  On the other hand, the control unit of the data management server 500 stores the communication error information included in the received transmission data in the storage unit.

  The control unit of the data management server 500 accumulates communication error information included in the output transmission data in an error information database DB (database) (not shown), and transmits the communication error information to the analysis PC 600. In addition, the control unit of the data management server 500 generates display data (for example, a web page) that allows the mobile terminal 400 to display the error content indicated by the received communication error information and the like. To reply (in the figure, one-dot chain line arrow). And the control part of the portable terminal 400 displays the screen 402 which shows an error content etc. on a display part based on the received display data. The clerk can confirm the error content from the screen 402.

  Further, the analysis PC 600 that has received the communication error information analyzes the cause of the communication error based on the communication error information and various information stored in the error information database DB. The cause of the communication error analyzed by the analysis PC 600 is that the game machine 1 manufacturer or system management company where the analysis PC 600 is installed improves the program or structure of the game machine 1 or installs the game machine 1. It will be used as appropriate, such as improved management in the halls.

  Next, the gaming machine 1 when the staff uses the error information history transmission service will be described. The sub CPU 71 of the gaming machine 1 employs two types of operation methods, a normal operation by a staff member and a simple operation, in order to display the error information history shown in FIG. 53 on the liquid crystal display device 5. When executing the normal operation, the clerk turns the door key 2 to the right to release the lock mechanism of the front door 1b, turns on the setting key to turn on the setting key switch 20S, and enters the liquid crystal display area 23. The menu screen shown in FIG. 53 is displayed.

  Then, when the clerk operates the operation key and selects the “error information history” item 23 a, the error information history screen shown in FIG. 53 is displayed in the liquid crystal display area 23. On the other hand, when executing a simple operation, the attendant resets the error by rotating the door key 2 counterclockwise when an error occurs or not playing, and holds the state for a predetermined time, for example, 5 seconds or more. As a result, the error information history screen shown in FIG. 53 is displayed in the liquid crystal display area 23.

  When the sub CPU 71 detects an operation of selecting the “error information history” item 23a using the selection button 24 and the determination button 25, the sub CPU 71 displays the error information history in the liquid crystal display area 23 as shown in FIG. . Further, when the sub CPU 71 detects an operation of selecting the “COM error alarm” item 23b by using the selection button 24 and the determination button 25, the sub CPU 71 generates transmission information based on the error information history, and FIG. As shown, the two-dimensional code 300 based on the transmission information is displayed on the right side of the “COM error alarm” item 23b.

  The sub CPU 71 does not display a COM error alarm when a communication error occurs once, and only when a communication error occurs again within 30 minutes after the first communication error occurs. Is displayed. For this reason, the sub CPU 71 includes a COM error timer for measuring an interval at which a communication error occurs. The COM error timer performs measurement based on the time measurement of the built-in RTC 70a or the time measurement by the function provided by the OS.

  In the present embodiment, the sub CPU 71 generates the two-dimensional code 300 only when a communication error occurs. For this reason, if a communication error occurs accidentally during, for example, a normal game, the data that is loaded as error information on the two-dimensional code 300 is communicated during normal processing as shown in FIG. An error occurs, and normal processing is executed again immediately after that. Here, the numerical values in FIG. 56 are the number of data characters, one character data indicates a command type, and two character data indicates a parameter for the immediately preceding command.

  In addition, when a communication error occurs due to the goto action and the setting is changed in the gaming machine 1, the data placed as error information in the two-dimensional code 300 is a communication error as shown in FIG. 56 (b). The settings are changed immediately after the occurrence. Furthermore, when a communication error occurs and continuous transmission is performed by lever operation, the data that is placed as error information on the two-dimensional code 300 is the command type immediately after the occurrence of the communication error, as shown in FIG. A certain lever operation and a parameterized winning combination are continuous.

  FIG. 57 shows that when the data in the sub-RAM 73-1 of the sub-control circuit 70 is destroyed, the sub-control circuit 70 has a thumb abnormality in the RAM data over almost the entire liquid crystal display area 23 of the gaming machine 1. An example of notifying that it cannot continue is shown.

  For example, when some or all of the data related to the command, effect data information, game state information, internal winning combination information, display combination information, various counters and various flags received from the main control circuit 60 are deleted, A notification that “RAM data abnormal game cannot be continued. Please change the setting” is given to the portion of the liquid crystal display area 23 of the gaming machine 1 excluding the symbol display areas 4L, 4C, 4R. By performing such notification, it can be expected to suppress goto action.

[Sub CPU]
Next, the power-on process of the sub CPU 71 will be described with reference to FIG. FIG. 58 is a flowchart of the power-on process of the sub CPU 71.

  The power-on process of the sub CPU 71 is an initialization process in the OS. When the power of the sub CPU 71 is turned on, a sub CPU initial setting process is performed to initialize the CPU and internal devices and peripheral ICs. It is executed (step S910).

  Next, the sub CPU 71 executes mother task activation request processing, which will be described later with reference to FIG. 59, for various task activation requests (step S911). Then, the sub CPU 71 executes a sub RAM management process described later based on FIG.

  Further, a power interruption detection circuit is provided in the sub control circuit 70 (not shown). When the power interruption detection circuit detects a voltage drop, for example, a voltage drop to 4.5 V, it outputs a power interruption detection signal. The sub CPU 71 executes a power interruption interrupt process shown in FIG. 60 by an interrupt input from the external interrupt port (NMI). In the power interruption process, a backup creation process (step S950) shown in FIG. 74 described later is executed.

  Unlike the main control, the sub CPU 71 does not calculate the sum value in the power interruption processing. The calculation of the sum value by the sub CPU 71 is performed every time a valid command is received, when the effect mode is changed, or the like.

  The mother task request process shown in FIG. 59 is a process of requesting the OS to start a task necessary for the function of the gaming machine 1. First, the sub CPU 71 makes an activation request for the effect registration process (step S1001). Next, as an activation request for subtasks, an accessory control task activation request (step S1002), a lamp control task activation request (step S1003), a sound control task activation request (step S1004), a main board communication task activation request (step S1005), An animation task activation request (step S1006) and then an RTC control task activation request (step S1007) are made.

  Next, the operation of the error information history transmission system described above will be described with reference to the flowcharts shown in FIGS. First, the main board communication reception interrupt process in the sub control circuit 70 will be described with reference to FIG. FIG. 61 is a flowchart of the main board communication reception interrupt process in the sub control circuit 70 of the present embodiment. The main board communication reception interrupt process program in the sub control circuit 70 is executed by the sub CPU 71 as an interrupt process when transmission data is transmitted from the main control circuit 60 to the sub control circuit 70.

  The sub CPU 71 acquires received data from the received data register of the I / O port interposed between the main CPU 31 (step S800). In addition, the sub CPU 71 acquires reception status data from the reception status register of the I / O port (step S801). Further, the sub CPU 71 registers the reception data and the reception status data related to the reception data in each queue buffer (step S802), and ends the main board communication reception interrupt process.

  The sub CPU 71 processes the received data of 1 byte by executing the main board communication reception interrupt process of steps S800 to S802 described above once. In the present embodiment, one command is composed of 8-byte data. Therefore, the sub CPU 71 completes processing of one command by executing serial data communication by processing steps S800 to S802 continuously eight times.

[Production registration process]
Next, with reference to the flowchart shown in FIG. 62, the operation | movement regarding the game of the sub control circuit 70 is demonstrated.

  With reference to FIG. 62, the effect registration process will be described. FIG. 62 is a diagram showing a flowchart of the effect registration process of the present embodiment.

  First, the sub CPU 71 sets a period of 4 ms for the effect registration process (step S310). Next, the sub CPU 71 takes out a message from the message queue (step S311). Next, the sub CPU 71 determines whether or not there is a message in the message queue (step S312). At this time, when the sub CPU 71 determines that there is no message in the message queue, the sub CPU 71 proceeds to the process of step S316.

  On the other hand, when the sub CPU 71 determines in step S312 that there is a message in the message queue, the sub CPU 71 copies the game information from the message (step S313), and then performs effect content determination processing (step S314). In the effect content determination process, the effect content according to various commands transmitted from the main CPU 31 is determined, and effect data corresponding to, for example, a gaming state or an operation state specified by the received command is registered. Subsequently, the sub CPU 71 performs a backup creation process for creating backup data from the sub RAM 73-1 to the SRAM 73-2 (step S315).

  Next, the sub CPU 71 registers animation data (step S316). Specifically, the sub CPU 71 registers animation data based on the effect data registered in the effect content determination process. Thereby, an image is displayed on the liquid crystal display device 5. That is, the sub CPU 71 transmits an image display command to the GPU 74 based on the effect data determined in the effect content determination process.

  The GPU 74 selects appropriate image data from the image data expanded in the VRAM 75 based on the received image display command, determines the display position and size of the image data, and provides the image data in the VRAM 75. Is stored in one of the specified frame buffers.

  The GPU 74 performs a bank switching process for exchanging the display image data area and the write image data area in the frame buffer area at predetermined intervals (1/30 seconds). In the bank switching process, the GPU 74 outputs the image data written in the write image data area to the liquid crystal display device 5, replaces the display image data area with the write image data area, and sets the image data to be displayed next. Write.

  Next, the sub CPU 71 registers sound data (step S317). Specifically, the sub CPU 71 registers sound data based on the effect data registered in the effect content determination process. Thereby, a sound is output from the speakers 21L and 21R. Next, the sub CPU 71 registers LED data (step S318).

  Specifically, the sub CPU 71 registers LED data based on the effect data registered in the effect content determination process. As a result, the various operation panels 101 to 103 and the display panel unit 110 are turned on or off. When this process ends, the sub CPU 71 waits for a period of 4 ms (step S319), and returns to the process of step S311.

  Next, with reference to FIG. 63, an effect content determination process in the flowchart of the effect registration process performed by the sub CPU shown in FIG. 62 will be described. FIG. 63 is a flowchart of the effect content determination process. The following processing is processing performed after the command decryption means 71a of the sub CPU 71 decrypts various commands that the main control circuit 60 encrypts and transmits.

  First, the sub CPU 71 determines whether or not a start command has been received (step S351). When determining that the start command has been received, the sub CPU 71 performs a start command reception process (step S352), registers the start effect data (step S353), and ends the effect content determination process.

  If the sub CPU 71 determines in step S351 that a start command has not been received, the sub CPU 71 then determines whether or not a reel stop command has been received (step S354).

  In the process of step S354, when the sub CPU 71 determines that a reel stop command has been received, the sub CPU 71 performs a reel stop command reception process (step S355), and displays stop effect data according to the type of the operation stop button and the like. Registration is performed (step S356), and the effect content determination process is terminated.

  When the sub CPU 71 determines in the process of step S354 that the reel stop command has not been received, the sub CPU 71 then determines whether or not a display command has been received (step S357). When the sub CPU 71 determines that a display command has been received, the sub CPU 71 performs a display command reception process (step S358), and ends the effect content determination process.

  If the sub CPU 71 determines in step S357 that it has not received a display command, it then determines whether or not a BET command has been received (step S359). When determining that the BET command has been received, the sub CPU 71 registers the effect data for the BET according to the number of inserted sheets (step S360), and ends the effect content determination process.

  If the sub CPU 71 determines in step S359 that the BET command has not been received, the sub CPU 71 then determines whether or not a bonus start command has been received (step S361). When determining that the bonus start command has been received, the sub CPU 71 registers the bonus start time effect data (step S362), and ends the effect content determination process.

  If the sub CPU 71 determines in step S361 that a bonus start command has not been received, the sub CPU 71 then determines whether or not a bonus end command has been received (step S363). At this time, when determining that the bonus end command has not been received, the sub CPU 71 ends the effect content determination process. On the other hand, when the sub CPU 71 determines that the bonus end command has been received, the sub CPU 71 performs a bonus end command reception process (step S364), registers bonus end time effect data (step S365), and ends the effect content determination process. Let

[Main board communication processing]
Next, the main board communication processing of the sub CPU 71 will be described with reference to FIG. FIG. 64 is a diagram showing a flowchart of main board communication processing of the sub CPU 71 of this embodiment.

  In response to the scheduling function of the OS, the sub CPU 71 sets a cycle so that the main board communication processing program of the sub CPU 71 is executed at a cycle of 2 ms (step S808). Thereby, this task is repeated at a cycle of 2 ms including the processing time. For this reason, the sub CPU 71 waits for a cycle of 2 ms (step S809), and waits for the remaining time of 2 ms when the flowchart is repeated.

  Note that the cycle of this task process is not limited to 2 ms, and may be executed between 2 ms and 4 ms. In addition, the main board communication processing program of the sub CPU 71 is not limited to one executed every predetermined time. For example, when a predetermined condition is satisfied regardless of the time interval, without setting the cycle and waiting for the cycle. It may be executed.

  Next, the sub CPU 71 acquires the reception data from the queue in which the reception data is registered in step S802 (step S810). The sub CPU 71 determines whether there is received data in the queue (step S811). If the sub CPU 71 determines that there is no received data in the queue, it acquires the received data from the queue again (step S810).

  When the sub CPU 71 determines that there is received data in the queue, it determines whether a physical layer error has occurred in the received data (step S812). If the sub CPU 71 determines that no physical layer error has occurred in the received data, the sub CPU 71 performs a decoding process on the received data, which will be described later (step S813), and checks and acquires the numerical range of the received command (step S813). S814). In the present embodiment, the numerical range of the received command is 01H to 10H as shown in FIG. Then, the sub CPU 71 determines whether or not the numerical value of the received command is within an appropriate range (step S815).

  When the sub CPU 71 determines that the numerical value of the command is within the proper range, the BCC check process is performed on the received data (step S816).

  Then, the sub CPU 71 determines whether or not the result of the BCC check process is normal (step S817). When the sub CPU 71 determines that the result of the BCC check process is normal, the command type is extracted (step S818).

  Then, the sub CPU 71 determines whether or not the extracted command is a no-operation command (step S819). If the sub CPU 71 determines that the extracted command is a no-operation command, the sub CPU 71 acquires the received data from the queue again (step S810).

  If the sub CPU 71 determines that the extracted command is not a no-operation command, the sub CPU 71 executes a received data log saving process to be described later (step S820). Further, the sub CPU 71 executes a main board reception command check process to be described later (step S821).

  Then, the sub CPU 71 determines whether or not the command received this time is different from the command received last time (immediately before) (step S822). If the sub CPU 71 determines that the command received this time is not different from the command received immediately before, that is, it is the same, it waits for a period of 2 ms (step S809) and acquires the received data from the queue again (step S809). S810).

  If the sub CPU 71 determines that the command received this time is different from the command received immediately before, the sub CPU 71 registers the command received this time in the message queue (step S823). Then, the sub CPU 71 performs a sum check on the game data sum value area 73b-1 (step S824).

  Further, the sub CPU 71 determines whether or not the game data is normal as a result of the sum check (step S825). If the sub CPU 71 determines that the game data is normal, the sub CPU 71 waits for a period of 2 ms (step S809), and acquires the received data from the queue again (step S810).

  When the sub CPU 71 determines that the game data is abnormal, the error information registration unit 71e registers the occurrence of the data destruction error in the error information history storage area 73d-1 (step S826). Then, the sub CPU 71 waits for a period of 2 ms (step S809), and obtains received data from the queue again (step S810).

  The sub CPU 71 determines that a physical layer error has occurred in the received data in step S812, determines that the command is not within the proper range in step S815, or determines that the result of the BCC check process is normal in step S817. If not, it is determined that a communication error has occurred, and a COM error check process described later is executed (step S827). Then, the sub CPU 71 waits for a period of 2 ms (step S809), and obtains received data from the queue again (step S810). If the sub CPU 71 determines in step S815 that the command is not within the proper range, or if the sub CPU 71 determines that the result of the BCC check process is not normal in step S817, the decrypted data includes an error factor. It would have been.

  Next, the received data decoding process in step S813 will be described with reference to FIG. FIG. 65 is a diagram showing a flowchart of the received data decoding process performed by the sub-control circuit 70 of the present embodiment.

  The sub CPU 71 refers to the decoding information area 72j (see FIG. 8) stored in the sub ROM 72, and determines whether or not the decoding sequence for performing the decoding process is data exchange (step S1321). If the sub CPU 71 does not determine that the data is to be replaced, the process proceeds to step S1325 described later.

  When the sub CPU 71 determines that the data is to be replaced, it is determined whether or not the data replacement pattern is A (step S1322). When determining that the data replacement pattern is A, the sub CPU 71 decodes the transmission data in the temporary communication storage area with the data replacement pattern A shown in FIG. 15 (step S1323), and ends the received data decoding process.

  If the sub-CPU 71 does not determine that the data replacement pattern is A, the sub-CPU 71 decodes the transmission data in the temporary communication storage area with the data replacement pattern B (see FIG. 16) (step S1324), and ends the received data decoding process. .

  In step S1321, if the sub CPU 71 does not determine that the data is to be replaced, the sub CPU 71 determines whether or not the calculation pattern is A (step S1325). When the sub CPU 71 determines that the calculation pattern is A, the transmission data in the temporary communication storage area is decoded by the calculation pattern A shown in FIG. 17 (step S1326), and the reception data decoding process is terminated.

  When the sub CPU 71 does not determine that the calculation pattern is A, the sub CPU 71 decodes the transmission data in the temporary communication storage area with the calculation pattern B shown in FIG. 18 (step S1327), and ends the reception data decoding process.

  Next, the main board reception data BCC check process in step S816 will be described with reference to FIG. FIG. 66 is a diagram showing a flowchart of the main board reception data BCC check process performed by the sub control circuit 70 of the present embodiment.

  The sub sum value calculating means 71j of the sub CPU 71 calculates BCC data as the sub sum value from the received data of the command (step S900). In the present embodiment, the sub-sum value calculating means 71j calculates BCC data by calculating the 0th to 6th bytes of the received data by XOR logic operation. Next, the sub CPU 71 acquires main key code-added BCC data from the seventh byte of the received data (step S901).

  Then, the key code acquisition unit 71i of the sub CPU 71 determines whether or not the current command reception is the first after the gaming machine 1 is started (step S902). This determination is based on whether or not the post-startup reception flag provided in the sub control circuit 70 has been received. When the key code acquisition means 71i determines that the current command reception is the first one after the game machine 1 is activated, it determines that it is necessary to create a key code, and is provided in the sub-control circuit 70. The activation flag is set to “received” (step S903).

  Further, the key code acquisition means 71i calculates the BCC data calculated by the sub sum value calculation means 71j and the received main key code added BCC data by XOR logic operation to create a key code (step S904). Since the sum value determining means 71m is immediately after the key code is set, BCC normal is set (step S908), and the main board received data BCC check process is terminated.

  On the other hand, when the key code acquisition means 71i determines that the current command reception is not the first one after the game machine 1 is activated, it determines that it is not necessary to create a key code. Then, the sub key code added sum value calculating means 71k of the sub CPU 71 calculates the BCC data calculated by the sub sum value calculating means 71j and the already obtained key code by the XOR logic operation, and the sub key code added sum value is calculated. Sub key code added BCC data, which is a value, is calculated (step S905).

  Then, the sum value determining means 71m of the sub CPU 71 compares the main key code added BCC data and the sub key code added BCC data to determine whether or not the BCC is normal (step S906). When the sum value determining means 71m determines that the BCC is normal, BCC normal is set (step S908), and the main board received data BCC check process is terminated. If the sum value determining means 71m determines that the BCC is not normal, the BCC abnormality is set (step S907), and the main board received data BCC check process is terminated.

  Next, the received data log saving process in step S820 will be described with reference to FIG. FIG. 67 is a diagram showing a flowchart of main board communication reception data log storage processing performed in the sub control circuit 70 of the present embodiment. The main board communication reception data log storage process is mainly executed by the reception data log storage means 71f of the sub CPU 71.

  When the main board communication received data log saving process is executed, the sub CPU 71 executes a main board communication received data log temporary area saving process described later (step S830). The main board communication reception data log temporary area saving process uses the communication log collection ring buffer area 73e-1 shown in FIG. 13 and saves all communication logs regardless of whether or not an error has occurred. ing.

  Subsequently, the sub CPU 71 executes main board communication error history data storage processing to be described later (step S831). The main board communication error history data storage process uses the communication error storage area shown in FIG. 14 and is a process for storing a related communication log when a communication error occurs. Thereafter, the sub CPU 71 ends the main board communication reception data log saving process.

  Next, with reference to FIG. 68, the main board communication received data log temporary area saving process in step S830 will be described. FIG. 68 is a diagram showing a flowchart of main board communication reception data log temporary area storage processing performed by the sub-control circuit 70 of the present embodiment.

  When the main board communication reception data log temporary area saving process is executed, the sub CPU 71 acquires the communication log data buffer index of the communication log collection ring buffer area 73e-1 (step S840). The number of buffers here is set as appropriate.

  Then, the sub CPU 71 calculates the communication log data buffer storage position of the communication log collection ring buffer area 73e-1 (step S841). Here, the sub CPU 71 calculates the storage position in the communication log collection ring buffer area 73e-1 from the value of the buffer index.

  Further, the sub CPU 71 stores the received data in the communication log collection ring buffer area 73e-1 (step S842). In the present embodiment, as shown in FIG. 13, a set of numerical values in which a command and a parameter corresponding to each command are consecutive is stored in a maximum of 256 sets. Then, the sub CPU 71 updates the communication log data buffer index (step S843). Here, the sub CPU 71 adds one buffer index storing the received data.

  Then, the sub CPU 71 determines whether or not the value of the buffer index is an upper limit value (step S844). If the sub CPU 71 determines that the value of the buffer index is the upper limit value, the sub CPU 71 returns the communication log data buffer index to the first one (step S845), and causes this buffer to function as a ring buffer. Thereafter, the sub CPU 71 ends the main board communication reception data log temporary area saving process. If the sub CPU 71 determines that the value of the buffer index is not the upper limit value, the sub-CPU 71 ends the main board communication reception data log temporary area saving process as it is.

  Next, the main board communication error history data storage processing in step S831 will be described with reference to FIG. FIG. 69 is a diagram showing a flowchart of main board communication error history data storage processing performed in the sub-control circuit 70 of the present embodiment.

  When the main board communication error history data storage process is executed, the sub CPU 71 acquires the storage buffer selection index of the communication error storage buffer area 73f-1 (step S850). Then, the sub CPU 71 selects a communication error storage buffer based on the storage buffer selection index (step S851).

  Here, the sub CPU 71 determines whether or not a communication error (COM error) has occurred (step S852). If the sub CPU 71 determines that a COM error has occurred, the received data log storage means 71f stores a communication log related to the communication error in the communication error storage buffer area 73f-1 selected in step S851 (step S851). S853). Then, the sub CPU 71 updates the selected buffer index (step S854). Thereafter, the sub CPU 71 ends the main board communication error history data storage process.

  If the sub CPU 71 determines that no COM error has occurred, the sub CPU 71 acquires the selected buffer index (step S855). Then, the sub CPU 71 determines whether or not reception data is being collected (step S856). If the sub CPU 71 determines that the received data is not being collected, the main CPU communication error history data storage process is terminated.

  If the sub CPU 71 determines that the received data is being collected, the sub CPU 71 determines whether or not the value of the buffer index is the upper limit value (step S857). In this embodiment, the value of the buffer index is 0 to 255, and the upper limit value is 255. When determining that the buffer index value is not the upper limit value, the sub CPU 71 stores the received data in the communication error storage buffer selected in step S851 (step S858). Then, the sub CPU 71 updates the selected buffer index (step S859). Thereafter, the sub CPU 71 ends the main board communication error history data storage process.

  If the sub CPU 71 determines that the buffer index value is the upper limit value, the sub CPU 71 obtains a storage buffer selection index (step S860). Then, the sub CPU 71 determines whether or not the value of the storage buffer selection index is an upper limit value (step S861). In the present embodiment, the upper limit value of the storage buffer selection index is 1024.

  When the sub CPU 71 determines that the value of the storage buffer selection index is not the upper limit value (step S861), the sub CPU 71 updates the storage buffer selection index (step S862). Here, the sub CPU 71 adds one storage buffer selection index. Thereafter, the sub CPU 71 ends the main board communication error history data storage process. When the sub CPU 71 determines that the value of the buffer selection index is the upper limit value (step S861), the main board communication error history data storage process is terminated.

  Next, the main board reception command check process in step S820 will be described with reference to FIG. FIG. 70 is a diagram showing a flowchart of main board reception command check processing performed by the sub control circuit 70 of the present embodiment.

  When the main board reception command check process is executed, the sub CPU 71 obtains reception data (step S870). Then, the sub CPU 71 sets a received command check table (step S871). Further, the sub CPU 71 acquires the previous (preceding time) received data (step S872).

  Then, the sub CPU 71 sets a command check counter (step S873). Further, the sub CPU 71 acquires confirmation data from the reception protocol confirmation data table (step S874). That is, here, a table of received commands and previous received commands shown in FIG. 55 is acquired.

Next, the sub CPU 71 checks the table of the received command acquired in step S874 and the previous received command, and determines whether or not the received commands are in an abnormal order (step S875). For example, if the received command shown in 03H of Data is “BET”, if the previous received command is a demo display, BET, payout end, bonus start or error, it is determined that the procedure is in normal order.

  If the sub CPU 71 determines in step S875 that the received commands are not in an abnormal order, that is, in a normal order, the sub CPU 71 ends the received command check process.

When the sub CPU 71 determines in step S875 that the received commands are in an abnormal order, for example, in the table shown in FIG. 55, if the received command shown in Data 07H is “display”, the previous received command is In the case of the second stop instead of the all-cylinder stop state, it is determined that the procedure is not performed in the normal game, and the received command check table is updated (step S876). Then, the sub CPU 71 subtracts the command check counter (step S877).

  Subsequent to step S877, the sub CPU 71 determines whether or not the command check is completed (step S878). Here, for example, the sub CPU 71 determines that the command check has been completed when the command check counter is equal to or less than a threshold value such as 0.

  If the sub CPU 71 determines in step S878 that the command check has not ended, the sub CPU 71 obtains confirmation data from the reception protocol confirmation data table again (step S874).

  If the sub CPU 71 determines in step S878 that the command check has ended, the error information registration unit 71e registers the occurrence of an abnormal procedure error (sequence error) in the error information history storage area 73d (step S879). Thereafter, the sub CPU 71 ends the received command check process.

  Next, the COM error check process in step S826 will be described with reference to FIG. FIG. 71 is a diagram showing a flowchart of the COM error check process performed in the sub control circuit 70 of the present embodiment.

  When the COM error check process is executed, the sub CPU 71 executes a received data log storage process (step S880). The procedure of the received data log saving process is as shown in the flowchart of the main board communication received data log saving process shown in FIG. In this case, it is determined in step S852 shown in FIG. 69 that a COM error has occurred, and the received data log storage unit 71f stores a communication log related to the communication error in the communication error storage buffer area 73f-1 (step S852). S853).

  Then, the sub CPU 71 determines whether or not the COM error timer is being counted (step S881). If the sub CPU 71 determines that the COM error timer is counting, it determines whether the COM error timer is within 30 minutes (step S882).

  If the sub CPU 71 determines that the COM error timer is within 30 minutes, the error information registration unit 71e registers the occurrence of a communication error (COM error) in the error information history storage area 73d-1 (step S883). Then, the sub CPU 71 sets the count stop of the COM error timer (step S884), and ends the COM error check process.

  If the sub CPU 71 determines that the COM error timer is not being counted, or if the COM error timer is determined not to be within 30 minutes, the sub CPU 71 sets the count start of the COM error timer (step S885), and the COM error End the check process.

  As described above, according to the gaming machine 1 of the present embodiment, the key code is generated immediately after the gaming machine 1 is powered on or reset. ing. For this reason, since the key code is created by turning on the power of the gaming machine at the start of business, the key code is changed once a day. Therefore, unlike the conventional case where the command transmitted from the main control circuit to the sub-control circuit is the same for each title, this kind of goto action can be suppressed.

  Further, according to the gaming machine 1 of the present embodiment, the key code acquisition unit 71h acquires a key code by performing an XOR logical operation on the command and the main key code added sum value. For this reason, there is no need to send the key code created by the main control circuit 60 directly to the sub-control circuit 70, so that communication data is extracted from the communication cable between the main control circuit 60 and the sub-control circuit 70 by a go-to action. Even if there is a key code, the key code is not extracted and security can be improved.

  Further, according to the gaming machine 1 of the present embodiment, since the XOR logic operation is used when calculating the sum value and the key code, the security can be further improved as compared with the case of simple addition. it can.

  The gaming machine management system according to the present embodiment also includes an analysis PC 600 that acquires error information from the two-dimensional code 300 received by the data management server 500 and analyzes the cause of the error based on the error information. Yes.

  Therefore, in the gaming machine 1 as in the prior art, it is not limited to simply specifying the content of the communication error, but the cause of the error can be analyzed and specified from the error information using the separately installed analysis PC 600. The cause of the obtained error can be used for the subsequent improvement of the gaming machine 1 or the like.

  Further, in the gaming machine 1 of the present embodiment, only when the occurrence of a communication error is detected by the sub CPU 71, the communication error information related to the communication error is converted into the two-dimensional code 300. Control can be simplified compared with the case of creating.

  Further, in the gaming machine 1 of the present embodiment, the error information history can be displayed on the liquid crystal display device 5 by operating the door key 2, so that the clerk displays the error information history without operating the setting key of the gaming machine 1. It becomes possible to confirm. For this reason, since the clerk can display the error information history of the gaming machine 1 even during business hours, the cause of the error can be more effectively promoted.

  Moreover, in the gaming machine 1 of the present embodiment, the attendant displays the error information history by rotating the door key 2 in the counterclockwise direction and holding the state where the error of the gaming machine 1 is reset for a certain period of time. It has become. For this reason, if it is a clerk who has the door key 2, the error information history can be displayed easily, and usually the clerk who has the door key 2 is more than the clerk who has the setting key, thereby improving convenience. be able to.

  Further, in the gaming machine 1 of the present embodiment, when the occurrence of a communication error is detected, the sub CPU 71 uses the sub RAM 73 as error information that indicates that a communication error has occurred, its occurrence time, and its release time. -1 is sequentially stored.

  Further, the sub CPU 71 creates an error information history from the stored error information, and causes the liquid crystal display device 5 to display the error information history when there is an information disclosure request by operating the door key 2.

  For this reason, it is possible to confirm the unauthorized release of the communication error notification in the gaming machine 1 and to confirm the occurrence time and the release time of the communication error notification later.

  Further, in the gaming machine 1 of the present embodiment, the sub CPU 71 detects that the procedure detecting means 71c detects a procedure that cannot occur in a normal game, that is, that the game has progressed in an abnormal procedure. The occurrence of an abnormal procedure and the procedure missed in the normal procedure are sequentially stored in the sub-RAM 73-1 as error information.

  Further, the sub CPU 71 creates an error information history from the stored error information, and causes the liquid crystal display device 5 to display the error information history when there is an information disclosure request by operating the door key 2.

  For example, FIG. 53 shows an example of the error information history in the liquid crystal display area 23. For example, no. In the error content “BLS123PE” shown in FIG. 7, the procedure of “L” and “S” indicating the start of rotation of the reel by the operation of the lever is usually followed by the procedure of “B” indicating insertion of a medal or the like, reel 1 The game ends after the procedure “1” indicating the stop of the reel 2, the procedure “2” indicating the stop of the reel 2, the procedure “3” indicating the stop of the reel 3, and the procedure “P” of the payment.

  However, the numeral “1” is circled to indicate that the procedure for stopping the reel 1 has been missed. Therefore, compared to the case where an abnormal procedure occurs as in the past, the procedure returns to the demo screen, the procedure that could not occur in normal games occurred, the number of steps that were missed, the number of occurrences, the presence or absence of continuous occurrence, etc. Since it can be confirmed, the occurrence of goto can be one of the judgment materials. In addition to enclosing a circle, the procedure that has been missed can be clearly expressed by distinguishing it by the color of the character itself, making the font different, or making the character line thicker.

  Further, in the gaming machine 1 according to the present embodiment, the sub CPU 71-1 uses the sub RAM 73-1 as error information to indicate that data corruption has occurred when the data corruption detection means 71d detects data corruption in the sub RAM 73-1. Are sequentially stored (step S825). Further, the sub CPU 71 reads the error information history from the error information history storage area 73 d-1 and displays it on the liquid crystal display device 5 when there is an information disclosure request by operating the door key 2.

  For this reason, according to this gaming machine 1, it becomes possible to detect the data destruction of the sub RAM 73-1 during the game, and thus it is possible to suppress the occurrence of the goto by immediately informing the error against the data destruction.

  As an error notification, for example, as shown in FIG. 57, when the data in the sub RAM 73-1 of the sub control circuit 70 is destroyed, a fatal error is detected on almost the entire surface of the liquid crystal display area 23 of the gaming machine 1. This indicates that the game cannot be continued because of an abnormality in the RAM data. Thereby, the RAM destruction action by a goto action can be suppressed. Such notification is canceled by a setting change such as power-off.

  In the gaming machine of the present embodiment described above, the case where the power of the gaming machine 1 is turned on or a reset operation is performed as a condition for creating a key code has been described. However, the gaming machine according to the present invention is not limited to this. For example, a predetermined time may be set by a timer, or other conditions may be used.

  Further, in the gaming machine of the present embodiment described above, the case where the XOR logic operation is used when calculating the sum value and the key code has been described. However, the gaming machine according to the present invention is not limited to this, and simple addition may be used.

  Further, in the gaming machine of the present embodiment described above, the case where the gaming machine 1 is a pachislot machine has been described. However, the gaming machine according to the present invention is not limited to this, and can be applied to, for example, a pachinko machine having a symbol variation display device as described later.

  Further, in the gaming machine of the present embodiment described above, the two-dimensional code 300 has been described as including only communication error history data. However, the gaming machine according to the present invention is not limited to this, and may include, for example, an error information history or a player's game record.

  As described above, the gaming machine according to the present embodiment can check the date and content of the occurrence of an error when a communication error occurs between the sub-control circuit and the scaler device. Useful for the machine.

  In the mother task flowchart shown in FIG. 59, when the main board communication task start request is issued from the OS in response to the main board communication task start request (step S1005), the main board communication task is shown in FIG. It is executed according to the flowchart.

  The RTC control task is executed along the flow chat shown in FIG. First, the sub CPU 71 sets a period of 100 ms for OS time management (step S1011). Next, the sub CPU 71 reads the date / time from the external RTC 70c (step S1012), and sets the read date / time of the external RTC 70c as an initial value of the internal RTC 70a (step S1013).

  Next, the sub CPU 71 reads the status information from the external RTC 70c (step S1014), determines whether or not the status information has been read normally (step S1015). It is determined whether there is an abnormality (step S1016). If there is no power supply abnormality, it is determined whether there is an oscillation abnormality (step S1017). If there is no oscillation abnormality, a reset signal is detected. If the reset signal is not detected, the date / time is read from the external RTC 70c (step S1019).

  When reading this date and time, the sub CPU 71 determines whether or not there is an abnormality in the date and time range (step S1020). For example, when the year, month, day, or time value exceeds two digits, it is determined that the date / time range is abnormal. When the sub CPU 71 determines that there is an abnormality in the date and time range, as shown in the table of FIG. 12, the error information (RTC TIM) of the error information history storage area 73d-1 of the sub RAM 73-1 is set as an RTC time abnormality. (Step S1021).

  On the other hand, if the sub CPU 71 determines in step S1015 that the status information cannot be normally read from the external RTC 70c, an error code (RTC) is stored in the error information history storage area 73d-1 as an RTC communication line abnormality. DSC) is registered (step S1021).

  If the sub CPU 71 determines in step S1016 that there is an abnormality in the power supply regarding the external RTC 70c, it registers an error code (RTC POWER) in the error information history storage area 73d-1 as the RTC voltage drop (step S1016). S1021).

  If the sub CPU 71 determines in step S1017 that there is an oscillation abnormality with respect to the external RTC 70c, it registers an error code (RTC CLK) in the error information history storage area 73d-1 as oscillation stop detection ( Step S1021).

  As described above, when registering an error code corresponding to the error type of the external RTC 70c as error information in step S1021, the sub CPU 71 initializes the external RTC 70c and sets the current date and time of the internal RTC 70a in the external RTC 70c. (Step S1022).

  As described above, when the external RTC 70c is initialized and the current date and time of the built-in RTC 70a is set in the external RTC 70c, or when it is determined in step S1020 that there is no abnormality in the date and time range read from the external RTC 70c in step S1019. In step S1023, the sub CPU 71 determines whether or not the date and time setting of the external RTC 70c has been changed from the staff operation screen. The RTC 70c is set (step S1024).

  If the date / time data of the built-in RTC 70a is set in the external RTC 70c in step S1024, or if it is determined in step S1023 that there is no change in the date / time setting of the external RTC 70c, the sub CPU 71 waits for a cycle of 100 ms. Then, the status information is read again from the external RTC 70c (step S1014).

  Next, management processing of the sub control backup memory (SRAM) 73-2 will be described with reference to FIG. FIG. 73 shows a flowchart of the sub RAM management processing.

  First, the sub CPU 71 calculates the sum value of the backup data 1 area 73a-2 of the SRAM 73-2 to obtain a 4-byte backup data 1 sum value (step S1031).

  Next, the sub CPU 71 determines whether the acquired sum value is normal and whether the magic code of the backup data 1 area 73a-2 and the magic code of the program management data area 72f of the sub ROM 72 are the same. If the answer is YES, the backup data 1 area 73a-2 of the backup RAM 73-2 is copied to the game data area 73a-1 of the sub RAM 73-1 (step S1033).

  If the sub CPU 71 determines NO in step S1032, the sub CPU 71 calculates the sum value of the backup data 2 area 73c-2, which is the mirroring of the backup data 1 area 73a-2, and calculates the 4-byte backup data 2 sum value. Is obtained (step S1034).

  Subsequent to step S1034, the sub CPU 71 determines whether the acquired sum value is normal and whether the magic code in the backup data 2 area 73c-2 and the magic code in the program management data area 72f of the sub ROM 72 are the same. Determination is made (step S1035).

  If the determination in step S1035 is YES, the sub CPU 71 copies the backup data 2 area 73c-2 of the backup RAM 73-2 to the game data area 73a-1 of the sub RAM 73-1 (step S1036).

  If the determination in step S1035 is NO, the sub CPU 71 copies the game data initialization setting data area 72c in the sub ROM 72 to the game data area 73a-1 in the sub RAM 73-1 (step S1037).

  When step S1036 or step S1037 is executed, the sub CPU 71 registers an error code (MEM ERR 1) in the error information history storage area 73d-1 as a game data sum abnormality (step S1038). However, the screen as shown in FIG. 57 for notifying the RAM data abnormality is not displayed.

  After executing the process of step S1033 or the process of step S1038, the sub CPU 71 calculates a 4-byte sum value from the attendant backup data area 73e-2 and stores it in the attendant backup data sum value area 73g-2. (Step S1039).

  Next, the sub CPU 71 determines whether or not the stored sum value of the clerk backup data area 73e-2 is normal (step S1040). The data is copied to the clerk operation setting data area 73g-1 of the RAM 73-1 (step S1041).

  If the determination in step S1040 is NO, the sub CPU 71 copies the data in the clerk operation initial setting data area 72d in the sub ROM 72 to the clerk operation setting data area 73g-1 in the sub RAM 73-1 (step S1042).

  After executing step S1042, the sub CPU 71 registers an error code (MEM ERR 2) in the error information history storage area 73d-1 as the clerk operation setting data sum abnormality (step S1043). Even for this RAM data abnormality, a screen for notifying abnormality as shown in FIG. 57 is not displayed.

  Next, after executing step S1041 or step S1043, the sub CPU 71 executes a backup creation process shown in FIG. 74 described later (step S1044).

  As described above, the sub CPU 71 determines whether the acquired sum value is normal and whether the magic code of the backup data 2 area 73c-2 and the magic code of the program management data area 72f of the sub ROM 72 are the same. However, if at least the sum value or the magic code is not the same, the sub CPU 71 copies the game data initialization setting data area 72c of the sub ROM 72 to the game data area 73a-1 of the sub RAM 73-1 (step S1035). Step S1037).

  Further, the sub CPU 71 determines whether or not the sum value of the clerk backup data area 73e-2 is normal (step S1040), and if abnormal, the data in the clerk operation initial setting data area 72d of the sub ROM 72 is stored in the sub RAM 73. -1 is copied to the clerk operation setting data area 73g-1 (step S1042).

  As a result, it is possible to confirm whether or not the data in the sub RAM 73-1 is damaged when the power is turned on, and the initial value can be automatically set without using the damaged SRAM data.

  FIG. 74 is a flowchart of the backup creation process of the sub RAM management process shown in FIG. This process allows the correct value to be saved as a backup even if the data is corrupted. As described above, this backup creation process is also executed in the power interruption interrupt process shown in FIG.

  First, the sub CPU 71 creates a sum value of the game data area 73a-1, and stores the created sum value in the game data sum value area 73b-1 (step S1051). Next, the sub CPU 71 copies the game data area 73a-1 to the backup data 1 area 73a-2, and stores the sum value stored in step S1051 in the backup data 1 sum value area 73b-2 (step S1052).

  Next, the sub CPU 71 copies the game data area 73a-1 to the backup data 2 area 73c-2 as mirroring of the backup data 1 area 73a-2, and uses the sum value stored in step S1051 as the backup data 2 sum value area. 73d-2 (step S1053).

  Next, the sub CPU 71 creates a sum value of the clerk operation setting data area 73g-1, and stores the created sum value in the clerk operation setting data sum value area 73h-1 (step S1054).

  Next, the sub CPU 71 copies the clerk operation setting data area 73g-1 to the clerk backup data area 73e-2 and saves the sum value stored in step S1054 in the clerk backup data sum value area 73g-2 (step S1055). ). Thereby, the backup creation process ends.

  As described above, the gaming machine 1 according to the present embodiment is configured to encrypt the command transmitted from the main control circuit 60 to the sub-control circuit 70 including the main key code added BCC data. It becomes difficult to analyze the command. In addition, the gaming machine 1 in the present embodiment decrypts a command encrypted by the main control circuit 60 by the sub control circuit 70, and when the decrypted command does not match a predetermined command, If the data does not match, it is registered as error information and the error history is displayed on the liquid crystal display device 5, so that the error information generated by fraud can be effectively used. As a result, the gaming machine 1 according to the present embodiment can display error information to the staff of the store where the game machine 1 is installed, or reflect the error information in the development of the next model by analyzing the error information.

[Configuration of pachinko machines]
The present invention is not limited to a pachislot machine but can also be applied to a pachinko gaming machine. Hereinafter, the pachinko gaming machine will be described.

  As shown in FIGS. 75 and 76, the pachinko machine 1010 includes a glass door 1011, a wooden frame 1012, a base door 1013, a game board 1014, a dish unit 1020, a liquid crystal display device 1032 that displays an image, and a launch that fires a game ball. The apparatus 1130 includes a dispensing unit (not shown) and a substrate unit.

  The glass door 1011 is attached to the base door 1013 so that it can be opened and closed by a rotating shaft. An opening 1011a is formed at the center of the glass door 1011. A protective glass 1019 having transparency is disposed in the opening 1011a.

  The dish unit 1020 is a unit body in which the upper dish 1021 and the lower dish 1022 are integrated, and is disposed below the glass door 1011 in the base door 1013. The upper plate 1021 and the lower plate 1022 are provided with payout ports 1021a and 1022a for renting out game balls and paying out game balls (prize balls). If predetermined payout conditions are met, The balls are discharged, and in particular, the upper plate 1021 stores game balls for launching into a game area 1015 described later.

  The launching device 1130 includes a launching handle 1026 that is disposed at the lower right portion of the base door 1013 and can be operated by the player, and a panel body 1027 that fits in the lower right portion of the dish unit 1020. The firing handle 1026 is provided on the front side of the panel body 1027. A drive device for launching a game ball is provided on the back side of the panel body 1027. A player can advance the game by firing the game ball by operating the launch handle 1026.

  The game board 1014 is disposed in front of the base door 1013 so as to be positioned behind the protective glass 1019. A liquid crystal display device 1032 and the like are disposed behind the game board 1014. A payout unit and a substrate unit are disposed behind the base door 1013. In the lower part of the lower plate 1022, a speaker for performance not shown is arranged.

  The game board 1014 is formed of various types of resin (permeability members) such as plate-shaped acrylic resin, polycarbonate resin, and methacrylic resin, all of which are permeable. In addition, the game board 1014 has a game area 1015 on the front side thereof in which the launched game ball can roll down. In the game area 1015, a plurality of game nails 1017 are driven. In addition, an LED unit 1053 is provided at the lower left portion of the game board 1014.

  The liquid crystal display device 1032 is disposed behind the game board 1014 (on the back side). The liquid crystal display device 1032 has a display area 1032a that enables display of an image relating to a game. In the display area 1032a, various kinds of images such as an identification pattern for effect, an effect image, and a decoration image for decoration are displayed.

  The firing handle 1026 is rotatable, and a firing solenoid (not shown) as a driving device is provided on the back side thereof. Further, a touch sensor (not shown) is provided on the peripheral edge of the firing handle 1026. Inside the firing handle 1026 is provided a firing volume that changes the resistance value according to the amount of rotation of the firing handle 1026 and changes the power supplied to the firing solenoid (not shown).

  When the player touches a touch sensor (not shown), it is detected that the firing handle 1026 is gripped by the player. When the firing handle 1026 is gripped by the player and rotated clockwise, the resistance value of the firing volume (not shown) changes according to the rotation angle, and corresponds to the resistance value at this time. Electric power is supplied to a firing solenoid (not shown). As a result, the game balls stored in the upper plate 1021 are sequentially launched into the game area 1015 and the game is advanced. When a firing stop button (not shown) is pressed, the game ball is stopped firing even when the firing handle 1026 is held and rotated.

  On the lower left side of the game board 1014, members forming the general winning ports 1056a, 1056b, and 1056c are arranged, and a portion of the member facing the LED unit 1053 is transparent. For this reason, the LED unit 1053 is visible from the lower left of the game board 1014. The LED unit 1053 includes a special symbol display device, a normal symbol display device 1033, a first special symbol hold display LED 1034a, 1034b, a second special symbol hold display LED 1034c, 1034d, a normal symbol hold display LED 1050a, 1050b, etc. Is provided.

  The special symbol display device is composed of 16 LEDs. These 16 LEDs are divided into two groups of 8 LEDs, one of which is a variable display triggered by the start winning to the first start port 1023, the other group is The change display is performed in response to the start winning at the second start port 1044. For convenience of the following description, one LED group is referred to as a first special symbol display device 1035a (see FIG. 77), and the other LED group is referred to as a second special symbol display device 1035b (see FIG. 77).

  The LEDs of the first and second special symbol display devices 1035a and 1035b perform special symbol variation display by repeatedly turning on and off in units of groups when a predetermined special symbol variation display start condition is satisfied. When the special symbol is in a specific stop display mode, the gaming state shifts from a normal gaming state to a winning gaming state (special gaming state) that is advantageous to the player. In this winning game state, as will be described later, the shutter 1040 is controlled to be in the open state, and the game ball can be received in the special winning opening 1039.

  The normal symbol display device 1033 is variably displayed as a normal symbol by alternately turning on and off the two display lamps, and the normal electric accessory 1048 is opened according to the stop mode.

  The normal symbol hold display LEDs 1050a and 1050b display the number of executions of fluctuation display of the normal symbols that are held by turning on, turning off, or blinking (so-called “hold number”, “hold number related to normal symbols”).

  The first special symbol hold display LEDs 1034a and 1034b and the second special symbol hold display LEDs 1034c and 1034d are executed by the number of executions of the variable symbol variable display held by turning on, turning off, or blinking (so-called “hold number”, “special symbols”). Display the number of pending items ").

  In the display area of the liquid crystal display device 1032, an effect image related to the special symbol displayed on the first special symbol display device 1035 a and the second special symbol display device 1035 b is displayed.

  As shown in FIG. 76, on the game board 1014, there are two guide rails 1030 (1030a and 1030b), a stage 1055, a first start port 1023, a second start port 1044, a passage gate 1054, a shutter 1040, and a prize winning port. 1039, a general winning opening 1056a, 1056b, 1056c, 1056d, an ordinary electric accessory 1048, etc. are provided.

  The stage 1055 is provided on the upper part of the game board 1014, and the guide rail 1030 is provided so as to surround the game area 1015.

  The guide rail 1030 includes an outer rail 1030a and an inner rail 1030b. The launched game ball is guided by the guide rail 1030 and moves to the upper part of the game board 1014, and its traveling direction is changed by the collision with the plurality of game nails (not shown), the stage 1055, etc. It flows down toward the bottom of the game board 1014. Specifically, a system that flows down the left side of the stage 1055 (so-called left-handed) and a firing handle 1026 are rotated to the right to the maximum, and a game ball is driven into the right side of the stage 1055 and flows down the right side of the stage 1055. There is a system (so-called right-handed).

  The first start port 1023 is provided below the center of the game board 1014. The passage gate 1054 is provided on the upper right side of the stage 1055, and a second start port 1044 is provided below the passage gate 1054. The ordinary electric accessory 1048 is provided at the second start port 1044.

  The ordinary electric accessory 1048 includes a tongue-like member 1048a that projects and retracts in the front-rear direction with respect to the game board surface. The ordinary electric accessory 1048 can win a game ball to the second start port 1044 when the tongue-like member 1048a protrudes, and cannot win a game ball to the second start port 1044 when retracted. The ordinary electric accessory 1048 may be a pair of blade members that are opened and closed (so-called electric tulips).

  Further, when the player strikes the right side, the game nail 1017 is configured such that the game ball cannot enter the first start port 1023 from the right side of the stage 1055.

  If the game ball passes through the passing gate 1054 during the normal symbol variation display, the display mode by the normal symbol hold display LEDs 1050a and 1050b is switched until the normal symbol during the variation display is stopped and displayed. Execution (start) of the normal symbol variation display based on the passing of the game ball to the passing gate 1054 is suspended. After that, when the normal symbol that has been variably displayed is stopped and displayed, the variably displayed normal symbol that has been suspended is started.

  When a specific symbol is stopped and displayed as a normal symbol on the normal symbol display device 1033, an effect image for allowing the player to grasp that the normal symbol lottery is won is displayed in the display area of the liquid crystal display device 1032. You may make it do.

  The shutter 1040 is disposed directly below the first start port 1023, and opens and closes the big prize port 1039. An out port 1057 is formed at the lowermost part of the game area 1015 immediately below the shutter 1040. The general winning ports 1056a, 1056b, 1056c are provided in the lower left part of the game area 1015. Further, a general winning opening 1056d is provided at the lower right side of the game area 1015.

  In addition, a winning area is provided in the first starting port 1023 described above, and a first starting winning port switch 1116 (see FIG. 77) is provided in this winning area. A winning area is provided in the second starting opening 1044, and a second starting winning opening switch 1117 (see FIG. 77) is provided in the winning area. When the game ball is detected by the first start winning a prize opening switch 1116, the first special symbol display device 1035a starts to display the variation of the special symbol.

  In addition, when a game ball enters the first start port 1023 during the special symbol variation display, the game ball enters the first start port 1023 until the special symbol during the variation display is stopped and displayed. Execution (start) of the special symbol variation display based on is suspended. Thereafter, when the special symbol that has been variably displayed is stopped and displayed, the variably displayed suspended special symbol is started. In the following description, the special symbol variably displayed on the first special symbol display device 1035a based on the game ball entering the first start port 1023 is referred to as a first special symbol.

  When the game ball is detected by the second start winning a prize opening switch 1117, the special symbol variation display by the second special symbol display device 1035b is started. In addition, when a game ball enters the second start opening 1044 during the variation display of the special symbol, the game ball enters the second start opening 1044 until the special symbol during the variation display is stopped and displayed. Execution (start) of the special symbol variation display based on is suspended. Thereafter, when the special symbol that has been variably displayed is stopped and displayed, the variably displayed suspended special symbol is started. In the following description, the special symbol variably displayed on the second special symbol display device 1035b based on the game ball entering the second start port 1044 is referred to as a second special symbol.

  Here, the first special symbol display device 1035a and the second special symbol display device 1035b do not fluctuate at the same time. In addition, the special symbol variation display is performed with priority given to the start winning at the second start port 1044.

  It should be noted that the upper limit of the number of suspensions of the special symbol variation display by entering the first start port 1023 and the second start port 1044 is four times. Therefore, a maximum of 8 holds is possible.

  In addition, as another condition (start of variable display of a predetermined special symbol), the special symbol is stopped and displayed. In other words, every time a predetermined special symbol variable display start condition is satisfied, the special symbol variable display is started.

  In the first special symbol display device 1035a and the second special symbol display device 1035b, when the special symbol becomes a specific stop display mode and the gaming state is shifted to the big hit gaming state, the shutter 1040 is opened. Driven. As a result, the special winning opening 1039 is in an open state (first state) in which a game ball can be easily received.

  On the other hand, the special winning opening 1039 provided on the back side (rear side) of the shutter 1040 has an area (not shown) having a count switch 1104 (see FIG. 77), and a predetermined number of game balls (for example, 7) or the shutter 1040 is driven to the open state until a predetermined time (for example, about 0.1 second or about 30 seconds) elapses. When either a predetermined number of game balls are awarded to the big winning opening 1039 or a predetermined time has elapsed in the open state, the shutter 1040 is driven to be in the closed state. As a result, the special winning opening 1039 is in a closed state in which it is difficult to accept a game ball (second state).

  Note that a game in which the special winning opening 1039 easily accepts a game ball for a certain period of time is referred to as a round game. Therefore, the shutter 1040 is opened during the round game and is closed between the round games. A round game is counted as the number of rounds such as “1” round, “2” round, and the like. For example, the first round game may be referred to as the first round and the second round as the second round. In this example, in one round, the shutter 1040 is opened and closed a plurality of times, and the open time may be set to a certain time.

  Subsequently, the shutter 1040 driven from the open state to the closed state (second state) is driven again to the open state. That is, when the round game is finished, it is possible to continue to the next round game. A game from the first round game until the end of the (final) round game that cannot continue to the next round game is called a special game or a big hit game. In this example, all jackpots are 15 rounds.

  Further, when a game ball is won in the first start port 1023, the second start port 1044, the general winning ports 1056a to 1056d, and the big winning port 1039, the number set in advance according to the type of each winning port. Of the game balls are paid out to the upper plate 1021 or the lower plate 1022.

  Also, in this example, after the big hit game is over, there is a case where the winning probability of the normal symbol lottery becomes a high probability state, and the support by the normal electric accessory 1048 makes a transition to a short time state where the reserved balls of the special symbol game are easily stored. . Here, in the short-time state, passing the game ball to the passing gate 1054 is a condition for executing the normal symbol lottery, so that the game proceeds while making a right strike.

  Further, when a big hit occurs in the right-handed state, it is possible to win the big winning opening 1039 by continuing the right-handed as it is. Further, when the support by the ordinary electric accessory 1048 cannot be received, the game is advanced while making a left strike.

  Also, as shown in FIG. 75, effect buttons 1080a, 1080b, and 1080c are provided on the front surface of the upper plate 1021, and these effects are performed during a mini-game such as an open game, a card flip, a sugoroku or the like. By pressing the button, the effect display content on the liquid crystal display device 1032 can be changed.

  In the pachinko machine 1010, the liquid crystal display device is described as an example of the production means. However, the present invention is not limited to this, and a plasma display, a rear projection display, a CRT display, a lamp, a speaker, a movable accessory, or the like is used as the production means. Also good.

  Next, the electrical configuration of the pachinko machine 1010 will be described with reference to FIG.

  As shown in FIG. 77, the pachinko machine 1010 mainly includes a main control circuit 1060 that controls a game and a sub-control circuit 1200 that controls an effect according to the progress of the game.

  The main control circuit 1060 includes a main CPU 1066, a main ROM 1068 (read only memory), and a main RAM 1070 (read / write memory). The main control circuit 1060 constitutes a main control unit according to the present invention.

  The main CPU 1066 is similar to the main CPU 31 (see FIG. 6) described in the pachislot machine of the present embodiment, and includes a key code creation means 1066a, a main sum value calculation means 1066b, a main key code added sum value calculation means 1066c, a command An encryption unit 1066d and a command transmission unit 1066e are provided. The command encryption unit 1066d encrypts the command generated by the main CPU 1066 based on the encryption information stored in the main ROM 1068. The command transmission unit 1066e transmits the encrypted command to the sub control circuit 1200.

  The key code creating means 1066a creates a key code for each predetermined condition in response to a command transmitted to the sub control circuit 1200. The key code here is a 1-byte random value acquired from the refresh register at the time of activation. However, the key code may be a random value, and may be set based on a random value using means other than the refresh register. Further, as a predetermined condition for generating the key code, the power of the pachinko machine 1010 is turned on or reset.

  The main sum value calculating means 1066b calculates the sum value by the XOR logic operation and sets it as the main sum value. Here, as an example of the main sum value, there is BCC data which is error check information for confirming the presence or absence of a communication error between the main control circuit 1060 and the sub control circuit 1200.

  The main key code added sum value calculation means 1066c performs an XOR logical operation using the main sum value and the key code, and calculates a main key code added sum value.

  The command encryption unit 1066d encrypts the command (including the main key code added sum value) generated by the main CPU 1066 based on the encryption information stored in the main ROM 1068. The command transmission unit 1066e transmits the encrypted command to the sub control circuit 1200.

  The main CPU 1066 is connected to a main ROM 1068, a main RAM 1070, and the like, and has a function of executing various processes according to a program stored in the main ROM 1068.

  The main ROM 1068 stores a program for controlling the operation of the pachinko machine 1010 by the main CPU 1066, a program for causing the main CPU 1066 to execute main processing, and various tables.

  The main RAM 1070 has a function of storing various flags and variable values as a temporary storage area of the main CPU 1066. The temporary storage area of the main CPU 1066 is not limited to the main RAM 1070, and other readable / writable storage media may be used.

  The main control circuit 1060 includes an initial reset circuit 1064 that generates a reset signal when the power is turned on, an I / O port 1071, and a command output port 1072. The initial reset circuit 1064 is connected to the main CPU 1066. The I / O port 1071 is used to transmit input signals from various devices to the main CPU 1066 and output signals from the main CPU 1066 to various devices.

  The command output port 1072 transmits a command from the main CPU 1066 to the sub control circuit 1200. The main control circuit 1060 includes a backup capacitor 1074. The backup capacitor 1074 is used to hold various data stored in the main RAM 1070, for example, by quickly supplying power to the main RAM 1070 when power is interrupted.

  Various devices are connected to the main control circuit 1060. For example, the main control circuit 1060 includes a first special symbol display device 1035a and a second special symbol display device 1035b, first special symbol hold display LEDs 1034a and 1034b, second special symbol hold display LEDs 1034c and 1034d, and a normal symbol display device 1033. The normal symbol hold display LEDs 1050a and 1050b, the start-port solenoid 1118 that causes the tongue-like member 1048a of the ordinary electric accessory 1048 to be in the protruding state or the retracted state, and the shutter 1040 are driven, and the grand prize winning port 1039 is opened or closed. A big prize solenoid 1120 or the like is connected.

  Further, the main control circuit 1060 has a call device (not shown) having a function of calling a hall attendant and a function of displaying the number of hits, and an external terminal used for transmitting data to a hall computer 1400 that manages pachinko machines for the entire hall. A plate 1310 is connected.

  The main control circuit 1060 also includes, for example, a count switch 1104 that supplies a predetermined detection signal to the main control circuit 1060 when a game ball passes through an area of the big prize opening 1039, and each general winning opening 1056. When a game ball passes through the general prize opening switches 1106, 1108, 1110, 1112 and the pass gate 1054, which supply a predetermined detection signal to the main control circuit 60 when the game passes, the predetermined detection signal is sent to the main control circuit 60. When the game ball wins the passing gate switch 1114 and the first starting port 1023 supplied to 1060, the first starting winning port switch 1116 and the second starting port 1044 that supply a predetermined detection signal to the main control circuit 1060 are played. Second start winning port switch 1117 for supplying a predetermined detection signal to the main control circuit 1060 when the ball has won, Such as backup clear switch 1124 to clear depending on the administrator of the operation of the game arcade is connected to a backup data in such.

  The main control circuit 1060 is connected to a payout / firing control circuit 1126. Connected to the payout / launch control circuit 1126 are a payout device 1128 for paying out game balls, a launch device 1130 for launching game balls, and a card unit 1300. The card unit 1300 can be transmitted / received to / from a ball lending operation panel 1155 that outputs a signal requesting the card unit 1300 to lend a game ball to the card unit 1300 by an operation of the player.

  The payout / launch control circuit 1126 receives a prize ball control command supplied from the main control circuit 1060 and a lending ball control signal supplied from the card unit 1300, and transmits a predetermined signal to the payout device 1128. The payout device 1128 is caused to pay out the game ball. Further, the payout / firing control circuit 1126 supplies electric power to the firing solenoid according to the turning angle when the launching handle 1026 is gripped by the player and is turned clockwise. Control to fire the ball.

  A sub control circuit 1200 is connected to the command output port 1072. The sub-control circuit 1200 has the same configuration as the sub-control circuit 70 (see FIG. 7) described in the pachislot machine of the present embodiment, and can execute various processes similar to the sub-control circuit 70. It is like that. For example, the sub control circuit 1200 includes a sub CPU 1201 having a command decryption unit 1201a for decrypting various commands encrypted and transmitted by the main control circuit 1060, and according to the decrypted command, the liquid crystal display device 1032 ( Display control in error information display means), control related to sound generated from the speaker 1046, control of lamps including decorative lamps, and the like. The sub-control circuit 1200 constitutes a sub-control unit according to the present invention.

  As described above, according to the pachinko gaming machine according to the present embodiment, the same effects as those of the pachislot gaming machine according to the above embodiment can be obtained.

5 Liquid crystal display (error information display means)
30 Microcomputer 31 Main CPU
31a Key code creation means 31b Main sum value calculation means 31c Main key code added sum value calculation means 31d Command encryption means 31e Command transmission means 32 Main ROM
33 Main RAM
60 Main control circuit (main control unit)
70 Sub Control Circuit (Sub Control Unit)
71 Sub CPU (command receiving means)
71a Command decoding means 71g Error information history display means (error information display means)
71i Key code acquisition means 71j Sub sum value calculation means 71k Sub key code added sum value calculation means 71m Sum value judgment means 72 Sub ROM
72j Decoded information area 1010 Pachinko machine 1032 Liquid crystal display device (error information display means)
1060 Main control circuit (main control unit)
1064 Initial reset circuit 1066 Main CPU
1066a Command encryption unit 1066b Command transmission unit 1200 Sub control circuit (sub control unit)
1201 Sub CPU (command receiving means)
1201a Command decoding means

Claims (1)

A first control unit that executes processing related to the progress of the game;
A second control unit for controlling the production according to the progress of the game;
Display means connected to the second control unit for displaying various information,
The first controller is
An encryption means for encrypting transmission data;
Data transmission means for transmitting the encrypted transmission data to the second control unit,
The second controller is
Data receiving means for receiving the encrypted transmission data as received data;
Decoding means for decoding the received data received by the data receiving means;
Based on the received data decoded by the decoding means, it is determined whether the received data is normal, it is determined that the received data is not normal, and the first control unit and the second control unit Error information registration means for registering error information related to the communication error on the condition that the communication error has occurred again within a predetermined time when a communication error has occurred ,
Error information display means for displaying the error information registered by the error information registration means on the display means,
The transmission data and the reception data are composed of a plurality of bytes of data arranged in a predetermined order,
The encryption means encrypts the transmission data by replacing the plurality of bytes of data constituting the transmission data with a predetermined encryption procedure,
The decryption means decrypts the encrypted received data by replacing with a predetermined decryption procedure,
The gaming machine according to claim 2, wherein the second control unit controls an effect based on the received data decoded by the decoding means.

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