JP6136978B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
JP6136978B2
JP6136978B2 JP2014034541A JP2014034541A JP6136978B2 JP 6136978 B2 JP6136978 B2 JP 6136978B2 JP 2014034541 A JP2014034541 A JP 2014034541A JP 2014034541 A JP2014034541 A JP 2014034541A JP 6136978 B2 JP6136978 B2 JP 6136978B2
Authority
JP
Japan
Prior art keywords
sealing resin
cavity
radiating plate
semiconductor chip
heat radiating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2014034541A
Other languages
Japanese (ja)
Other versions
JP2015159256A (en
Inventor
憲宗 織本
憲宗 織本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyota Motor Corp
Original Assignee
Toyota Motor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyota Motor Corp filed Critical Toyota Motor Corp
Priority to JP2014034541A priority Critical patent/JP6136978B2/en
Publication of JP2015159256A publication Critical patent/JP2015159256A/en
Application granted granted Critical
Publication of JP6136978B2 publication Critical patent/JP6136978B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

本発明は、半導体チップが封止樹脂によって封止されている半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device in which a semiconductor chip is sealed with a sealing resin and a method for manufacturing the same.

特許文献１には半導体装置が開示されている。特許文献１の半導体装置は、横に並んだ一対の半導体チップを備えている。半導体チップの裏面側には放熱板が配置されており、半導体チップと放熱板がはんだを介して接合されている。また、一対の半導体チップは、それぞれ封止樹脂により封止されている。一方側の半導体チップを封止する封止樹脂と他方側の半導体チップを封止する封止樹脂との間には、封止樹脂による応力を緩和するための隙間（溝）が形成されている。   Patent Document 1 discloses a semiconductor device. The semiconductor device of Patent Document 1 includes a pair of semiconductor chips arranged side by side. A heat sink is disposed on the back side of the semiconductor chip, and the semiconductor chip and the heat sink are joined together via solder. The pair of semiconductor chips are each sealed with a sealing resin. A gap (groove) is formed between the sealing resin for sealing the semiconductor chip on one side and the sealing resin for sealing the semiconductor chip on the other side to relieve stress due to the sealing resin. .

特開２０１２−１４６７４５号公報JP 2012-146745 A

半導体装置では、半導体チップを効率的に冷却するために半導体チップの裏面側だけでなく表面側にも放熱板を配置することがある。特許文献１の技術では、半導体チップの表面側と裏面側の両側に放熱板を配置すると、一方側と他方側の半導体チップを封止する封止樹脂の間に応力緩和用の隙間（溝）を形成することができない。そこで本発明では、半導体チップの表面側と裏面側の両側に放熱板が配置された構成において、封止樹脂による応力を緩和するための技術を提供する。   In a semiconductor device, in order to cool a semiconductor chip efficiently, a heat sink may be arranged not only on the back surface side but also on the front surface side of the semiconductor chip. In the technique of Patent Document 1, when heat sinks are arranged on both the front surface side and the back surface side of a semiconductor chip, a gap (groove) for stress relaxation between the sealing resin for sealing the semiconductor chip on one side and the other side. Can not form. Therefore, the present invention provides a technique for alleviating stress due to the sealing resin in a configuration in which heat sinks are arranged on both the front surface side and the back surface side of the semiconductor chip.

本発明に係る半導体装置は、第１表面と前記第１表面の反対側に位置する第２表面とを有する第１の半導体チップと、前記第１の半導体チップに所定間隔をあけて隣接する第２の半導体チップと、前記第１表面にはんだを介して接合された第１放熱板と、前記第２表面にはんだを介して接合された第２放熱板と、を備えている。また、この半導体装置は、前記第１放熱板と前記第２放熱板の間に充填されて前記半導体チップを封止する封止樹脂であって、隣接する２つの前記半導体チップの間に前記第１放熱板及び前記第２放熱板に沿って延びるように空洞が形成されており、端部で前記空洞が開口している封止樹脂を備えている。   A semiconductor device according to the present invention includes a first semiconductor chip having a first surface and a second surface located on the opposite side of the first surface, and a first semiconductor chip adjacent to the first semiconductor chip at a predetermined interval. 2 semiconductor chips, a first heat radiating plate joined to the first surface via solder, and a second heat radiating plate joined to the second surface via solder. The semiconductor device is a sealing resin that is filled between the first heat radiation plate and the second heat radiation plate to seal the semiconductor chip, and the first heat radiation is between the two adjacent semiconductor chips. A cavity is formed so as to extend along the plate and the second heat radiating plate, and a sealing resin having an opening at the end is provided.

このような構成によれば、隣接する２つの半導体チップの間において第１放熱板と第２放熱板の間に充填された封止樹脂に空洞が形成されているので、半導体チップと封止樹脂との熱膨張率の差などにより応力が発生したとしても、空洞により応力を逃がすことができる。よって、封止樹脂による応力を緩和することができる。   According to such a configuration, since the cavity is formed in the sealing resin filled between the first heat dissipation plate and the second heat dissipation plate between two adjacent semiconductor chips, the semiconductor chip and the sealing resin Even if stress is generated due to a difference in thermal expansion coefficient or the like, the stress can be released by the cavity. Therefore, the stress due to the sealing resin can be relaxed.

本発明に係る半導体装置の製造方法は、第１表面と前記第１表面の反対側に位置する第２表面を有する複数の半導体チップと、前記第１表面にはんだを介して接合された第１放熱板と、前記第２表面にはんだを介して接合された第２放熱板と、を備えるモジュールを成形型にセットするセット工程であって、前記成形型が備える中型が、前記第１放熱板と前記第２放熱板の間に配置され、前記第１放熱板及び前記第２放熱板に沿って延びるように前記モジュールをセットするセット工程を備えている。また、この製造方法は、前記成形型にセットされた前記モジュールの前記第１放熱板と前記第２放熱板の間に封止樹脂を充填して前記半導体チップを封止する封止工程を備えている。   A method for manufacturing a semiconductor device according to the present invention includes a first surface and a plurality of semiconductor chips having a second surface located on the opposite side of the first surface, and a first bonded to the first surface via solder. A setting step of setting a module including a heat radiating plate and a second heat radiating plate joined to the second surface via solder in a molding die, wherein the middle die provided in the molding die is the first heat radiating plate. And a setting step of setting the module so as to extend along the first heat dissipation plate and the second heat dissipation plate. In addition, the manufacturing method includes a sealing step of sealing the semiconductor chip by filling a sealing resin between the first heat radiating plate and the second heat radiating plate of the module set in the mold. .

このような構成によれば、封止工程により、半導体チップが封止樹脂で封止されると共に、中型の形状に対応する空洞が封止樹脂に形成される。空洞により封止樹脂の応力を逃がすことができるので、封止樹脂による応力を緩和することができる。また、第１放熱板及び第２放熱板を加工しなくても中型の形状に応じた空洞を封止樹脂に形成することができるので、半導体装置の冷却性能が低下することがない。   According to such a configuration, the semiconductor chip is sealed with the sealing resin by the sealing step, and a cavity corresponding to the shape of the medium size is formed in the sealing resin. Since the stress of the sealing resin can be released by the cavity, the stress due to the sealing resin can be relieved. In addition, since the cavity corresponding to the shape of the middle size can be formed in the sealing resin without processing the first heat radiating plate and the second heat radiating plate, the cooling performance of the semiconductor device does not deteriorate.

実施形態に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on embodiment. 図１のII−II断面図である。It is II-II sectional drawing of FIG. 半導体装置の製造方法を説明するための図である。It is a figure for demonstrating the manufacturing method of a semiconductor device. 図３のIV−IV断面図である。It is IV-IV sectional drawing of FIG. 図４のV−V断面図である。It is VV sectional drawing of FIG. 他の実施形態に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on other embodiment. 更に他の実施形態に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on other embodiment. 図７のVIII−VIII断面図である。It is VIII-VIII sectional drawing of FIG. 更に他の実施形態に係る半導体装置の図２に対応する断面図である。FIG. 6 is a cross-sectional view corresponding to FIG. 2 of a semiconductor device according to still another embodiment. 更に他の実施形態に係る半導体装置の要部を拡大して示す断面図である。Furthermore, it is sectional drawing which expands and shows the principal part of the semiconductor device which concerns on other embodiment. 更に他の実施形態に係る半導体装置の断面図である。It is sectional drawing of the semiconductor device which concerns on other embodiment.

以下に説明する実施形態の主要な特徴を列記する。なお、以下に記載する技術要素は、それぞれ独立した技術要素であって、単独であるいは各種の組合せによって技術的有用性を発揮するものである。   The main features of the embodiments described below are listed. Note that the technical elements described below are independent technical elements, and exhibit technical usefulness alone or in various combinations.

（特徴１）半導体装置において、第１放熱板と空洞との間に封止樹脂が存在していてもよい。   (Feature 1) In the semiconductor device, a sealing resin may exist between the first heat dissipation plate and the cavity.

（特徴２）前記空洞が前記封止樹脂を貫通しており、前記封止樹脂の両端部で開口していてもよい。あるいは、前記空洞が前記封止樹脂を貫通しておらず、前記封止樹脂の一端部で開口していてもよい。   (Feature 2) The cavity may penetrate the sealing resin, and may be open at both ends of the sealing resin. Alternatively, the cavity may not open through the sealing resin and may open at one end of the sealing resin.

（特徴３）封止樹脂に空洞が複数形成されていてもよい。また、複数の空洞が半導体チップを取り囲んでいてもよい。   (Feature 3) A plurality of cavities may be formed in the sealing resin. A plurality of cavities may surround the semiconductor chip.

（特徴４）半導体装置の製造方法において、セット工程では、前記中型は、隣接する２つの前記半導体チップの間に配置されていてもよい。また、セット工程では、中型は、第１放熱板との間に隙間を形成するように配置されていてもよい。   (Feature 4) In the method of manufacturing a semiconductor device, in the setting step, the middle die may be disposed between two adjacent semiconductor chips. In the setting process, the middle mold may be arranged so as to form a gap with the first heat radiating plate.

（特徴５）半導体装置の製造方法は、封止樹脂から中型を引き抜く引抜工程を更に備えていてもよい。   (Feature 5) The semiconductor device manufacturing method may further include a drawing step of drawing the middle mold from the sealing resin.

以下、実施形態について添付図面を参照して説明する。実施形態に係る半導体装置１は、図１及び図２に示すように、複数の半導体チップ２と、半導体チップ２にはんだ７を介して接合された放熱板３（表面側放熱板３１及び裏面側放熱板３２）とを備えている。また、半導体装置１は、表面側放熱板３１と裏面側放熱板３２の間に充填された封止樹脂５を備えている。   Hereinafter, embodiments will be described with reference to the accompanying drawings. As shown in FIGS. 1 and 2, the semiconductor device 1 according to the embodiment includes a plurality of semiconductor chips 2 and a heat radiating plate 3 (surface-side heat radiating plate 31 and back surface side) joined to the semiconductor chip 2 via solder 7. And a heat radiating plate 32). Further, the semiconductor device 1 includes a sealing resin 5 filled between the front surface side heat radiating plate 31 and the back surface side heat radiating plate 32.

複数の半導体チップ２は、互いに間隔をあけて並んで配置されている。本実施形態では２つの半導体チップ２を用いている。複数（２つ）の半導体チップ２（第１の半導体チップおよび第２の半導体チップ）は所定間隔をあけて隣接している。複数の半導体チップ２としては、ＩＧＢＴ（Insulated Gate Bipolar Transistor）やＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）等を例示することができる。複数の半導体チップ２は、表面２１（第１表面の一例）及び裏面２２（第２表面の一例）を有している。複数の半導体チップ２は、表面側放熱板３１と裏面側放熱板３２の間に配置されている。複数の半導体チップ２で発生した熱が表面側放熱板３１及び裏面側放熱板３２に伝達されて外部に放熱される。複数の半導体チップ２にはボンディングワイヤを介して小信号用の端子が接続される（図示省略）。   The plurality of semiconductor chips 2 are arranged side by side at intervals. In this embodiment, two semiconductor chips 2 are used. A plurality (two) of semiconductor chips 2 (first semiconductor chip and second semiconductor chip) are adjacent to each other with a predetermined interval. Examples of the plurality of semiconductor chips 2 include IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). The plurality of semiconductor chips 2 have a front surface 21 (an example of a first surface) and a back surface 22 (an example of a second surface). The plurality of semiconductor chips 2 are disposed between the front surface side heat radiating plate 31 and the back surface side heat radiating plate 32. The heat generated in the plurality of semiconductor chips 2 is transmitted to the front surface side heat radiating plate 31 and the back surface side heat radiating plate 32 and radiated to the outside. Small signal terminals are connected to the plurality of semiconductor chips 2 via bonding wires (not shown).

半導体チップ２と表面側放熱板３１との間にはスペーサー８が配置されている。スペーサー８は、例えば銅（Ｃｕ）等の金属から形成されており、導電性を有している。はんだ７は、裏面側放熱板３２と半導体チップ２との間、半導体チップ２とスペーサー８との間、およびスペーサー８と表面側放熱板３１との間にそれぞれ充填されている。これにより、半導体チップ２、スペーサー８、表面側放熱板３１及び裏面側放熱板３２が、はんだ７により固定されている。   A spacer 8 is disposed between the semiconductor chip 2 and the surface side heat radiating plate 31. The spacer 8 is made of a metal such as copper (Cu), for example, and has conductivity. The solder 7 is filled between the back surface side radiator plate 32 and the semiconductor chip 2, between the semiconductor chip 2 and the spacer 8, and between the spacer 8 and the front surface side radiator plate 31. As a result, the semiconductor chip 2, the spacer 8, the front surface side heat radiating plate 31, and the back surface side heat radiating plate 32 are fixed by the solder 7.

表面側放熱板３１（第１放熱板の一例）および裏面側放熱板３２（第２放熱板の一例）は、互いに間隔をあけた状態で縦方向（ｚ方向）に対向するように配置されている。図３に示すように、表面側放熱板３１は、平面視における形状が四角形である平板状の部材である。図示していないが、裏面側放熱板３２も、平面視における形状が四角形である平板状の部材である。表面側放熱板３１および裏面側放熱板３２には孔が形成されていない。表面側放熱板３１および裏面側放熱板３２は、例えば銅（Ｃｕ）やアルミニウム（Ａｌ）等の熱伝導性を有する金属により形成されている。表面側放熱板３１は、半導体チップ２の表面側に配置されており、半導体チップ２の上方を覆っている。裏面側放熱板３２は、半導体チップ２の裏面側に配置されており、半導体チップ２の下方を覆っている。表面側放熱板３１は、半導体チップ２の表面２１にはんだを介して固定されている。裏面側放熱板３２は、半導体チップ２の裏面２２にはんだを介して固定されている。表面側放熱板３１および裏面側放熱板３２の一方面は半導体チップ２側を向いており、他方面は外方を向いて露出している。表面側放熱板３１および裏面側放熱板３２は、半導体チップ２で発生した熱を外部に放熱する。表面側放熱板３１および裏面側放熱板３２は電極としての機能も有している。また、表面側放熱板３１および裏面側放熱板３２には、それぞれパワー端子が接続される（図示省略）。   The front side heat radiating plate 31 (an example of the first heat radiating plate) and the back surface side radiating plate 32 (an example of the second heat radiating plate) are arranged so as to face each other in the longitudinal direction (z direction) with a space therebetween. Yes. As shown in FIG. 3, the front-side heat radiating plate 31 is a flat plate member having a quadrangular shape in plan view. Although not shown, the back side heat radiating plate 32 is also a flat plate-like member having a quadrangular shape in plan view. No holes are formed in the front-side heat sink 31 and the back-side heat sink 32. The front-side heat sink 31 and the back-side heat sink 32 are formed of a metal having thermal conductivity such as copper (Cu) or aluminum (Al). The front side heat radiating plate 31 is disposed on the front side of the semiconductor chip 2 and covers the upper side of the semiconductor chip 2. The rear surface side heat sink 32 is disposed on the rear surface side of the semiconductor chip 2 and covers the lower side of the semiconductor chip 2. The front-side heat sink 31 is fixed to the surface 21 of the semiconductor chip 2 via solder. The back surface side heat sink 32 is fixed to the back surface 22 of the semiconductor chip 2 via solder. One surface of the front surface side heat radiating plate 31 and the back surface side heat radiating plate 32 faces the semiconductor chip 2 side, and the other surface is exposed facing outward. The front side heat radiating plate 31 and the back side heat radiating plate 32 radiate heat generated in the semiconductor chip 2 to the outside. The front surface side heat sink 31 and the back surface side heat sink 32 also have a function as an electrode. In addition, power terminals are connected to the front-side heat sink 31 and the back-side heat sink 32 (not shown).

表面側放熱板３１および裏面側放熱板３２の外部に露出した面には、冷却器９を取り付けることができる。冷却器９によって表面側放熱板３１および裏面側放熱板３２を介して半導体チップ２を冷却する。冷却器９と表面側放熱板３１および裏面側放熱板３２の間には、例えば絶縁板とグリスにより電気的な絶縁を取っている。半導体チップ２は、その表面側および裏面側から冷却される。冷却器９としては水冷式あるいは空冷式の公知の構成を用いることができる。   The cooler 9 can be attached to the surfaces exposed to the outside of the front surface side heat radiating plate 31 and the back surface side heat radiating plate 32. The semiconductor chip 2 is cooled by the cooler 9 through the front surface side heat radiating plate 31 and the back surface side heat radiating plate 32. Between the cooler 9 and the front surface side heat radiating plate 31 and the back surface side heat radiating plate 32, for example, an electric insulation is taken by an insulating plate and grease. The semiconductor chip 2 is cooled from the front side and the back side. As the cooler 9, a known structure of a water cooling type or an air cooling type can be used.

表面側放熱板３１と裏面側放熱板３２の間の封止樹脂５は、半導体チップ２の周囲に充填されており、半導体チップ２を覆っている。封止樹脂５は、表面側放熱板３１及び裏面側放熱板３２に密着している。封止樹脂５は例えばエポキシ樹脂などの封止用の公知の樹脂を用いることができる。封止樹脂５は、半導体チップ２を封止している。封止樹脂５には空洞４が形成されている。本実施形態では１つの空洞４が形成されている。また、封止樹脂５は薄肉部５１を有している。薄肉部５１は、空洞４と表面側放熱板３１の間及び空洞４と裏面側放熱板３２の間に形成されている。   The sealing resin 5 between the front surface side heat radiating plate 31 and the back surface side heat radiating plate 32 is filled around the semiconductor chip 2 and covers the semiconductor chip 2. The sealing resin 5 is in close contact with the front surface side heat radiating plate 31 and the back surface side heat radiating plate 32. As the sealing resin 5, for example, a known resin for sealing such as an epoxy resin can be used. The sealing resin 5 seals the semiconductor chip 2. A cavity 4 is formed in the sealing resin 5. In the present embodiment, one cavity 4 is formed. Further, the sealing resin 5 has a thin portion 51. The thin portion 51 is formed between the cavity 4 and the front surface side heat sink 31 and between the cavity 4 and the back surface side heat sink 32.

空洞４は、表面側放熱板３１と裏面側放熱板３２の間に形成されている。図２に示すように、空洞４は、表面側放熱板３１と裏面側放熱板３２に沿ってｙ方向に延びている。空洞４は、半導体チップ２の表面２１及び裏面２２と平行な方向（ｙ方向）に沿って直線状に延びている。空洞４は、放熱板３（表面側放熱板３１及び裏面側放熱板３２）の一端側から他端側に向かって延びている。空洞４は、封止樹脂５をｙ方向に貫通している。空洞４は、封止樹脂５の両端部で開口している。空洞４は、隣接する２つの半導体チップ２の間に形成されている。空洞４は、半導体チップ２より内側（一対の半導体チップ２が向かい合う側）に形成されている。空洞４は半導体チップ２に隣接している。空洞４の断面形状は、楕円形状に形成されている。空洞４の断面形状は特に限定されるものではなく、例えば円形状や長方形状などであってもよい。空洞４の内部は何も充填されていない。空洞４が形成されることにより封止樹脂５の厚みが薄くなっている部分に薄肉部５１が形成されている。   The cavity 4 is formed between the front surface side heat radiating plate 31 and the back surface side heat radiating plate 32. As shown in FIG. 2, the cavity 4 extends in the y direction along the front surface side heat radiating plate 31 and the back surface side heat radiating plate 32. The cavity 4 extends linearly along a direction (y direction) parallel to the front surface 21 and the back surface 22 of the semiconductor chip 2. The cavity 4 extends from one end side to the other end side of the heat radiating plate 3 (the front surface side heat radiating plate 31 and the back surface side heat radiating plate 32). The cavity 4 penetrates the sealing resin 5 in the y direction. The cavity 4 is open at both ends of the sealing resin 5. The cavity 4 is formed between two adjacent semiconductor chips 2. The cavity 4 is formed inside the semiconductor chip 2 (on the side where the pair of semiconductor chips 2 face each other). The cavity 4 is adjacent to the semiconductor chip 2. The cross-sectional shape of the cavity 4 is formed in an elliptical shape. The cross-sectional shape of the cavity 4 is not particularly limited, and may be, for example, a circular shape or a rectangular shape. The inside of the cavity 4 is not filled with anything. A thin portion 51 is formed in a portion where the thickness of the sealing resin 5 is reduced by forming the cavity 4.

次に上述の半導体装置を製造する方法について説明する。半導体装置を製造するときはまず、複数の半導体チップ２と、半導体チップ２にはんだ７を介して接合された放熱板３（表面側放熱板３１および裏面側放熱板３２）とを備えるモジュールを準備する（準備工程）。半導体チップ２及び放熱板３（表面側放熱板３１および裏面側放熱板３２）の構成については上述したので説明を省略する。   Next, a method for manufacturing the above-described semiconductor device will be described. When manufacturing a semiconductor device, a module including a plurality of semiconductor chips 2 and a heat radiating plate 3 (surface-side heat radiating plate 31 and back-side heat radiating plate 32) joined to the semiconductor chip 2 via solder 7 is first prepared. (Preparation process). Since the configurations of the semiconductor chip 2 and the heat sink 3 (the front side heat sink 31 and the back side heat sink 32) have been described above, the description thereof will be omitted.

次に、図３、図４及び図５に示すように、半導体チップ２、表面側放熱板３１、および裏面側放熱板３２を備えるモジュール６０を成形型１００にセットする（セット工程）。成形型１００は、金属の上型１０１と、金属の下型１０２と、金属の中型１０３を備えている。上型１０１と下側１０２を閉じると、収容室１１０が形成される。また、上型１０１と下側１０２には、中型挿入口１０５が形成されている。中型挿入口１０５には、樹脂製のシール材１０４が設置されている。中型１０３は、柱形状を有している。中型１０３の断面形状は、空洞４と同様の楕円形状となっている。中型１０３は、中型挿入口１０５を通じて収容室１１０内に挿入される。図４に示すように、中型１０３は、収容室１１０を貫通するように配置される。   Next, as shown in FIGS. 3, 4, and 5, the module 60 including the semiconductor chip 2, the front-side heat radiating plate 31, and the back-side heat radiating plate 32 is set in the mold 100 (setting process). The mold 100 includes a metal upper mold 101, a metal lower mold 102, and a metal middle mold 103. When the upper mold 101 and the lower side 102 are closed, a storage chamber 110 is formed. In addition, a middle mold insertion port 105 is formed in the upper mold 101 and the lower side 102. A resin-made sealing material 104 is installed in the middle mold insertion port 105. The middle mold 103 has a column shape. The cross-sectional shape of the middle mold 103 is an elliptical shape similar to that of the cavity 4. The middle mold 103 is inserted into the accommodation chamber 110 through the middle mold insertion port 105. As shown in FIG. 4, the middle mold 103 is disposed so as to penetrate the accommodation chamber 110.

セット工程では、図３に示すように、上型１０１が表面側放熱板３１の上に配置され、下型１０２が表面側放熱板３１の下に配置されるように、モジュール６０を収容室１１０内に配置する。表面側放熱板３１が上型１０１の内面に密着し、裏面側放熱板３２が下型１０２の内面に密着する。また、図５に示すように、中型挿入口１０５（すなわち、シール材１０４の内孔）を通して収容室１１０内に中型１０３を挿入することで、収容室１１０内に中型１１０を配置する。ここでは、図３に示すように、中型１０３は、隣接する２つの半導体チップ２の間に配置される。また、中型１０３は、表面側放熱板３１と裏面側放熱板３２の間に配置される。図４に示すように、中型１０３は、表面側放熱板３１と裏面側放熱板３２に沿って（ｙ方向）に延びるように配置される。中型１０３の長さは表面側放熱板３１及び裏面側放熱板３２の長さより長いので、放熱板３１、３２の両端部から中型１０３の端部が突出する。図２に示すように、中型１０３は、表面側放熱板３１及び裏面側放熱板３２から離間した位置に配置される。すなわち、中型１０３と表面側放熱板３１の間に隙間１５１が形成され、中型１０３と裏面側放熱板３２との間に隙間１５１が形成される。   In the setting step, as shown in FIG. 3, the module 60 is accommodated in the housing chamber 110 so that the upper mold 101 is disposed on the surface side heat sink 31 and the lower mold 102 is disposed below the surface side heat sink 31. Place in. The front-side heat sink 31 is in close contact with the inner surface of the upper mold 101, and the rear-surface heat sink 32 is in close contact with the inner surface of the lower mold 102. In addition, as shown in FIG. 5, the middle mold 110 is placed in the storage chamber 110 by inserting the middle mold 103 into the storage chamber 110 through the middle mold insertion port 105 (that is, the inner hole of the sealing material 104). Here, as shown in FIG. 3, the middle mold 103 is disposed between two adjacent semiconductor chips 2. The middle mold 103 is disposed between the front surface side heat radiating plate 31 and the back surface side heat radiating plate 32. As shown in FIG. 4, the middle mold 103 is disposed so as to extend in the y direction along the front surface side heat radiating plate 31 and the back surface side heat radiating plate 32. Since the length of the middle mold 103 is longer than the lengths of the front surface side heat sink 31 and the back surface heat sink 32, the end portions of the middle mold 103 protrude from both end portions of the heat sinks 31 and 32. As shown in FIG. 2, the middle mold 103 is disposed at a position separated from the front surface side heat radiating plate 31 and the back surface side heat radiating plate 32. That is, a gap 151 is formed between the middle mold 103 and the front surface side heat sink 31, and a gap 151 is formed between the middle mold 103 and the back surface side heat sink 32.

モジュール６０に対して成形型１００を配置した後、図３に示すように、成形型１００の内部に封止樹脂５を充填して半導体チップ２を封止する（封止工程）。封止樹脂５は、注入口１０６から収容室１１０に注入される。注入された封止樹脂５は、表面側放熱板３１と裏面側放熱板３２の間に充填される。また、半導体チップ２の周囲に充填され、半導体チップ２を封止する。また、封止樹脂５は、中型１０３の周囲に充填され、中型１０３を覆う。なお、中型挿入口１０５では、シール材１０４によって封止樹脂５の漏出が防止される。上型１０１と下型１０２が封止樹脂５の外形を画定し、中型１０３により空洞４が形成される。封止樹脂５は、時間が経過すると硬化する。封止工程により、半導体チップ２が封止樹脂５で封止されると共に、中型１０３の形状に対応する空洞４が封止樹脂５に形成される。   After the mold 100 is arranged with respect to the module 60, as shown in FIG. 3, the inside of the mold 100 is filled with the sealing resin 5 to seal the semiconductor chip 2 (sealing process). The sealing resin 5 is injected into the storage chamber 110 from the injection port 106. The injected sealing resin 5 is filled between the front surface side heat radiating plate 31 and the back surface side heat radiating plate 32. Further, the periphery of the semiconductor chip 2 is filled, and the semiconductor chip 2 is sealed. The sealing resin 5 is filled around the middle mold 103 and covers the middle mold 103. Note that the sealing resin 104 prevents leakage of the sealing resin 5 at the middle-sized insertion port 105. The upper mold 101 and the lower mold 102 define the outer shape of the sealing resin 5, and the cavity 4 is formed by the middle mold 103. The sealing resin 5 is cured with time. Through the sealing process, the semiconductor chip 2 is sealed with the sealing resin 5, and the cavity 4 corresponding to the shape of the middle mold 103 is formed in the sealing resin 5.

続いて、封止樹脂５から中型１０３を引き抜く（引抜工程）。封止樹脂５から中型１０３を引き抜き易くするために、中型１０３の表面に離型剤を塗布しておいてもよい。離型剤としては、例えばフッ素系やシリコン系の離型剤を用いることができる。中型１０３を引き抜くことにより、中型１０３が配置されていた部分に中型１０３の形状に対応した空洞４が形成される。さらに、成形型１００を開いて、成形品を取り出す。これにより、封止樹脂５に空洞４が形成された半導体装置１が製造される。   Subsequently, the middle mold 103 is extracted from the sealing resin 5 (extraction process). In order to make it easy to pull out the middle mold 103 from the sealing resin 5, a release agent may be applied to the surface of the middle mold 103. As the release agent, for example, a fluorine-based or silicon-based release agent can be used. By pulling out the middle mold 103, the cavity 4 corresponding to the shape of the middle mold 103 is formed in the portion where the middle mold 103 is disposed. Further, the mold 100 is opened and the molded product is taken out. Thereby, the semiconductor device 1 in which the cavity 4 is formed in the sealing resin 5 is manufactured.

上述の説明から明らかなように、実施形態に係る半導体装置１によれば、封止樹脂５に空洞４が形成されているので、半導体チップ２と封止樹脂５との熱膨張率の差などにより応力が発生したとしても、空洞４により応力を逃がすことができる。よって、上述の半導体装置１によれば、封止樹脂５による応力を緩和することができる。また、半導体チップ２の表面側に接合された表面側放熱板３１及び裏面側に接合された裏面側放熱板３２により半導体チップ２を冷却することができる。これにより、半導体チップ２を表裏両面から冷却できるので、冷却性能を維持することができる。   As is clear from the above description, according to the semiconductor device 1 according to the embodiment, since the cavity 4 is formed in the sealing resin 5, the difference in thermal expansion coefficient between the semiconductor chip 2 and the sealing resin 5, etc. Even if stress is generated by the above, the stress can be released by the cavity 4. Therefore, according to the semiconductor device 1 described above, the stress caused by the sealing resin 5 can be relaxed. Further, the semiconductor chip 2 can be cooled by the front surface side heat radiating plate 31 bonded to the front surface side of the semiconductor chip 2 and the back surface side heat radiating plate 32 bonded to the back surface side. Thereby, since the semiconductor chip 2 can be cooled from both front and back surfaces, the cooling performance can be maintained.

また、空洞４と裏面側放熱板３２の間に薄肉部５１が存在することによって、裏面側放熱板３２と半導体チップ２を接合しているはんだ７を好適に保護することができる。また、表面側についても同様に、空洞４と表面側放熱板３１の間に薄肉部５１が存在することによって、表面側放熱板３１を接合するはんだ７を好適に保護することができる。また、隣接する半導体チップ２と半導体チップ２の間に空洞４が形成されているので、バランス良く応力を緩和することができる。   In addition, the presence of the thin portion 51 between the cavity 4 and the back surface side heat sink 32 can suitably protect the solder 7 that joins the back surface side heat sink 32 and the semiconductor chip 2. Similarly, on the surface side, the presence of the thin portion 51 between the cavity 4 and the surface side heat radiating plate 31 makes it possible to suitably protect the solder 7 that joins the surface side heat radiating plate 31. Further, since the cavity 4 is formed between the adjacent semiconductor chips 2 and the semiconductor chip 2, the stress can be relaxed in a well-balanced manner.

また、上述の半導体装置１の製造方法によれば、表面側放熱板３１と裏面側放熱板３２の間に中型１０３を配置して封止樹脂５を充填する。これにより、表面側放熱板３１及び裏面側放熱板３２を加工しなくても中型１０３の形状に応じた空洞４を封止樹脂５に形成することができる。表面側放熱板３１及び裏面側放熱板３２を加工しないので、冷却性能が低下することがない。   Moreover, according to the manufacturing method of the semiconductor device 1 described above, the middle mold 103 is disposed between the front surface side heat radiating plate 31 and the back surface side heat radiating plate 32 to fill the sealing resin 5. Thereby, the cavity 4 corresponding to the shape of the middle mold 103 can be formed in the sealing resin 5 without processing the front surface side heat radiating plate 31 and the back surface side heat radiating plate 32. Since the front surface side heat sink 31 and the back surface side heat sink 32 are not processed, the cooling performance does not deteriorate.

以上、一実施形態について説明したが、具体的な態様は上記実施形態に限定されるものではない。以下の説明において、上述の説明における構成と同様の構成については、同一の符号を付して説明を省略する。上記実施形態では隣接する半導体チップ２と半導体チップ２の間に空洞４が形成されていたが、この構成に限定されるものではない。例えば他の実施形態では、図６に示すように、半導体チップ２の外側に空洞４が形成されていてもよい。図６に示す例では、複数の空洞４が形成されており、一部の空洞４が半導体チップ２から外側に離間した位置に形成されている。この空洞４は、半導体チップ２と封止樹脂５の周縁部との間に形成されている。複数の空洞４が半導体チップ２を取り囲んでいる。また、このような空洞４を備える半導体装置１を製造するときは、セット工程において半導体チップ２の外側に中型１０３を配置する。   As mentioned above, although one embodiment was described, a specific mode is not limited to the above-mentioned embodiment. In the following description, the same components as those described above are denoted by the same reference numerals and description thereof is omitted. In the above embodiment, the cavity 4 is formed between the adjacent semiconductor chips 2, but the configuration is not limited to this. For example, in another embodiment, as shown in FIG. 6, the cavity 4 may be formed outside the semiconductor chip 2. In the example shown in FIG. 6, a plurality of cavities 4 are formed, and some of the cavities 4 are formed at positions spaced outward from the semiconductor chip 2. The cavity 4 is formed between the semiconductor chip 2 and the peripheral edge portion of the sealing resin 5. A plurality of cavities 4 surround the semiconductor chip 2. Further, when manufacturing the semiconductor device 1 having such a cavity 4, the middle mold 103 is disposed outside the semiconductor chip 2 in the setting process.

また、上記実施形態では隣接する半導体チップ２と半導体チップ２の間の空洞４が形成されていたが、半導体チップ２と半導体チップ２の間の空洞４を形成せずに省略することもできる。また、空洞４の数は限定されるものではなく、１つ又は複数の空洞４を形成することができる。   In the above embodiment, the cavity 4 between the adjacent semiconductor chips 2 and the semiconductor chip 2 is formed. However, the cavity 4 between the semiconductor chip 2 and the semiconductor chip 2 can be omitted without being formed. The number of cavities 4 is not limited, and one or a plurality of cavities 4 can be formed.

また、複数の空洞４を形成する場合は、図７及び図８に示すように、各空洞４が異なる方向に延びていてもよい。封止樹脂５には、ｘ方向に延びる空洞４およびｙ方向に延びる空洞４が形成されている。複数の空洞４は平面視において格子状に配置されている。ｘ方向の空洞４とｙ方向の空洞４は、平面視において交差しており（図７参照）、縦方向（ｚ方向）において離間している（図８参照）。交差する複数の空洞４を備える半導体装置１を製造するときは、型配置工程において複数の中型１０３を格子状に配置する。   When a plurality of cavities 4 are formed, the cavities 4 may extend in different directions as shown in FIGS. In the sealing resin 5, a cavity 4 extending in the x direction and a cavity 4 extending in the y direction are formed. The plurality of cavities 4 are arranged in a lattice shape in plan view. The x-direction cavity 4 and the y-direction cavity 4 intersect in plan view (see FIG. 7), and are separated in the longitudinal direction (z direction) (see FIG. 8). When manufacturing the semiconductor device 1 including a plurality of intersecting cavities 4, a plurality of middle dies 103 are arranged in a lattice shape in a mold arranging step.

また、上記実施形態では空洞４が封止樹脂５を貫通していたが、この構成に限定されるものではなく、空洞４は封止樹脂５を貫通していなくてもよい。この場合、図９に示すように、空洞４の先端部４１が封止樹脂５の内部で止まっている。空洞４は封止樹脂５の一端部から中央部まで直線状に延びている。空洞４は封止樹脂５の一端部で開口している。   In the above embodiment, the cavity 4 penetrates the sealing resin 5. However, the present invention is not limited to this configuration, and the cavity 4 may not penetrate the sealing resin 5. In this case, as shown in FIG. 9, the tip 41 of the cavity 4 is stopped inside the sealing resin 5. The cavity 4 extends linearly from one end of the sealing resin 5 to the center. The cavity 4 is opened at one end of the sealing resin 5.

また、図１０に示すように、空洞４をボンディングワイヤ７０の近傍に形成するときは、中型１０３を配置する位置を調整することにより、ボンディングワイヤ７０を避けた位置に空洞４を形成する。空洞４の位置とボンディングワイヤ７０の位置が重なっておらず、ボンディングワイヤ７０が封止樹脂５により封止されている。図１０に示す例では、空洞４は、ボンディングワイヤ７０と表面側放熱板３１の間に形成されている。   As shown in FIG. 10, when the cavity 4 is formed in the vicinity of the bonding wire 70, the cavity 4 is formed at a position avoiding the bonding wire 70 by adjusting the position where the middle mold 103 is arranged. The position of the cavity 4 and the position of the bonding wire 70 do not overlap, and the bonding wire 70 is sealed with the sealing resin 5. In the example shown in FIG. 10, the cavity 4 is formed between the bonding wire 70 and the surface-side heat radiating plate 31.

また、上記実施形態では、表面側放熱板３１と空洞４の間、及び、裏面側放熱板３２と空洞４の間の両方に封止樹脂５の薄肉部５１が形成されていたが、この構成に限定されるものではなく、片方のみに薄肉部５１が形成されている構成であってもよい。例えば、図１１に示すように、表面側放熱板３１と空洞４の間に薄肉部５１が形成されており、裏面側放熱板３２と空洞４の間に薄肉部５１が形成されておらず、裏面側放熱板３２と空洞４が接触していてもよい。あるいは反対に、裏面側放熱板３２と空洞４の間に薄肉部５１が形成され、表面側放熱板３１と空洞４が接触している構成であってもよい。このように、表面側放熱板３１及び裏面側放熱板３２の少なくとも一方と空洞４との間に封止樹脂５が充填されていればよい。   Moreover, in the said embodiment, although the thin part 51 of the sealing resin 5 was formed in both between the surface side heat sink 31 and the cavity 4, and between the back surface side heat sink 32 and the cavity 4, this structure It is not limited to this, The structure by which the thin part 51 is formed only in one side may be sufficient. For example, as shown in FIG. 11, the thin portion 51 is formed between the front surface side heat sink 31 and the cavity 4, and the thin portion 51 is not formed between the back surface side heat sink 32 and the cavity 4, The back surface side heat sink 32 and the cavity 4 may be in contact. Or conversely, the thin part 51 may be formed between the back surface side heat sink 32 and the cavity 4, and the structure by which the surface side heat sink 31 and the cavity 4 are contacting may be sufficient. As described above, it is only necessary that the sealing resin 5 is filled between the cavity 4 and at least one of the front surface side heat radiating plate 31 and the back surface side heat radiating plate 32.

また、このような半導体装置１を製造するときは、セット工程において、表面側放熱板３１及び裏面側放熱板３２の少なくとも一方と中型１０３との間に隙間１５１が形成されるように中型１０３を配置する。例えば、中型１０３を表面側放熱板３１から離間すると共に裏面側放熱板３２に接触する位置に配置する。すなわち、表面側放熱板３１と中型１０３との間に隙間１５１が形成されると共に裏面側放熱板３２と中型１０３との間に隙間１５１が形成されないように中型１０３を配置する。これにより、中型１０３に対応する空洞４が形成されたときに、表面側放熱板３１と空洞４の間に封止樹脂５の薄肉部５１が形成される。一方、裏面側放熱板３２と空洞４の間に薄肉部５１が形成されない。   Further, when manufacturing such a semiconductor device 1, in the setting step, the middle mold 103 is formed such that a gap 151 is formed between at least one of the front-side heat sink 31 and the rear-surface heat sink 32 and the middle mold 103. Deploy. For example, the middle mold 103 is disposed at a position that is separated from the front surface side heat radiating plate 31 and contacts the back surface side heat radiating plate 32. That is, the middle mold 103 is arranged so that a gap 151 is formed between the front surface side heat sink 31 and the middle mold 103 and a gap 151 is not formed between the rear surface side heat sink 32 and the middle mold 103. Thereby, when the cavity 4 corresponding to the middle mold 103 is formed, the thin portion 51 of the sealing resin 5 is formed between the front-side heat sink 31 and the cavity 4. On the other hand, the thin-walled portion 51 is not formed between the rear surface side heat sink 32 and the cavity 4.

以上、本発明の具体例を詳細に説明したが、これらは例示に過ぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。本明細書または図面に説明した技術要素は、単独であるいは各種の組合せによって技術的有用性を発揮するものであり、出願時請求項記載の組合せに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成し得るものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。   Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

１；半導体装置
２；半導体チップ
３；放熱板
４；空洞
５；封止樹脂
７；はんだ
８；スペーサー
９；冷却器
２１；表面
２２；裏面
３１；表面側放熱板
３２；裏面側放熱板
４１；先端部
５１；薄肉部
６０；モジュール
７０；ボンディングワイヤ
１００；成形型
１０１；上型
１０２；下型
１０３；中型
１０４；シール材
１０５；中型挿入口
１０６；注入口
１１０；収容室
１５１；隙間 DESCRIPTION OF SYMBOLS 1; Semiconductor device 2; Semiconductor chip 3; Heat sink 4; Cavity 5; Sealing resin 7; Solder 8; Spacer 9; Tip part 51; Thin part 60; Module 70; Bonding wire 100; Mold 101; Upper mold 102; Lower mold 103; Middle mold 104; Sealing material 105; Middle mold insertion port 106;

Claims (7)

第１表面と前記第１表面の反対側に位置する第２表面とを有する第１の半導体チップと、
前記第１の半導体チップに所定間隔をあけて隣接する第２の半導体チップと、
前記第１表面にはんだを介して接合された第１放熱板と、
前記第２表面にはんだを介して接合された第２放熱板と、
前記第１放熱板と前記第２放熱板の間に充填されて前記半導体チップを封止する封止樹脂であって、隣接する２つの前記半導体チップの間に前記第１放熱板及び前記第２放熱板に沿って延びるように空洞が形成されており、端部で前記空洞が開口している封止樹脂と、を備え、
前記封止樹脂に空洞が複数形成されており、
複数の前記空洞が前記半導体チップを取り囲んでいる、半導体装置。 A first semiconductor chip having a first surface and a second surface located opposite to the first surface;
A second semiconductor chip adjacent to the first semiconductor chip at a predetermined interval;
A first heat radiating plate joined to the first surface via solder;
A second heat radiating plate joined to the second surface via solder;
A sealing resin that is filled between the first heat radiation plate and the second heat radiation plate to seal the semiconductor chip, the first heat radiation plate and the second heat radiation plate between two adjacent semiconductor chips. A cavity is formed so as to extend along the edge, and a sealing resin in which the cavity is open at an end , and
A plurality of cavities are formed in the sealing resin,
A semiconductor device , wherein the plurality of cavities surround the semiconductor chip . 前記第１放熱板と前記空洞との間に前記封止樹脂が存在している、請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the sealing resin is present between the first heat radiation plate and the cavity. 前記空洞が前記封止樹脂を貫通しており、前記封止樹脂の両端部で開口している、請求項１又は２に記載の半導体装置。   The semiconductor device according to claim 1, wherein the cavity penetrates the sealing resin and opens at both ends of the sealing resin. 前記空洞が前記封止樹脂を貫通しておらず、前記封止樹脂の一端部で開口している、請求項１又は２に記載の半導体装置。   The semiconductor device according to claim 1, wherein the cavity does not penetrate the sealing resin and opens at one end of the sealing resin. 第１表面と前記第１表面の反対側に位置する第２表面を有する複数の半導体チップと、前記第１表面にはんだを介して接合された第１放熱板と、前記第２表面にはんだを介して接合された第２放熱板と、を備えるモジュールを成形型にセットするセット工程であって、前記成形型が備える中型が、隣接する２つの前記半導体チップの間において前記第１放熱板と前記第２放熱板の間に配置され、前記第１放熱板及び前記第２放熱板に沿って延びるように前記モジュールをセットするセット工程と、
前記成形型にセットされた前記モジュールの前記第１放熱板と前記第２放熱板の間に封止樹脂を充填して前記半導体チップを封止する封止工程と、を備え、
前記成形型が中型を複数備えており、
前記セット工程では、複数の前記中型が前記半導体チップを取り囲んで配置される、半導体装置の製造方法。 A plurality of semiconductor chips having a first surface and a second surface located on the opposite side of the first surface, a first heat radiating plate joined to the first surface via solder, and solder on the second surface A module including a second heat radiating plate joined to the molding die, wherein the middle die provided in the molding die is located between the two adjacent semiconductor chips and the first heat radiating plate. A setting step of setting the module so as to be disposed between the second heat radiation plate and extend along the first heat radiation plate and the second heat radiation plate;
A sealing step of sealing the semiconductor chip by filling a sealing resin between the first heat dissipation plate and the second heat dissipation plate of the module set in the mold ,
The mold includes a plurality of middle molds;
In the setting step, a plurality of the middle dies are disposed so as to surround the semiconductor chip . 前記セット工程では、前記中型は、前記第１放熱板との間に隙間を形成するように配置される、請求項５に記載の半導体装置の製造方法。 6. The method of manufacturing a semiconductor device according to claim 5 , wherein, in the setting step, the middle mold is disposed so as to form a gap with the first heat radiating plate. 前記封止樹脂から前記中型を引き抜く引抜工程を更に備える、請求項５又は６に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 5 , further comprising a drawing step of drawing the middle mold from the sealing resin.
JP2014034541A 2014-02-25 2014-02-25 Semiconductor device and manufacturing method thereof Expired - Fee Related JP6136978B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2014034541A JP6136978B2 (en) 2014-02-25 2014-02-25 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2014034541A JP6136978B2 (en) 2014-02-25 2014-02-25 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2015159256A JP2015159256A (en) 2015-09-03
JP6136978B2 true JP6136978B2 (en) 2017-05-31

Family

ID=54183038

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014034541A Expired - Fee Related JP6136978B2 (en) 2014-02-25 2014-02-25 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP6136978B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7155748B2 (en) * 2018-08-22 2022-10-19 株式会社デンソー semiconductor equipment

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10144821A (en) * 1996-11-11 1998-05-29 Rohm Co Ltd Resin packaged semiconductor device and manufacturing method thereof
JP2002170850A (en) * 2000-11-30 2002-06-14 Matsushita Electric Ind Co Ltd Electronic component packaging structure and manufacturing method thereof
US20060076694A1 (en) * 2004-10-13 2006-04-13 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device package with concavity-containing encapsulation body to prevent device delamination and increase thermal-transferring efficiency
JP4407489B2 (en) * 2004-11-19 2010-02-03 株式会社デンソー Semiconductor device manufacturing method and semiconductor device manufacturing apparatus
JP5076549B2 (en) * 2007-02-23 2012-11-21 株式会社デンソー Semiconductor device
JP2009253206A (en) * 2008-04-10 2009-10-29 Sharp Corp Resin sealed semiconductor device and its mounting structure
DE112011105693T5 (en) * 2011-09-29 2014-08-21 Toyota Jidosha Kabushiki Kaisha Semiconductor device
JP5737272B2 (en) * 2012-11-14 2015-06-17 トヨタ自動車株式会社 Semiconductor device
JP6083399B2 (en) * 2014-02-25 2017-02-22 トヨタ自動車株式会社 Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
JP2015159256A (en) 2015-09-03

Similar Documents

Publication Publication Date Title
JP6083399B2 (en) Semiconductor device and manufacturing method thereof
CN106463420B (en) Power semiconductor device and its manufacturing method
JP4899481B2 (en) Manufacturing method of resin-encapsulated semiconductor device having a heat radiator exposed outside
CN105552039B (en) Electronic device and manufacturing method with the encapsulating structure for improving electric accessibility
JP5747737B2 (en) Semiconductor device and manufacturing method thereof
JP5955251B2 (en) Power semiconductor module
US9390995B2 (en) Semiconductor device and method of manufacturing the same
WO2012137439A1 (en) Encapsulated semiconductor device and method for producing same
KR101359188B1 (en) Power semiconductor device
JP2006222347A (en) Semiconductor module and manufacturing method thereof
JP5910653B2 (en) Lead frame with heat sink, method of manufacturing lead frame with heat sink, semiconductor device, and method of manufacturing semiconductor device
CN103824830A (en) Chip arrangements and methods for manufacturing chip arrangement
CN111373527B (en) Semiconductor device with a semiconductor device having a plurality of semiconductor chips
JP5267238B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP2016072354A (en) Power module
JP6136978B2 (en) Semiconductor device and manufacturing method thereof
TWI730499B (en) Heat spreading plate
KR101255930B1 (en) Power Module Package and Method for Manufacturing the same
JP2015185835A (en) Semiconductor device and manufacturing method of the same
TW201546991A (en) Power device
US20090212446A1 (en) Semiconductor Device
JP6588154B2 (en) Case, semiconductor device, and method of manufacturing case
JP4334296B2 (en) Method for manufacturing hybrid integrated circuit device
JP5062189B2 (en) Mounting structure of semiconductor device
JP7118839B2 (en) POWER UNIT, POWER UNIT MANUFACTURING METHOD AND ELECTRICAL DEVICE HAVING POWER UNIT

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20160309

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20170130

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20170221

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170313

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20170404

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20170417

R151 Written notification of patent or utility model registration

Ref document number: 6136978

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees