JP6127168B2 - Liquid crystal display - Google Patents

Description

The present invention relates to a semiconductor device having a circuit in which an inverted staggered type or bottom gate type thin film transistor (hereinafter abbreviated as TFT) using a semiconductor film and a manufacturing method thereof. In particular, the present invention provides a technique that can be suitably used for an electro-optical device typified by a liquid crystal display device and an electronic apparatus equipped with such an electro-optical device. Note that in this specification, a semiconductor device refers to all devices that function by utilizing semiconductor characteristics, and includes the above-described electro-optical device and an electronic apparatus in which the electro-optical device is mounted.

Currently, liquid crystal display devices are used to display image and text information in notebook personal computers (notebook personal computers) and portable information terminals.
Since the active matrix type liquid crystal display device can obtain a high-definition image as compared with the passive type liquid crystal display device, the latter is preferably used in the above applications. In an active matrix liquid crystal display device, TFTs which are active elements in a pixel portion are arranged in a matrix corresponding to each pixel. TFT is usually n-channel TF
T is used, and a desired image display is performed by controlling the voltage applied to the liquid crystal as a switching element for each pixel.

Some reverse stagger type (or bottom gate type) TFTs have an active layer formed for an amorphous semiconductor film. As the amorphous semiconductor material, an amorphous silicon film is preferably used. An amorphous silicon film is considered to be a material suitable for mass production because it can be formed on a large substrate at a low temperature of 300 ° C. or lower. However, a TFT in which an active layer is formed of an amorphous silicon film has a small field effect mobility, and only about 1 cm ² / Vsec is obtained. For this purpose, a drive circuit for displaying an image is formed of an LSI chip, and is a TAB (tape automated bonding) method or COG.
(Chip on glass) method.

Such an active matrix type liquid crystal display device is not limited to a notebook personal computer.
The application has expanded to the TV system of the type class, and the demand for higher definition and higher aperture ratio has been increased for the purpose of improving the image quality while increasing the screen size. For example, "" The
Development of Super-High Aperture Ratio with Low Electrically Resistive Materi
al for High-Resolution TFT-LCDs ", S. Nakabu, et al., 1999 SID International Sympos
ium Digest of Technical Papers, pp732-735 ”has a pixel density of UXGA (1600 × 1
200), a technique for manufacturing a 20-inch liquid crystal display device is reported.

In order to supply such products to the market and disseminate them, it becomes a challenge to simultaneously improve productivity and reduce costs, and to increase reliability. An active matrix type liquid crystal display device uses a plurality of photomasks and TFTs by photolithography
On the substrate. In order to improve productivity and improve yield, reducing the number of steps is considered as an effective means.
Specifically, it is necessary to reduce the number of photomasks required for manufacturing TFTs. A photomask is used in photolithography to form a photoresist pattern as a mask for an etching process on a substrate. Therefore, the use of a single photomask means that resist coating, pre-baking, exposure, development, post-baking and the like, and steps before and after that, such as film formation and etching, resist stripping, cleaning, A drying process and the like are added, which is complicated.

The present invention is a technique for solving such a problem. In an electro-optical device typified by an active matrix liquid crystal display device and a semiconductor device, the number of steps for manufacturing TFTs can be reduced to reduce the manufacturing cost. The goal is to improve yield.

In order to solve the above problems, a semiconductor device of the present invention is an inverted staggered (or bottom gate type) T having a channel formation region formed of a semiconductor layer having an amorphous structure on a substrate.
A first interlayer insulating layer made of an inorganic material on the FT; a second interlayer insulating layer made of an organic material formed on the first interlayer insulating film; and the second interlayer insulating layer. And an input terminal portion that is formed along an end portion of the substrate and is electrically connected to a wiring of another substrate, and the input terminal portion is made of the same material as the gate electrode. It is characterized by being formed of a first layer and a second layer made of the same material as the pixel electrode. With such a configuration, the number of photomasks used in the photolithography technique can be five.

In another aspect of the invention, a first interlayer made of an inorganic material is formed on an inverted stagger type (or bottom gate type) TFT having a channel formation region formed of a semiconductor layer having an amorphous structure on a substrate. An insulating layer is provided, a pixel electrode formed in contact with the insulating layer formed on the gate electrode of the TFT, and an input formed along the edge of the substrate and electrically connected to the wiring of another substrate The input terminal portion is formed of a first layer made of the same material as the gate electrode and a second layer made of the same material as the pixel electrode. It is said.

According to another aspect of the invention, there is provided a first step of forming a gate electrode and a first layer of an input terminal portion electrically connected to a wiring on another substrate on a substrate having an insulating surface; A second step of forming a gate insulating layer on the gate electrode; a third step of forming a semiconductor layer having an amorphous structure on the gate insulating layer; and a semiconductor layer having the amorphous structure. A fourth step of forming a semiconductor layer containing an impurity of one conductivity type, a fifth step of forming a source wiring and a drain wiring in contact with the semiconductor layer containing an impurity of one conductivity type, and the source A sixth step of removing a part of the semiconductor layer containing an impurity of one conductivity type and a semiconductor layer having an amorphous structure using the wiring and the drain wiring as a mask; and an inorganic material on the source wiring and the drain wiring Forming a first interlayer insulating layer comprising A seventh step, an eighth step of forming a second interlayer insulating layer made of an organic material on the first interlayer insulating layer, the first interlayer insulating layer and the second interlayer insulating layer, A ninth step of selectively removing the gate insulating layer to expose the first layer of the input terminal portion; a pixel electrode on the second interlayer insulating film; and a second layer of the input terminal portion And a tenth step of forming the structure.

According to another aspect of the invention, there is provided a first step of forming a gate electrode and a first layer of an input terminal portion electrically connected to a wiring on another substrate on a substrate having an insulating surface; A second step of forming a gate insulating layer on the gate electrode; a third step of forming a semiconductor layer having an amorphous structure on the gate insulating layer; and a semiconductor layer having the amorphous structure. A fourth step of forming a semiconductor layer containing an impurity of one conductivity type, a fifth step of selectively removing the gate insulating layer to expose the first layer of the input terminal portion, and the gate A sixth step of forming a pixel electrode and a second layer of the input terminal portion in contact with the insulating layer; a first step of forming a source wiring and a drain wiring in contact with the semiconductor layer containing the impurity of one conductivity type; Step 7 and the source wiring and drain wiring as a mask An eighth step of removing a part of the semiconductor layer containing an impurity of one conductivity type and a semiconductor layer having an amorphous structure; and a first interlayer insulating layer made of an inorganic material on the source wiring and the drain wiring. And a ninth step of forming.

The top view and sectional drawing which show the manufacturing process of pixel TFT and an input terminal part. The top view and sectional drawing which show the manufacturing process of pixel TFT and an input terminal part. The top view and sectional drawing which show the manufacturing process of pixel TFT and an input terminal part. The top view and sectional drawing which show the manufacturing process of pixel TFT and an input terminal part. The top view and sectional drawing which show the manufacturing process of pixel TFT and an input terminal part. Sectional drawing which shows the structure of a liquid crystal display device. Sectional drawing which shows the mounting structure of a liquid crystal display device. Sectional drawing explaining the structure of a gate electrode. 4A and 4B illustrate a taper structure at an end portion of a gate electrode. FIG. 6 is a top view illustrating the arrangement of a pixel portion and an input terminal portion of a liquid crystal display device. Sectional drawing explaining the structure of an input terminal part. FIG. 11 illustrates an example of a semiconductor device.

  The embodiment of the present invention will be described in detail with reference to the following examples.

An embodiment of the present invention will be described with reference to FIGS. This embodiment shows a method for manufacturing a liquid crystal display device, and a method for forming a TFT of a pixel portion on a substrate in an inverted staggered type and manufacturing a storage capacitor connected to the TFT will be described in detail according to steps. In addition, the same drawing shows a process of manufacturing an input terminal portion provided at an end portion of the substrate and electrically connected to wiring of a circuit provided on another substrate. Here, in FIGS. 1A and 1B and FIGS. 2A and 2B, (I) is a top view, and a cross-sectional view along the line AA ′ is shown in (II).

In FIG. 1A, a glass substrate such as barium borosilicate glass or alumino borosilicate glass typified by Corning # 7059 glass or # 1737 glass can be used for the substrate 101. In addition, a stainless steel substrate or a ceramic substrate having a silicon oxide film or a silicon nitride film formed on the surface can also be used.

The gate electrode 102 and the gate wiring 102 ′, the storage capacitor wiring 103, and the terminal 104 of the input terminal portion are preferably formed of a low resistance conductive material such as aluminum (Al).
Al alone is inferior in heat resistance and easily corroded, so it is formed in combination with a heat resistant conductive material. Heat resistant conductive materials include titanium (Ti) and tantalum (Ta)
And an element selected from tungsten (W), an alloy containing the element as a component, an alloy film combining the elements, or a nitride containing the element as a component. Or you may form combining only such a heat resistant conductive material.

The selection of such a material is appropriately determined according to the screen size of the liquid crystal display device.
The heat-resistant conductive material has a sheet resistance of about 10Ω and can be applied if the screen size is up to about 5 inches, but is not necessarily suitable for a liquid crystal display device having a screen size larger than that. This is because the problem of wiring delay cannot be ignored if the routing length of the gate wiring connected to the gate electrode inevitably increases on the substrate. For example, when the pixel density is VGA, 4
80 gate wirings and 640 source wirings are formed. In the case of XGA, 768 gate wirings and 1024 source wirings are formed. The resistance of the gate wiring is determined by the film thickness and width of the wiring in addition to the specific resistance value of the material to be used, but it is naturally limited in consideration of the aperture ratio, and miniaturization is required as the pixel density increases. The The screen size of the display area is 13
The diagonal length is 340 mm for the inch class, and 46 for the 18 inch class.
0 mm. In that case, in order to realize the liquid crystal display device, it is originally desirable to form the gate wiring with a low-resistance conductive material such as Al.

Therefore, the gate electrode and the gate wiring are formed by combining a heat resistant conductive material and a low resistance conductive material. A suitable combination at this time will be described with reference to FIG. Screen size is 5
If it is up to the mold type, as shown in FIG. 8A, a conductive layer (A
) And a conductive layer (B) 802 made of a heat-resistant conductive material. The conductive layer (B) 802 may be formed using an element selected from Al, Ta, Ti, and W, an alloy containing the element as a component, or an alloy film combining the elements. A tantalum nitride (TaN) film, a tungsten nitride (WN) film, a titanium nitride (TiN) film, or the like is used. In order to adapt to a large screen, as shown in FIG. 8B, a conductive layer (A) 803 made of a nitride of a heat-resistant conductive material and a conductive layer (B) 804 made of a low-resistance conductive material, A conductive layer (C) 805 made of a nitride of a heat-resistant conductive material is laminated. The conductive layer (B) 804 made of a low-resistance conductive material is formed of a material containing aluminum (Al) as a component, and in addition to pure Al,
A containing 0.01 to 5 atomic% scandium (Sc), Ti, silicon (Si), etc.
l is used. The conductive layer (C) 805 has an effect of preventing hillocks from being generated in Al of the conductive layer (B) 804.

In FIG. 8A, the conductive layer (A) 801 has a thickness of 10 to 100 nm (preferably 20 to 50 nm).
nm), and the conductive layer (B) 802 has a thickness of 200 to 400 nm (preferably 250 to 350 nm).
). For example, when a W film is formed as a gate electrode, Ar gas and nitrogen (N ₂ ) gas are introduced by sputtering using W as a target, and the conductive layer (A) 801 is formed as a WN film by 50 n.
The conductive layer (B) 802 is formed with a W film to a thickness of 250 nm. But W
In order to use the film as a gate electrode, it is necessary to reduce the resistance, and the resistivity is 20 μm.
It is desirable to make it Ωcm or less. The resistivity of the W film can be reduced by increasing the crystal grains. However, when there are many impurity elements such as oxygen in W, crystallization is hindered and the resistance is increased. Therefore, when sputtering is used, a W target having a purity of 99.9999% is used, and the W film is formed with sufficient consideration so that impurities are not mixed in from the gas phase during film formation.
In particular, the oxygen concentration was preferably 30 ppm or less. For example, W has an oxygen concentration of 30
By setting it to ppm or less, a specific resistance value of 20 μΩcm or less can be realized.

On the other hand, in FIG. 8A, a TaN film is formed on the conductive layer (A) 801 and a TN film is formed on the conductive layer (B) 802.
When the a film is used, it can be similarly formed by sputtering. TaN film is Ta
As a target, a sputtering gas is formed using a mixed gas of Ar and nitrogen, and the Ta film uses Ar as a sputtering gas. In addition, when an appropriate amount of Xe or Kr is added to these sputtering gases, the internal stress of the film to be formed can be relaxed and the film can be prevented from peeling. α phase Ta
Although the resistivity of the film is about 20 μΩcm and can be used for a gate electrode, the resistivity of a β-phase Ta film is about 180 μΩcm, which is not suitable for a gate electrode. TaN film is α
Since it has a crystal structure close to the phase, an α-phase Ta film can be easily obtained by forming a Ta film thereon. In any case, the conductive layer (B) 802 is preferably formed with a resistivity in the range of 10 to 50 μΩcm.

8B, the conductive layer (A) 803 has a thickness of 10 to 100 nm (preferably 20 to 50 nm), and the conductive layer (B) 804 has a thickness of 200 to 400 nm (preferably 250).
To 350 nm), and the conductive layer (C) 805 is 10 to 100 nm (preferably 20 to 50 n).
m). Here, for the conductive layer (A) and the conductive layer (C), as described above, a WN film or a TaN film, or a Ti film, a Ta film, a W film, or the like, which is a heat-resistant conductive material, is applied. Conductive layer (B) 8
04 is also formed by sputtering, and is formed of an Al film containing 0.01 to 5 atomic% of Sc, Ti, Si, etc. in addition to pure Al.

The gate electrode 102, the gate wiring 102 ′, the storage capacitor wiring 103, and the terminal 104 are formed by forming a conductive mask on the entire surface of the substrate, performing a first photolithography process, forming a resist mask, and performing unnecessary portions by etching. Is formed. At this time, etching is performed so that a tapered portion is formed at least at the end portion of the gate electrode 102.

In order to etch a heat-resistant conductive material such as a W film or a Ta film at high speed and with high accuracy and further to make the end tapered, a dry etching method using high-density plasma is suitable. Microwave and inductively coupled plasma (Inductively Coup) are used to obtain high-density plasma.
An etching apparatus using LED Plasma (ICP) is suitable. In particular, the ICP etching apparatus can easily control the plasma and can cope with an increase in the area of the processing substrate. For example, as specific etching conditions for the W film, a mixed gas of CF ₄ and Cl ₂ is used as the etching gas, the flow rate is 30 SCCM, the discharge power is 3.2 W / cm ² (13.56 MHz), the substrate bias power is 224 mW / Etching is performed at cm ² (13.56 MHz) and a pressure of 1.0 Pa. Under such etching conditions, a tapered portion whose thickness gradually increases from the end toward the inside is formed at the end of the gate electrode 102, and the angle is 1 to 20 °, preferably 5 to 15 °. And
As shown in FIG. 9, the angle of the tapered portion at the end of the gate electrode 102 is the angle of the portion indicated as θ. The angle θ of the tapered portion is represented by Tan (θ) = HG / WG using the length (WG) of the tapered portion and the thickness (HG) of the tapered portion.

Thus, the gate electrode 102 and the gate wiring 102 ′, the storage capacitor wiring 103, the terminal 1
After forming 04, an insulating film is formed on the entire surface to form a gate insulating layer. The gate insulating layer 105 is formed using an insulating film with a film thickness of 50 to 200 nm by plasma CVD or sputtering. For example, it is formed from a silicon oxynitride film with a thickness of 150 nm. In addition, a silicon oxynitride film manufactured by adding O ₂ to SiH ₄ and N ₂ O is a preferable material for this application because the fixed charge density in the film is reduced. Of course, the gate insulating layer is not limited to such a silicon oxynitride film, and other insulating films such as a silicon oxide film, a silicon nitride film, and a tantalum oxide film are used, and a single layer or a stacked layer made of these materials is used. It may be formed as a structure. For example, when a silicon oxide film is used, tetraethyl orthosilicate (TEOS) and O ₂ are mixed by a plasma CVD method, and the reaction pressure is 4
0 Pa, substrate temperature 250-350 ° C., high frequency (13.56 MHz) power density 0.5-0.
It can be formed by discharging at 8 W / cm ² . The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating layer by thermal annealing at 300 to 400 ° C. thereafter.

Next, 50 to 200 nm (preferably 100 to 150 nm) is formed on the gate insulating layer.
A semiconductor layer having an amorphous structure with a thickness of 5 mm is formed on the entire surface by a known method such as plasma CVD or sputtering (not shown). Typically, a hydrogenated amorphous silicon (a-Si: H) film is formed to a thickness of 100 nm by a plasma CVD method. In addition, a compound semiconductor film having an amorphous structure such as a microcrystalline semiconductor film or an amorphous silicon germanium film can be applied to the semiconductor layer having an amorphous structure. Further, an n-type semiconductor film is formed to a thickness of 20 to 80 nm as a semiconductor layer containing one conductivity type impurity element. For example, an n-type a-Si: H film may be formed, and for that purpose, 0.1 to 5% with respect to silane (SiH ₄ ).
Add phosphine (PH ₃ ) at a concentration of Alternatively, the n-type semiconductor film may be formed using a hydrogenated microcrystalline silicon film (μc-Si: H).

A gate insulating film, a semiconductor layer having an amorphous structure, and a semiconductor layer containing an impurity element having one conductivity type are each formed by a known method, and can be manufactured by a plasma CVD method or a sputtering method. These films can be formed continuously by appropriately switching the reaction gas in the case of the plasma CVD method and by appropriately switching the target and the sputtering gas in the case of the sputtering method. That is, in a plasma CVD apparatus or a sputtering apparatus, the same reaction chamber or a plurality of reaction chambers can be used, and these films can be continuously stacked without being exposed to the atmosphere.

Then, the semiconductor layer formed as described above is subjected to a second photolithography process and subjected to patterning, so that an island shape is formed so as to partially overlap with the gate electrode 102 as illustrated in FIG. A semiconductor layer 106 is formed. The island-shaped semiconductor layer includes the amorphous semiconductor layer 106a and n
A semiconductor layer 106b of a type.

Then, a conductive metal layer is formed by a sputtering method or a vacuum evaporation method, a resist mask pattern is formed by a third photolithography process, and etching is performed to form a source wiring 107 and a drain wiring 108 as shown in FIG. Then, the storage capacitor wiring 109 is formed. Although not shown, in this embodiment, this wiring is formed by forming a Ti film with a thickness of 50 to 150 nm and making contact with an n-type semiconductor film that forms the source or drain region of the island-shaped semiconductor layer. The Ti
Aluminum over the film (Al)
Is formed with a thickness of 300 to 400 nm, and a Ti film is further formed thereon with a thickness of 100 to 150 nm.

In the input terminal portion connected to the source wiring, the wiring 110 is formed on the gate insulating layer so as to match the input terminal portion. Although this state is omitted in FIG. 2A, the wiring 110 is shown.
Extends on the gate insulating layer and is connected to the source wiring.

(II) in FIG. 2A using the source wiring 107 and the drain wiring 108 as a mask.
As shown in FIG. 2, the n-type semiconductor layer 106b and part of the amorphous semiconductor layer 106a are removed by etching to form an opening 111 in the island-shaped semiconductor layer. The n-type semiconductor layer 106b is separated into the source region 112 and the drain region 113 by the opening 111, and a channel formation region is formed in the island-shaped semiconductor layer 106 in a self-aligning manner.

After that, as shown in (II) of FIG. 2B, an inorganic material which covers the hole 111 and is in contact with at least a part of the channel formation region over the semiconductor layer having an amorphous structure and the n-type semiconductor layer. A first interlayer insulating layer 114 made of is formed. The first interlayer insulating film 114 is a silicon oxide film,
A silicon oxynitride film, a silicon nitride film, or a stacked film formed by combining these films is formed.
The film thickness of the first interlayer insulating film 114 is 100 to 200 nm. For example, in the case where the first interlayer insulating film 114 is formed of a silicon oxide film, TEOS and O ₂ are mixed by a plasma CVD method to a reaction pressure of 40 Pa, a substrate temperature of 200 to 300 ° C., and a high frequency (13.56 MHz). )
It can be formed by discharging at a power density of 0.5 to 0.8 W / cm ² . In the case of using a silicon oxynitride film, a silicon oxynitride film manufactured from SiH ₄ , N ₂ O, and NH ₃ by a plasma CVD method or a silicon oxynitride film manufactured from SiH ₄ and N ₂ O is used. What is necessary is just to form. The production conditions in this case are a reaction pressure of 20 to 200 Pa, a substrate temperature of 200 to 300 ° C., and a high frequency (60 MHz) power density of 0.1 to 1.0 W / cm ² . Si
A silicon oxynitride silicon film formed from H ₄ , N ₂ O, and H ₂ may be used. Similarly, the silicon nitride film can be formed from SiH ₄ and NH ₃ by plasma CVD.

Further, a second interlayer insulating layer 1 made of an organic material formed on the first interlayer insulating film 114.
15 is formed with an average thickness of 1.0 to 2.0 μm. As the organic resin material, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. For example, in the case of using a type of polyimide that is thermally polymerized after being applied to the substrate, it is formed by baking at 200 to 300 ° C. in a clean oven. When acrylic is used, a two-component type is used, and after mixing the main material and the curing agent, applying the entire surface of the substrate using a spinner, preheating at 80 ° C. for 60 seconds with a hot plate. It can be formed by baking in a clean oven at 180 to 250 ° C. for 60 minutes.

Thus, the surface can be satisfactorily planarized by forming the second interlayer insulating film 114 from an organic insulating material. In addition, since the organic resin material generally has a low dielectric constant, parasitic capacitance can be reduced. However, since it is hygroscopic and is not suitable as a protective film, a silicon oxide film, a silicon oxynitride film formed as the first interlayer insulating film 114, as in this embodiment,
It may be used in combination with a silicon nitride film or the like.

Thereafter, a fourth photolithography step is performed to form a resist mask having a predetermined pattern, and contact holes reaching the source region or the drain region formed in each island-shaped semiconductor layer are formed. Contact holes are formed by dry etching.
In this case, the second interlayer insulating film 115 made of an organic resin material is first etched using a mixed gas of CF ₄ , O ₂ and He as an etching gas, and then the etching gas is changed to CF ₄ , O _2.
As a result, the first interlayer insulating film 114 is etched. In the input terminal portion, the second interlayer insulating film 115, the first interlayer insulating film 114, and a part of the gate insulating layer 105 are etched so that the terminal 104 and a part of the wiring 110 are exposed.

Then, a transparent conductive film is formed to a thickness of 50 to 200 nm by a sputtering method or a vacuum evaporation method, and a fifth photolithography step is performed to form a pixel electrode 118 as shown in FIG. The pixel electrode 118 is connected to the drain wiring 108 at the connection portion 116, and is connected to the storage capacitor electrode 109 at the connection portion 117. At the same time, a transparent conductive film 119 is provided so that the terminal 104 and the wiring 110 are at least partially in contact with each other. FIG. 11A shows details of a cross section of the BB ′ cross section seen in the direction of the arrow shown in FIG. In the figure, the gate electrode 104 is composed of a conductive layer (A) 130 and a conductive layer (B) 131, and the transparent conductive film 119 is in contact with at least part of the conductive layer (A) 130 and the conductive layer (B) 131. Form. Also,
FIG. 11B shows details of a cross section when the CC ′ cross section is viewed in the direction of the arrow shown in FIG. 2B. The wiring 110 has a three-layer structure of a Ti film 132, an Al film 133, and a Ti film 134, and the transparent conductive film 119 is formed so that at least a part thereof is in contact with these films. In this way, the terminal 104 and the wiring 110 are electrically connected.
However, it is not necessary to provide the wiring 110 in the input terminal portion connected to the gate wiring.
A transparent conductive film 119 is provided so as to be in contact with at least a part of 4.

The material of the transparent conductive film is indium oxide (In ₂ O ₃ ) or indium oxide tin oxide alloy (I
n ₂ O ₃ —SnO ₂ , abbreviated as ITO) or the like is formed using a sputtering method, a vacuum deposition method, or the like. Etching treatment of such a material is performed with a hydrochloric acid based solution. But especially ITO
In this etching, a residue is likely to be generated. Therefore, an indium oxide-zinc oxide alloy (In ₂ O ₃ —ZnO) may be used to improve etching processability. Since the indium oxide-zinc oxide alloy has excellent surface smoothness and thermal stability as compared with ITO, it can prevent a corrosion reaction even if the terminal 104 is formed of an Al film. Similarly, zinc oxide (ZnO) is also a suitable material, and zinc oxide (ZnO: Ga) to which gallium (Ga) is added to further increase the transmittance and conductivity of visible light can be used.

In this manner, the inverted staggered n-channel TFT 120 and the storage capacitor 121 can be completed by using five photomasks through five photolithography processes. Then, by arranging these in a matrix corresponding to each pixel to form a pixel portion, one substrate for manufacturing an active matrix liquid crystal display device can be obtained. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

FIG. 10 is a diagram for explaining the arrangement of the pixel portion and the input terminal portion of the active matrix substrate.
A pixel portion 902 is provided over the substrate 901, and the pixel portion includes a gate wiring 908 and a source wiring 9.
07 are formed so as to intersect with each other, and n-channel TFTs 910 connected thereto are provided corresponding to the respective pixels. A storage capacitor 911 is connected to the drain side of the n-channel TFT 910,
The other terminal of the storage capacitor 911 is connected to the storage capacitor wiring 909. n-channel T
The structures of the FT 910 and the storage capacitor 911 are the same as those of the n-channel TFT 120 and the storage capacitor 121 illustrated in FIG.

An input terminal portion 905 for inputting a scanning signal is formed at one end of the substrate, and the connection wiring 9
06 is connected to the gate wiring 908. Further, an input terminal portion 903 for inputting an image signal is formed at the other end portion, and is connected to the source wiring 907 by a connection wiring 904. A plurality of gate wirings 908, source wirings 907, and storage capacitor wirings 909 are provided in accordance with the pixel density, and the number thereof is as described above. Further, an input terminal portion 912 for inputting an image signal and a connection wiring 913 may be provided, and the input terminal portion 903 may be alternately connected to the source wiring. An arbitrary number of input terminal portions 903, 905, and 912 may be provided, and the practitioner may determine as appropriate.

This embodiment will be described with reference to FIGS. 3 to 4 in which a TFT of a pixel portion is formed in a reverse stagger type on a substrate with a structure different from that of Embodiment 1, and a storage capacitor connected to the TFT is manufactured. Similarly, in FIGS. 3A and 3B and FIGS. 4A and 4B, (I) is a top view and A
A cross-sectional view along the line -A 'is shown in (II). The active matrix substrate manufactured in this embodiment corresponds to a transmissive liquid crystal display device, and the difference from Embodiment 1 will be mainly described below.

In FIG. 3A, a glass substrate such as barium borosilicate glass or alumino borosilicate glass typified by Corning # 7059 glass or # 1737 glass is used for the substrate 201. In addition, a stainless steel substrate or a ceramic substrate having a silicon oxide film or a silicon nitride film formed on the surface can also be used.

The gate electrode 202, the gate wiring 202 ′, the storage capacitor wiring 203, and the terminal 204 of the input terminal portion are formed in combination with a low resistance wiring material such as Al and a heat resistant conductive material in the same manner as in the first embodiment. Alternatively, it is formed by combining only such heat-resistant conductive materials. For example, a stacked structure of a WN film and a W film is used. Then, after a conductive layer having such a structure is formed over the entire surface of the substrate, a first photolithography process is performed to form a resist mask, and unnecessary portions are removed by etching. At this time, etching is performed so that a tapered portion is formed at least at the end portion of the gate electrode 202.

As the gate insulating layer 205, a silicon oxide film, a silicon oxynitride film, a silicon nitride proposal, a tantalum oxide film, or the like is formed with a thickness of 50 to 200 nm by a plasma CVD method or a sputtering method. Subsequently, 50 to 200 nm (preferably 100 to 1 nm) is formed on the gate insulating layer 205.
A semiconductor layer having an amorphous structure with a thickness of 50 nm is formed on the entire surface by a known method such as plasma CVD or sputtering (not shown).
. Typically, a hydrogenated amorphous silicon (a-Si: H) film is formed by a plasma CVD method. Further, as a semiconductor layer containing an impurity element of one conductivity type, an n-type semiconductor film is 20 to 8
It is formed with a thickness of 0 nm. For example, an n-type a-Si: H film is formed.

Then, the semiconductor layer thus formed is subjected to a second photolithography step, and the island-shaped semiconductor layer 2 is partially overlapped with the gate electrode 202 as shown in FIG.
06 is formed. The island-shaped semiconductor layer includes an amorphous semiconductor layer 206a and an n-type semiconductor layer 206b.

Next, as shown in (II) of FIG. 4A, a third photolithography step is performed, and a part of the gate insulating film formed over the terminal 204 is removed by etching to open the hole 217.
Form. Then, the transparent conductive film is formed by sputtering, vacuum deposition, spraying, etc.
A film having a thickness of 0 nm is formed, and a transparent conductive film 208 is provided over the pixel electrode 207 and the terminal 217 by a fourth photolithography step.

Then, similarly to Example 1, a conductive layer is formed by a sputtering method or a vacuum deposition method, a resist mask pattern is formed by a fifth photolithography process, and etching is performed as shown in FIG.
The source wiring 209 and the drain wiring 210 are formed as shown in FIG. Drain wiring 210
Is formed so as to overlap the pixel electrode 207 at the end, and is electrically connected at that portion. Also,
For connection between the source wiring and the input terminal portion, an end portion 211 of the source wiring extending to the gate insulating film is formed so as to overlap the transparent conductive film 208 and is electrically connected to the terminal 204.

(II) in FIG. 4B using the source wiring 209 and the drain wiring 210 as a mask.
As shown in FIG. 2, a part of the n-type semiconductor layer 206b and the amorphous semiconductor layer 206a is removed by etching to form an opening 212 in the island-shaped semiconductor layer. By this opening 212, the n-type semiconductor layer 206b is separated into a source region 213 and a drain region 214, and a channel formation region is formed in the island-shaped semiconductor layer 206 in a self-aligning manner.

After that, as shown in (II) of FIG. 4B, an inorganic material which covers the opening 212 and is in contact with at least a part of the channel formation region over the semiconductor layer having an amorphous structure and the n-type semiconductor layer. A first interlayer insulating layer 215 made of is formed. The first interlayer insulating film 215 is a silicon oxide film,
A silicon oxynitride film, a silicon nitride film, or a stacked film formed by combining these films is formed.
The first interlayer insulating film 215 has a thickness of 100 to 200 nm. Then, a first photolithography process is performed on the pixel electrode 207 and the transparent conductive film 208 in the input terminal portion by a sixth photolithography process.
The interlayer insulating layer 215 is removed.

Thus, the inverted staggered n-channel TFT 220 and the storage capacitor 221 can be completed by using six photomasks through six photolithography processes. In the active matrix substrate manufactured in this embodiment, the arrangement of the pixel portion and the input terminal portion is as shown in FIG.
As shown in FIG.

In Embodiment 2, a method for manufacturing an active matrix substrate corresponding to a transmissive liquid crystal display device is shown, but in this embodiment, an example corresponding to a reflective liquid crystal display device is shown.

First, similarly to Example 2, the steps up to the step shown in FIG. Then, (II
), A third photolithography process is performed, and a part of the gate insulating film provided over the terminal 204 is removed by etching to form the opening 230. Then, as in Example 1, a conductive layer is formed by sputtering or vacuum deposition, a resist mask pattern is formed by a fourth photolithography process, and etching is performed to form source wiring 2 as shown in FIG.
31 and drain wiring 232 are formed. The drain wiring 32 also serves as a pixel electrode and is formed so as to overlap the storage capacitor wiring 203. Further, the connection between the source wiring and the input terminal portion is electrically connected to the terminal 204 in the opening 230.

Thereafter, as in Example 2, a first interlayer insulating layer 234 made of an inorganic material is formed. Then, the first interlayer insulating layer 234 over the pixel electrode and the input terminal portion is removed by a fifth photolithography process. In this manner, an active matrix substrate corresponding to a reflective liquid crystal display device can be manufactured using five photomasks by five photolithography processes.

In this embodiment, a process of manufacturing an active matrix liquid crystal display device from the active matrix substrate manufactured in Embodiment 1 will be described. As shown in FIG. 6, an alignment film 600 is formed on the active matrix substrate in the state of FIG.
Usually, a polyimide resin is often used for the alignment film of the liquid crystal display element.

The counter substrate 601 on the counter side includes a light shielding film 602, a color filter 603, and a planarizing film 60.
4. A transparent conductive film 605 and an alignment film 606 are formed. The light shielding film 602 is formed of Ti, Al, chromium (Cr) or the like, and a pattern is formed in accordance with the arrangement of TFTs on the active matrix substrate. The color filter 603 is provided with red, green, and blue filters corresponding to each pixel. The planarization film 604 is formed of an organic resin film, and the same material as that of the second interlayer insulating film used in Embodiment 1 may be used. After the alignment film is formed, a rubbing process is performed so that the liquid crystal molecules are aligned with a certain pretilt angle.

Then, the active matrix substrate on which the pixel portion is formed and the counter substrate are bonded to each other through a spacer 607 with a sealant 608 including the spacer 609 by a known cell assembling process. Thus, a liquid crystal injection region 610 is formed. A known material may be applied as the liquid crystal material, and typically a TN liquid crystal is used. After injecting the liquid crystal material, the injection port is sealed with a resin material. In the case of a transmissive liquid crystal display device, polarizing plates 611 and 612 are attached to complete the active matrix liquid crystal display device shown in FIG. In the case of a reflective liquid crystal display device, the polarizing plate 612 is omitted, and the polarizing plate 611 is provided only on the counter substrate 601 side.

In this embodiment, a method for manufacturing an active matrix liquid crystal display device based on the active matrix substrate manufactured in Embodiment 1 is described. However, the same applies to the active matrix substrate described in Embodiment 2 or Embodiment 3. Can be produced by a simple method.

The active matrix substrate and the liquid crystal display device manufactured by implementing the present invention can be used for various electro-optical devices. The present invention can be applied to all electronic devices in which such an electro-optical device is incorporated as a display medium. Examples of the electronic device include a personal computer, a digital camera, a video camera, a portable information terminal (such as a mobile computer, a mobile phone, and an electronic book), a television, and the like.

FIG. 12A illustrates a personal computer which includes a main body 2001 including a microprocessor, a memory, and the like, an image input portion 2002, a display device 2003, and a keyboard 2004. The present invention can be applied to the display device 2003.

FIG. 12B illustrates a video camera, which includes a main body 2101, a display device 2102, and an audio input unit 2.
103, an operation switch 2104, a battery 2105, and an image receiving unit 2106. The present invention can be applied to the display device 2102.

FIG. 12C illustrates a portable information terminal, which includes a main body 2201, an image input unit 2202, and an image receiving unit 22.
03, an operation switch 2204, and a display device 2205. The present invention is a display device 220.
5 can be applied.

FIG. 12C illustrates an electronic gaming device such as a video game or a video game. The main body 2301 on which an electronic circuit 2308 such as a CPU, a recording medium 2304, and the like are mounted, the controller 2
305, display device 2303, speaker 2307, display device 2 incorporated in main body 2301
302. Display device 2303 and display device 2302 incorporated in main body 2301
May display the same information, or display the information on the recording medium 2304 with the former as the main display device and the latter as the sub display device, display the operating state of the device, or the function of the touch sensor. Can be added to provide an operation panel. In addition, the main body 2301 and the controller 23
05 and the display device 2303 may be wired communication to transmit signals to each other, or may be wireless communication or optical communication by providing sensor units 2306 and 2307. The present invention can be applied to the display devices 2302 and 2303. The display device 2303 has a screen size of 30.
The size can be increased to about the size of a mold, and it can be used as a television in combination with a tuner (not shown).

FIG. 12D shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded. The main body 2401, display device 2402, speaker unit 2403, and recording medium 24 are used.
04 and an operation switch 2405. The recording medium is a DVD (Digital Versati
le disc) or compact disc (CD) can be used to play music programs, display images, display video games (or video games), and display information via the Internet. The present invention can be suitably used for the display device 2402 and other signal control circuits.

FIG. 12E illustrates a digital camera, which includes a main body 2501, a display device 2502, and an eyepiece unit 25.
03, an operation switch 2504, and an image receiving unit (not shown). The present invention is a display device 2
The present invention can be applied to 502 and other signal control circuits.

FIG. 7 shows an example of a mounting method of a liquid crystal display device mounted on such an electro-optical device.
In the liquid crystal display device, an input terminal portion 702 is formed at an end portion of a substrate 701 on which a TFT is manufactured, and this is a terminal 703a formed of the same material as a gate wiring and a transparent conductive film as shown in the first embodiment. 703b. Then, the counter substrate 704 and the spacer 706 are bonded together with a sealing agent 705, and polarizing plates 707 and 708 are further provided. Then, it is fixed to the housing 721 by the spacer 722.

The drive circuit is formed on the LSI chip 713 and mounted by the TAB method. For this, a flexible printed circuit (FPC) is used, and the FPC has a copper wiring 710 formed on an organic resin film 709 such as polyimide and is connected to the input terminal 702 with an anisotropic conductive adhesive. To do. The anisotropic conductive adhesive is composed of an adhesive 711 and particles 712 having a conductive surface with a diameter of several tens to several hundreds μm mixed therein and plated with gold or the like. The particles 712 are input terminals 702. By making contact with the copper wiring 710, electrical contact is formed at this portion. A resin layer 718 is provided to increase the mechanical strength of this portion.

The LSI chip 713 is connected to the copper wiring 710 with bumps 714 and sealed with a resin material 715. The copper wiring 710 is connected at a connection terminal 716 to a printed board 717 on which other signal processing circuits, amplifier circuits, power supply circuits, and the like are formed. In the transmissive liquid crystal display device, a light source 719 and a light guide 720 are provided on the counter substrate 704 and used as a backlight.

Although not shown here, the present invention can also be applied to a navigation system, a portable television, and the like. As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields.
Such an electronic apparatus of the present embodiment can be realized by using the techniques of the first to fourth embodiments.

101, 201 Substrate 102, 202 Gate electrode 102 ', 202' Gate wiring 103, 203 Storage capacitor wiring 104, 204 Terminal 105, 205 Gate insulating film 106, 206 Island-like semiconductor layer 107, 209 Source wiring 108, 210 Drain wiring 114 215 First interlayer insulating film 115 Second interlayer insulating film 118, 207 Pixel electrode

Claims (1)

A pixel portion and a terminal portion;
The pixel portion is
A gate electrode;
A gate insulating layer on the gate electrode;
A semiconductor film on the gate insulating layer;
A source electrically connected to the semiconductor film;
A drain electrically connected to the semiconductor film;
A first insulating film having an inorganic material on the source and on the drain;
A second insulating film having an organic material on the first insulating film;
A pixel electrode electrically connected to the drain;
The terminal portion is
A first conductive layer;
A third insulating film on the first conductive layer;
A second conductive layer on the third insulating film,
The first conductive layer has a conductive material common to the gate electrode,
The second conductive layer has a transparent conductive film,
The second conductive layer is in contact with an upper surface and a side surface of the first conductive layer ,
The pixel electrode is on the second insulating film;
The liquid crystal display device, wherein the pixel electrode is electrically connected to the drain through a contact hole of the first insulating film and a contact hole of the second insulating film.

Images