JP6125617B2 - マルチスレッドプロセッサ内の区分された共有キャッシュにおけるスレッド単位のキャッシュライン割当て機構 - Google Patents
マルチスレッドプロセッサ内の区分された共有キャッシュにおけるスレッド単位のキャッシュライン割当て機構 Download PDFInfo
- Publication number
- JP6125617B2 JP6125617B2 JP2015511642A JP2015511642A JP6125617B2 JP 6125617 B2 JP6125617 B2 JP 6125617B2 JP 2015511642 A JP2015511642 A JP 2015511642A JP 2015511642 A JP2015511642 A JP 2015511642A JP 6125617 B2 JP6125617 B2 JP 6125617B2
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- JP
- Japan
- Prior art keywords
- cache
- partition
- thread
- data
- allocation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
- G06F12/0848—Partitioned cache, e.g. separate instruction and operand caches
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/466,359 US9824013B2 (en) | 2012-05-08 | 2012-05-08 | Per thread cacheline allocation mechanism in shared partitioned caches in multi-threaded processors |
| US13/466,359 | 2012-05-08 | ||
| PCT/US2013/040040 WO2013169836A1 (en) | 2012-05-08 | 2013-05-08 | Per thread cacheline allocation mechanism in shared partitioned caches in multi-threaded processors |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2017067172A Division JP6279787B2 (ja) | 2012-05-08 | 2017-03-30 | マルチスレッドプロセッサ内の区分された共有キャッシュにおけるスレッド単位のキャッシュライン割当て機構 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2015519654A JP2015519654A (ja) | 2015-07-09 |
| JP2015519654A5 JP2015519654A5 (https=) | 2016-06-09 |
| JP6125617B2 true JP6125617B2 (ja) | 2017-05-10 |
Family
ID=48446688
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2015511642A Active JP6125617B2 (ja) | 2012-05-08 | 2013-05-08 | マルチスレッドプロセッサ内の区分された共有キャッシュにおけるスレッド単位のキャッシュライン割当て機構 |
| JP2017067172A Expired - Fee Related JP6279787B2 (ja) | 2012-05-08 | 2017-03-30 | マルチスレッドプロセッサ内の区分された共有キャッシュにおけるスレッド単位のキャッシュライン割当て機構 |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2017067172A Expired - Fee Related JP6279787B2 (ja) | 2012-05-08 | 2017-03-30 | マルチスレッドプロセッサ内の区分された共有キャッシュにおけるスレッド単位のキャッシュライン割当て機構 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US9824013B2 (https=) |
| EP (1) | EP2847684A1 (https=) |
| JP (2) | JP6125617B2 (https=) |
| CN (1) | CN104272278B (https=) |
| WO (1) | WO2013169836A1 (https=) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2651891B2 (ja) | 1993-11-05 | 1997-09-10 | 株式会社日本開発コンサルタント | 円形型金属性帯板張力付与装置 |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10430190B2 (en) * | 2012-06-07 | 2019-10-01 | Micron Technology, Inc. | Systems and methods for selectively controlling multithreaded execution of executable code segments |
| US10089238B2 (en) * | 2014-07-17 | 2018-10-02 | Qualcomm Incorporated | Method and apparatus for a shared cache with dynamic partitioning |
| US9588893B2 (en) | 2014-11-10 | 2017-03-07 | International Business Machines Corporation | Store cache for transactional memory |
| US9727239B2 (en) * | 2014-11-13 | 2017-08-08 | Samsung Electronics Co., Ltd. | Electronic system with partitioning mechanism and method of operation thereof |
| US9678875B2 (en) | 2014-11-25 | 2017-06-13 | Qualcomm Incorporated | Providing shared cache memory allocation control in shared cache memory systems |
| US10698827B2 (en) | 2014-12-14 | 2020-06-30 | Via Alliance Semiconductor Co., Ltd. | Dynamic cache replacement way selection based on address tag bits |
| EP3055774B1 (en) | 2014-12-14 | 2019-07-17 | VIA Alliance Semiconductor Co., Ltd. | Multi-mode set associative cache memory dynamically configurable to selectively allocate into all or a subset of its ways depending on the mode |
| WO2016097810A1 (en) * | 2014-12-14 | 2016-06-23 | Via Alliance Semiconductor Co., Ltd. | Multi-mode set associative cache memory dynamically configurable to selectively select one or a plurality of its sets depending upon mode |
| EP3258382B1 (en) * | 2016-06-14 | 2021-08-11 | Arm Ltd | A storage controller |
| US10678690B2 (en) | 2017-08-29 | 2020-06-09 | Qualcomm Incorporated | Providing fine-grained quality of service (QoS) control using interpolation for partitioned resources in processor-based systems |
| GB201806997D0 (en) * | 2018-04-30 | 2018-06-13 | Univ Leuven Kath | Configurable hardware device |
| CN112148665B (zh) * | 2019-06-28 | 2024-01-09 | 深圳市中兴微电子技术有限公司 | 缓存的分配方法及装置 |
| CN114726925B (zh) * | 2020-12-21 | 2024-04-19 | 瑞昱半导体股份有限公司 | 具有存储器共享机制的无线通信装置及其存储器共享方法 |
| KR20230075914A (ko) | 2021-11-23 | 2023-05-31 | 삼성전자주식회사 | 프로세싱 장치 및 이의 동작 방법과 전자 장치 |
Family Cites Families (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5761720A (en) * | 1996-03-15 | 1998-06-02 | Rendition, Inc. | Pixel engine pipeline processor data caching mechanism |
| GB9701960D0 (en) | 1997-01-30 | 1997-03-19 | Sgs Thomson Microelectronics | A cache system |
| EP0856798B1 (en) | 1997-01-30 | 2004-09-29 | STMicroelectronics Limited | A cache system |
| US6078994A (en) * | 1997-05-30 | 2000-06-20 | Oracle Corporation | System for maintaining a shared cache in a multi-threaded computer environment |
| US6223256B1 (en) | 1997-07-22 | 2001-04-24 | Hewlett-Packard Company | Computer cache memory with classes and dynamic selection of replacement algorithms |
| US6205519B1 (en) * | 1998-05-27 | 2001-03-20 | Hewlett Packard Company | Cache management for a multi-threaded processor |
| GB9901933D0 (en) | 1999-01-28 | 1999-03-17 | Univ Bristol | Cache memory |
| US6493800B1 (en) * | 1999-03-31 | 2002-12-10 | International Business Machines Corporation | Method and system for dynamically partitioning a shared cache |
| US6535905B1 (en) | 1999-04-29 | 2003-03-18 | Intel Corporation | Method and apparatus for thread switching within a multithreaded processor |
| US6421761B1 (en) * | 1999-11-09 | 2002-07-16 | International Business Machines Corporation | Partitioned cache and management method for selectively caching data by type |
| US6859862B1 (en) | 2000-04-07 | 2005-02-22 | Nintendo Co., Ltd. | Method and apparatus for software management of on-chip cache |
| US6604174B1 (en) * | 2000-11-10 | 2003-08-05 | International Business Machines Corporation | Performance based system and method for dynamic allocation of a unified multiport cache |
| JP2002342163A (ja) | 2001-05-15 | 2002-11-29 | Fujitsu Ltd | マルチスレッドプロセッサ用キャッシュ制御方式 |
| US6871264B2 (en) | 2002-03-06 | 2005-03-22 | Hewlett-Packard Development Company, L.P. | System and method for dynamic processor core and cache partitioning on large-scale multithreaded, multiprocessor integrated circuits |
| US7039760B2 (en) | 2003-04-28 | 2006-05-02 | International Business Machines Corporation | Programming means for dynamic specifications of cache management preferences |
| US7536692B2 (en) * | 2003-11-06 | 2009-05-19 | Intel Corporation | Thread-based engine cache partitioning |
| JP4725181B2 (ja) * | 2005-04-28 | 2011-07-13 | アイシン・エィ・ダブリュ株式会社 | ナビゲーションシステム及びキャッシュ管理方法 |
| JP2007065743A (ja) | 2005-08-29 | 2007-03-15 | Sony Ericsson Mobilecommunications Japan Inc | 携帯情報端末及びその携帯情報端末の記憶領域管理方法 |
| US7895415B2 (en) * | 2007-02-14 | 2011-02-22 | Intel Corporation | Cache sharing based thread control |
| US7725657B2 (en) * | 2007-03-21 | 2010-05-25 | Intel Corporation | Dynamic quality of service (QoS) for a shared cache |
| US20090157968A1 (en) * | 2007-12-12 | 2009-06-18 | International Business Machines Corporation | Cache Memory with Extended Set-associativity of Partner Sets |
| CN101286138A (zh) | 2008-06-03 | 2008-10-15 | 浙江大学 | 基于数据划分的多线程共享多核处理器二级缓存的方法 |
| US8250332B2 (en) * | 2009-06-11 | 2012-08-21 | Qualcomm Incorporated | Partitioned replacement for cache memory |
| CN101609432B (zh) | 2009-07-13 | 2011-04-13 | 中国科学院计算技术研究所 | 共享缓存管理系统及方法 |
| US9952977B2 (en) * | 2009-09-25 | 2018-04-24 | Nvidia Corporation | Cache operations and policies for a multi-threaded client |
-
2012
- 2012-05-08 US US13/466,359 patent/US9824013B2/en not_active Expired - Fee Related
-
2013
- 2013-05-08 CN CN201380023546.2A patent/CN104272278B/zh not_active Expired - Fee Related
- 2013-05-08 WO PCT/US2013/040040 patent/WO2013169836A1/en not_active Ceased
- 2013-05-08 JP JP2015511642A patent/JP6125617B2/ja active Active
- 2013-05-08 EP EP13723374.8A patent/EP2847684A1/en not_active Ceased
-
2017
- 2017-03-30 JP JP2017067172A patent/JP6279787B2/ja not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2651891B2 (ja) | 1993-11-05 | 1997-09-10 | 株式会社日本開発コンサルタント | 円形型金属性帯板張力付与装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP6279787B2 (ja) | 2018-02-14 |
| JP2015519654A (ja) | 2015-07-09 |
| WO2013169836A1 (en) | 2013-11-14 |
| JP2017152009A (ja) | 2017-08-31 |
| US9824013B2 (en) | 2017-11-21 |
| EP2847684A1 (en) | 2015-03-18 |
| US20130304994A1 (en) | 2013-11-14 |
| CN104272278B (zh) | 2017-05-24 |
| CN104272278A (zh) | 2015-01-07 |
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