JP6124638B2 - Signal output circuit and data processing circuit - Google Patents

Description

  The present invention relates to a signal output circuit and a data processing circuit including the signal output circuit.

  Conventionally, a high-side and low-side switch element is provided between a voltage source and a ground point, and a signal output circuit formed so as to output a pulse signal from a connection point of these switch elements is used.

  According to this form of the signal output circuit, the high-side and low-side switch elements are driven so as to be complementarily turned on / off, and a pulse signal is generated. These switch elements are driven and controlled by a control signal (gate signal) received from the pre-driver circuit.

JP 2010-193020 A

  In the signal output circuit as described above, voltage fluctuation of the voltage source may occur due to various factors. This voltage fluctuation may cause a malfunction in the operation of the signal output circuit. For example, in the case of a signal output circuit that handles a data signal, the electrical characteristics of the circuit may fluctuate due to voltage fluctuations of the voltage source, and the slew rate of the data signal may vary greatly. When such a situation occurs, it becomes difficult for the signal output circuit to appropriately transmit the data signal.

  For this reason, it is desirable that the configuration of the signal output circuit be taken into consideration so as not to cause problems due to voltage fluctuations of the voltage source. In view of the above problems, an object of the present invention is to provide a signal output circuit, a data processing circuit, and the like that can suppress problems caused by voltage fluctuations of a voltage source.

  A signal output circuit according to the present invention outputs a first FET element and a second FET element connected in series between a voltage source and a ground point, and a gate signal generated using a constant current to the first FET element. A signal output circuit that outputs a pulse signal from a connection point between the first FET element and the second FET element, comprising: a first pre-driver circuit that drives the element; and a second pre-driver circuit that drives the second FET element; An N-channel FET element is used as the first FET element and the second FET element, and the first pre-driver circuit generates the constant current so that the magnitude changes according to voltage fluctuations of the voltage source. To do.

  According to this configuration, it is possible to suppress problems caused by voltage fluctuations of the voltage source. It should be noted that the “FET element” herein includes other types of FET elements other than MOSFETs without departing from the gist of the present invention.

  More specifically, the first pre-driver circuit may be configured to generate the constant current using a circuit in which the voltage source is grounded via a resistor. More specifically, as the above configuration, the second pre-driver circuit may be configured using an element having a lower breakdown voltage specification than an element configuring the first pre-driver circuit.

  More specifically, the first pre-driver circuit and the second pre-driver circuit each have a circuit configured using a switch element, and the switch element in the second pre-driver circuit is: The first pre-driver circuit may have a lower breakdown voltage specification than the switch element.

  More specifically, as the above configuration, the first pre-driver circuit and the second pre-driver circuit may have a current mirror circuit and a CMOS circuit as a circuit configured using the switch element. .

  More specifically, as the above configuration, the first FET element and the second FET element are MOSFETs, the drain of the first FET element is connected to the voltage source, the source of the first FET element is connected to the drain of the second FET element, The source of the second FET element may be grounded.

  More specifically, the above configuration may be configured such that a data signal representing predetermined data is input and the pulse signal corresponding to the data signal is output.

  A data processing circuit according to the present invention includes an I / O circuit having the signal output circuit having the above-described configuration and a logic circuit for recording data, and the data signal represents data recorded in the logic circuit. It is good also as a structure which is a signal. According to this configuration, it is possible to enjoy the advantages of the signal output circuit configured as described above.

  More specifically, as the above configuration, a write operation that is connected to an external device and causes the logic circuit to record data input from the external device, and a read operation that outputs the data signal to the external device, It may be configured to execute.

  The HDD controller according to the present invention includes the data processing circuit having the above-described configuration and controls the operation of the HDD. An electronic apparatus according to the present invention includes the HDD controller configured as described above and an HDD whose operation is controlled by the HDD controller. According to these configurations, it is possible to enjoy the advantages of the data processing circuit configured as described above.

  According to the signal output circuit of the present invention, it is possible to suppress problems caused by voltage fluctuations of the voltage source. Further, according to the data processing circuit or the like according to the present invention, it is possible to enjoy the advantages of the signal output circuit according to the present invention.

It is a schematic block diagram of the data processing circuit which concerns on this embodiment. It is a more detailed block diagram of the data processing circuit. It is explanatory drawing regarding the flow of each signal in the case of Write mode. It is explanatory drawing regarding the flow etc. of each signal in the case of Read mode. It is a detailed block diagram of the I / O circuit which concerns on this embodiment. It is a graph regarding the waveform of the data signal and clock signal at the time of overpowering. It is a graph regarding the waveform of the data signal and clock signal at the time of power reduction. 1 is a configuration diagram of an HDD controller and its surroundings according to the present embodiment. It is a perspective view showing an example of 1 composition of HDD concerning this embodiment. It is an external view which shows the example of 1 structure of the desktop personal computer which concerns on this embodiment.

  Embodiments of the present invention will be described below with reference to the drawings.

[Data processing circuit configuration, etc.]
FIG. 1 is a schematic configuration diagram of a data processing circuit 1 according to the present embodiment. As shown in the figure, the data processing circuit 1 includes an I / O [Input / Output] circuit 10 and a LOGIC circuit 20.

The I / O circuit 10 is disposed between an external device (for example, an SOC circuit described later) and the LOGIC circuit 20, and is used for input / output of a data signal (a signal representing predetermined data) between the two. . I / O circuit 10, the process of outputting the data signals S _DI inputted from an external device to the LOGIC circuit 20, and executes a process of outputting a data signal S _DO input from the LOGIC circuit 20 to an external device.

The LOGIC circuit 20 outputs an RW signal S _RW indicating one of the read mode and the write mode to the I / O circuit 10. LOGIC circuit 20, when outputting RW signal S _RW of Write mode, receives a data signal S _DI from the I / O circuit 10 records the data. The LOGIC circuit 20 outputs a data signal S _DO of recorded data to the I / O circuit 10 when outputting the RW signal S _RW in the Read mode.

The I / O circuit 10 and the LOGIC circuit 20 receive a clock signal _SCLK from an external device. Processing such as data signal transmission and data recording performed by the data processing circuit 1 is executed in synchronization with the clock signal _SCLK .

FIG. 2 is a more detailed configuration diagram of the data processing circuit 1. As shown in the figure, the data processing circuit 1 has a terminal T _SCLK and a buffer BF in addition to the I / O circuit 10 and the LOGIC circuit 20. A terminal T _SCLK is a serial clock terminal connected to an external device, and is used to input a clock signal S _CLK from the external device. The clock signal S _CLK input to the terminal T _SCLK is sent to the I / O circuit 10 and the LOGIC circuit 20 via the buffer BF.

The I / O circuit 10 includes a terminal T _SDIO , a buffer 11, an output circuit 12, and a predriver circuit 13.

The terminal T _SDIO is a terminal connected to the external device, and is shared by the serial input of the data signal _SDI from the external device and the serial output of the data signal S _DO to the external device. The buffer 11 has an input side connected to the terminal T _SDIO and an output side connected to the LOGIC circuit 20.

  The output circuit 12 includes a first FET element 12a and a second FET element 12b. These FET elements (12a, 12b) are all N-channel FET elements (in the case of this embodiment, MOSFETs [Metal-Oxide-Semiconductor FETs]).

Each FET elements (12a, 12b) are a pair of switching elements connected in series between the ground point and a voltage source V _IO with the I / O circuit 10, the connection first 1FET element 12a and the 2FET element 12b The point is connected to the terminal T _SDIO . Each FET elements (12a, 12b) pulse signal is generated by is complementarily turned on / off, the pulse signal as the data signal S _DO, will be output from the terminal T _SDIO.

  The term “complementary” here refers to the case where the first FET element 12a and the second FET element 12b are completely turned on / off, and the first FET element 12a and the second FET element 12b from the viewpoint of preventing through current. This is a concept that includes a case where a delay is given to the on / off transition timing (when a so-called dead time is provided).

  The pre-driver circuit 13 is a circuit that drives each FET element (12a, 12b) by generating and outputting a gate signal. As described later, the predriver circuit 13 includes a predriver circuit that drives the first FET element 12a and a predriver circuit that drives the second FET element 12b.

The LOGIC circuit 20 includes a serial I / F 21 and a register 22. Serial I / F21, when outputting the RW signal S _RW of Write mode, based on the clock signal S _CLK and a data signal S _DI that is serially input to record the data in the register 22. On the other hand the serial I / F21, the when outputting RW signal S _RW of the Read mode, based on the recorded data to the clock signal S _CLK and a register 22 which is the serial input data signal to the I / O circuit 10 S _DO Serial output.

FIG. 3 schematically shows the flow of each signal and the like when the LOGIC circuit 20 outputs the RW signal S _RW in Write mode (that is, in the Write mode). At this time, as shown in the figure, the gate signal input to each FET element (12a, 12b) is set to the low level, and the output side of the output circuit 12 is in a high impedance state.

The clock signal S _CLK input to the terminal T _SCLK is sent to the LOGIC circuit 20 via the buffer BF. The data signals S _DI inputted to the terminal T _SDIO is transmitted to LOGIC circuit 20 via the buffer 11. As a result, the LOGIC circuit 20 can write data to the register 22. In this way, the data processing circuit 1 performs an operation (write operation) for recording data input from the external device in the LOGIC circuit 20 in the write mode.

FIG. 4 schematically shows the flow of each signal and the like when the LOGIC circuit 20 outputs the RW signal _SRW in the Read mode (that is, in the Read mode). As shown in the figure this time, the clock signal S _CLK input to the terminal T _SCLK, is sent via the buffer BF to the I / O circuit 10 and the LOGIC circuit 20.

The pre-driver circuit 13 generates a gate signal to be output to each FET element (12a, 12b) in accordance with the data signal S _DO received from the LOGIC circuit 20. The gate signal is generated so that one is at a high level and the other is at a low level so that the FET elements (12a, 12b) are complementarily turned on / off. From this the output side of the output circuit 12, High level and the Low level pulse signal appear alternately is output as the data signal S _DO.

That is, the data signal S _DO output from the LOGIC circuit 20 is output from the terminal T _SDIO via the pre-driver circuit 13 and the output circuit 12. As a result, data can be read from the register 22. In this way, the data processing circuit 1 performs an operation (read operation) for outputting the data signal _SDO to the external device in the Read mode.

[Detailed configuration of I / O circuit]
FIG. 5 shows a detailed configuration of the I / O circuit 10. As shown in the figure, the I / O circuit 10 includes the above-described terminal T _SDIO , buffer 11, output circuit 12, pre-driver circuit 13, D flip-flop circuits (31 a and 31 b), and level shifter circuits (32 a , 32b), and each NAND gate (33a-33c). Further, the I / O circuit 10 includes, as the pre-driver circuit 13, a first pre-driver circuit 13a that drives the first FET element 12a and a second pre-driver circuit 13b that drives the second FET element 12b.

The D input terminal of the D flip-flop circuit 31a is set to receive the RW signal _SRW . The D input terminal of the D flip-flop circuit 31b is set to receive the data signal _SDO . The clock input terminal of each D flip-flop circuit (31a, 31b) is set to receive the clock signal _SCLK .

  The Q output terminal of the D flip-flop circuit 31a is connected to one input terminal of the NAND gate 33a, and through the level shifter circuit 32a, one input terminal of the NAND gate 33b and one input terminal of the NAND gate 33c. It is connected to the. The Q output terminal of the D flip-flop circuit 31b is connected to the other input terminal of the NAND gate 33a, and is connected to the other input terminal of the NAND gate 33c through the level shifter circuit 32b.

The output terminal of the NAND gate 33c is connected to the other input terminal of the NAND gate 33b. Each level shifter circuit (32a, 32b) operates to receive driving power from, for example, a 5 V voltage source V _LSD and adjust (shift) the level of an input signal and output the signal.

  The first pre-driver circuit 13a includes N-channel MOSFETs (Q1, Q2, Q6), P-channel MOSFETs (Q3 to Q5), a resistor R1, and an open / close switch Sw.

The MOSFET (Q1) has a gate connected to the gate of the MOSFET Q2, a source grounded, and a drain connected to the voltage source _VIO via the resistor R1. Note that the voltage of the voltage source V _IO varies in a range of approximately 1.5 V to 2.6 V depending on conditions at that time. The gate and drain of the MOSFET (Q1) are short-circuited. The MOSFET (Q2) has a source grounded and a drain connected to the drain of the MOSFET (Q3).

The MOSFET (Q3) has a gate connected to the gate of the MOSFET (Q4) and a source connected to the voltage source V _LSD . The gate and drain of the MOSFET (Q3) are short-circuited. The MOSFET (Q4) has a source connected to the voltage source V _LSD and a drain connected to the source of the MOSFET (Q5). The drain of the MOSFET (Q5) is connected to the drain of the MOSFET (Q6) via the open / close switch Sw. The source of the MOSFET (Q6) is grounded.

  The gate of the MOSFET (Q5) and the gate of the MOSFET (Q6) are connected to the output terminal of the NAND gate 33b. The open / close switch Sw opens and closes according to the output of the NAND gate 33c. The connection point between the MOSFET (Q5) and the open / close switch Sw is connected to the gate of the first FET element 12a.

The first pre-driver circuit 13a configured as described above generates the constant current Ia using a circuit in which the voltage source _VIO is grounded through the resistor R1. The current corresponding to the constant current Ia is supplied to the drain of the MOSFET (Q4) using the current mirror circuit constituted by the MOSFETs (Q1, Q2) and the current mirror circuit constituted by the MOSFETs (Q3, Q4). Taken from. This extracted current is supplied to a CMOS circuit constituted by each MOSFET (Q5, Q6).

The CMOS circuit receives the output signal of the NAND gate 33b, and outputs a signal obtained by logically inverting the output signal to the first FET element 12a. The open / close switch Sw is opened when data is written (when the data signal S _DO is not output), and is closed otherwise.

  The second pre-driver circuit 13b includes P-channel MOSFETs (Q7 to Q9), an N-channel MOSFET (Q10), and a resistor R2.

In the MOSFET (Q7), the gate is connected to the gate of the MOSFET (Q8), the drain is grounded via the resistor R2, and the source is connected to a voltage source V _{CD of} 1.5 V, for example. The gate and drain of the MOSFET Q7 are short-circuited. The MOSFET (Q8) has a source connected to the voltage source V _CD and a drain connected to the source of the MOSFET (Q9). The drain of the MOSFET (Q10) is connected to the drain of the MOSFET (Q9), and the source is grounded.

  The gate of the MOSFET (Q9) and the gate of the MOSFET (Q10) are connected to the output terminal of the NAND gate 33a. The connection point between the MOSFET (Q9) and the MOSFET (Q10) is connected to the gate of the second FET element 12b.

The second pre-driver circuit 13b configured as described above generates the constant current Ib by using a circuit in which the voltage source V _CD is grounded via the resistor R2. The current corresponding to the constant current Ib is taken out from the drain of the MOSFET (Q8) using a current mirror circuit constituted by the MOSFETs (Q7, Q8). This extracted current is supplied to a CMOS circuit constituted by each MOSFET (Q9, Q10). The CMOS circuit receives the output signal of the NAND gate 33a, and outputs a signal obtained by logically inverting the output signal to the second FET element 12b.

The drain of the 1FET element 12a is connected to a voltage source V _IO, source of the 1FET element 12a is connected to the drain of the 2FET element 12b, the source of the 2FET element 12b is grounded. The connection point between the first FET element 12 a and the second FET element 12 b is connected to the terminal T _SDIO and the input side of the buffer 11. The first FET element 12a functions as a high-side switch element, and the second FET element 12b functions as a low-side switch element. The I / O circuit 10 has the above-described configuration, and functions so that each operation of the data processing circuit 1 described above is appropriately performed.

[Responding to voltage fluctuations]
However as previously described, the voltage source V _IO is generally varies between 1.5V～2.6V. The I / O circuit 10 is configured in consideration so as to suppress such problems caused by voltage fluctuations as much as possible. Hereinafter, this point will be specifically described.

First, regarding the configuration of the output circuit 12, it seems that a P-channel type MOSFET may be used as the first FET element 12a. However, in this case, when the voltage source _VIO is de-energized (when the voltage fluctuates to the lower side), for example, the gate-source voltage may be insufficient and may not operate properly. Therefore, in the present embodiment, N-channel MOSFETs are used for both the first FET element 12a and the second FET element 12b so as to suppress such problems.

The first pre-driver circuit 13a is configured to generate the constant current Ia using a circuit in which the voltage source _VIO is grounded via the resistor R1. Therefore, the first pre-driver circuit 13a can generate the constant current Ia so that the magnitude changes according to the voltage fluctuation of the voltage source _VIO , and can obtain the drive capability according to the voltage fluctuation. As a result, fluctuations in the electrical characteristics of the I / O circuit 10 due to voltage fluctuations of the voltage source _VIO can be canceled as much as possible. As a result, the I / O circuit 10 can suppress (stabilize) fluctuations in the slew rate of the data signal as much as possible.

As the respective MOSFET (Q1～6) used in the construction of the first pre-driver circuit 13a, for example, a voltage source V _IO of overvoltage during As can withstand (the voltage when the change in the high side), the 5V An element with a withstand voltage specification is used. Here, for each MOSFET (Q7 to 10) used for the configuration of the second pre-driver circuit 13b, it is possible to use an element having a withstand voltage specification of 5 V as in the case of the first pre-driver circuit 13a. .

  However, in this embodiment, an element having a withstand voltage specification of 1.5 V is used as each MOSFET (Q7 to 10) used for the configuration of the second pre-driver circuit 13b. That is, the second pre-driver circuit 13b is configured using a switch element having a lower withstand voltage specification than the switch element configuring the first pre-driver circuit 13a. An element with a low withstand voltage specification has the advantage of a high operating speed, although the withstand voltage performance is lower than that of an element with a high withstand voltage specification.

Therefore, in this embodiment, it is possible to prevent the low-side operation speed from decreasing as much as possible, and to suppress a decrease in slew rate. In the second pre-driver circuit 13b, a voltage source V _{CD that} is set to a relatively low voltage different from the voltage source V _IO is used, so that no trouble occurs even if an element with a low breakdown voltage specification is used. Considered.

6 and 7 are graphs showing the waveforms of the data signal (S _DI or S _DO ) and the clock signal S _CLK in the I / O circuit 10. 6 is a graph when the voltage source _VIO is overpowered, and FIG. 7 is a graph when the voltage source _VIO is powered down.

Focusing on the slew rate of the data signal in overvoltage when the voltage source V _IO (the slope at the range of signal levels from 20% to 80%), as shown in FIG. 6, the rising slew rate 1.16 V / ns ( = 2.6V × 0.6 / 1.34ns), and the falling slew rate is 1.08V / ns (= 2.6V × 0.6 / 1.45ns).

On the other hand, paying attention to the slew rate of the data signal at the time of voltage reduction of the voltage source V _IO (with a slope in the signal level range of 20% to 80%), the rising slew rate is 0.92 V as shown in FIG. / ns (= 1.5V × 0.6 / 0.76ns), and the falling slew rate is 0.83V / ns (= 1.5V × 0.6 / 1.09ns).

As described above, since the I / O circuit 10 is configured to suppress the fluctuation of the slew rate of the data signal as much as described above, the fluctuation of the slew rate due to the voltage fluctuation of the voltage source _VIO is very small. . According to the I / O circuit 10, the data signal can be transmitted more appropriately between the external device and the LOGIC circuit 20 because the fluctuation of the slew rate of the data signal is small.

[Application example of data processing circuit]
The data processing circuit 1 according to the present embodiment can be applied to various devices that handle data. As an example, the data processing circuit 1 can be applied to an HDD controller that controls the operation of an HDD [Hard Disk Drive]. Hereinafter, the HDD controller including the data processing circuit 1 will be described more specifically.

  FIG. 8 is a configuration diagram of the HDD controller 52 including the data processing circuit 1 and its periphery. As shown in the figure, the HDD controller 52 is connected to an SOC [System-On-a-Chip] circuit 51 and an HDD 53.

The SOC [System-On-a-Chip] circuit 51 functions as a control device for an electronic device (such as a personal computer) on which the HDD controller 52 and the HDD 53 are mounted, for example. SOC circuit 51 performs output and the clock signal S _CLK and a data signal S _DI to the data processing circuit 1, the receive of the data signal S _DO from the data processing circuit 1.

  The HDD 53 is a kind of magnetic disk storage device. Here, FIG. 9 is a perspective view showing a configuration example of the HDD 53 (with the top cover removed). As shown in the figure, the HDD 53 includes a platter Y1, a magnetic head Y2, a swing arm Y3, a ramp mechanism Y4, a head amplifier Y5, a spindle motor Y6, a voice coil motor Y7, a latch mechanism Y8, an interface connector Y9, and a jumper switch Y10. Have.

  The platter Y1 is a magnetic disk formed by laminating a magnetic layer on the surface of an aluminum substrate or a glass substrate. One HDD 53 incorporates about 1 to 4 platters Y1. The magnetic head Y2 plays a role of reading / writing data from / to the platter Y1. The swing arm Y3 plays a role of supporting the magnetic head Y2 at the tip thereof.

  The ramp mechanism Y4 is a retreat destination of the magnetic head Y2 when the platter Y1 is not rotated, and is provided further outside the outermost periphery of the platter Y1. The head amplifier Y5 plays the role of amplifying the reproduction signal obtained by the magnetic head Y2.

  The spindle motor Y6 plays a role of rotating the platter Y1 at a constant rotational speed (4200 rpm, 5400 rpm, 7200 rpm, 10000 rpm, 15000 rpm, etc.). The voice coil motor Y7 serves to move the magnetic head Y2 in the radial direction of the platter Y1 by moving the swing arm Y3 in an arc.

  The latch mechanism Y8 plays a role of fixing the swing arm Y3 while the HDD 53 is stopped. The interface connector Y9 is connected to a host interface circuit mounted on a motherboard such as a personal computer with a cable. The jumper switch Y10 is a switch for performing device settings (master / slave etc.) of the HDD 53 using jumper pins when connecting a plurality of HDDs to one personal computer.

  Returning to FIG. 8, the HDD controller 52 includes a data processing circuit 1, a spindle driver 2, and an actuator driver 3.

Spindle driver 2 in accordance with an instruction of the data processing circuit 1 (logic circuit 20), and outputs a control signal S _SM for controlling the operation of the spindle motor Y6. Thereby, the operation of the spindle motor Y6 is controlled so that the reading and writing of data with respect to the platter Y1 is appropriately performed.

The actuator driver 3 outputs a control signal S _VCM for controlling the operation of the voice coil motor Y7 in response to an instruction from the data processing circuit 1 (logic circuit 20). As a result, the operation of the voice coil motor Y7 is controlled so that reading and writing of data with respect to the platter Y1 is appropriately performed.

The data processing circuit 1 (logic circuit 20) transmits / receives a data signal _SD to / from the HDD 53, supplies data for writing to the platter Y1 from the register 22, and reads data read from the platter Y1. Is recorded in the register 22. The data processing circuit 1 provided in the HDD controller 52 functions so that data transmission between the SOC circuit 51 and the HDD 53 is appropriately performed.

  FIG. 10 is an external view showing a configuration example of the desktop personal computer 60 on which the HDD controller 52 and the HDD 53 are mounted. The desktop personal computer 60 of this configuration example includes a main body case X10, a liquid crystal monitor X20, a keyboard X30, and a mouse X40.

  The main body case X10 houses the central processing unit X11, the memory X12, the optical drive X13, and the HDD 53. Although not shown in FIG. 10, the main body case X10 also houses the SOC circuit 51 and the HDD controller 52. The HDD 53 serves as a large-capacity auxiliary storage device that stores programs and data in a nonvolatile manner using a magnetic disk sealed in a housing.

  The central processing unit X11 comprehensively controls the operation of the desktop personal computer 60 by executing an operating system and various application programs stored in the HDD 53. The memory X12 is used as a work area of the central processing unit X11 (for example, an area for storing task data when executing a program).

  The optical drive X13 reads / writes the optical disc. Examples of the optical disk include CD [Compact Disc], DVD [Digital Versatile Disc], and BD [Blu-ray (registered trademark) Disc]. The liquid crystal monitor X20 outputs a video based on an instruction from the central processing unit X11. The keyboard X30 and the mouse X40 are one of human interface devices that accept user operations.

  The above-described desktop personal computer 60 is an example of an electronic device in which the HDD controller 52 and the HDD 53 are mounted. In addition, the HDD controller 52 and the HDD 53 can be mounted on various electric devices such as a notebook computer, a tablet computer, a hard disk recorder, an audio player, and a game machine.

  The configuration of the present invention can be variously modified in addition to the above embodiment without departing from the spirit of the invention. That is, the above-described embodiment is an example in all respects and should not be considered as limiting, and the technical scope of the present invention is not the description of the above-described embodiment, but the claims. It should be understood that all modifications that come within the meaning and range of equivalents of the claims are included.

  The present invention can be used for an HDD controller, for example.

DESCRIPTION OF SYMBOLS 1 Data processing circuit 2 Spindle driver 3 Actuator driver 10 I / O circuit 11 Buffer 12 Output circuit 12a 1st FET element 12b 2nd FET element 13 Predriver circuit 13a 1st predriver circuit 13b 2nd predriver circuit 20 LOGIC circuit 21 Serial I / F
22 Register 31a, 31b D flip-flop circuit 32a, 32b Level shifter circuit 33a-33c NAND gate 51 SOC circuit 52 HDD controller 53 HDD
60 Desktop PC BF Buffer X10 Body Case X11 Central Processing Unit X12 Memory X13 Optical Drive X20 Liquid Crystal Monitor X30 Keyboard X40 Mouse Y1 Platter Y2 Magnetic Head Y3 Swing Arm Y4 Lamp Mechanism Y5 Head Amplifier Y6 Spindle Motor Y7 Voice Coil Motor Y8 Latch Mechanism Y8 Interface connector Y10 Jumper switch

Claims (13)

A first FET element and a second FET element connected in series between a voltage source and a ground point;
A first pre-driver circuit that outputs a gate signal generated using a constant current to the first FET element and drives the first FET element;
A second pre-driver circuit for driving the second FET element,
A signal output circuit for outputting a pulse signal from a connection point between the first FET element and the second FET element,
N-channel FET elements are used as the first FET element and the second FET element,
The first pre-driver circuit is
The constant current is generated so that the magnitude changes according to voltage fluctuation of the voltage source ,
A signal output circuit , wherein a second voltage larger than a voltage of the voltage source is applied to generate the gate signal from the constant current and the second voltage . The first pre-driver circuit is
The signal output circuit according to claim 1, wherein the constant current is generated by using a circuit in which the voltage source is grounded through a resistor. The second pre-driver circuit is
The signal output circuit according to claim 2, wherein the signal output circuit is configured using an element having a lower breakdown voltage specification than an element constituting the first pre-driver circuit. The first pre-driver circuit and the second pre-driver circuit each have a circuit configured using a switch element,
The switch element in the second pre-driver circuit is:
The signal output circuit according to claim 3, wherein the signal output circuit has a lower breakdown voltage specification than the switch element in the first pre-driver circuit. The first pre-driver circuit and the second pre-driver circuit are:
The signal output circuit according to claim 4, wherein the circuit configured using the switch element includes a current mirror circuit and a CMOS circuit. The first pre-driver circuit is
A first current mirror circuit and a second current mirror circuit;
The first current mirror circuit turns back the constant current,
The second voltage is applied to a second current mirror circuit;
4. The signal output circuit according to claim 2, wherein the second current mirror circuit returns the current supplied from the first current mirror circuit. 5. The first pre-driver circuit is
A CMOS circuit having a configuration in which a P-channel MOSFET and an N-channel MOSFET are connected in series, and current is supplied from a second current mirror circuit;
A switch provided between the drain of the P-channel MOSFET and the drain of the N-channel MOSFET,
The signal output circuit according to claim 6, wherein a connection node between the P-channel type MOSFET and the switch is an output node of a first pre-driver circuit. The first FET element and the second FET element are MOSFETs,
8. The drain of the first FET element is connected to the voltage source, the source of the first FET element is connected to the drain of the second FET element, and the source of the second FET element is grounded. A signal output circuit according to any one of the above. A data signal representing predetermined data is input,
The signal output circuit according to claim 1, wherein the pulse signal corresponding to the data signal is output. An I / O circuit comprising the signal output circuit according to claim 9;
A logic circuit for recording data,
The data processing circuit, wherein the data signal is a signal representing data recorded in the logic circuit. Connected to an external device,
The data processing circuit according to claim 10, wherein a write operation for recording data input from the external device in the logic circuit and a read operation for outputting the data signal to the external device are executed. . A data processing circuit according to claim 10 or 11,
An HDD controller for controlling the operation of an HDD. An HDD controller according to claim 12;
An HDD whose operation is controlled by the HDD controller;
An electronic device characterized by comprising:

Images