JP2001177392A - Method and device for shifting level - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problems in a conventional level shift circuit where the circuit requires steady-state power consumption and is unsuitable for high- voltage switching. SOLUTION: This invention provides a structure of a level shifter, with a high-voltage drive capability and ultra-low power consumption through the adoption of dynamic charge control to the gate electrode of a high-voltage output transistor(TR). The structure can be made into an integrated circuit by the CMOS technology but no limited to the integrated circuit, and applicable to a high-voltage display driver circuit as applications of battery drive.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates to a method and circuit for low power, high voltage level shifting and related circuits.

[0002]

2. Description of the Related Art Many integrated circuits, such as display drivers, have a high voltage drive capability and a standard 5V CMO.
A combination of digital control by means of S logic is required. Therefore, a complicated level shift circuit is required to convert the 5V control signal into a desired high voltage output waveform. Moreover, in many of these applications, the system is battery powered and there are very strong restrictions on the power consumption of the level shifter. A promising and interesting application that requires both high voltage drive capability and very low power consumption is the design of drive chips for cholesteric LCDs (12th International Display Research Conference (japan 9).
2), “Fr by JWDoane, K. Yang and Z. Yaniv” on p. 73.
ont-lit flatpanel display from polymer stabilized
cholesteric textures "). Actually high voltage (50 volts) to switch this kind of liquid crystal from one stable state to another
V rms), but its inherent memory function (keeping the image unchanged on the screen without the need for continuous refreshing) is without a doubt large compared to other types of liquid crystals. This is an advantage, which allows the realization of a display system with a very low frame rate and a high level of power efficiency. Thus, these cholesteric LCDs are ideal components for slowly or sporadically changing images in battery operated display systems, but due to the generation of the required waveforms in the rows and columns of the display. Therefore, a high-voltage driving circuit with low power consumption must be developed.

In most high voltage CMOS technologies, FIG.
As shown in Figure 5, five different types of n- and p-
A type MOS transistor is used. device
(a) and (b) are standard 5V standard non-floating (used for CMOS control logic).
In contrast to NMOS and floating PMOS transistors, PMOS device (c) can float up to a higher voltage than the substrate potential. However, VGS and VDS of the PMOS device (c) are 5
V and therefore ideally this transistor is suitable for controlling the gate electrode of the output stage PDMOS transistor and also serves perfectly as an active load at the Miller voltage. (At the output stage,
MOSFETs that must withstand high voltages between source and drain electrodes (such as those in switching transistors at mirror voltages) are non-floating NDMOS and floating PDMOS devices (d) and (e).

A basic version of a high voltage level shifter is the known circuit of FIG. This is NDMOS
And a classic complementary output stage for individually controlling the gate voltages of the PDMOS devices T1 and T2. Standard 5V logic is used to control the NDMOS, while the voltage mirrors (T3, T4)
Is required to supply a suitable gate signal to the PDMOS. Unfortunately, the gate control of PDMOS device T2 is not optimal as demonstrated in the HSPICE-simulation of FIG.
Based on transistor model parameters from high voltage extension of 7 μm CMOS technology. When the input data line is switched from logic "1" to "0", T4
And V _GS of T2 is not completely discharged to 0V, PMOS
This is the threshold voltage of the transistor T4. Almost-
Discharged to a value of 1V. As a result, the PDMOS output transistor T2, which has a slightly different threshold voltage, is not driven to 100% cut-off operation and produces an output voltage of 0.5V instead of the ideal 0V value. Furthermore, the simultaneous conduction of both DMOS transistors in the output stage causes significant energy waste.

[0007] This problem is caused by the current mirror means shown in FIG.
_This can be solved by completely discharging _GS to 0V. When the input signal changes from "1" to "0", the constant current source I _BIAS
And current mirrors (T5, T6) are T2 and T4
Of to ensure that pulling the V _GS to 0V, creating a logical "0" state to meet the output of the driver, and to avoid unnecessary power consumption in the DMOS transistors in the output. FIG. 5 shows the HS at this current.
13 shows PICE-simulation results. Alternate Figure 4
The circuit is a level shifter proposed by M.Declercq and M.Schubert (M.Declercq and M.Sc
“Circuit intermediaire entre un circ by hubert
uit logique a basse tension et un etage de sortie
a haute tension realises dans une technologie CMOS
standard "Institut National de la Paopriete Indust
Patent 92 06030 of rielle, Paris (France). Here, the current source I _BIAS is no longer constant and is controlled by the inverting input signal, yielding a very balanced current form. However, the level shifter of FIG. 4 and all variants described in the literature have one major drawback. That is, the logic "0" and / or
Or in the voltage mirror for logic "1":
Exhibit continuous power consumption. In the case of the simulation of FIG. 5, when a "1" bit of logic is applied to the data input, a quiescent current of 150 .mu.A
Will flow through the drain terminal of For obvious reasons, this is not acceptable in battery powered applications.

When considering a cholesteric LCD driver, a low power consumption high voltage CMOS level shifter cannot be used directly. The reason is pure digital output
In order (the output voltage is switched between the V _HV supply voltage 0V) it is, LCD cholesteric structure requires a fairly complex waveforms. Some of the driving schemes require 3-, 4- or even 5-level logic, and others require analog multiplexers to select complex analog waveforms. For this reason,
For all of these applications, some analog switches are required as high voltage level shifters that withstand high voltages and exhibit the same very low power consumption. A classic circuit for a high voltage analog switch is shown in FIG. In this complementary analog switch, two diodes are used to avoid unnecessary conduction of the drain-bulk diode in the DMOS transistor. To obtain the "on" state of the switch, the source-gate voltage of the DMOS device must be V _{GS, N} = 5V, V
_{GS, P} should be -5V. Turn off switch
_{VGS, N} = _{VGS, P}
= 0V is required. Although this circuit is widely used for all kinds of applications, it has some significant drawbacks. The gate potential of the PDMOS must be lower than the analog signal V _HV by 5 V in order to turn on the switch, and the gate potential of the NDMOS exceeds the V _HV signal by 5 V under the same environment. Have to do
This is because the voltage range of the control circuit must exceed the total _VHV range by at least 10V. A first voltage mirror shifts the 5V control input signals upward to an auxiliary supply voltage at least 5V higher than the maximum _VHV value, and then a second shifts these signals to _VHV. Lower to the level. The choice of transistor parameters in this dual voltage mirror is extremely critical and much extra care must be taken to avoid applying excessive voltage to the transistor gate. The actual transistor parameters are
Any deviation from the values used in the simulation will result in transistor breakdown. This classic high voltage analog switch uses a floating NDMOS device, which means that the object can float to a high potential relative to the substrate potential. Unfortunately, in many high voltage CMOS technologies, only non-floating NDMOS transistors (the substrate acts as the transistor itself) are available.

[0007]

In summary, it can be said that a technique which is not low power consumption and high voltage level shift circuit has been found. Indeed, level shift circuits have been observed which simultaneously turn on the output stage transistors or the circuits controlling these output stage transistors, which involves a constant power consumption. Also, the concept of ordinary analog switches is not suitable for high voltage switching. Such analog switches are suitable for high voltage switching and require control circuits, as in low power consumption level shifters, and such are not available in this field.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a circuit which can be used for a high voltage level shift circuit and an analog switch which does not have a constant power consumption and has no simultaneous conduction in an output stage transistor. The use of the circuit results in very low power consumption in the high voltage level shifters and analog switches. The circuit can fluidly control the charging of the gate electrode of the high-voltage output transistor.

[0009]

SUMMARY OF THE INVENTION In accordance with the present invention, there is provided an apparatus and circuit having an output voltage. The device includes an output circuit and at least one input circuit. The output circuit is divided into a first part and a second part. The first and second parts are electrically complementary,
It is electrically equivalent. Each of the portions of the output circuit has an input terminal. The apparatus implements fluid control guidelines for at least one of the portions of the output circuit. Only when the input strobe voltage is externally set to a first predetermined voltage level, the input circuit is connected to the input circuit at at least one of the input terminals. Setting a voltage level related to an externally input voltage, and storing the latest voltage level in the input terminal when the input strobe voltage is set to a second predetermined voltage level. Means Such storage is enabled by electrically isolating the input terminals from the rest of the circuit.

In one embodiment of the invention, the device is a high voltage level shift circuit wherein the output circuit includes first and second electrically complementary portions. It is sufficient for this device to have only one input circuit.

In another embodiment of the invention, the device is an analog switch having first and second portions electrically equivalent to the output circuit. In such a circuit, both the first and second parts are controlled by an input circuit.

[0012] In yet another embodiment, the apparatus is a combination of the digital high voltage level shift circuit and the analog switch circuit. Such a combination can generate multiple levels of logic.

In yet another embodiment, the device is an analog multiplexer having high voltage drive capability and zero quiescent power. This analog multiplexer depends on a logic-valued 5 V input control signal, between its output and a first analog input signal or between its output and a second analog input signal (very low resistance). of)
Enables electrical coupling.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A level shift circuit has a function of generating an output voltage from an input voltage. The output voltage has a first range. The input voltage has a second range. In the high voltage level shift circuit, the first range is:
It is larger than the second range. The input voltage is between a first voltage level (eg, digital “1” or 5V) and a second voltage level (eg, digital “0” or 1V), and the difference between the voltage levels is Determine the input voltage range. The output voltage is between a third voltage level (eg, 50V) and a fourth voltage level (eg, digital 0V), and the difference between the voltage levels determines the range of the output voltage. The input voltage is meant to be two levels, and in an ideal situation would be considered either the first or the second voltage level. In actual situations,
A deviation from the level occurs. The deviation is always within the margin allowed for the technology used, and the input voltage is only two levels. Similarly for the output voltage, the third and fourth voltage levels determine the two levels of the output voltage.

In the general scheme of a level shift circuit, an output stage or circuit (100) and an input stage or circuit (130) can be distinguished. The output circuit generates the output voltage. The input circuit controls the output circuit and can input the input voltage. The input circuit includes:
At least one of the input terminals is set to a voltage level related to an input voltage externally input to the input circuit. The relationship is predetermined. The output circuit typically includes two parts (110) (120). Each of the parts has an input terminal connected to the input circuit, and the input circuit can control the operation of the part. The connection to each of the parts is adapted to be connected to a high or low voltage level. These voltage levels should be considered relative to each other. The part is electrically complementary, which means that the current flowing through the first part is determined by the voltage between its input terminal and its connection to a high voltage level, and It means that the current flowing through the part is determined by the voltage between its input terminal and its connection to a low voltage level.

In a first embodiment (FIG. 7) suitable for level shifting, the first part (110) and the second part (120) are provided in series. First part (110) and second part
There is an output circuit (100) comprising (120) and at least one input circuit (130) connected to at least one of said parts, here the first part.

The input circuit has two sub-circuits (14
0) and (150) and a switch circuit (160).
The first part is that one of its connections is at a third voltage level
(400). The second part has one connection connected to a fourth voltage level (410). The remaining connections of these two parts are connected together and determine the output voltage of the level shift circuit. The operation of such an arrangement is based on the fact that the input circuit controls the output circuit such that either the first part or the second part is activated. Activating means that the part conducts or current flows through it, so that the output voltage is within an acceptable margin with the third or fourth voltage level. Become equal. The first part is, but is not limited to, a PDMOS device. The second part is, but is not limited to, an NDMOS device. Depending on the type of device and whether the part is connected to a high or low voltage level, the connection is determined to be a source or a drain. The input terminal is determined to be a gate. The word source and drain is still used or generalized for that part even when said part is more than a single device. Selection of the voltage to the input terminal is made to avoid simultaneous conduction of the first and second portions.

In a second embodiment (FIG. 8) which is suitable for an analog switch and is slightly modified from the first embodiment, the first part (210) and the second part (220) are provided in series. Can be Both the first and second parts have one of their connections connected to a third voltage level (500). The remaining connections of these two parts are connected together and determine the output voltage of the analog switch circuit. The operation of such an arrangement is based on the fact that the input circuit controls the output circuit such that both the first part or the second part is active or inactive at the same time. The first and second portions are, but are not limited to, a floating PDMOS device connected in series via a diode. However, the diodes and PDMOS devices are different from the first and second parts. A connection between at least one of the diodes of the portion and the PDMOS is connected to the input circuit (240), thereby providing a virtual power supply.
(250) is realized.

The form of the analog switch will be described below.

The first level shift mode will be described in detail. Since low power consumption is intended, simultaneous conduction of the first and second parts must be avoided. This can be achieved when the input circuit appropriately controls at least one of the parts, so that the input circuit is adapted to be set to an input voltage at at least one of the input terminals. The voltage to be set at the input terminal depends on the relationship determined from the voltage of the external input.

As mentioned in the background of the invention, there are several input circuits, which either do not have the appropriate controls, or which themselves consume power on a regular basis, so that, for example, battery-powered It has the disadvantage of being unacceptable in products.

Therefore, the invention uses the principle of dynamic control, which makes it possible to control the input terminals of the part under consideration in dependence on an additional signal such as a strobe signal or a strobe voltage. means. The strobe voltage is also provided to the input circuit. The stove voltage also uses two levels, preferably the same voltage level as the input voltage. The strobe voltage is the first
At this strobe voltage level, the input circuit is activated, and a predetermined voltage is set at the input terminal under consideration so that a voltage suitable for the output of the level shift circuit is obtained. It can be stated that the voltage level of the input terminal under consideration is related to said input voltage. When the strobe voltage is the second strobe voltage, the input circuit is inactive and therefore consumes no power. Further, when the strobe voltage is at the second strobe voltage level, the input terminal under consideration should retain its latest value or store this latest value. Therefore, the input circuit should be configured such that when the strobe voltage is at the second strobe voltage level, the input terminals under consideration are electrically isolated. The latest value is then stored by the capacitance of the input terminal. Referring to the analog switch configuration, the same dynamic control principles can be applied, but not to both the first and second parts of the output stage of the analog switch.

When the voltage of the generalized absolute value between the gate and the source exceeds a certain positive margin from a certain threshold value, which depends on the form of the part, the first and the second circuits of the output circuit are provided. It is sufficient for the second part to be conductive. When the voltage of the generalized gate-source absolute value falls below a certain threshold, which depends on the form of the part, the first and the second part of the output circuit need only be non-conductive. Enough, and the gate-source voltage is preferably zero. Therefore, the input circuit should supply the appropriate voltage level to the input terminal under consideration, which will sufficiently reduce the gate-source voltage to zero when the part under consideration is expected to be inactive. Approach, otherwise generating a gate-source voltage well in excess of the threshold voltage dependent feature.

For another explanation, the principle of dynamic control is applied to the first part of the output circuit, which part is connected to a third voltage level. However,
The same reason applies when the principle of dynamic control is applied to the second part or both.

As shown in FIG. 7, for a gate-source voltage of zero, an input terminal is provided, the input terminal is connected through a first switch to a third voltage level, and a non-zero gate-source voltage is applied. A potential approach is taken to the source voltage such that a voltage drop in the electronic device with respect to the third voltage is realized, wherein the voltage drop is such that a non-zero gate-source voltage is an absolute value of the first portion. Exceeding the threshold is sufficient. The voltage of the input terminal of the first portion has a fifth voltage level. The first switch is, for example, a general PMOS transistor. Electronic devices for achieving the voltage drop are also common PMOs.
An S transistor, the gate of which is connected to its drain. Obviously, the first switch must be controlled by the same circuit. Also, the electronic device for achieving the voltage drop must be controlled by another circuit, which draws sufficient current through the electronic device.

The first switch and the electronic device may be considered as part of a switch circuit, the circuit having two inputs, the first being for controlling the first switch, The second is the drain of the electronic device. The output of the switch circuit then becomes the input terminal of the part of the output circuit under consideration. A circuit is required to control the two inputs of the switch circuit. The input circuit therefore includes first and second sub-circuits. Since different operations are required depending on the input voltage, and the operation also depends on the strobe voltage via the principle of dynamic control, the input voltage is set to the second voltage level and the strobe signal is When set to the first voltage level and the first sub-circuit is deactivated for another coupling,
The first sub-circuit is activated. When both the input voltage and the strobe voltage are set to the first voltage level and the others are deactivated, the second sub-circuit is activated. Since the first sub-circuit is connected to the first switch,
Active means closing the switch, thereby providing a suitable voltage for the shape of the transistor in the first switch. Since the second sub-circuit is connected to the drain of the electronic device, active means drawing current through the device. Said sub-circuit can have a similar form, for example a series connection of PMOS and NDMOS transistors. The only difference is that the input supplied to the sub-circuit is then, for the first circuit, logic and the operation between the input voltage of the logic inversion and the strobe voltage, the second circuit Is an operation between the input voltage and the strobe voltage. Different forms of the sub-circuit are also allowed. An essential feature of the form of the switch circuit and the interconnection with the sub-circuit is that the input terminal under consideration is electrically isolated when the strobe voltage is set to a second voltage level. is there.

[0027] Additional circuitry may be provided to prevent a slow discharge of the capacitance of the input terminal used to maintain the current value through the first switch. This can be achieved by using a second switch to connect the control terminal of the first switch to the third voltage level. By using a third switch, the voltage drop across the electronic device is also preferably set to zero. The second and third switches are connected to a PM
It may be an OS transistor, which is controlled by the circuit and closes the second and third switches when the input terminal has to be electrically isolated from the input circuit.

As described above, the input circuit can be used in other forms for realizing an analog switch, for example. In fact, an analog switch is realized when the first and second parts of the output circuit are designed to be electrically equivalent instead of complementary. The third voltage level may be determined as a first side of the analog switch, and the output voltage may be determined as the other side of the analog switch. The input voltage is then used to set the analog switch on or off. Since it is necessary to turn on and off both parts of the output circuit at the same time in order to obtain excellent switching characteristics, the principle of the dynamic control can be used again. Such an analog switch includes the two input circuits. Each of the input circuits is connected to one input terminal of the portion of the output circuit. Naturally, each input circuit is connected to a different input terminal. The input circuit is configured to set an input terminal to which the circuit is connected to a voltage level in relation to an input voltage of the input circuit. When the strobe voltage is equal to a first voltage level, the input terminal is set to a voltage associated with the input voltage of the input circuit. When the strobe voltage is equal to the second voltage level, the input terminal is electrically isolated from the rest of the circuit, thus storing the latest voltage in the capacitance of the input terminal. When the input voltage of the input circuit is set to a first voltage level, the voltage at the input terminal is set to a voltage level that activates both parts of the output circuit, thereby conducting. The device, including the analog switch shown, is therefore in conduction mode. When the input voltage of the input circuit is set to a second voltage level, the voltage at the input terminal is set to a voltage level that deactivates both portions of the output circuit, thereby providing a non-conductive mode. Becomes This device is therefore in non-conducting mode. Functionally, the output voltage of the device or analog switch substantially equals a third voltage when the switch is in a conduction mode and when the switch is in a non-conduction mode and is electrically isolated. Equal to level. To achieve that, each part of the output circuit must be connected on at least one side to the third voltage level. In certain implementations, the first and second portions of the output circuit include both a floating PDMOS in series with a diode. The diode and PDMOS device, however, are in different orientations in both parts. Each of the input circuits is coupled to two voltage levels. A first input circuit is coupled, for example, between the levels of the third and fourth voltages. The second voltage circuit is not connected to the third voltage level, but is connected to the fourth voltage level;
It is coupled between a side of an output circuit controlled by the input circuit. This determines a kind of virtual power supply for the second input circuit.

Some further alternative embodiments of the present invention are described below.

In the first embodiment, consider a form having a PDMOS output transistor as the first part of the output circuit. To reduce power consumption to a decisive minimum, P
Dynamic (fluid) control is used for charging the gate capacitance of the DMOS output transistor. The basic version of this design and the corresponding HSPICE simulation are shown in FIGS. 9, 10 and 11. It can be seen that the operation of the entire level shifter is controlled by the strobe voltage VSTROBE or the signal _VPASS . When this strobe signal goes high (first voltage level), one of the transistors T3 or T5 will conduct a 150 μA drain current, resulting in a p-type loaded transistor T4 or T4.
At 6 a voltage drop of 5 V is produced. For the “0” bit (second voltage level) in the data input section,
The 5V drop at T4 turns on transistor T7, resulting in the total discharge-source capacitance of PDMOS T2. The transistor T7 functions as a switch that connects the input terminal of the PDMOS to the third voltage level. In contrast,
"1" bit (first voltage level) in the data input section
, A 5V drop at T6 causes transistor T8 (just a pn between its drain and bulk terminals)
(Used as a diode) to pull down the gate potential of the transistor T2 to generate a source-gate voltage of approximately -4.5 V for the output transistor of T2. When the strobe signal goes low, the transistor T3
And T5 are switched off, and the voltage drops at T4 and T6 are reduced to approximately 1V. As a result, the transistor T7 is turned off (when the input bit is logic "0" during the strobe pulse) or the "diode" T
Inverts the polarity by 8 (when the input bit is "1"). In both cases, the gate electrode of the PDMOS output transistor remains electrically isolated from the rest of the circuit.
(Meaning that there is simply a high impedance connection between the gate electrode and the other components), therefore, the charge previously stored in its gate capacitance during the strobe voltage will cause the next strobe pulse (input signal (0 V or -4.5 V based on the voltage). This approach of using the gate capacitance of the PDMOS output transistor as the storage capacitor and updating its charge with the rhythm of the strobe signal in synchronization with the data, reduces the duration of the strobe pulse by one.
If it can be kept very small compared to the input data of the bits, the power consumption is dramatically reduced (because power is consumed only during the strobe pulse). This is a limiting case for cholesteric LCD drivers with very low image frame rates. ND in FIG. 9
For the gate control of the MOS output transistor, DC
A static 5V sense amplifier that consumes no power is used, but dynamic charging control methods can be used here as well. The simulation results in FIG. 11 show that this circuit still has a small inconvenience: T7 V during the strobe pulse.
_{G S} is set to approximately -1 V, the voltage keeps the transistor T7 at the cut-off operation of the edge. As a result, a small but insignificant leakage current (actually a subthreshold current) flows between its source and drain terminals. This current slowly discharges the gate capacitance of the PDMOS output transistor (if the "1" bit was sampled during the strobe pulse), and
If the charge is not updated in time, the level shifter will no longer operate correctly.

In the second embodiment of the present invention, this problem is considered in the improved circuit of FIG. 12, and the corresponding HSPICE simulation results are shown in FIGS. During the high-to-low conversion of the strobe signal, each V _GS of transistors T12 and T13 (conductive during the strobe pulse) is discharged to approximately -1V.
Since T12 and T13 are in series, devices T14 and T15 receive a V _GS of approximately -2V, so that actively loaded T4 and T6 are completely discharged to 0V. As a result, the transistor T7 is driven away from the cutoff operation such that the leakage current can be ignored. In this method, the PDMOS output transistor T
The charge stored in the gate capacitance of FIG.
Is no longer affected during successive strobe pulses, as shown by the simulation results of Reliable charge storage is obtained even at very low strobe signal frequencies of a few pulses per second.

In the third embodiment of the present invention, the dynamic control principle is used in designing an analog switch suitable for use in a liquid crystal driver. A solution to the classic analog switch shown in FIG. 6 and the previously discussed problem is to replace the floating NDMOS transistor with a second floating PDMOS device as shown in FIG. To turn on the switch, V
_{GS, 1} = V _{GS, 2} = −5V must be applied to the gates of the two PDMOS transistors, while V _{GS , 1} =
V _{GS, 2} = 0V turns off the switch. In this configuration, the analog signal at the gate potential V _HV of the PDMOS device must not be exceeded and therefore the voltage range of the circuit for dynamic control of the two PDMOS transistors is V
Should be 5V higher than the entire _HV range. PDMO
Since only S-devices are used in this circuit, double voltage mirrors are no longer needed, resulting in higher reliability. For control of PDMOS T2, the 5V switch control input signal is shifted toward the V _HV level by the strobe pulse rhythm, while for PDMOS T1 gate control, the 5V input signal goes to the point A potential. Shifted, this point can be considered as a kind of "virtual power supply" for the T1 control circuit. This is clearly shown in FIG. For each dynamic level shifter, the transistor configuration of FIG. 12 is used, and the 5V CMOS control logic is, of course, shared by the two level shifters, so that both transistors T1 and T2 are always "on" or "on" at the same time. It is in the "OFF" state. The complete configuration of the high-voltage analog switch with steady state and zero power consumption by dynamic control shown in FIG. 17 is thus obtained. Diodes D3 and D4 are added to give the circuit perfect switching characteristics. Diode D3, under certain circumstances (for some very special waveforms), may have a PDMO due to the capacitive effect in transistor T2 and diode D2.
Eliminate any negative voltage spikes that may occur at the S T2 drain electrode. Diode D4 reduces the effect of the non-negligible drain resistance of PDMOS T1 during the strobe pulse.

In a fourth embodiment of the present invention, the novel analog switch can function as the basic building block for more complex high voltage switches with zero steady power consumption. For example, combining this one high voltage analog switch with the other pure digital high voltage level shifter yields a high voltage level shifter that provides three levels of logic output. By adding a second high-voltage analog switch, for example, four-level logic is obtained. HSPICE simulations on all these circuits show proper level shifter operation.

In a fifth embodiment, a two-input analog multiplexer having high voltage drive capability and steady zero power consumption is provided. The analog multiplexer may be connected between its output and the first analog input signal, or between its output and the second analog input signal, depending on the logic value of the 5V input control signal.
Electrical connection between the analog input signals. Obviously, such a multiplexer comprises two analog switches (the first being between the output and the first analog input voltage and the second being between the output and the second analog input voltage). When the first switch is in the "off" state and the first must be conductive, the control signal is 5V complementary. Therefore, 5V CMOS control logic is used for both switches, but the connection to the voltage mirror must be swapped. This is illustrated in FIG. 18 which shows a dynamically controlled high voltage two input analog multiplexer. The practical use of this new multiplexer circuit is quite simple and easy. V _{HV, A} and V _{HV, B} are the high voltage input signals, V _OUT is the high voltage output signal, while V _CON is the 5 V control input signal (which is the output of the two analog switches in the multiplexer). Select one) and VPASS is 5 following simple _VCON input data.
V strobe pulse. If V _CON = “1” (5 V) during the strobe pulse, the output V _OUT and the input signal V
_An electrically low resistance connection is established between _{HV and A.} On the other hand, if V _CON = “0” (0 V) during the strobe pulse,
Output V _OUT is connected to input signal V _{HV, B.} During a strobe pulse, the state of the multiplexer, which is limited during the most recent strobe pulse, is maintained until the next pulse. The operation of this dynamically controlled analog multiplexer (except for continuous strobe pulses) can be simplified by the symbols in FIG. To find out if this dynamically controlled analog multiplexer works satisfactorily, HSPICE simulation was used and the results are shown in FIG. These simulations (run on a capacitive multiplexer including capacitive) show that the multiplexer circuit worked very well. At this point, important opinions are made.
Observing the simulation results, the output voltage V _OUT due to the threshold voltage of the diode at the output of the circuit
Is slightly different from the selected analog input waveform
(Maximum deviation of 0.5V). In these simulations, a strobe voltage greater than exactly required for the selected data input string VCON is used.
The reason is as follows: Simulations show that sudden changes in the high voltage waveform cause changes in the source-gate voltage of the output PDMOS device due to capacitive coupling between the gate and drain. Is shown.
So, if the V _{GS of} these transistors is not updated at the time of a sudden change in one of the high voltage signals, the V _GS value will be affected in series and the multiplexer circuit will no longer operate correctly. Disappears. Therefore, the rules of very simple operation are always repeated: one or more high voltage signals V _{HV, A} , V _{HV, B} and V
Each time abrupt changes occur at _OUT , a special strobe pulse V _PASS is required to update the V _{GS of the} PDMOS output transistor. To demonstrate that these dynamically controlled analog multiplexers are indeed useful components for monolithically integrated cholesteric LCD drivers, a three-row, three-row based on a conventional "minimal sweep, single polarity" drive scheme The simulation was performed with a driver for the column display. This driving scheme has been found to be the best if long-term DC compensation of cholesteric liquid crystals is allowed. FIG.
Indicates a complete driver mechanism. As can be seen, the column driver consists of five dynamically controlled multiplexers, each with two inputs. The first multiplexer selects the correct column select voltage according to the V _frame control signal. The second multiplexer is also V _frame
The correct column non-select voltage is selected according to the value of the control signal. Each one of the other three multiplexers connects a column select voltage or a column deselect voltage to a corresponding column of the LCD. The same configuration is used for row drivers,
Two of the multiplexers respond to select a suitable "cone of focus" (FC) or "stable plane" (SP) voltage corresponding to _Vframe . The voltages used in the simulation are as follows. V _sel1 : column selection voltage, frame 1: 55 V, V _sel2 : column selection voltage, frame 2: 5 V, V _nonsel1 : column non-selection voltage, frame 1:
15V, V _nonsel2 : column non-selection voltage, frame 2:45
V, V _FC1 : row “focal cone” voltage, frame 1:25
V, V _FC2 : row “focal cone” voltage, frame 2:35
V, V _SP1 : row "stable plane" voltage, frame 1: 5V,
V _SP2 : row "stable plane" voltage, frame 2: 55V.

The gate potential of the PDMOS output transistor in the multiplexer should be 5V lower than the high voltage input signal in order to switch the transistor on. Therefore, all high voltage input signals of the multiplexer should be at least 5V higher than the substrate potential defined as the 0V reference (ground) at any one time. Signals Vi _{, row1} , Vi _{, row2} , Vi _{, row3} , Vi _{, col1} , V
_{i, col2} and V _{i, col3} are 5V CMOS input control signals for column and row drivers, a value of "1" (5V) is for column selection, and "0" (0V) is for column unselection and For row "stable plane" voltage. The strobe signal V _pass is common to all ten dynamically controlled analog multiplexers. The HSPICE simulation was performed on the display patterns in Table 1.

[0036]

[Table 1]

The following waveforms were simulated using HSPICE. V _sel : column selection voltage, V _nonsel : column non-selection voltage, V _row1 , V _row2 , V _row3 : display column voltage, V _FC : row “focal cone” voltage, V _SP : row “stable plane” voltage, V _col1 , V
_{col 2} , V _col3 : display row voltage, V _{pix, ij} (i = 1,2,3 j = 1,2,
3): Pixel voltage between column i and row j.

The simulations of FIGS. 22 and 23 show that the structure of the proposed driver with a dynamically controlled high voltage analog multiplexer works quite satisfactorily. It should be noted that in the simulation, a column address time of only 100 μs was used, whereas in a typical drive scheme a real cholesteric LCD would require a column address time of at least a few ms. The value of 100 μs was chosen simply to reduce the total number of steps in the HSPICE simulation, and the simulation time was shorter due to the large number of transistors in the circuit (620).
Anyway, for example, a column address time of 10 ms output exactly the same waveform. From the simulation results,
The obtained waveform almost completely matched the theoretically expected waveform. The maximum deviation between theory and simulation is simply 0.8V, caused solely by the diode threshold voltage at the output of the multiplexer.

[0039]

As described above, the device of the present invention
An output circuit comprising first and second parts, each having an input terminal, and at least one input circuit adapted to receive at least two levels of input voltage and at least two levels of strobe voltage When the strobe voltage is set to a first voltage level, the input circuit sets at at least one of the input terminals a voltage level related to the input voltage; When the strobe voltage is set to a second voltage level, the input circuit is adapted to be electrically insulated at at least one of the input terminals, thereby providing high voltage drive capability and ultra-low power. Power consumption can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram corresponding to claims of a possible CMOS device used in the circuit of the present invention.

FIG. 2 is a circuit diagram of a known high-voltage level shifter.

FIG. 3 is an HSPICE simulation diagram of the level shifter of FIG. 2;

FIG. 4 is a circuit diagram of another known high voltage level shifter.

FIG. 5 is an HSPICE simulation diagram of the level shifter of FIG. 4;

FIG. 6: Classic analog switch circuit

FIG. 7 is a diagram showing a first embodiment of a level shifter according to one embodiment of the present invention.

FIG. 8 is a diagram showing a second form of the level shifter according to one embodiment of the present invention.

FIG. 9 is a circuit diagram realized based on the first embodiment described in the present invention.

FIG. 10 is an HSPICE simulation diagram of the circuit of FIG. 9;

FIG. 11 is an HSPICE simulation diagram of the circuit of FIG. 9;

FIG. 12 is a circuit diagram in which a function of discharging a gate capacitance is extended in the circuit of FIG. 9;

13 is an HSPICE simulation diagram of the circuit of FIG.

14 is an HSPICE simulation diagram of the circuit of FIG.

FIG. 15 is a conceptual diagram of a novel analog switch having two PMOS devices (300) and (310).

FIG. 16 shows the PMO according to a second embodiment of the present invention.
Circuit diagram of a novel analog switch that has both inputs of S-devices (300) and (310) and is controlled by dynamic level shifters (320) and (330)

FIG. 17 is a circuit diagram illustrating a particular implementation in the circuit diagram of FIG.

FIG. 18 is a diagram showing a form of an analog multiplexer described in the present invention.

FIG. 19 is a diagram in which such an analog multiplexer is symbolized.

20 is an HSPICE simulation diagram of the circuit of FIG.

FIG. 21 shows a driver architecture that can be used in the circuit of the present invention.

FIG. 22 is a HSPICE simulation diagram of the circuit of the present invention used for the driver architecture of FIG. 21 and for the display patterns of Table 1.

23 is a HSPICE simulation diagram of the circuit of the present invention used for the driver architecture of FIG. 21 and for the display patterns of Table 1.

FIG. 24 is a HSPICE simulation diagram of the circuit of the present invention used for the driver architecture of FIG. 21 and for the display patterns of Table 1.

[Explanation of symbols]

 110 first part 120 second part 130 input circuit 140 sub-circuit 150 sub-circuit 160 switch circuit 170 input terminal 310 third voltage level 210 first part 220 second part 500 third voltage level

 ────────────────────────────────────────────────── ─── Continuation of the front page (71) Applicant 500454769 Universiteit Gent Univ. Hoest Strat 22

Claims (31)

[Claims] An apparatus for determining an output voltage, comprising: an output circuit comprising first and second parts, each of which has an input terminal; at least two levels of input voltage and at least two levels. At least one input circuit adapted to input a strobe voltage of at least one of said input terminals when said strobe voltage is set to a first voltage level. The strobe voltage is set to a voltage level related to an input voltage, and the input circuit is electrically isolated at at least one of the input terminals when the strobe voltage is set to a second voltage level. An apparatus characterized in that: 2. The apparatus of claim 1, wherein said first and second portions are electrically complementary. 3. The voltage level to be set at the input terminal, wherein the input voltage is set to a first voltage level.
When at least one of the portions of the output circuit is activated and the input voltage is set to a second voltage level,
The apparatus of claim 1, wherein at least one of said portions of said output circuit is selected to be deactivated. 4. The apparatus according to claim 1, wherein said output circuit is adapted to generate an output voltage. 5. The apparatus of claim 4, wherein said output voltage is level shifted relative to said input voltage. 6. The apparatus of claim 1, wherein said output circuit is connected to a third voltage level and a fourth voltage level, wherein said third and fourth voltage levels are different. 7. The first portion is a floating PDMOS.
The device of claim 1, wherein the second portion is a non-floating NDMOS. 8. The input circuit comprises first and second sub-circuits, wherein the input voltage is at the second voltage level and the strobe voltage is at the first voltage level. , The first sub-circuit is activated, otherwise deactivated, and when the input voltage and the strobe voltage are brought to the first voltage level, the second sub-circuit is activated. The apparatus of claim 1, wherein the apparatus is otherwise deactivated. 9. The apparatus of claim 8, wherein said sub-circuit is connected between said third voltage level and said fourth voltage level. 10. The first sub-circuit and the second sub-circuit each provide an input to a switch circuit, wherein the switch circuit has an output serving as one of the input terminals, and the switch The circuit connects the output of the switch circuit to the third voltage level when the first sub-circuit is active, and the switch circuit connects the output of the switch circuit when the second sub-circuit is active. 9. Apparatus according to claim 8, wherein the output of the switch circuit is connected to a fifth voltage level. 11. An input terminal is connected to an output of the switch circuit, wherein when the output of the switch circuit is connected to the third voltage level, the portion of the output circuit is deactivated; 11. The part of the output circuit according to claim 10, wherein an input terminal is connected to an output part of the switch circuit when the output part of the switch circuit is connected to a fifth voltage level. apparatus. 12. The apparatus of claim 11, wherein the output of the switch circuit is electrically isolated when the first and second sub-circuits are inactive. 13. The first sub-circuit and the second sub-circuit have a PMOS connection, a gate connected to a drain and an NDMOS, and a gate connected to an input of the sub-circuit. An apparatus according to claim 10. 14. The apparatus of claim 13, wherein an input of the first sub-circuit is a logical AND of a logic inverted input voltage and a strobe voltage. 15. The apparatus of claim 14, wherein the input of said second sub-circuit is a logical AND of the input voltage and the strobe voltage. 16. The switch circuit comprises a first switch controlled by an input provided by the first sub-circuit, a first end of the first switch being connected to the third switch.
And the switch circuit further includes a one-way conductive element, a first end of the element connected to a second end of the first switch, and a second end of the element.
Is connected to an input provided by the second sub-circuit, and the second end of the first switch and the first end of the element are outputs of the switch circuit. The device according to claim 15. 17. The apparatus of claim 16, wherein said first switch is a PMOS, and whose gate is controlled by an input provided by said first sub-circuit. 18. The apparatus of claim 16, wherein said one-way conductive element is a diode. 19. The apparatus of claim 16, wherein said one-way conductive element is a PMOS, the gate of which is connected to its source and its bulk. 20. The semiconductor device further comprising a second and third switch and a circuit for controlling the second and third switches, wherein a second end of the second switch is connected to the first and second switches by the first and second switches. A first end of the third switch is connected to the third voltage level, and a third second end is connected to the switch circuit. When the input terminal of the portion of the output circuit connected to the input provided by the second sub-circuit and connected to the output of the switch circuit is isolated from the input circuit, the circuit is connected to the second and 11. The device according to claim 10, wherein the third switch is closed. 21. The second and third switches are connected to a PM.
21. The apparatus of claim 20, wherein the devices are OS devices, the gates of which are connected to the circuit. 22. The apparatus of claim 20, wherein said circuit is a connection of two PMOSs, whose gates are connected to their drain and NDMOS, and whose gate is connected to said strobe voltage. 23. The device according to claim 1, implemented in CMOS technology. 24. The apparatus of claim 1, wherein said first and second portions are electrically equivalent. 25. The apparatus of claim 25, further comprising: two input circuits, each of the input circuits being connected to one of the input terminals, wherein both of the input circuits have the strobe voltage set to a first voltage level. When the input circuit is connected to a voltage level related to the input voltage, is adapted to an input terminal connected to the input circuit, and when the strobe voltage is set to a second voltage level, The apparatus of claim 24, wherein the apparatus is adapted to electrically isolate an input terminal to which the input circuit is connected. 26. When the input voltage is set to a first voltage level, the portions of both of the output circuits are activated, thereby setting the device to a conduction mode, wherein the input voltage is When set to a voltage level of 2,
Said portions of both of said output circuits are deactivated;
26. The device of claim 25, wherein said voltage level set at said input terminal is selected to set said device in a non-conducting mode. 27. The output voltage is associated with a third voltage level when the device is in a conductive mode, and is electrically isolated from the third voltage level when the device is in a non-conductive mode. Item 29. The device according to Item 26. 28. The apparatus of claim 24, wherein each portion of said output circuit is connected on one side to said third voltage level. 29. The apparatus of claim 24, wherein said first portion and said second portion are float PDMOSs in series with diodes. 30. At least one of said two input circuits comprises two sub-circuits, wherein said sub-circuit comprises a fourth voltage level and said input circuit not connected to said third voltage level. 29. The device of claim 28, connected between one of the output circuits to be controlled. 31. The apparatus of claim 1, wherein the input circuit stores a value of at least one of the input terminals when the strobe voltage is set to a second voltage level.