JP6123398B2 - DEFECT LOCATION PREDICTION DEVICE, IDENTIFICATION MODEL GENERATION DEVICE, DEFECT LOCATION PREDICTION PROGRAM, AND DEFECT LOCATION PREDICTION METHOD - Google Patents

Description

  The present invention relates to a defect location prediction device, an identification model generation device, a defect location prediction program, and a defect location prediction method.

  In recent years, in integrated circuits such as LSI (Large Scale Integration), the dimensions of transistors and wirings have become smaller than the wavelength of light due to advances in miniaturization technology. Due to this influence, even if exposure is performed with a mask formed according to the designed layout pattern in the lithography process, a part that cannot be exposed according to the layout pattern may occur in the integrated circuit due to the optical proximity effect (Optical Proximity Effect). is there. For example, even if the wiring pattern is exposed on the wafer with a mask formed according to the layout pattern, the wiring pattern formed on the wafer is thinned and disconnected, or conversely, the wiring pattern is thickened and shorted, Such a defect may occur.

  FIG. 19 is a diagram illustrating an example of a layout pattern and a wiring pattern to be formed. In the example of FIG. 19, when the layout pattern shown in FIG. 19A is exposed on the wafer, due to the optical proximity effect, part of the wiring becomes thin as shown in FIG. It has occurred.

  In the design of integrated circuits, in order to suppress the occurrence of defects and form the layout pattern faithfully on the wafer, in general, correction that anticipates deterioration due to the optical proximity effect on the layout pattern in advance, so-called OPC (Optical Proximity Correction) Is performed. FIG. 20 is a diagram illustrating an example in which OPC is performed on a layout pattern. FIG. 20A shows an example in which OPC is applied to the layout pattern shown in FIG. In FIG. 20A, the OPC is performed so that the wiring shape of the defective portion in which a part of the wiring in FIG. When the layout pattern shown in FIG. 20A is transferred onto the wafer, a pattern as shown in FIG. 20B is formed on the wafer.

  In order to perform OPC, it is necessary to predict where a defect occurs in the layout pattern before manufacturing. Techniques for predicting where a defect occurs are as follows.

  For example, there is a technique for predicting a location where a defect occurs by simulating a lithography process itself using a layout pattern. The prediction by this simulation can accurately predict the location where the defect occurs, but it takes a long time to predict due to the recent high integration and large scale of the integrated circuit. For example, it may take several weeks to predict a defective part by simulation.

  Therefore, in recent years, a technique based on pattern recognition has attracted attention. For example, in this pattern recognition method, the feature of the location where the defect has occurred is extracted from the layout pattern of the wiring layer where the defect has occurred in the past design data where the defect has occurred. In the pattern recognition method, a part having the same feature in the wiring layer to be inspected for design data is extracted as a defect candidate.

JP 2006-126745 A JP 2012-118787 A JP 2006-343587 A

  Incidentally, there are a plurality of process technologies for manufacturing an integrated circuit. This process technology is a technology adopted for manufacturing an integrated circuit such as a wiring width, a wiring interval, and a minimum via size. The designer designs a layout pattern with design rules according to the process technology to be adopted. For this reason, in order to predict a location where a defect occurs by a pattern recognition technique, an identification model for identifying the defect location is generated for each process technology by extracting features of the location where the defect has occurred. For example, in a process technology with minimum line widths of 45 nm and 28 nm, the identification model is generated separately.

  However, when an identification model is generated for each process technology, it takes time to generate the identification model when adopting a new process technology.

  In one aspect, an object is to provide a defect location prediction apparatus, an identification model generation device, a defect location prediction program, and a defect location prediction method that can predict a location where a defect occurs even when process technologies are different.

  According to one aspect of the present invention, the defect location prediction apparatus includes an extraction unit, a generation unit, and a prediction unit. The extraction unit normalizes a layout pattern in which a defect occurs in the lithography process based on the design rule of the layout pattern, and extracts feature information indicating the feature of the defective part from the normalized layout pattern. The generation unit generates an identification model for identifying a defect location based on the feature information extracted by the extraction unit and a predetermined element of the design rule including the normalization element used for the normalization. The prediction unit normalizes a layout pattern to be inspected based on a design rule of the layout pattern, and predicts a location where a defect occurs from the normalized layout pattern using the identification model generated by the generation unit. .

  Even when the process technology is different, it is possible to predict where a defect will occur.

FIG. 1 is a diagram illustrating an overall configuration of a defect location prediction apparatus. FIG. 2 is a diagram illustrating an example of a sample pattern included in the sample data. FIG. 3 is a diagram schematically showing a configuration of a lithography apparatus that performs exposure. FIG. 4 is a diagram illustrating an example of an intensity distribution of light irradiated on the wafer. FIG. 5 is a diagram illustrating an example of a layout pattern in which a defect has occurred. FIG. 6 is a diagram illustrating an example of layout pattern normalization. FIG. 7 is a diagram for explaining the flow of Delaunay triangulation. FIG. 8 is a diagram illustrating an example of a convex vertex and a concave vertex. FIG. 9 is a diagram illustrating an example in which the sample pattern is divided into a plurality of regions according to the distance from the pattern center. FIG. 10 is a diagram illustrating an example of rotation and inversion of the layout pattern. FIG. 11 is a diagram illustrating an example of the shift of the center position of the layout pattern. FIG. 12 is a diagram illustrating an example of feature information. FIG. 13 is a diagram illustrating an example of hot spot position information. FIG. 14 is a diagram schematically showing an overall processing flow for generating an identification model and predicting a defect location. FIG. 15 is a flowchart showing the procedure of the feature vector extraction process. FIG. 16 is a flowchart illustrating the procedure of the model generation process. FIG. 17 is a flowchart illustrating the procedure of the defect location prediction process. FIG. 18 is a diagram illustrating a computer that executes a defect location prediction program. FIG. 19 is a diagram illustrating an example of a layout pattern and a wiring pattern to be formed. FIG. 20 is a diagram illustrating an example in which OPC is performed on a layout pattern.

  Embodiments of a defect location prediction device, an identification model generation device, a defect location prediction program, and a defect location prediction method according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments. Each embodiment can be appropriately combined within a range in which processing contents are not contradictory. Hereinafter, the “defect portion” is also referred to as a “hot spot”.

  The defect location prediction apparatus 10 according to the first embodiment will be described. FIG. 1 is a diagram illustrating an overall configuration of a defect location prediction apparatus. The defect location prediction apparatus 10 is a device that predicts a position of a defect location that occurs in a pattern formation process of an integrated circuit such as an LSI, particularly a defect location that occurs due to an optical proximity effect in a lithography process. The defect location prediction apparatus 10 is, for example, a computer such as a personal computer or a server computer. The defect location prediction apparatus 10 may be implemented as a single computer, or may be implemented as a cloud of a plurality of computers. In the present embodiment, a case where the defect location prediction apparatus 10 is a single computer will be described as an example. The defect location prediction apparatus 10 may be a design apparatus that operates circuit design software that supports the design of an integrated circuit by a designer, such as a CAD (Computer Aided Design) apparatus. As illustrated in FIG. 1, the defect location prediction apparatus 10 includes an input unit 20, a display unit 21, a communication I / F (interface) unit 22, a storage unit 23, and a control unit 24.

  The input unit 20 is an input device that inputs various types of information. Examples of the input unit 20 include an input device that accepts an input of an operation such as a mouse or a keyboard. The input unit 20 receives input of various types of information. For example, the input unit 20 receives input of various operations related to prediction of a defective part. The input unit 20 receives an operation input from the user, and inputs operation information indicating the received operation content to the control unit 24.

  The display unit 21 is a display device that displays various types of information. Examples of the display unit 21 include display devices such as an LCD (Liquid Crystal Display) and a CRT (Cathode Ray Tube). The display unit 21 displays various information. For example, the display unit 21 displays various screens such as a registration screen, an operation screen, and a prediction result screen.

  The communication I / F unit 22 is an interface that controls communication with other devices. The communication I / F unit 22 transmits / receives various information to / from other devices via a network (not shown). For example, the communication I / F unit 22 receives design data and layout pattern data used as sample data 30 and inspection target data 33 to be described later from another device. As the communication I / F unit 22, a network interface card such as a LAN card can be adopted. The defect location prediction apparatus 10 may acquire information such as the sample data 30 and the inspection target data 33 via a storage medium such as a memory card. Further, the sample data 30 and the inspection object data 33 may be input from the input unit 20.

  The storage unit 23 is a storage device such as a hard disk, an SSD (Solid State Drive), or an optical disk. The storage unit 23 may be a semiconductor memory that can rewrite data, such as a random access memory (RAM), a flash memory, and a non-volatile static random access memory (NVSRAM).

  The storage unit 23 stores an OS (Operating System) executed by the control unit 24 and various programs. For example, the storage unit 23 stores various programs used for predicting a defect location described later. Furthermore, the storage unit 23 stores various data used in programs executed by the control unit 24. For example, the storage unit 23 stores sample data 30, feature information 31, identification model information 32, inspection object data 33, and hot spot information 34.

  The sample data 30 is data in which a plurality of sample patterns used for generating an identification model for identifying a defective portion is stored. The sample data 30 stores a layout pattern that is used as a sample pattern and has known defects. For example, the sample data 30 stores a layout pattern of a wiring layer in which a defect occurs in a lithography process as a sample pattern. The sample data 30 also stores, as a sample pattern, a layout pattern of a wiring layer that is similar to a layout pattern in which a defect is generated but has no defect. As this sample pattern, design data of the integrated circuit may be used. For example, as the sample pattern, design data of an integrated circuit in which a defect has occurred in the lithography process as a result of actually manufacturing the integrated circuit may be used. As the sample pattern, integrated circuit design data in which the occurrence of a defect is predicted by simulation may be used. The sample data 30 includes a vertex coordinate list of rectangles and polygons constituting the sample pattern, and hot spot information regarding the presence / absence of a defect.

  FIG. 2 is a diagram illustrating an example of a sample pattern included in the sample data. In the vertex coordinate list, the vertex coordinates of a plurality of figures constituting the sample pattern are recorded for each line. For example, in the example of FIG. 2, four vertex coordinates of the rectangle RECT1 and seven vertex coordinates of the polygon POLY2 are shown. As the vertex coordinate list, an existing graphic data format such as GDS (Graphic Data System) or OASIS (Open Artwork System Interchange Standard) may be used.

  Here, the size of the sample pattern will be described. In the integrated circuit, a wiring pattern is formed by exposure using a mask formed according to a layout pattern in a lithography process. FIG. 3 is a diagram schematically showing a configuration of a lithography apparatus that performs exposure. In the lithography apparatus 50, the light emitted from the light source 51 is irradiated onto the mask 53 through the lens 52, and the light transmitted through the mask 53 is condensed by the projection lens 54 and irradiated onto the wafer 55. The lithography apparatus 50 divides the layout pattern into a certain range and exposes the wafer 55. FIG. 4 is a diagram illustrating an example of an intensity distribution of light irradiated on the wafer. The horizontal axis of the graph shown in FIG. 4 indicates the distance from the exposure center on the wafer 55 corresponding to the position of the optical axis. The vertical axis of the graph indicates the light intensity. As shown in FIG. 4, the intensity of light irradiated onto the wafer 55 tends to decrease as the distance from the exposure center increases. An area exposed on the wafer 55 by one exposure is a range in which the light intensity is a certain level or more. For example, as shown in FIG. 4, the lithographic apparatus 50 divides the light intensity, which is the maximum after the exposure center, into square areas each having a length of one side, the distance L first obtained from the exposure center. To expose the pattern. The sample pattern is a pattern having substantially the same size as the region to be exposed at a time, with the defect occurrence position being substantially the center position. For example, the sample pattern is a square area pattern with the distance L as one side length.

  The feature information 31 is data that stores the features of each sample pattern of the sample data 30. The feature information 31 stores information about the features of the sample pattern extracted by the extraction unit 41 described later.

  The identification model information 32 is data that stores an identification model for identifying a defective part. The identification model information 32 stores information related to the identification model generated by the generation unit 42 described later.

  The inspection target data 33 is design data for inspecting a defect occurrence location. The inspection target data 33 includes at least a layout pattern of a wiring layer for inspecting a defect occurrence location.

  The hot spot information 34 is data that stores information related to the identified defect location. The hot spot information 34 stores information such as the position of a defect portion predicted by a prediction unit 43 described later using each identification model stored in the identification model information 32.

  The control unit 24 is a device that controls the defect location prediction apparatus 10. As the control unit 24, an electronic circuit such as a CPU (Central Processing Unit) and an MPU (Micro Processing Unit), or an integrated circuit such as an ASIC (Application Specific Integrated Circuit) and an FPGA (Field Programmable Gate Array) can be employed. The control unit 24 has an internal memory for storing programs defining various processing procedures and control data, and executes various processes using these. The control unit 24 functions as various processing units by operating various programs. For example, the control unit 24 includes a reception unit 40, an extraction unit 41, a generation unit 42, a prediction unit 43, and an output unit 44.

  The reception unit 40 performs various types of reception. For example, the reception unit 40 receives registration of a layout pattern used as the sample data 30. The accepting unit 40 accepts registration of design data to be inspected. For example, the accepting unit 40 displays a registration screen (not shown) and accepts registration of a layout pattern used as sample data 30 and design data to be inspected from the registration screen. The registered layout pattern is stored as sample data 30. The registered design data of the inspection object is stored as inspection object data 33.

  The receiving unit 40 receives various operation instructions. For example, the receiving unit 40 displays an operation screen (not shown) and receives an instruction to start verification of a hot spot. The receiving unit 40 may display various screens on other devices via a network and perform various receiving operations.

  Here, an example of defects occurring in the integrated circuit will be described. FIG. 5 is a diagram illustrating an example of a layout pattern in which a defect has occurred. 5A and 5B show layout patterns of different process technologies in which defects have occurred. For example, FIG. 5A shows a layout pattern of process technology having a minimum line width of 28 nm. FIG. 5B is a layout pattern of process technology having a minimum line width of 45 nm. In the example of FIGS. 5A and 5B, the designed layout pattern is indicated by a line. In the examples of FIGS. 5A and 5B, the wiring to be formed is indicated by a dot pattern.

  In the layout patterns of FIGS. 5A and 5B, defect portions 61 and 62 in which the wiring pattern is thick and short-circuiting easily occurs. Locations where defects occur in the lithography process tend to be common regardless of process technology. For example, patterns shown by broken lines including the defective portions 61 and 62 in FIGS. 5A and 5B are similar in shape, although the sizes are different. That is, a layout pattern in which a defect occurs in a lithography process is often similar regardless of process technology. However, even if the shape is similar, there are cases in which the location where the defect occurs and whether or not the defect occurs differ depending on the process technology.

  The extraction unit 41 extracts pattern features from each of a plurality of sample patterns stored in the sample data 30. For example, the extraction unit 41 normalizes the layout pattern around the defective portion of the wiring layer where the defect occurs in the lithography process stored as the sample pattern based on the design rule of the layout pattern. For example, in an integrated circuit, a minimum line width, a minimum interval, a via size, and the like are determined as design rules according to process technology. The extraction unit 41 normalizes the layout pattern around the defective portion, for example, with the minimum line width that is a layout pattern design rule. The sample pattern design rule may be stored in the sample data 30 or may be stored as other data.

  FIG. 6 is a diagram illustrating an example of layout pattern normalization. In the example of FIG. 6, layout patterns A and B of two process technologies A and B are shown. Numerical values shown in the layout patterns A and B indicate dimensions such as a wiring width, a wiring interval, and a wiring length. In the example of FIG. 6, it is assumed that the minimum line width of the process technology A is 100 and the minimum line width of the process technology B is 80. For example, the extraction unit 41 normalizes the layout patterns A and B by dividing each dimension by the minimum line width, and obtains the layout pattern at a ratio to the minimum line width. In this way, both the layout patterns A and B can be expressed as the layout pattern C by dividing by the minimum line width and normalizing.

  The extraction unit 41 extracts feature information indicating the feature of the defective portion from the normalized layout pattern C. This feature information may be any as long as it indicates the feature of the pattern. For example, the extraction unit 41 obtains a layout pattern of a wiring layer in which a defect occurs. Then, the extraction unit 41 extracts, as feature information, a first feature vector including a feature amount related to the relative positional relationship between figures constituting the layout pattern from the obtained layout pattern. For example, the extraction unit 41 performs Delaunay triangulation by connecting the vertices of the figures forming the layout pattern, and obtains a plurality of triangles obtained by connecting the vertices of the figures.

  FIG. 7 is a diagram for explaining the flow of Delaunay triangulation. FIG. 7A shows an example of a wiring pattern. FIG. 7B shows a Voronoi diagram generated for the wiring pattern shown in FIG. FIG. 7C is a Delaunay diagram generated for the wiring pattern shown in FIG. 7A or the Voronoi diagram shown in FIG. 7B. In FIGS. 7A to 7C, the dot pattern portion indicates a wiring portion.

  The extraction unit 41 obtains the vertex coordinates of the wiring portion of the layout pattern shown in FIG. 7A, and generates the Voronoi diagram shown in FIG. 7B from the obtained vertex coordinates. A Voronoi diagram is a diagram generated by dividing each point of a point set on a plane or space depending on which point is closest to the point. Then, the extraction unit 41 generates a Delaunay diagram shown in FIG. 7C by connecting the generatrix of adjacent regions from the Voronoi diagram shown in FIG. 7B. This Delaunay diagram expresses the relative positional relationship between each figure.

  The extraction unit 41 obtains a triangle attribute for each triangle from the Delaunay diagram. Examples of this attribute include vertex coordinates, area, perimeter, and interior angles of triangles. Note that other items may be added to the attribute, and any item may be excluded.

  The extraction unit 41 obtains various feature amounts for each sample pattern, and generates a first feature vector having each feature amount as an element for each sample pattern. For example, the extraction unit 41 obtains the number of triangles, the average area of the triangles, the minimum area of the triangles, the maximum area of the triangles, and the barycentric coordinates of all the triangles as the feature quantities. Then, the extraction unit 41 generates a first feature vector having each obtained feature amount as an element. Note that the elements of the first feature vector are not limited to those described above, and other elements may be added, or any element may be omitted. For example, the extraction unit 41 may obtain, as elements, the number of vertices, the number of sides of the triangle, the standard deviation of the area, the distance between each center of gravity of a predetermined number of triangles having a small area and the center of the layout pattern, and the like. . The distance between each center of gravity of a predetermined number of triangles having a small area and the center of the layout pattern indicates whether a fine figure in the layout pattern is present at a location near or far from the pattern center. It becomes an indicator.

  In addition, the vertex has a convex vertex and a concave vertex. FIG. 8 is a diagram illustrating an example of a convex vertex and a concave vertex. The number of vertices may be obtained separately from the number of convex vertices and the number of concave vertices. FIG. 8 is a diagram illustrating an example of a convex vertex and a concave vertex.

Furthermore, the element of the first feature vector may be a feature obtained by dividing the sample pattern into a plurality of regions and obtaining each region. For example, the element of the first feature vector may be obtained for each region by dividing the sample pattern into a plurality of regions according to the distance from the pattern center. FIG. 9 is a diagram illustrating an example in which the sample pattern is divided into a plurality of regions according to the distance from the pattern center X. In the example of FIG. 9, the sample pattern is divided into regions by a radius r _{1, a} radius r _{2, and a} radius r ₃ from the center X. For example, the extraction unit 41 calculates the number of convex vertices, the number of concave vertices, the number of via vertices in the adjacent upper wiring layer, and the via in the adjacent lower wiring layer for each area within the radius r _{1, the} radius r _{2, and the} radius r _3. The first feature vector may be generated using the number of vertices as an attribute. In this manner, by extracting features in a plurality of regions according to the distance from the pattern center, the features of each region can be extracted individually. For example, it is possible to individually extract the features of a region near the center X and a region including a position away from the center X. Thereby, the influence of each area | region with respect to a defect can be reflected in the identification model mentioned later. Note that the areas may be determined so as not to overlap. For example, regions, the radius r ₁ within the area, the radius r ₂ within a region from the radius r _1, may be divided and region larger than the radius r _3.

  In the above-described example, the extraction unit 41 generates the Delaunay diagram from the Voronoi diagram. For example, by using the sequential addition method, the vertex coordinates of each figure forming the wiring pattern without generating the Voronoi diagram. Delaunay diagrams can also be generated from

  In the above-described example, the extraction unit 41 extracts the feature amount from the Delaunay diagram, but based on the polygon in the Voronoi diagram generated for the vertices of the figures constituting the layout pattern, the feature related to the relative positional relationship. The amount may be extracted.

  The extraction unit 41 generates a plurality of layout patterns by changing some or all of the shift, inversion, and rotation of the center position of the normalized layout pattern, and generates the above-described layout patterns from each of the generated plurality of layout patterns. In this way, pattern features may be extracted. For example, the extraction unit 41 generates a plurality of layout patterns by rotating and inverting each of the layout patterns stored as sample patterns by 90 degrees. Further, the extraction unit 41 generates a plurality of layout patterns by shifting the center position of each layout pattern stored as a sample pattern by a predetermined amount. FIG. 10 is a diagram illustrating an example of rotation and inversion of the layout pattern. The original layout pattern 80 is a layout pattern stored as a sample pattern. FIG. 10 shows a layout pattern 81 obtained by rotating the original layout pattern 80 counterclockwise by 90 degrees, and a layout pattern 82 obtained by inverting the original layout pattern 80 about the vertical axis (vertical direction in FIG. 10). Has been. FIG. 11 is a diagram illustrating an example of the shift of the center position of the layout pattern. The original layout pattern 85 is a layout pattern stored as a sample pattern. FIG. 11 shows a center 86a of the layout pattern and positions 86b to 86e shifted from the center by a predetermined amount in the vertical and horizontal directions. This predetermined amount is, for example, the number of wires. As an example, the predetermined amount is twice the minimum line width. In the example of FIG. 11, a layout pattern 87 in which the center of the original layout pattern 85 is shifted to a position 86b is shown.

The extraction unit 41 uses a predetermined element of the design rule including the first feature vector extracted from the layout pattern and the normalization element used for normalizing the layout pattern as the feature of the layout pattern. For example, in the example of FIG. 6, the case where two layout patterns A and B are normalized with the minimum line width and (f _p1 , f _p2 , f _p3 ,..., F _p8 ) are extracted as the first feature vectors. Show. In the example of FIG. 6, the features of the layout patterns A and B are shown using the first feature vector, the minimum line width, the minimum interval, and the via size of the design rule as the features of the layout pattern. When the extraction unit 41 generates a plurality of layout patterns by changing some or all of the shift, inversion, and rotation of the center position, the feature information 31 includes the feature amount of the changed change element. . For example, when the rotation is performed, the extraction unit 41 includes the rotation angle in the feature information 31 as a feature amount.

  The extraction unit 41 stores the feature of the layout pattern in the storage unit 23 as feature information 31 together with hot spot information that is known in advance. As described above, the hot spot information is information indicating whether or not the corresponding pattern has a hot spot, and is “1” when there is a hot spot and “0” when there is no hot spot.

FIG. 12 is a diagram illustrating an example of feature information. In the feature information 31 shown in FIG. 12, the first feature vector extracted from one layout pattern in each row, the design rule feature of the layout pattern, and hot spot information of the layout pattern are recorded. In the example of FIG. 12, the elements of the first feature vector are (f _p1 , f _p2 , f _p3 ,..., F _p8 ) and eight elements, and the design rule elements are (f _d1 , f _d2 , f _This shows the case of _d3 ) and three elements. Here, the feature amounts of the layout pattern described above are used as the feature amounts f _p1 , f _p2 , f _p3 ,..., F _p8 included in the first feature vector. As the feature amounts f _d1 , f _d2 , and f _d3 , feature amounts of predetermined elements of the design rule including the above-described normalization elements are used. The row number of the feature information 31 is used as identification information for each feature vector. Further, the hot spot information may indicate a value within a range of 0 to 1 in order to indicate the likelihood of becoming a hot spot, for example.

The generation unit 42 generates an identification model that identifies the presence or absence of a hot spot based on the first feature vector extracted by the extraction unit 41 and a predetermined element of the design rule including the normalization element used for normalization. For example, the extraction unit 41 calculates whether or not a defect has occurred by performing predetermined calculations on the feature amount and the design rule, the minimum line width, the minimum interval, and the via size as elements of the feature vector. An arithmetic expression to be generated is generated as an identification model. For example, let the feature vector be (f _p1 , f _p2 , f _p3 ..., F _pm ). f _p1 , f _p2 , f _p3 ..., f _pm are feature quantities that are elements of the first feature vector. m is the number of feature quantities as elements, and is “8” when the number of feature quantities as elements is eight. Further, the feature amounts of the elements of the design rule are assumed to be f _d1 , f _d2 , f _d3 ... F _dn . n is the number of feature quantities as elements of the design rule. For example, when the feature quantities are the minimum line width, the minimum interval, and the via size, “n” is “3”.

As shown in the following equation (1), the extraction unit 41 multiplies each element f _pi of the feature vector by each weight value W _i and each element f _dj of the feature vector by each weight value W _j. An arithmetic expression for calculating the calculated value as the defect degree G is generated as an identification model. For example, the defect degree G is higher in the range of 0 to 1 as being closer to 1, and is likely to be defective, and as it is close to 0, the possibility of being defective is low.

The generation unit 42 substitutes the feature quantity f _pi of each element of the feature vector of the feature information 31 and the feature quantity f _dj of the element of the design rule into the above-described equation (1). When the degree G is “1” and no defect has occurred, an arithmetic expression with the degree of defect G being “0” is obtained. Then, the generation unit 42 uses the weight values W _i and W _j of the respective arithmetic expressions as parameters, for example, performs fitting by machine learning using a known regression analysis method such as a least square method and support vector regression, and each arithmetic expression The values of the weight values W _i and W _j from which values close to the defect degree G are obtained. The generation unit 42 generates, as an identification model, Expression (1) in which the obtained weight values W _i and W _j are substituted. Then, the generation unit 42 stores the generated identification model as identification model information 32. This identification model is generated for each registered sample data 30. Therefore, when a plurality of sample data 30 are registered, the storage unit 23 stores a plurality of identification models.

The prediction unit 43 predicts a location where a defect occurs from the inspection target data 33 using each identification model stored in the identification model information 32. For example, the prediction unit 43 divides the layout pattern of the design data set as the inspection target data 33 into a size corresponding to the sample pattern of the identification model. The prediction unit 43 extracts pattern features from each of the divided layout patterns. For example, the prediction unit 43 extracts a second feature vector including a feature amount related to a relative positional relationship between figures constituting the layout pattern from the layout pattern of the wiring layer to be inspected and the adjacent wiring layer adjacent to the wiring layer. . Each element of the second feature vector is an element used for the calculation of the identification model. That is, when the identification model calculates the defect degree G using the feature quantities f _p1 , f _p2 , f _p3 ..., F _pm , the prediction unit 43 uses the feature quantities f _p1 , f as elements of the second feature vector. _{At least p2} , _fp3 ..., _fpm are extracted. Also, the prediction unit 43, from the design rule of design data inspection target data 33, a feature quantity of the elements of design rules used for the operation of the identification model _{f d1, f d2, f d3} ···, the _{f dn} Identify.

The predicting unit 43 obtains the defect degree G by substituting the feature quantity f _pi of the second feature vector and the feature quantity f _dj of the design rule respectively extracted from each of the divided layout patterns into the expression of the identification model. The predicting unit 43 identifies that a defect has occurred in the divided layout pattern portion in which the defect degree G is equal to or greater than a predetermined threshold. In this embodiment, the center position of the layout pattern portion identified as having a defect corresponds to the hot spot occurrence position. Therefore, when the predicting unit 43 identifies that the layout pattern after the division has a hot spot, the prediction unit 43 estimates and predicts the center position of the layout pattern after the division as the position of the hot spot in the prediction target pattern. The prediction unit 43 stores the estimated / predicted position of the hot spot, that is, the X coordinate value and the Y coordinate value in the storage unit 23 as the hot spot information 34.

  FIG. 13 is a diagram illustrating an example of hot spot position information. In the example shown in FIG. 13, ID as identification information for identifying each hot spot, the X coordinate value and the Y coordinate value indicating the position of the hot spot specified by the ID, and the score of the hot spot specified by the ID And are recorded in association with each other. As the score, the defect degree G is recorded. For example, “1” or “0” may be recorded corresponding to the presence or absence of a hot spot.

  Here, when the identification model is generated from a layout pattern in which a defect occurs regardless of the process technology, the weight value for the feature value of the design rule tends to be small, and the defect occurs even if the process technology is different. You can predict where to go. On the other hand, when an identification model is generated from a layout pattern in which a defect occurs in a specific process technology, the weight value for the feature value of the design rule tends to increase, and a point where a defect occurs in the specific process technology is predicted. it can. In other words, by generating an identification model that includes design rule features, it is possible to predict both the locations where defects occur in common and the locations where defects occur in a specific process technology, even if the process technologies are different. .

  The output unit 44 outputs the prediction result. For example, the output unit 44 displays the position of the hot spot stored in the hot spot information 34 on the display unit 21 as a prediction result screen.

Next, a specific example will be described. In the following, in order to simplify the description, two items to be extracted as feature vectors are f _p1 and f _p2 , and an item of a normalization element using a feature of the design rule for normalization is one of f _d1 . This will be described as an example. That is, the features of the layout pattern are represented by (f _p1 , f _p2 , f _d1 ). For example, as a result of extracting features from the layout patterns A to C, the features of the layout patterns A to C are as shown in the following equations (2) to (4). Layout patterns A and B have hot spots, and layout pattern C has no hot spots.

Layout pattern A: (19, 9, 80) (2)
Layout pattern B: (20, 6, 100) (3)
Layout pattern C: (10, 2, 80) (4)

  Substituting the respective feature quantities of the layout patterns A to C into the above equation (1), the following equations (5) to (7) are obtained. The layout patterns A and B have a defect degree G of “1” because defects occur. The layout pattern C has a defect degree G of “0” because no defect occurs.

19 × W ₁ + 9 × W ₂ + 80 × W ₃ = 1 (5)
20 × W ₁ + 6 × W ₂ + 100 × W ₃ = 1 (6)
10 × W ₁ + 2 × W ₂ + 80 × W ₃ = 0 (7)

From these equations (5) to (7), the weight values W ₁ , W ₂ and W ₃ are obtained as in the following equations (8) to (10).

W ₁ = 1/6 (8)
W ₂ = −1 / 14 (9)
W ₃ = −2 / 105 (10)

The defect location prediction apparatus 10 predicts whether or not a defect will occur by predicting the occurrence of a defect using the equation (1) into which the values of the weight values W ₁ , W ₂ , and W ₃ are substituted, as an identification model. It becomes possible.

  Next, the flow of processing executed by the defect location prediction apparatus 10 according to the present embodiment will be described with reference to FIGS. FIG. 14 is a diagram schematically showing an overall processing flow for generating an identification model and predicting a defect location.

  As shown in FIG. 14, the process by the defect location prediction apparatus 10 is divided into an identification model generation process and a detection process. The identification model generation process is a process for generating a hot spot identification model based on the sample data 30 whose presence or absence of the hot spot is known. The identification model generation process includes a feature vector extraction process (S1) and a model generation process (S2). The detection process is a process of predicting / detecting the position of the hot spot in the prediction target pattern using the generated hot spot identification model. The detection process includes a defect location prediction process (S3). The identification model generation process and the detection process are executed at a timing when a predetermined operation instructing the start of the process is performed from the operation screen.

  Prior to starting the process by the defect location prediction apparatus 10, sample data 30 is stored and registered in the storage unit 23 in advance.

  The defect location prediction apparatus 10 extracts a first feature vector including a feature amount related to a relative positional relationship between figures constituting each sample pattern by a feature vector extraction process (S1). Each feature amount of the extracted first feature vector is stored in the storage unit 23 as feature information 31 together with the feature amount of the design rule and the hot spot information of each sample pattern. The feature vector extraction process will be described in detail with reference to FIG.

  When the feature information 31 is obtained, the defect location prediction apparatus 10 generates an identification model that identifies the presence or absence of a hot spot by the model generation process (S2). The generated identification model is stored in the storage unit 23. The model generation process will be described in detail with reference to FIG.

  When the identification model is obtained and the inspection target data 33 for detecting a hot spot is set, the defect location prediction apparatus 10 executes a defect location prediction process (S3) for the inspection target data 33. The defect location prediction process will be described in detail with reference to FIG.

  The defect location prediction device 10 divides the layout pattern of the inspection target data 33 by the defect location prediction process (S3), extracts the second feature vector and the feature amount of the design rule, and determines whether there is a defect based on the identification model. Identify The detected hot spot position is stored in the storage unit 23 as hot spot information 34.

  Next, the feature vector extraction process will be described. FIG. 15 is a flowchart showing the procedure of the feature vector extraction process.

  The extraction unit 41 selects an unselected sample pattern from the sample patterns stored in the sample data 30 (S10).

  The extraction unit 41 normalizes the selected sample pattern based on the design rule of the layout pattern that is the sample pattern (S11). Then, the extraction unit 41 changes some or all of the shift, inversion, and rotation of the center position of the normalized layout pattern to generate a plurality of layout patterns (S12).

  The extraction unit 41 extracts, from each generated layout pattern, a first feature vector including a feature amount related to the relative positional relationship between figures constituting the layout pattern (S13). For example, the extraction unit 41 performs Delaunay triangulation by connecting the vertices of the figures forming the layout pattern, and obtains a plurality of triangles obtained by connecting the vertices of the figures. Then, the extraction unit 41 obtains various feature amounts from a plurality of triangles, and extracts a first feature vector having each feature amount as an element.

  For each layout pattern, the extraction unit 41 extracts each feature quantity of the extracted first feature vector and each feature quantity of a predetermined element of the design rule including the normalization element used for normalization together with the hot spot information and the feature information 31. Is stored in the storage unit 23 (S14).

  The extraction unit 41 determines whether or not all sample patterns have been selected (S15). When an unselected sample pattern exists (No at S15), the extraction unit 41 proceeds to S10 and extracts the first feature vector from the unselected sample pattern. On the other hand, when all the sample patterns have been selected (Yes at S15), the process ends.

  Through the above processing, the first feature vector is obtained from each sample pattern of the sample data 30. The acquired feature amounts of the first feature vectors and the design rules are stored in the storage unit 23 as feature information 31 together with hot spot information of each sample pattern.

  Next, the model generation process will be described. FIG. 16 is a flowchart illustrating the procedure of the model generation process.

  The generation unit 42 reads each feature amount of the first feature vector and each feature amount of the design rule for the layout pattern in which the defect is generated and the layout pattern in which the defect is not generated from the feature information 31 (S20). The generation unit 42 substitutes the read feature amount into the above-described equation (1), and when a defect occurs, the defect degree G is set to “1”, and when no defect occurs, the defect degree G is set to “0”. Is calculated (S21).

  Then, the generation unit 42 performs fitting by machine learning, and obtains a weight value that provides a value close to the defect degree G of each arithmetic expression (S22). The generation unit 42 generates an identification model in which the obtained weight value is substituted (S23). And the production | generation part 42 stores the produced | generated identification model in the identification model information 32 (S24), and complete | finishes a process.

  Through the above processing, the identification model generated from the sample data 30 is stored in the identification model information 32.

  Next, the defect location prediction process will be described. FIG. 17 is a flowchart illustrating the procedure of the defect location prediction process.

  The prediction unit 43 selects an unselected identification model from among the identification models stored in the identification model information 32 (S30). The prediction unit 43 divides the layout pattern of the design data set as the inspection target data 33 into a size corresponding to the sample pattern of the selected identification model (S31).

  The prediction unit 43 normalizes each divided layout pattern based on the design rule of the layout pattern (S32). Then, the predicting unit 43 extracts the second feature vector used in the selected identification model from the wiring layer to be inspected in each normalized layout pattern and the layout pattern of the adjacent wiring layer adjacent to the wiring layer. (S33). Then, the prediction unit 43 selects, for each divided layout pattern, the feature amount of each element of the second feature vector and each feature amount of the predetermined element of the design rule including the normalization element used for normalization. The defect degree G is obtained by substituting it into the identified model (S34).

  The predicting unit 43 identifies that a defect occurs in the divided layout pattern portion having a defect degree G of a predetermined threshold or more, and stores the center position of the divided layout pattern in the hot spot information 34 as the hot spot position. (S35).

  The prediction unit 43 determines whether selection of all the identification models has been completed (S36). When an unselected identification model exists (No at S36), the prediction unit 43 proceeds to S30, selects an unselected identification model, and identifies a defective portion. On the other hand, when all the identification models have been selected (Yes at S36), the process ends.

  As described above, the defect location prediction apparatus 10 normalizes a layout pattern in which a defect occurs in the lithography process based on the design rule of the layout pattern, and extracts feature information indicating the feature of the defect location from the normalized layout pattern. To do. The defect location prediction apparatus 10 generates an identification model for identifying a defect location based on the extracted feature information and a predetermined element of the design rule including the normalization element used for normalization. The defect location prediction apparatus 10 normalizes the layout pattern to be inspected based on the design rule of the layout pattern, and predicts a location where a defect occurs from the normalized layout pattern using the generated identification model. Thereby, the defect location prediction apparatus 10 can predict a location where a defect occurs even when the process technologies are different.

  In addition, the defect location prediction apparatus 10 generates a plurality of layout patterns by changing some or all of the shift, inversion, and rotation of the center position of the normalized layout pattern. The defect location prediction apparatus 10 extracts feature information indicating the feature of the defect location from each of the generated layout patterns. The defect location prediction apparatus 10 identifies a plurality of layout patterns based on feature information extracted from the layout patterns, predetermined elements of a design rule including a normalization element used for normalization, and changed change elements. Generate each model. The defect location prediction apparatus 10 predicts a location where a defect occurs from the layout pattern to be inspected using each generated identification model. As a result, the defect location prediction apparatus 10 can predict a location where a defect occurs even when there is a positional shift or a rotation angle difference between the layout pattern as the sample data 30 and the layout pattern to be inspected.

  Further, the defect location prediction apparatus 10 normalizes a layout pattern in which a defect occurs with the minimum line width of the layout pattern. The defect location prediction apparatus 10 generates an identification model for identifying a defect location based on the feature information, the minimum line width, the minimum interval, and the minimum via size of the layout pattern. Thereby, the defect location prediction apparatus 10 can normalize a layout pattern to a common pattern that does not depend on process technology, and can predict a location where a defect occurs even when the process technology is different.

  Although the embodiments related to the disclosed apparatus have been described so far, the disclosed technology may be implemented in various different forms other than the above-described embodiments. Therefore, another embodiment included in the present invention will be described below.

  For example, in the above-described embodiment, the case where the features of the layout pattern are extracted to generate the identification model and the defect portion prediction using the identification model is performed by the same single device has been described. It is not limited to. For example, the features of the layout pattern may be extracted to generate an identification model and the defect location prediction using the identification model may be performed by another device. For example, one eye computer extracts features of a layout pattern to generate an identification model, two eye computers acquire an identification model from one eye computer, and defect locations using the acquired identification model are identified. A prediction may be made. In this case, the first computer corresponds to the identification model generation device, and the second computer corresponds to the defect location prediction device.

  In the above-described embodiment, the case has been described in which the feature model indicating the features of the layout pattern is extracted from the sample data 30 as the feature information to generate the identification model. However, the disclosed apparatus is not limited thereto. For example, as a feature information, a pattern around a defective portion of a wiring layer in which a defect occurs from a layout pattern and an adjacent wiring layer adjacent to the wiring layer is extracted, and the defective portion is predicted using the extracted pattern as an identification model. Also good.

  In the above-described embodiment, a case has been described in which the Delaunay triangulation is performed by connecting the vertices of the figures constituting the layout pattern, and the feature amount relating to the relative positional relationship between the figures constituting the layout pattern is extracted. However, the apparatus is not limited to this. Any method may be used for extracting the feature amount.

  In the above-described embodiment, the case where the identification model is generated from the layout pattern of the wiring layer in which the defect occurs is described, but the disclosed apparatus is not limited to this. For example, the wiring layer may be defective due to the influence of a via formed in an adjacent wiring layer adjacent to the wiring layer in which the defect occurs. Therefore, an identification model may be generated from the layout pattern around the defective portion of the wiring layer where the defect occurs and the adjacent wiring layer adjacent to the wiring layer. For example, the layout pattern of the wiring of the wiring layer where the defect occurs and the via arrangement of the adjacent wiring layer adjacent to the wiring layer may be obtained, and the identification model may be generated from the obtained layout pattern. Prediction of the location where a defect occurs is, for example, extracting features from the layout pattern around the defective portion of the wiring layer of the wiring layer to be inspected and the adjacent wiring layer adjacent to the wiring layer as to the layout pattern to be inspected. And the location where a defect generate | occur | produces from a layout pattern is estimated from the extracted characteristic using the produced | generated identification model.

  Further, each component of each illustrated apparatus is functionally conceptual, and does not necessarily need to be physically configured as illustrated. In other words, the specific state of distribution / integration of each device is not limited to the one shown in the figure, and all or a part thereof may be functionally or physically distributed or arbitrarily distributed in arbitrary units according to various loads or usage conditions. Can be integrated and configured. For example, the processing units such as the reception unit 40, the extraction unit 41, the generation unit 42, the prediction unit 43, and the output unit 44 illustrated in FIG. 1 may be appropriately integrated or divided. Each processing function performed by each processing unit may be realized in whole or in part by a CPU and a program that is analyzed and executed by the CPU, or may be realized as hardware by wired logic. .

[Defect location prediction program]
The various processes described in the above embodiments can also be realized by executing a program prepared in advance on a computer system such as a personal computer or a workstation. Therefore, in the following, an example of a computer system that executes a program having the same function as in the above embodiment will be described. FIG. 18 is a diagram illustrating a computer that executes a defect location prediction program.

  As illustrated in FIG. 18, the computer 300 includes a CPU 310, a ROM (Read Only Memory) 320, an HDD (Hard Disk Drive) 330, and a RAM (Random Access Memory) 340. These units 310 to 340 are connected via a bus 400.

  The ROM 320 stores in advance a defect location prediction program 320a that performs the same function as each processing unit of the above embodiment. For example, the defect location prediction program 320a that exhibits the same functions as the reception unit 40, the extraction unit 41, the generation unit 42, the prediction unit 43, and the output unit 44 of the above embodiment is stored. Note that the defect location prediction program 320a may be separated as appropriate.

  Various data are stored in the HDD 330. For example, the HDD 330 stores the OS and various data.

  And CPU310 reads the defect location prediction program 320a from ROM320, and performs the operation | movement similar to each process part of an Example. That is, the defect location prediction program 320a performs the same operations as the reception unit 40, the extraction unit 41, the generation unit 42, the prediction unit 43, and the output unit 44 of the embodiment.

  The defect location prediction program 320a described above does not necessarily need to be stored in the ROM 320 from the beginning. The defect location prediction program 320a may be stored in the HDD 330.

  For example, a program is stored in a “portable physical medium” such as a flexible disk (FD), a compact disk read only memory (CD-ROM), a digital versatile disk (DVD), a magneto-optical disk, or an IC card inserted into the computer 300. Remember. Then, the computer 300 may read and execute the program from these.

  Furthermore, the program is stored in “another computer (or server)” connected to the computer 300 via a public line, the Internet, a LAN, a WAN, or the like. Then, the computer 300 may read and execute the program from these.

DESCRIPTION OF SYMBOLS 10 Defect location prediction apparatus 20 Input part 21 Display part 22 Communication I / F part 23 Storage part 24 Control part 30 Sample pattern 31 Feature information 32 Identification model information 33 Inspection object data 34 Hot spot information 40 Reception part 41 Extraction part 42 Generation part 43 Prediction unit 44 Output unit

Claims (7)

Created respectively in a different process technology to different design rule correspondingly, whether a known layout pattern of occurrence of defects in a lithographic process, and normalized based on the design rule of the layout pattern, normalized each layout pattern An extraction unit for extracting feature information indicating the feature of the defective part from,
Based on the predetermined information of the design rule including the feature information of each layout pattern extracted by the extraction unit, the presence / absence of a defect in each layout pattern, and the normalization element used for the normalization A generation unit for generating an identification model for identification;
A prediction unit that normalizes a layout pattern to be inspected based on a design rule of the layout pattern, and predicts a location where a defect occurs from the normalized layout pattern using the identification model generated by the generation unit;
The defect location prediction apparatus characterized by having. The extraction unit generates a plurality of layout patterns by changing any or all of the shift, inversion, and rotation of the center position of the normalized layout pattern, and detects a defective portion from the generated plurality of layout patterns. Extract feature information indicating the features,
The generating unit, for each of the plurality of layout patterns, based on feature information extracted from the layout pattern, a predetermined element of the design rule including a normalization element used for the normalization, and the changed change element , Generate each identification model,
The defect prediction apparatus according to claim 1, wherein the prediction unit predicts a position where a defect is generated from a layout pattern to be inspected using each identification model generated by the generation unit. The extraction unit normalizes the layout pattern in which the defect occurs with the minimum line width of the layout pattern,
3. The defect according to claim 1, wherein the generation unit generates an identification model for identifying a defect location based on the feature information, a minimum line width, a minimum interval, and a minimum via size of the layout pattern. Location prediction device. Created respectively in a different process technology to different design rule correspondingly, whether a known layout pattern of occurrence of defects in a lithographic process, and normalized based on the design rule of the layout pattern, normalized each layout pattern The defect location generated based on the predetermined elements of the design rule including the feature information indicating the feature of the defect location extracted from the presence / absence of a defect in each layout pattern and the normalization element used for the normalization A storage unit for storing an identification model for identifying
A prediction unit that normalizes a layout pattern to be inspected based on a design rule of the layout pattern, and predicts a location where a defect occurs from the normalized layout pattern using an identification model stored in the storage unit;
The defect location prediction apparatus characterized by having. Created respectively in a different process technology to different design rule correspondingly, whether a known layout pattern of occurrence of defects in a lithographic process, and normalized based on the design rule of the layout pattern, normalized each layout pattern An extraction unit for extracting feature information indicating the feature of the defective part from,
Based on the predetermined information of the design rule including the feature information of each layout pattern extracted by the extraction unit, the presence / absence of a defect in each layout pattern, and the normalization element used for the normalization A generation unit for generating an identification model for identification;
An identification model generation device characterized by comprising: On the computer,
Created respectively in a different process technology to different design rule correspondingly, whether a known layout pattern of occurrence of defects in a lithographic process, and normalized based on the design rule of the layout pattern, normalized each layout pattern Extract feature information indicating the features of the defect from
An identification model for identifying a defect location based on feature information of each extracted layout pattern, presence / absence of a defect in each layout pattern, and predetermined elements of the design rule including a normalization element used for the normalization Produces
The layout pattern to be inspected is normalized based on the design rule of the layout pattern, and a process for predicting a location where a defect occurs from the normalized layout pattern is executed using the generated identification model. Defect location prediction program. Computer
Created respectively in a different process technology to different design rule correspondingly, whether a known layout pattern of occurrence of defects in a lithographic process, and normalized based on the design rule of the layout pattern, normalized each layout pattern Extract feature information indicating the features of the defect from
An identification model for identifying a defect location based on feature information of each extracted layout pattern, presence / absence of a defect in each layout pattern, and predetermined elements of the design rule including a normalization element used for the normalization Produces
Normalizing the layout pattern to be inspected based on the design rule of the layout pattern, and using the generated identification model, executing a process for predicting a location where a defect occurs from the normalized layout pattern Defect location prediction method.

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