JP6119560B2 - Power controller - Google Patents

Description

  The present invention relates to a power controller that controls a supply amount of power.

  In artificial satellites, a power controller is used to supply a stabilized voltage of about 50V or 100V as a bus power source.

  As a conventional power controller for artificial satellites, the power generated from a plurality of solar cell arrays during sunlight is used as the power supplied to the load, and the surplus generated power short-circuits a specific solar cell array output (hereinafter referred to as a shunt). It is known to perform bus voltage control that suppresses an increase in bus voltage. This power controller is a satellite having various uses such as a technical test satellite (ETS series), a communication / broadcasting technology satellite (for example, COMETS), an earth observation satellite (for example, JERS-1), and a meteorological satellite (for example, MTSAT-2). Has been adopted.

  In this power controller, the output of each solar cell array is shunted or opened to adjust the total value of electric power or current generated from a plurality of solar cell arrays composed of about 10 to 40 stages, thereby providing a bus. Voltage control is performed. In this bus voltage control, each solar cell array is shunted or opened in a sequential manner according to the bus voltage variation, and each solar cell array is shunted or opened corresponding to the bus voltage variation range allowed in advance. The operating area is allocated. By this shunt or open operation and the operation of negative feedback oscillation control (commonly referred to as bang-bang control) composed of a capacitor bank provided to smooth the bus voltage, the bus voltage is stabilized within a specified fluctuation range. (For example, refer nonpatent literature 1).

  Further, in the conventional system, since the shunt or open operation area of each of the plurality of solar cell arrays is allocated according to the fluctuation of the bus voltage, there is no shunt corresponding to a specific solar cell array selected arbitrarily. Since the continuous shunting or opening operation is performed, there is a problem that the switch element generates heat according to the maximum switching frequency of the specific shunt switch element.

  As a means to solve this problem, the ratio of shunt and open is determined by negative feedback voltage control for each solar cell array according to the fluctuation of the bus voltage, and the respective switching elements are operated by switching in order. A method has been devised in which heat generated by the switch elements is distributed to all the switch elements (see, for example, Patent Document 1).

S. Kuwajima, et al., “Digital sequential shunt regulator for solar power conditioning of engineering test satellite (ETS-V),” Power Electronics Specialists Conference 1988 (PESC '88), IEEE, April 1988

Japanese Patent Application No. 2012-215378

  In such a power controller, the fluctuation of the bus voltage caused by the fluctuation of the load is stabilized by the negative feedback oscillation control or the negative feedback voltage control as described above, and the bus voltage fluctuation width increases as the negative feedback loop gain is set higher. Can be set narrowly, and more stabilized power can be supplied to the load. However, setting a high negative feedback loop gain has limitations in the design technology of the elements that make up the device that implements negative feedback oscillation control or negative feedback voltage control, so a specific bus voltage fluctuation range must be allowed. Therefore, it was a factor that hindered improvement in the quality of power supplied to the load.

  In addition, by increasing the capacitor bank, there is a tendency to relax in the design technology limits of devices that realize negative feedback oscillation control or negative feedback voltage control, and the negative feedback loop gain can be set high, so the bus voltage fluctuation range is narrowed be able to. However, in this case, the reduction in size and weight of the apparatus has been hindered.

  Further, the power controller shown in Patent Document 1 performs bus voltage control by switching each switch element in order after determining the ratio of shunt and opening by negative feedback voltage control for each solar cell array. Thus, the negative feedback voltage control operation is updated every time the operation of all the switch elements is completed. For this reason, it is impossible to respond to load fluctuations faster than this one-cycle period, and a large bus voltage fluctuation may occur transiently, which hinders improvement in the quality of power supplied to the load.

  In this case as well, it is possible to alleviate a large bus voltage fluctuation that occurs transiently by increasing the capacitor bank, but this hinders the reduction in size and weight of the device.

  As described above, the conventional power controller stabilizes the bus voltage fluctuation caused by the load fluctuation by the negative feedback oscillation control or the negative feedback voltage control. Therefore, by setting the negative feedback loop gain as high as possible, the bus voltage fluctuation range can be narrowed, and more stabilized power can be supplied to the load. However, there is a limit in setting the negative feedback loop gain high due to the design technical limit of the elements constituting the device. For this reason, a specific bus voltage fluctuation range must be allowed, which has been a factor that hinders improvement in power quality supplied to the load. Increasing the capacitor bank tends to relax the limit of the negative feedback loop gain that can be set, and the bus voltage fluctuation range can be narrowed. However, in this case, the reduction in size and weight of the device has been hindered.

  In addition, the power controller shown in Patent Document 1 performs bus voltage control by switching each switch element in order after determining the ratio of shunt and opening by negative feedback voltage control for each solar cell array. The negative feedback voltage control operation is updated every time the operation of all the switch elements is completed. For this reason, it is impossible to respond to load fluctuations faster than this one-cycle period, and a large bus voltage fluctuation may occur transiently, which hinders improvement in the quality of power supplied to the load. In this case as well, it is possible to alleviate a large bus voltage fluctuation that occurs transiently by increasing the capacitor bank, but this hinders the reduction in size and weight of the device. Further, although this problem can be solved by shortening the switching cycle of the switch elements, in that case, the heat generated by the switching of each switch element is increased, and the effect of the original heat distribution shown in Patent Document 1 is lost. This will hinder the reduction in size and weight.

  The present invention has been made in order to solve the above-described problems. The bus voltage fluctuation range is narrowed without hindering the reduction in size and weight of the apparatus, and the bus voltage transiently increases with respect to fast load fluctuations. An object of the present invention is to provide a power controller that suppresses the occurrence of fluctuations and has good power quality.

The power controller according to the present invention is connected in series to a plurality of power supplies that supply power, and is connected in parallel to the plurality of backflow prevention elements for preventing the backflow of current to each of the power supplies. In addition, a plurality of switch elements connected in series with the respective backflow prevention elements and switching the connection with the respective power supplies to short circuit or open, and error amplification indicating the excess or deficiency of the power supply state by the plurality of power supplies An error amplifier that outputs a signal, and an arithmetic drive unit that sequentially switches each of the switch elements by determining a power supply and a shunt ratio for each of the power sources by comparing the error amplified signal with a reference value. A first current detector indicating a total value of currents generated from the respective power supplies, and a supply state of electric power supplied from the respective power supplies. Comprising a second current detector that indicates the leakage current value, and an amplifier for outputting a signal indicating the difference of the current value of the first current detector and a second current detector, the operation drive unit, the The respective switch elements are switched so that an average current equal to the difference between the respective current values flows through the respective switch elements.

  According to the present invention, it is possible to narrow the bus voltage fluctuation range and suppress the generation of a large transient bus voltage fluctuation with respect to a fast load fluctuation, and provide a power controller with good power quality. It becomes possible to do.

3 is a circuit diagram showing a configuration of a power controller according to Embodiment 1. FIG. FIG. 3 is a circuit diagram illustrating a configuration of a power controller in which a bus voltage control system according to Embodiment 1 is represented by an equivalent circuit. 6 is a circuit diagram showing a configuration of a power controller according to Embodiment 2. FIG. 6 is a timing chart illustrating an operation of the power controller according to the second embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Embodiment 1 FIG.
FIG. 1 is a circuit diagram showing a configuration of a power controller according to Embodiment 1 of the present invention. FIG. 2 is a circuit diagram showing a configuration of a power controller in which the bus voltage control system is represented by an equivalent circuit based on FIG. In FIG. 1, a plurality of solar cell arrays SA1 to SAn (n is an integer of 3 or more) are connected in parallel to a load 6 and a capacitor bank 7 via a power bus 2, and power is supplied to the load 6 and the capacitor bank 7. Supply. The solar cell arrays SA1 to SAn are power supplies that supply power to the load 6. The power controller 1 short-circuits (shunts) surplus power of the solar cell arrays SA1 to n, and is connected to the solar cell arrays SA1 to n. The power controller 1 includes switching elements SW1 to SWn composed of field effect transistors, backflow prevention elements D1 to n composed of diodes, arithmetic drivers A1 to n, an error amplifier 3, and a timing signal generator. 4, an amplifier 5, a first current detector 8, and a second current detector 9.

  Each solar cell array SA1 to n is connected in parallel between the drain terminal and the source terminal of each switch element SW1 to n, and each connection circuit of each solar cell array SA1 to n and each switch element SW1 to n is connected. Connected to the power bus 2. The bus voltage Vbus falls within the specified fluctuation range from the operation of supplying or shunting the outputs of the solar cell arrays SA1 to SA to the load 6 and the accompanying increase / decrease of the bus voltage Vbus due to charging / discharging of the capacitor bank 7. Bus voltage control is performed.

  Further, the connection points of the positive terminals of the solar cell arrays SA1 to SAn and the drain terminals of the switch elements SW1 to SWn are connected in series to the anode terminal sides of the backflow prevention elements D1 to n, respectively. The cathode terminal side of the backflow prevention elements D1 to n is connected to the power bus 2. The output terminals of the arithmetic drive units A1 to n are arranged in parallel with the solar cell arrays SA1 to n and connected to the gate terminals of the switch elements SW1 to SWn, respectively. The first input terminals of the arithmetic drive units A1 to n are connected to the output terminal of the error amplifier 3. An error amplification signal Drive that is an output signal of the error amplifier 3 is input to each of the arithmetic drive units A1 to n. The input terminal of the error amplifier 3 is connected to the power bus 2. The first current detector 8 collectively detects solar cell array generated currents Istr1 to n that are outputs of the solar cell arrays SA1 to n. The current detected by the first current detector 8 indicates the total value of currents generated from the solar cell arrays SA1 to SAn that are a plurality of power supplies that supply power. The second current detector 9 detects the load current Iload. The current detected by the second current detector 9 indicates a current value based on the supply state of the power supplied from each of the solar cell arrays SA1 to SAn. The amplifier 5 takes in detection signals respectively obtained from both the first current detector 8 and the second current detector 9, and both the first current detector 8 and the second current detector 9. A signal proportional to the difference between the current values of the detected currents is generated and input to the arithmetic drive units A1 to n.

  The output terminal of the timing signal generator 4 is connected to the second input terminal of each of the arithmetic drivers A1 to n. The timing signal generator 4 outputs timing signals t1 to tn. Timing signals t1 to n output from the timing signal generator 4 are input to the arithmetic drivers A1 to n at a cycle Tpe. Further, the third input terminals of the arithmetic drive units A1 to n are connected to the reference voltage. A reference value Vth of the reference voltage is defined for the arithmetic drive units A1 to n.

  The arithmetic driving units A1 to n perform arithmetic processing based on the error amplification signal Drive output from the error amplifier 3 and the reference value Vth. The arithmetic driving units A1 to n perform this arithmetic processing at timings according to the timing signals t1 to n input from the timing signal generating unit 4, respectively, and for each switch element SW1 to n corresponding to the timing, The shunt time is determined from the power supply from each solar cell array SA1 to SAn and the ratio of shunts corresponding to the cycle Tpe in which the timing signals t1 to n are generated, and the switch elements SW1 to SWn are driven.

  Here, the timing signals t1 to n have an equal phase difference tph, and the value of the phase difference tph is determined so as to ensure the maximum frequency determined from the main performance requirements of the power controller 1. The period Tpe is set to a value obtained by multiplying the value of the phase difference tph by n times the number of stages of the solar cell array. The power controller 1 as a whole performs power supply and shunt switching operation at the maximum frequency determined by the phase difference tph. In each of the switch elements SW1 to SWn, a switching operation is performed at a frequency determined by a period Tpe that is 1 / n times the maximum frequency determined by the phase difference tph. Thus, power supply from the corresponding solar cell arrays SA1 to SAn to the load 6 is controlled by the arithmetic drive units A1 to n and the switch elements SW1 to SWn.

  The solar cell arrays SA1 to SAn shown in the first embodiment are an example of a power source that supplies electric power, and may be replaced with another power source having a similar function. In the first embodiment, the solar cell arrays SA1 to SAn are mounted on the artificial satellite, but may be installed on a space station, a space base, the ground, or the like. The backflow prevention elements D1 to n are examples of backflow prevention elements that prevent backflow of current to the corresponding solar cell arrays SA1 to n, respectively, and may be replaced with other backflow prevention elements having the same function. In the first embodiment, field effect transistors (FETs) are used as the switch elements SW1 to SWn, but other switch elements may be used.

  The bus voltage Vbus falls within the specified fluctuation range from the operation of supplying or shunting the outputs of the solar cell arrays SA1 to SA to the load 6 and the accompanying increase / decrease of the bus voltage Vbus due to charging / discharging of the capacitor bank 7. Bus voltage control is performed.

  The error amplifier 3 generates the error amplification signal Drive as a signal proportional to the fluctuation of the bus voltage Vbus, and the ratio of supply and shunt so that the bus voltage Vbus falls within the control target value Vbus (max) and the control allowable error ΔVbus. To decide.

  The error amplification signal Drive is expressed by Equation (1) in the constants A and B.

  Constants A and B in equation (1) are expressed by equations (2) and (3).

  The error amplification signal Drive is transmitted from the amplifier 3 to the arithmetic driving units A1 to n. The arithmetic drive units A1 to n perform arithmetic processing based on the comparison between the error amplification signal Drive and the reference value Vth, and supply the bus voltage Vbus to the control target value Vbus (max) and the control allowance while supplying appropriate power to the load 6. The power supply rate ONduty is determined so as to be within the error ΔVbus.

  The power supply amount ratio ONduty is expressed by Equation (4).

  This arithmetic processing is performed according to timing signals t1 to n supplied from the timing signal generator 4.

  The shunt time tshunt with respect to the generation period Tpe of the timing signals t1 to n is determined from the ratio ONduty of the power supply amount based on the calculation processing result of Expression (4), and the switch elements SW1 to n are driven. During this time, the generated power of the corresponding solar cell arrays SA1 to SAn is short-circuited (shunted) by the switch elements SW1 to SWn, so that the generated power is not supplied to the power bus 2.

  The shunt time tshunt is expressed by equation (5).

  By these operations, the amount of power supplied from the solar cell arrays SA1 to SAn to the power bus 2 is adjusted, and the bus voltage Vbus is controlled within a certain fluctuation range.

  In the above operation, in the first embodiment according to the present invention, the first current detector 8 that collectively detects the solar cell array generated currents Istr1 to n that are the outputs of the solar cell arrays SA1 to n, and the load A second current detector 9 for detecting the current Iload is provided, and a detection signal obtained from both is taken into the amplifier 5 to generate a signal proportional to the difference between the detected currents and input to the arithmetic drive unit A. It is made up of. In addition, each of the arithmetic drive units A1 to n causes an average current equal to the difference between the current values of the first current detector 8 and the second current detector 9 to flow through the switch elements SW1 to SWn. Also good.

  FIG. 2 is a circuit diagram showing the configuration of the power controller represented by an equivalent circuit for explaining the bus voltage control operation based on FIG. 2, the solar cell SA corresponds to the plurality of solar cell arrays SA1 to SAn (n is an integer of 3 or more) in FIG. 1, and is represented by one as an equivalent circuit in which n is infinite. Via the bus 2, the load 6 and the capacitor bank 7 are connected in parallel to supply power to the load 6 and the capacitor bank 7.

  The switch element SW corresponds to the switch elements SW1 to n in FIG. 1, and is represented by one as an equivalent circuit in which n is infinite, and the backflow prevention elements D1 to Dn in FIG. 1 are omitted in the equivalent circuit. Yes.

  The arithmetic drive unit A represents the arithmetic drive units A1 to n in FIG. 1 as one equivalent circuit. If n is infinite, the shunt current Is in the bus voltage control in the equivalent circuit is generated by the error amplifier 3. Controlled linearly.

  Therefore, the timing signal generator 4 and the timing signals t1 to tn are omitted in an equivalent circuit for explaining the bus voltage control operation with n being infinite.

  Further, in order to explain the principle of the bus voltage control operation, the reference value Vth is omitted and replaced with the bus voltage control target Vref in the error amplifier 3.

  At this time, the bus voltage control result Vout by the negative feedback voltage control operation with respect to the bus voltage control target Vref at the amplification degree G of the error amplifier 3, the resistance value R of the load 6 and the solar cell array generated current Istr is expressed by the following equation (6). expressed.

  As shown in Expression (6), the bus voltage control result Vout in FIG. 1 involves an error depending on the amplification degree G with respect to the bus voltage control target Vref.

  Therefore, in FIG. 2, in contrast to the bus voltage control in FIG. 1, the detection obtained from the first current detector 8 that detects the solar cell array generated current Istr and the second current detector 9 that detects the load current Iload. The signal is taken into the amplifier 5 and a signal proportional to the difference between the detected currents is generated and input to the arithmetic drive unit A. In the arithmetic drive unit A, the condition shown in Expression (7) is satisfied. Thus, the switch element SW is driven to control the shunt current Is.

  Since the bus voltage control result Vout is expressed by Expression (8), Expression (9) is satisfied under the condition that Expression (7) is satisfied.

  Therefore, if formula (8) and formula (9) are arranged, it can be expressed by formula (10).

  By such a principle, the bus voltage control result Vout matches the bus voltage control target Vref without depending on the amplification degree G.

  Since the conventional power controller stabilizes the fluctuation of the bus voltage caused by the fluctuation of the load by the negative feedback oscillation control or the negative feedback voltage control, a specific bus voltage fluctuation width must be allowed. Even if the gain is set as high as possible to narrow the bus voltage fluctuation range and supply more stabilized power to the load, the negative feedback oscillation control or the negative feedback voltage control is implemented. Due to limitations in design technology, there is a limit to setting a high negative feedback loop gain, which has been a factor that hinders improvement in the quality of power supplied to the load. Increasing the capacitor bank tends to relax the limit of the negative feedback loop gain that can be set, and the bus voltage fluctuation range can be narrowed. However, in this case, the reduction in the size and weight of the device has been hindered.

  Therefore, in the present embodiment, as shown in FIG. 1, detection signals obtained from the first current detector 8 that detects the solar cell array generated current Istr and the second current detector 9 that detects the load current Iload are obtained. The amplifier 5 generates a signal proportional to the difference between the detected currents and inputs the signal to the arithmetic drive unit A. The arithmetic drive unit calculates the difference between the solar cell array generated current Istr and the load current Iload. By driving the switch element SW so as to have the shunt current Is, the bus voltage control result Vout matches the bus voltage control target Vref without depending on the amplification degree G.

  The equation (1) indicating the error amplification signal Drive used in the description of the present embodiment shows an example that is directly proportional to the change in the bus voltage Vbus, but the same principle is applicable even when applied to an inversely proportional example. And replace the form of the formula.

  In the equations (6), (8), and (9) used in the description of the present embodiment, the resistance value R of the load 6 is shown as a DC resistance for convenience. However, in a transient operation, the impedance depends on the frequency. And replace the form of the equation on the same principle.

  Further, the error amplifier 3, the arithmetic drive unit A, and the bus voltage control target Vref in the description of the present embodiment may be configured by performing a digital signal processing by configuring a corresponding operation by a digital circuit program.

  Thus, in the present embodiment, in the power controller in FIG. 1, in addition to stabilizing the bus voltage fluctuation caused by the load fluctuation by the negative feedback voltage control, the difference between the solar cell array generated current and the load current is calculated. By controlling the shunt current, the bus voltage control result can be matched with the bus voltage control target.

  Therefore, it is possible to provide a power controller with good power quality by narrowing the bus voltage fluctuation range without hindering the reduction in size and weight of the device.

  As described above, the power controller 1 according to the first embodiment is the n of the power controller 1 including the solar cell arrays SA1 to n and the switch elements SW1 to n that are n-stage power supplies that supply power. A solar cell array SA, which is a power source that supplies power as an equivalent circuit with an infinite value, and a switch element SW that is connected in parallel with the power source and that is driven and controlled from being short-circuited to open. An error amplifier 3 that generates an error amplification signal from an error of the bus voltage control result Vout with respect to the bus voltage control target Vref, and an arithmetic drive unit A that determines a ratio of the amount of power supplied from the power source from the error amplification signal. Furthermore, the first current detector 8 that detects the solar cell array generated current Istr supplied from the power source, the second current detector 9 that detects the current of the load current Iload, and both current detectors. And an amplifier 5 that generates a signal that is proportional to the difference between the detected currents and receives a signal from the amplifier and shunts the difference between the solar cell array generated current and the load current in the arithmetic drive unit. The switch element is driven so as to be diverted to the switch element as the current Is. That is, the power controller 1 is connected in series with a plurality of power supplies (SA1 to n) that supply power, and a plurality of backflow prevention elements (preventing backflow of current to the respective power supplies (SA1 to n)) ( D1 to n) are connected in parallel to the respective power sources (SA1 to n) and connected in series to the respective backflow prevention elements (D1 to n), and are connected to the respective power sources (SA1 to n). A plurality of switch elements (SW1 to n) for switching the connection to short circuit or open; an error amplifier 3 for outputting an error amplification signal indicating an excess or deficiency of the power supply state by the plurality of power supplies (SA1 to n); Comparing the error amplification signal 3 with the reference value, the power supply and shunt ratio is determined for each of the power sources, and the arithmetic drive units (A1 to A1 to switch the switch elements (SW1 to SWn) in turn). n) and each of the above power supplies (SA1 to n) A first current detector 8 indicating a total value of generated currents; a second current detector 9 indicating a current value based on a supply state of power supplied from the respective power sources; and the first current detection. And an amplifier 5 for outputting a signal indicating a difference between current values of the second current detector 9 and the second current detector 9. Further, the arithmetic drive units (A1 to n) cause the respective switch elements (SW1 to n) to flow an average current equal to the difference between the respective current values to the respective switch elements (SW1 to n). It is characterized by switching.

  Thus, in addition to stabilizing the bus voltage fluctuation caused by the load fluctuation by the negative feedback voltage control, the bus voltage control is performed by controlling the difference between the solar cell array generated current and the load current as the shunt current. Since the result can be matched with the bus voltage control target, it is possible to provide a power controller with good power quality by narrowing the bus voltage fluctuation range without hindering reduction in size and weight of the apparatus.

Embodiment 2. FIG.
FIG. 3 is a circuit diagram showing a configuration of the power controller 1 according to the second embodiment of the present invention. The power controller 1 in FIG. 3 is characterized in that the power controller 1 in FIG. 1 further includes a differentiator 10 and a level determination unit 11. 3, the same symbols and names as those in FIG. 1 perform the same functions and operations as in FIG.

  The differentiator 10 is expressed by equation (11) using the load current change amount ΔIload and the design coefficient a in unit time Δt, using the detection signal of the load current Iload detected by the second current detector 9. The differential coefficient Dif is generated.

  The level determination unit 11 compares the absolute value of the differential coefficient Dif with the coefficient b to generate a differential coefficient variable Dif_t. Here, under the condition of Expression (12), the differential coefficient variable Dif_t is set to Expression (13).

  Further, under the condition of Expression (14), the differential coefficient variable Dif_t is set to Expression (15).

  The timing signal generation unit 4 generates timing signals t1 to tn based on the calculation result input from the level determination unit 11. When the absolute value of the differential coefficient Dif exceeds the coefficient b from the calculation result of the level determination unit 11, the timing signal generation unit 4 differentiates the phase difference tph so that the phase difference tph becomes narrower as the absolute value of the differential coefficient Dif increases. The phase difference tph is varied in inverse proportion to the coefficient variable Dif_t. As a result, the cycle Tpe in which the timing signals t1 to n make a round is expressed by Expression (16). In the equation (16), n is the number of constituent stages of the solar cell arrays SA1 to n and the switch elements SW1 to SWn, and tph is a fixed value under the condition of the equation (12).

  The value of the coefficient a in the equation (11) is a design constant that can be arbitrarily set.

  The value of the coefficient b in the equations (12) and (14) is set to an appropriate value at a practical level in order to suppress an increase in heat generated by switching by shortening the cycle Tpe more than necessary. It is a constant.

  By such a principle, the period Tpe is fixed to an appropriate value at the time of steady load, and the period Tpe is shortened according to the transient load fluctuation.

  FIG. 4 is a timing chart showing the operation of the power controller according to the second embodiment. 4, (a) shows the load current Iload that fluctuates transiently, (b) shows the differential coefficient Dif for the load current Iload, (c) shows the differential coefficient variable Dif_t for the load current Iload, (d ) Is a diagram showing a transition state of the cycle Tpe in which the timing signals t1 to n make a round. In FIG. 4, when the amount of change in the load current Iload per unit time exceeds a specified value determined by a constant coefficient b as shown in the equations (12) to (16), the cycle is inversely proportional to the differential coefficient variable Dif_t. It shows that Tpe is shortened.

  The conventional power controller performs bus voltage control by switching and operating each switch element in turn after determining the shunt and open ratio by negative feedback voltage control for each solar cell array. Since the negative feedback voltage control operation is updated every time the operation of the element makes a round, it cannot respond to load fluctuations faster than this one round cycle, and a large bus voltage fluctuation may occur transiently, This is a factor that degrades the quality of power supplied to the load. By increasing the capacitor bank, it is possible to mitigate large bus voltage fluctuations that occur transiently, but this hinders the reduction in size and weight of the device. Although this problem can be solved by shortening the switching cycle of the switch elements, in that case, the heat generated by switching of each switch element is increased, and the effect of the original heat distribution shown in Patent Document 1 is lost. It was supposed to hinder downsizing and lightening.

  Therefore, in the second embodiment, with respect to the bus voltage control by the negative feedback voltage control, the differentiator 10 detects a transient change of the load current Iload to generate the differential coefficient Dif, and the level determination unit 11 performs the differentiation. Compares the absolute value of the coefficient Dif with the coefficient b, and is fixed to an appropriate value in the area where the absolute value of the differential coefficient Dif does not exceed the coefficient b. From the area where the absolute value of the differential coefficient Dif exceeds the coefficient b A differential coefficient variable Dif_t that is varied in proportion to the absolute value of the differential coefficient Dif is generated, and the timing signal generator 4 varies the phase difference tph and the period Tpe in inverse proportion to the differential coefficient variable Dif_t.

  It should be noted that the differential coefficient Dif, coefficient b, differential coefficient variable Dif_t, phase difference tph and period Tpe relative to each other used in the description of the second embodiment are based on the logic for explaining the principle. The expression may be replaced by reversing the relationship of magnitude, proportionality, and inverse proportion.

  Further, the differentiator 10, level determination unit 11, timing signal generation unit 4, coefficient a, coefficient b, differential coefficient Dif, and differential coefficient variable Dif_t in the description of the second embodiment perform corresponding operations by a program of a digital circuit. It may be configured to perform digital signal processing.

  Thus, in the second embodiment, the ratio of shunt and open is determined by the negative feedback voltage control for each of the solar cell arrays SA1 to SAn, and then the switching elements SW1 to SWn are sequentially switched to operate the bus voltage. Take control. The power controller 1 updates the negative feedback voltage control operation every time the operation of all the switching elements SW1 to SWn completes, and fixes this one-cycle period to an appropriate value at the time of steady load, and at the time of transient load fluctuation By shortening this one-cycle period, it is possible to make a control response to a fast load fluctuation.

  Therefore, since heat generation due to switching of each switch element SW1 to n does not increase during a steady load and a control response can be made to a rapid load change, without hindering the reduction in size and weight of the device, The power controller 1 with good power quality can be provided.

  As described above, the power controller 1 according to the second embodiment has the n-stage power supply for supplying power, the solar cell arrays SA1 to SAn, the switch elements SW1 to SWn, and the timing signals t1 to tn for driving the switch elements. And a differentiator 10 for generating a differential coefficient Dif from the detection signal of the load current Iload detected by the second current detector 9 in a part of the configuration of the power controller 1 and the like, and the absolute value and coefficient of the differential coefficient A level determination unit 11 that generates a differential coefficient variable Dif_t by performing a comparison operation on b and a timing signal generation unit 4 that receives the differential coefficient variable and generates a timing signal are provided. The level of each timing signal is inversely proportional to the differential variable. The switching elements SW1 to SWn are driven by varying the phase difference tph and the period Tpe. That is, in the power controller 1 of the first embodiment, the differentiator 10 for differentiating the current signal obtained from the second current detector 9, the differential coefficient obtained from the differential signal of the differentiator 10, and the specific coefficient A level determination unit 11 that compares and outputs a differential coefficient variable is provided. The level determination unit 11 includes a timing signal generation unit 4 that generates a timing signal for determining a phase difference between the plurality of switch elements based on the differential coefficient variable input from the level determination unit 11. When the absolute value of the differential coefficient exceeds the specific coefficient, the phase difference is varied so that the phase difference becomes narrower in inverse proportion to the differential coefficient variable as the absolute value of the differential coefficient increases. And

  As a result, the cycle Tpe is fixed to an appropriate value at the time of steady load, and the cycle Tpe can be shortened according to transient load fluctuations without increasing heat generation due to switching of the switch elements SW1 to SWn. Control response is possible even with respect to load fluctuations, and it is possible to prevent transient bus voltage fluctuations from occurring. For this reason, it becomes possible to provide the power controller 1 with good power quality without hindering the reduction in size and weight of the apparatus.

  The invention according to the first and second embodiments is a power controller that controls the amount of power supplied via, for example, a power stabilization and non-stabilization bus of a solar cell mounted on an artificial satellite. Can be applied to.

  1 power controller, 2 power bus, 3 error amplifier, 4 timing signal generator, 5 amplifier, 6 load, 7 capacitor bank, 8 first current detector, 9 second current detector, 10 differentiator, 11 Level judgment unit, A computation drive unit, A1 to n computation drive unit, a coefficient, b coefficient, D1 to n Backflow prevention element, Dif differential coefficient, Dif_t differential coefficient variable, G amplification factor, Istr Solar cell array generated current, Istr Solar array generated current, Istr1-n Solar array generated current, Is shunt current, Iload load current, SA solar array, SA1-n solar array, SW switch element, SW1-n switch element, t1-n Timing signal , Vth reference value, Vref bus voltage control target.

Claims (2)

A plurality of backflow prevention elements that are connected in series with a plurality of power supplies that supply power, and that prevent backflow of current to each of the power supplies,
A plurality of switch elements connected in parallel with the respective power sources and connected in series with the respective backflow prevention elements, and switching the connection with the respective power sources to short circuit or open;
An error amplifier that outputs an error amplification signal indicating an excess or deficiency of the power supply state by the plurality of power supplies;
Comparing the error amplification signal with a reference value, an arithmetic drive unit that determines the ratio of power supply and shunt for each power source and sequentially switches the switch elements;
A first current detector indicating a total value of currents generated from the respective power sources;
A second current detector indicating a current value based on a supply state of power supplied from each of the power sources;
An amplifier that outputs a signal indicating a difference between current values of the first current detector and the second current detector;
Equipped with a,
The power controller according to claim 1, wherein the arithmetic drive unit switches the switch elements so that an average current equal to a difference between the current values flows through the switch elements . A plurality of backflow prevention elements that are connected in series with a plurality of power supplies that supply power, and that prevent backflow of current to each of the power supplies,
A plurality of switch elements connected in parallel with the respective power sources and connected in series with the respective backflow prevention elements, and switching the connection with the respective power sources to short circuit or open;
An error amplifier that outputs an error amplification signal indicating an excess or deficiency of the power supply state by the plurality of power supplies;
Comparing the error amplification signal with a reference value, an arithmetic drive unit that determines the ratio of power supply and shunt for each power source and sequentially switches the switch elements;
A current detector that indicates a current value based on a supply state of power supplied from each of the power sources;
A differentiator for differentiating a current signal obtained from the current detector;
A level determination unit that compares a differential coefficient obtained from the differential signal of the differentiator with a specific coefficient and outputs a differential coefficient variable;
A timing signal generating unit that generates a timing signal for determining a phase difference between the plurality of switch elements based on a differential coefficient variable input from the level determination unit;
When the absolute value of the differential coefficient exceeds the specific coefficient, the level determination unit increases the absolute value of the differential coefficient so that the phase difference is reduced in inverse proportion to the differential coefficient variable. A power controller characterized by varying a phase difference .

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