JP6115637B2 - PWM control circuit and switching power supply device - Google Patents

Description

  The present invention relates to a PWM control circuit that generates two PWM signals having a phase difference, and a switching power supply device including the PWM control circuit in a switching control unit.

  An example of a switching control circuit by PWM control in a switching power supply device is shown in Patent Document 1. Further, Patent Document 2 discloses a power supply device that applies an alternating voltage by a pseudo rectangular wave to a capacitive load.

  Generally, the PWM control circuit basically includes a triangular wave generation circuit that generates a triangular wave (sawtooth wave) and a comparison circuit that compares the triangular wave signal with a modulation signal. In the switching control circuit of the switching power supply device, the modulation signal is an output voltage detection signal, and the switching element is driven by the output signal of the PWM control circuit.

  FIG. 15 is a circuit diagram of the power supply device disclosed in Patent Document 2. In FIG. As shown in FIG. 15, a switching circuit SW1 and SW2 and capacitors C1 and C2 constitute a bridge circuit. The primary winding N1 of the transformer T is connected to the bridge circuit via the inductor L1. A capacitive load Cload or the like is connected to the secondary winding N2 of the transformer T. The switching elements SW1 and SW2 are alternately turned on / off by the control circuit 20. As a result, a pseudo rectangular wave signal is generated, and an AC voltage is applied to the capacitive load Cload.

JP 59-191478 A Japanese Patent No. 3228298

  In the power supply device shown in FIG. 15, the control circuit 20 is a circuit that alternately distributes a PWM signal having a fixed period between the high side and the low side, and therefore the phase difference of the drive signal with respect to the switching elements SW1 and SW2 is 180 °. The duty ratio of the pseudo rectangular wave to be generated is 50%. Therefore, even if a PWM control circuit as shown in Patent Document 1 is applied to the control circuit 20 shown in FIG. 15, the on-periods of the switching elements SW1 and SW2 are maintained while maintaining the phase difference of 180 °. It is only controlled.

  In order to obtain a pseudo rectangular wave signal with a duty ratio other than 50%, it is necessary to set the phase difference between the drive signals of the high-side switching element SW1 and the low-side switching element SW2 to a value other than 180 °. However, such a phase difference cannot be set in a conventional general PWM control circuit that generates a PWM signal by comparing a triangular wave signal and a modulation signal.

  Further, it is not possible to cope with the case where the duty of the pseudo rectangular wave is desired to be changed by an external signal or the like.

  In addition, when it is desired to synchronize the phases of a plurality of pseudo-rectangular wave outputs controlled independently, a plurality of the above controllers are used, but each of them has a triangular wave oscillator and cannot cope with it.

  An object of the present invention is to provide a PWM control circuit capable of generating two PWM signals having an arbitrary phase difference without complicating the circuit, or a PWM capable of obtaining a pseudo rectangular wave signal having an arbitrary duty ratio. It is to provide a control circuit and to provide a switching power supply device including the PWM control circuit.

(1) The PWM control circuit of the present invention is configured as follows.

A square wave signal setting means for inputting a square wave signal of a predetermined (arbitrary frequency and duty ratio) from the outside or generating internally,
A modulation signal input terminal for inputting a modulation signal;
First and second modulated signal output terminals for outputting two modulated signals having different timings (phases);
A first ramp wave generating circuit for starting sweeping of the first ramp wave in synchronization with a rising edge of the square wave signal;
A second ramp wave generating circuit for starting a sweep of the second ramp wave in synchronization with a falling edge of the square wave signal;
A first comparison circuit that compares the first ramp wave with the modulation signal and generates a first modulated signal by inverting the level according to the comparison result;
A second comparison circuit for comparing the second ramp wave and the modulation signal and generating a second modulated signal by inverting the level according to the comparison result;
It is provided with.

  With the above configuration, two PWM signals synchronized with the rising and falling of the square wave signal are generated without forming a complicated logic circuit. Further, since the two PWM signals are respectively synchronized with the rising and falling of the square wave signal, the timing difference (phase difference) between the two PWM signals can be freely controlled.

(2) The first ramp wave is reset to a potential at which a sweep starts between the falling and rising edges of the square wave signal, and the second ramp wave is a rising and falling edge of the square wave signal. It is preferable to reset to the potential at which the sweep starts.

(3) The first ramp wave is reset to the potential at which the sweep starts at the rising edge of the square wave signal, and the second ramp wave is reset to the potential at which the sweep starts at the falling edge of the square wave signal. May be.

(4) The first ramp wave is reset to the potential at which the sweep starts at the falling edge of the square wave signal, and the second ramp wave is reset to the potential at which the sweep starts at the rising edge of the square wave signal. May be.

  By resetting the first and second ramp waves to the potential at which the sweep is started at these timings, a ramp wave that does not affect the comparison with the modulation signal can be obtained.

(5) The first ramp wave generating circuit includes a first time constant circuit including a first capacitor connected between a reference potential (GND) and a power source, and the first time constant circuit. Are connected in series, and the first switch element whose on / off state changes in accordance with the level of the square wave signal and the state of the first time constant circuit are reset in synchronization with the fall of the square wave signal. A first reset circuit, and outputs an output voltage of the first time constant circuit as the first ramp wave,
The second ramp wave generating circuit is connected in series with a second time constant circuit including a second capacitor connected between a reference potential (GND) and a power source, and the second time constant circuit. And a second switch element whose on / off state changes according to the level of the square wave signal, and a second reset that resets the state of the second time constant circuit in synchronization with the rising of the square wave signal. And a circuit that outputs the output voltage of the second time constant circuit as the second ramp wave.

  With the above configuration, charging and discharging (reset) of the capacitor of the time constant circuit are performed by controlling the switch element, so that a simple circuit can be configured.

(6) The first ramp wave generating circuit is connected in series to the first time constant circuit having a first capacitor on the reference potential (GND) side, and the square wave A first switch element whose on / off state changes in accordance with a signal level; and a diode connected to the first capacitor in a direction in which a discharge current of the first capacitor flows through the first switch element. ,
The second ramp wave generating circuit is connected in series with a second time constant circuit having a second capacitor on the reference potential (GND) side, and the level of the square wave signal. A second switching element whose on / off state changes in response to the second switching element, and a diode connected to the second capacitor in a direction in which the discharge current of the second capacitor flows via the second switching element,
A first level shift circuit for level-shifting the modulation signal input by the first comparison circuit according to the state of the first switch element, and a modulation signal input by the second comparison circuit according to the state of the second switch element It is preferable that the second level shift circuit for level shifting be provided.

  With the above configuration, charging and discharging (reset) of the capacitor of the time constant circuit are performed by controlling the switch element, so that a simple circuit can be configured.

(7) In the above (5) or (6), the first time constant circuit includes a first constant current circuit that supplies a constant charging current to the first capacitor, and the second time constant. The circuit preferably includes a second constant current circuit for supplying a constant charging current to the second capacitor.

  With the above configuration, since the charging voltage to the capacitor changes linearly with time, the relationship between the pulse width of the PWM signal and the magnitude of the modulation signal becomes linear.

(8) The switching power supply device of the present invention is configured as follows.

In a switching power supply device comprising at least two switching elements and a switching control circuit for controlling these switching elements,
The switching control circuit includes the PWM control circuit according to any one of (1) to (7),
The modulation signal is an output feedback signal of a switching power supply circuit, and the first modulated signal and the second modulated signal are control signals for the two switching elements.

  With the above configuration, an AC voltage can be generated by an arbitrary pseudo rectangular wave signal with a duty ratio other than 50% with a switching control circuit having a simple circuit configuration.

  According to the present invention, two PWM signals synchronized with the rising edge and falling edge of the square wave signal are generated without forming a complicated logic circuit. Further, since the two PWM signals are respectively synchronized with the rising and falling of the square wave signal, the timing difference (phase difference) between the two PWM signals can be freely set.

FIG. 1 is a block diagram of a PWM control circuit 101 according to the first embodiment of the present invention. FIG. 2 is a circuit diagram of the PWM control circuit 101. FIG. 3 is a voltage waveform diagram of each part of the PWM control circuit 101. FIG. 4 is a circuit diagram of the PWM control circuit 102 according to the second embodiment. FIG. 5 is a diagram showing a charging current path when the first switch element SW11 is on and a discharge current path when the first switch element SW11 is off. FIG. 6 is a voltage waveform diagram of each part of the PWM control circuit 102. FIG. 7 is a circuit diagram of the PWM control circuit 103 according to the third embodiment. FIG. 8 is a voltage waveform diagram of each part of the PWM control circuit 103. FIG. 9 is a circuit diagram of the PWM control circuit 104 according to the fourth embodiment. FIG. 10 is a diagram showing a charging current path when the first switch element SW11 is on and a discharge current path when the first switch element SW11 is off. FIG. 11 is a voltage waveform diagram of each part of the PWM control circuit 104. FIG. 12 is a circuit diagram of the switching power supply device 201 of the fifth embodiment. FIG. 13 is a waveform diagram showing an example of the state of switching elements Q1 and Q2, the square wave signal, and the output voltage to capacitive load Cload in FIG. FIG. 14 is a waveform diagram showing an example of the state of switching elements Q1 and Q2, the square wave signal, and the output voltage to capacitive load Cload in FIG. FIG. 15 is a circuit diagram of the power supply device disclosed in Patent Document 2. In FIG.

  Hereinafter, some specific examples will be given to describe embodiments for carrying out the present invention. Each embodiment is an exemplification, and it is needless to say that still other embodiments can be obtained by partial replacement or combination of configurations shown in different embodiments.

<< First Embodiment >>
FIG. 1 is a block diagram of a PWM control circuit 101 according to the first embodiment of the present invention. The PWM control circuit 101 includes a square wave signal input terminal 11 for inputting a square wave signal, a modulation signal input terminal 12, a first modulated signal output terminal 21, and a second modulated signal output terminal 22.

  The PWM control circuit 101 includes a first ramp wave generation circuit 31, a second ramp wave generation circuit 32, a first comparison circuit 41, and a second comparison circuit 42. The second ramp wave generating circuit 32 includes a ramp wave generating circuit 30 and an inverting circuit 29.

  The first ramp wave generating circuit 31 generates a first ramp wave synchronized with the rising of the square wave signal input to the square wave signal input terminal 11. The ramp wave here is a waveform in which the sweep of the potential is started from a predetermined potential, and thereafter it is repeatedly reset to the predetermined potential. The ramp wave generation circuit 30 has the same configuration as that of the first ramp wave generation circuit 31 and generates a ramp wave synchronized with the rising edge of the input signal. The inverting circuit 29 inverts the polarity of the square wave input to the square wave signal input terminal 11. Therefore, the second ramp wave generation circuit 32 generates a second ramp wave that is synchronized with the falling edge of the square wave signal input to the square wave signal input terminal 11.

  The first comparison circuit 41 compares the first ramp wave and the modulation signal, and inverts the level according to the comparison result to generate the first modulated signal. The second comparison circuit 42 compares the second ramp wave with the modulation signal, and inverts the level according to the comparison result to generate the second modulated signal.

  FIG. 2 is a circuit diagram of the PWM control circuit 101. The PWM control circuit 101 operates using the power supply Vdc1 as a power supply. The first ramp wave generation circuit 31 includes a constant current circuit CC1, a first capacitor C11, a diode D11, a resistor R12, and a first switch element SW11. The second ramp wave generating circuit 32 includes a constant current circuit CC2, a second capacitor C21, a diode D21, a resistor R22, an inverting circuit 29, and a second switch element SW21. Both the first comparison circuit 41 and the second comparison circuit 42 are constituted by comparators. Here, the constant current circuits CC1 and CC2 are variable impedance type constant current circuits.

  In FIG. 2, the first time constant circuit 51 is configured by the constant current circuit CC1 and the first capacitor C11. Similarly, a second time constant circuit 52 is configured by the constant current circuit CC2 and the second capacitor C21. The diode D11, the resistor R12, and the first switch element SW11 constitute a first reset circuit 61. Similarly, a second reset circuit 62 is configured by the diode D21, the resistor R22, and the second switch element SW21.

  FIG. 3 is a voltage waveform diagram of each part of the PWM control circuit 101. First, when the square wave signal input to the square wave signal input terminal 11 rises at t0, the first switch element SW11 is turned on. Thereby, the constant current circuit CC1 starts charging the first capacitor C11 with a constant current. Therefore, the potential at the point b is swept and rises. Since the potential of the first capacitor C11 is input to the inverting input of the first comparison circuit 41 and the voltage of the modulation signal (potential at the point d) is input to the non-inverting input, the output of the first comparison circuit 41 at the timing t0. (Potential at point e), that is, the first modulated signal is at a high level.

  After that, when the potential of the first capacitor C11 (potential at the point b) exceeds the voltage of the modulation signal (potential at the point d) at the timing t1, the output (potential at the point e) of the first comparison circuit 41, that is, the first One modulated signal is at a low level.

  With the above operation, the first modulated signal becomes a high-level rectangular wave signal from timing t0 to timing t1.

  Thereafter, when the square wave signal falls at timing t2, the second switch element SW21 is turned on. Thereby, the constant current circuit CC2 starts charging the second capacitor C21 with a constant current. Therefore, the potential at the point c is swept and rises. Since the potential of the second capacitor C21 is input to the inverting input of the second comparison circuit 42 and the voltage of the modulation signal (potential at the point d) is input to the non-inverting input, the output of the second comparison circuit 42 at timing t2. (Potential at point f), that is, the second modulated signal is at a high level.

  Thereafter, when the potential of the second capacitor C21 (potential at the point c) exceeds the voltage of the modulation signal (potential at the point d) at the timing t3, the output (potential at the point f) of the second comparison circuit 42, that is, the first The second modulated signal is at a low level.

  With the above operation, the second modulated signal becomes a high-level rectangular wave signal from timing t2 to timing t3.

  The constant current value of the constant current circuit CC1 and the capacitance value of the first capacitor C11 are determined so that the rate of increase of the charging potential (ramp of the ramp wave) of the first capacitor C11 becomes a predetermined value. Similarly, the constant current value of the constant current circuit CC2 and the capacitance value of the second capacitor C21 are determined such that the rate of increase of the charging potential (ramp of the ramp wave) of the second capacitor C21 becomes a predetermined value. In this example, the slopes of the two ramp waves are equal.

  When the first switch element SW11 is turned off at the timing t2, the charge of the first capacitor C11 is discharged through the path of the diode D11 → the resistor R12 → the capacitor C11. However, since the first switch element SW11 is off at this time, the potential at the point b is kept at a high level even during the discharge of the capacitor C11. The value of the resistor R12 is determined so as to have a discharge time constant at which the potential of the first capacitor C11 becomes approximately zero until the next timing t0.

  Similarly, when the second switch element SW2 is turned off at timing t0, the charge of the second capacitor C21 is discharged through the path of the diode D21 → the resistor R22 → the capacitor C21. At this time, since the second switch element SW2 is off, the potential at the point c is kept at a high level even during the discharge of the capacitor C21. The value of the resistor R22 is determined so as to have a discharge time constant at which the potential of the second capacitor C21 becomes approximately zero until the next timing t2.

  When the voltage of the modulation signal (potential at point d) rises, as shown in FIG. 3, the inversion timing of the first comparison circuit 41 and the inversion timing of the second comparison circuit 42 are both delayed, and the first modulated signal and The on-duty of the second modulated signal increases.

  As described above, the first modulated signal is generated in synchronization with the rising timing of the square wave signal, and the second modulated signal is generated in synchronization with the falling timing of the square wave signal. Also, by setting the duty of the square wave signal, the first modulated signal and the second modulated signal can have an arbitrary phase difference other than 180 °.

<< Second Embodiment >>
FIG. 4 is a circuit diagram of the PWM control circuit 102 according to the second embodiment. The PWM control circuit 102 includes a first ramp wave generation circuit 31, a second ramp wave generation circuit 32, a first comparison circuit 41, and a second comparison circuit 42. The difference from the PWM control circuit 101 shown in FIG. 2 in the first embodiment is that resistors R11 and R21 are provided instead of the constant current circuits CC1 and CC2. That is, in the PWM control circuit 102, the resistor R11 and the first capacitor C11 constitute a first time constant circuit 51. Similarly, a second time constant circuit 52 is configured by the resistor R21 and the second capacitor C21.

  FIG. 5 is a diagram showing a charging current path when the first switch element SW11 is on and a discharge current path when the first switch element SW11 is off. When the first switch element SW11 is turned on, a charging current flows through the path of the resistor R11 and the capacitor C11, and the potential of the capacitor C11 increases exponentially. Further, when the first switch element SW11 is turned off, a discharge current flows through the diode D11 and the resistor R12, thereby resetting.

  FIG. 6 is a voltage waveform diagram of each part of the PWM control circuit 102. First, when the square wave signal input to the square wave signal input terminal 11 rises at t0, the first switch element SW11 is turned on. As a result, charging of the first capacitor C11 is started. Therefore, the potential at the point b is swept and rises exponentially. Since the potential of the first capacitor C11 is input to the inverting input of the first comparison circuit 41 and the voltage of the modulation signal (potential at the point d) is input to the non-inverting input, the output of the first comparison circuit 41 at the timing t0. (Potential at point e), that is, the first modulated signal is at a high level.

  After that, when the potential of the first capacitor C11 (potential at the point b) exceeds the voltage of the modulation signal (potential at the point d) at the timing t1, the output (potential at the point e) of the first comparison circuit 41, that is, the first One modulated signal is at a low level.

  With the above operation, the first modulated signal becomes a high-level rectangular wave signal from timing t0 to timing t1.

  Thereafter, when the square wave signal falls at timing t2, the second switch element SW21 is turned on. Thereby, charging of the second capacitor C21 is started. Therefore, the potential at the point c is swept and rises exponentially. Since the potential of the second capacitor C21 is input to the inverting input of the second comparison circuit 42 and the voltage of the modulation signal (potential at the point d) is input to the non-inverting input, the output of the second comparison circuit 42 at timing t2. (Potential at point f), that is, the second modulated signal is at a high level.

  Thereafter, when the potential of the second capacitor C21 (potential at the point c) exceeds the voltage of the modulation signal (potential at the point d) at the timing t3, the output (potential at the point f) of the second comparison circuit 42, that is, the first The second modulated signal is at a low level.

  With the above operation, the second modulated signal becomes a high-level rectangular wave signal from timing t2 to timing t3.

  As described above, even if the ramp wave generating circuit is configured by the CR time constant circuit, the first and second modulated signals subjected to PWM modulation can be generated.

<< Third Embodiment >>
FIG. 7 is a circuit diagram of the PWM control circuit 103 according to the third embodiment. The PWM control circuit 103 operates using the power supply Vdc1 as a power supply voltage. The first ramp wave generating circuit 31 includes a constant current circuit CC1, a first capacitor C11, a diode D11, a resistor R12, a first switch element SW11, and an inverting circuit 29. The second ramp wave generation circuit 32 includes a constant current circuit CC2, a second capacitor C21, a diode D21, a resistor R22, and a second switch element SW21. Both the first comparison circuit 41 and the second comparison circuit 42 are constituted by comparators.

  In FIG. 7, the first time constant circuit 51 is configured by the constant current circuit CC1 and the first capacitor C11. Similarly, a second time constant circuit 52 is configured by the constant current circuit CC2 and the second capacitor C21. As will be described later, in FIG. 7, resistors R12 and R22 are not resistors that determine a charging time constant.

  In FIG. 7, the diode D11 and the first switch element SW11 constitute a first reset circuit 61. Similarly, a second reset circuit 62 is configured by the diode D21 and the second switch element SW21. The resistor R13 and the diode D12 constitute a first level shift circuit 71. Similarly, a second level shift circuit 72 is configured by the resistor R23 and the diode D22.

  FIG. 8 is a voltage waveform diagram of each part of the PWM control circuit 103. First, when the square wave signal input to the square wave signal input terminal 11 rises at t0, the first switch element SW11 is turned off. Thereby, the constant current circuit CC1 starts charging the first capacitor C11 with a constant current. For this reason, the potential at the point n rises in a ramp waveform. Since the n-point potential is input to the inverting input of the first comparison circuit 41 and the voltage of the modulation signal (potential of the p-point) is input to the non-inverting input, the output (r-point) of the first comparison circuit 41 at timing t0. ), That is, the first modulated signal is at a high level.

  After that, when the potential at the point n exceeds the voltage of the modulation signal (potential at the point p) at timing t1, the output of the first comparison circuit 41 (potential at the point r), that is, the first modulated signal is low level. Become.

  With the above operation, the first modulated signal becomes a high-level rectangular wave signal from timing t0 to timing t1.

  Thereafter, when the square wave signal falls at timing t2, the second switch element SW21 is turned off. Thereby, the constant current circuit CC2 starts charging the second capacitor C21 with a constant current. Therefore, the potential at point o rises in a ramp waveform. Since the potential at the point o is input to the inverting input of the second comparison circuit 42 and the voltage of the modulation signal (potential at the point q) is input to the non-inverting input, the output (point s) of the second comparison circuit 42 at the timing t2. ), That is, the second modulated signal is at a high level.

  Thereafter, when the potential at point o exceeds the voltage of the modulation signal (potential at point q) at timing t3, the output of the second comparison circuit 42 (potential at point s), that is, the second modulated signal becomes low level. Become.

  With the above operation, the second modulated signal becomes a high-level rectangular wave signal from timing t2 to timing t3.

  Since the first switch element SW11 is in the ON state from the timing t2 to the next t0, the voltage of the inverting input of the first comparison circuit 41 (the potential at the n point) decreases, but the non-inversion of the first comparison circuit 41 The input voltage (potential at point p) is shifted to a low level. In this state, the voltage of the inverting input (potential at the n point) is higher than the voltage of the non-inverting input of the first comparison circuit 41 (potential at the p point) by the drop voltage of the resistor R12. The output remains low. Similarly, since the second switch element SW21 is in the ON state from timing t0 to t1, the voltage of the inverting input of the second comparison circuit 42 (potential at the point o) decreases, but the non-inverting input of the second comparison circuit 42 Is shifted to a low level. In this state, the voltage at the inverting input (potential at the point o) is higher than the voltage at the non-inverting input (potential at the point q) of the second comparison circuit 42 by the drop voltage of the resistor R22. The output remains low.

<< Fourth Embodiment >>
FIG. 9 is a circuit diagram of the PWM control circuit 104 according to the fourth embodiment. The PWM control circuit 104 includes a first ramp wave generation circuit 31, a second ramp wave generation circuit 32, a first comparison circuit 41, and a second comparison circuit 42. The third embodiment differs from the PWM control circuit 103 shown in FIG. 7 in that resistors R11 and R21 are provided instead of the constant current circuits CC1 and CC2. In other words, in the PWM control circuit 104, the resistors R11 and R12 and the first capacitor C11 constitute a first time constant circuit 51. Similarly, a second time constant circuit 52 is configured by the resistors R21 and R22 and the second capacitor C21.

  FIG. 10 is a diagram showing a charging current path when the first switch element SW11 is on and a discharge current path when the first switch element SW11 is off. When the first switch element SW11 is turned off, a charging current flows through the path of the resistors R11, R12 and the capacitor C11, and the potential of the capacitor C11 increases exponentially. Further, when the first switch element SW11 is turned on, a discharge current flows through the diode D11 and is reset thereby.

  FIG. 11 is a voltage waveform diagram of each part of the PWM control circuit 104. First, when the square wave signal input to the square wave signal input terminal 11 rises at t0, the first switch element SW11 is turned off. As a result, charging of the first capacitor C11 is started. Therefore, the potential at the point n rises exponentially (substantially in a ramp waveform). Since the n-point potential is input to the inverting input of the first comparison circuit 41 and the voltage of the modulation signal (potential of the p-point) is input to the non-inverting input, the output (r-point) of the first comparison circuit 41 at timing t0. ), That is, the first modulated signal is at a high level.

  After that, when the potential at the point n exceeds the voltage of the modulation signal (potential at the point p) at timing t1, the output of the first comparison circuit 41 (potential at the point r), that is, the first modulated signal is low level. Become.

  With the above operation, the first modulated signal becomes a high-level rectangular wave signal from timing t0 to timing t1.

  Thereafter, when the square wave signal falls at timing t2, the second switch element SW21 is turned off. Thereby, charging of the second capacitor C21 is started. Therefore, the potential at point o rises exponentially (substantially in a ramp waveform). Since the potential at the point o is input to the inverting input of the second comparison circuit 42 and the voltage of the modulation signal (potential at the point d) is input to the non-inverting input, the output (point f) of the second comparison circuit 42 at timing t2. ), That is, the second modulated signal is at a high level.

  Thereafter, when the potential at point o exceeds the voltage of the modulation signal (potential at point q) at timing t3, the output of the second comparison circuit 42 (potential at point s), that is, the second modulated signal becomes low level. Become.

  With the above operation, the second modulated signal becomes a high-level rectangular wave signal from timing t2 to timing t3.

  As described above, even if the ramp wave generating circuit is configured by the CR time constant circuit, the first and second modulated signals subjected to PWM modulation can be generated.

<< Fifth Embodiment >>
In the fifth embodiment, a configuration example of a switching power supply device is shown. FIG. 12 is a circuit diagram of the switching power supply device 201 of the fifth embodiment. The switching power supply device 201 includes a transformer T, a capacitor Cr, an inductor Lr, driver circuits 211 and 212, switching elements Q1 and Q2, an output feedback circuit 220, an error amplifier 221 and a PWM control circuit 101. The PWM control circuit 101 functions as a switching control circuit that controls the switching elements Q1 and Q2. The PWM control circuit 101 is the PWM control circuit 101 shown in FIG. 1, but may be any of the PWM control circuits 102, 103, and 104 of another embodiment.

  13 and 14 are waveform diagrams showing the relationship among the states of the switching elements Q1 and Q2, the square wave signal, and the output voltage to the capacitive load Cload in FIG. As shown in FIGS. 13 and 14, the output voltage rises during the on period of the low side switching element Q1, and after the low side switching element Q1 is turned off, the output voltage further rises only during the on period of the body diode of the high side switching element Q2. To do. Further, the output voltage decreases during the ON period of the high side switching element Q2, and after the high side switching element Q2 is turned OFF, the output voltage further decreases only during the ON period of the body diode of the low side switching element Q1. For example, the square wave signal input to the square wave signal input terminal 11 is a square wave signal having a frequency of 3 kHz and a duty of 30%. As a result, a pseudo rectangular wave AC voltage having a frequency of 3 kHz and a duty of 30% is applied to the capacitive load Cload.

  Since the waveform of the rise and fall of the output voltage is a sine waveform determined by the circuit constants of the capacitive load Cload and the inductor Lr, as shown in FIG. 13, the longer the on-time Ton of the switching elements Q1 and Q2, the longer The amplitude of the output voltage increases. In the example shown in FIG. 12, the on-time Ton of the switching elements Q1 and Q2 is feedback-controlled so that the amplitude of the output voltage becomes constant according to the output voltage of the output feedback circuit 220 and the error amplifier 221.

  Further, as shown in FIG. 14, the duty of the output voltage (pseudo rectangular wave) can be controlled by the on-timing difference between the switching elements Q1 and Q2, that is, the on-period T of the square wave signal.

  In the example shown in FIG. 12, the on-time Ton of the switching elements Q1, Q2 is feedback-controlled. However, the amplitude of the output voltage is controlled by adjusting the voltage input to the modulation signal input terminal 12. A circuit may be configured.

  In each of the embodiments described above, an example in which a square wave signal generation circuit is provided externally and a square wave signal is input from the external square wave signal generation circuit has been described. However, the square wave signal generation circuit is included in the PWM control circuit. May be provided. This square wave signal generating circuit includes, for example, a triangular wave generating circuit and a comparator, and the circuit is configured to set the duty of the square wave signal by controlling a reference signal input to the comparator. Further, the present invention can be applied to a circuit system having high-side and low-side switching elements such as a push-pull system and a half-bridge system.

C11: First capacitor C21: Second capacitors CC1, CC2: Constant current circuit
Cload ... capacitive load Cr ... resonant capacitors D11, D12, D21, D22 ... diode L1 ... inductor Lr ... resonant inductor Q1 ... low-side switching element Q2 ... high-side switching element SW11 ... first switch element SW21 ... second switch element T ... Transformer Vdc1 ... Power source 11 ... Square wave signal input terminal 12 ... Modulated signal input terminal 21 ... First modulated signal output terminal 22 ... Second modulated signal output terminal 29 ... Inverting circuit 31 ... First ramp wave generating circuit 32 Second ramp wave generation circuit 41 First comparison circuit 42 Second comparison circuit 51 First time constant circuit 52 Second time constant circuit 61 First reset circuit 62 Second reset circuit 71 ... first level shift circuit 72 ... second level shift circuits 102, 103, 104 ... PWM control circuit 201 ... switch Mode power supply device 211, 212 ... driver circuit 220 ... output feedback circuit 221 ... error amplifier

Claims (4)

A square wave signal setting means for inputting a square wave signal from the outside or generating internally, and
A modulation signal input terminal for inputting a modulation signal;
First and second modulated signal output terminals for outputting two modulated signals having different timings;
A first ramp wave generating circuit for starting sweeping of the first ramp wave in synchronization with a rising edge of the square wave signal;
A second ramp wave generating circuit for starting a sweep of the second ramp wave in synchronization with a falling edge of the square wave signal;
A first comparison circuit that compares the first ramp wave with the modulation signal and generates a first modulated signal by inverting the level according to the comparison result;
Comparing the modulated signal and the second ramp wave, and a second comparator circuit for generating a second modulated signal by inverting the level according to the comparison result,
The first ramp wave generating circuit includes a first time constant circuit having a first capacitor connected to a reference potential side, and a first reset circuit connected in parallel with the first capacitor, Outputting the output voltage of the first time constant circuit as the first ramp wave;
The first reset circuit includes a first switch element whose on / off state changes in accordance with a level of the square wave signal, and when the first switch element is on, the first reset circuit Holding the potential to start sweeping, and when the first switch element is in an OFF state, sweeping the first ramp wave;
The second ramp wave generation circuit includes a second time constant circuit having a second capacitor connected to a reference potential side, and a second reset circuit connected in parallel with the second capacitor, Outputting the output voltage of the second time constant circuit as the second ramp wave;
The second reset circuit includes a second switch element configured to reverse an on / off state with the first switch element, and when the second switch element is in the on state, the second lamp circuit Held at a potential to start sweeping the wave, and when the second switch element is in an off state, the second ramp wave is swept,
A signal input to the first comparison circuit is held at a level lower than the first ramp wave when the first switch element is in an on state, and the first comparison is performed when the first switch element is in an off state. A first level shift circuit for inputting the modulation signal to the circuit;
A signal input to the second comparison circuit is held at a level lower than the second ramp wave when the second switch element is in an on state, and the second comparison is performed when the second switch element is in an off state. A second level shift circuit for inputting the modulation signal to the circuit;
A PWM control circuit comprising: A square wave signal setting means for inputting a square wave signal from the outside or generating internally, and
A modulation signal input terminal for inputting a modulation signal;
First and second modulated signal output terminals for outputting two modulated signals having different timings;
A first ramp wave generating circuit for starting sweeping of the first ramp wave in synchronization with a rising edge of the square wave signal;
A second ramp wave generating circuit for starting a sweep of the second ramp wave in synchronization with a falling edge of the square wave signal;
A first comparison circuit that compares the first ramp wave with the modulation signal and generates a first modulated signal by inverting the level according to the comparison result;
A second comparison circuit that compares the second ramp wave and the modulation signal and generates a second modulated signal by inverting the level according to the comparison result;
The first ramp wave generating circuit includes a first time constant circuit and a first reset circuit,
The first time constant circuit includes a first capacitor and is connected between a reference potential and a power supply via a first switch element whose on / off state changes according to the level of the square wave signal. ,
The first reset circuit includes a first discharge resistor and the first switch element connected in parallel to the first time constant circuit, and when the first switch element is in an ON state, The output voltage of the time constant circuit of 1 is output as the sweep waveform of the first ramp wave, and the first capacitor is discharged via the first discharge resistor when the first switch element is in the OFF state. And resetting the state of the first time constant circuit and holding the first ramp wave at a power supply voltage or higher level,
The second ramp wave generating circuit includes a second time constant circuit and a second reset circuit,
The second time constant circuit includes a second capacitor via a second switch element configured to invert an on / off state between the first switch element and a reference potential and a power source. Connected,
The second reset circuit includes a second discharge resistor and the second switch element connected in parallel to the second time constant circuit, and when the second switch element is in an ON state, 2 is output as a sweep waveform of the second ramp wave, and when the second switch element is in an OFF state, the second capacitor is discharged via the second discharge resistor. Thus, the state of the second time constant circuit is reset, and the second ramp wave is held at a power supply voltage or higher level.
A PWM control circuit characterized by the above . The first time constant circuit includes a first constant current circuit that supplies a constant charging current to the first capacitor, and the second time constant circuit includes a constant charging current to the second capacitor. It was provided with a second constant current circuit for supplying, PWM control circuit according to claim 1 or 2. In a switching power supply device comprising at least two switching elements and a switching control circuit for controlling these switching elements,
To the switching control circuit includes a PWM control circuit according to any one of claims 1 to 3
A switching power supply apparatus, wherein the modulation signal is an output feedback signal of a switching power supply circuit, and the first modulated signal and the second modulated signal are control signals for the two switching elements.

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