JP6114630B2 - Method for manufacturing crystalline silicon solar cell - Google Patents

Description

The present invention relates to a method for manufacturing a crystalline silicon solar cells.

  In recent years, expectations for solar cells that directly convert solar energy into electrical energy have increased rapidly, particularly from the viewpoint of global environmental problems. In a solar cell, electric power is generated by taking out carriers (electrons and holes) generated by light irradiation to a photoelectric conversion unit made of a semiconductor junction or the like to an external circuit. In order to efficiently extract carriers generated in the photoelectric conversion unit to an external circuit, a collector electrode is provided on the photoelectric conversion unit of the solar cell.

  There are various types of solar cells, such as those using compound semiconductors or organic materials, but the mainstream is currently using silicon crystals. In particular, a crystalline silicon solar cell having a conductive amorphous silicon layer having a band gap different from that of single crystal silicon on the surface of a single crystal silicon substrate is called a heterojunction solar cell. The heterojunction solar cell has a transparent electrode layer on the conductive amorphous silicon-based layer, and a collector electrode is provided on the transparent electrode layer.

  The collector electrode of a solar cell is generally formed by pattern printing of a silver paste by a screen printing method. Although this method is simple in itself, there are problems that the material cost of silver is large and the silver paste material containing a resin is used, so that the resistivity of the collector electrode is increased. In order to reduce the resistivity of the collector electrode formed using the silver paste, it is necessary to print the silver paste thickly. However, when the printed thickness is increased, the line width of the electrode also increases, so that it is difficult to make the electrode thin, and the light shielding loss due to the collecting electrode increases.

  As a technique for solving these problems, a method of forming a collecting electrode by a plating method that is excellent in terms of material cost and process cost is known. For example, Patent Documents 1 and 2 disclose a solar cell method in which a metal layer made of copper or the like is formed by plating on a transparent electrode constituting a photoelectric conversion unit. In this method, first, a resist material layer (insulating layer) having an opening corresponding to the shape of the collector electrode is formed on the transparent electrode layer of the photoelectric conversion portion, and electroplating is performed on the resist opening of the transparent electrode layer. As a result, a metal layer is formed. Thereafter, the resist is removed to form a collector electrode having a predetermined shape.

  In Patent Document 3, an insulating layer such as SiO2 is provided on the transparent electrode, and then a groove penetrating the insulating layer is provided to expose the surface or side surface of the transparent electrode layer so as to be electrically connected to the exposed portion of the transparent electrode. Discloses a method of forming a metal collector electrode. Specifically, a method has been proposed in which a metal seed is formed on the exposed portion of the transparent electrode layer by a photoplating method or the like, and a metal electrode is formed by electroplating using the metal seed as a starting point. Such a method is more advantageous in terms of material cost and process cost because it is not necessary to use a resist as in Patent Documents 4 and 5. Moreover, by providing a low-resistance metal seed, the contact resistance between the transparent electrode layer and the collector electrode can be reduced.

Also, in Patent Document 4, by increasing the unevenness of the conductive seed, the entire surface of the photoelectric conversion portion other than the conductive seed is covered and a discontinuous opening is formed on the conductive seed when forming the insulating layer. In addition, it is described that a plating layer is formed through the opening.
By the way, as one of the contrivances in the structure of a solar cell using a single crystal silicon substrate, a texture structure having a pyramidal uneven shape on the surface serving as a light receiving surface of the single crystal silicon substrate, which is several μm to several tens μm. There is a technique for forming an uneven shape having a height difference. In this way, by forming an uneven shape on the light receiving surface of the solar cell, it is possible to reduce the reflection of light incident on the light receiving surface and at the same time increase the amount of light entering the solar cell, and to improve the photoelectric conversion efficiency of the solar cell. Can be increased.

  Examples of means for forming an uneven shape on the light-receiving surface of the single crystal silicon substrate include a wet etching method using metal fine particles as a catalyst, a reactive ion etching method, and the like. It is not preferable in terms of mass productivity and manufacturing cost. For this reason, as a general method for forming the concavo-convex shape, an etching rate is low by anisotropically etching a single crystal silicon substrate having a (100) plane on the initial surface using an alkaline solution. A method of preferentially displaying the (111) plane on the surface and forming pyramidal irregularities is preferably used.

  Specifically, it is a method of etching with an etching solution in which a low boiling alcohol solvent is added to an alkaline aqueous solution such as potassium hydroxide heated to 70 ° C. or higher and 90 ° C. or lower. Patent Document 5 describes that by performing anisotropic etching using an alkaline aqueous solution containing a surfactant, a uniform uneven shape can be obtained with good reproducibility even when a damaged silicon substrate is used. .

  Further, Patent Document 6 discloses a method of rounding a valley portion in the concavo-convex portion by performing isotropic etching after anisotropic etching. Patent Document 6 describes that a substrate having a large number of uneven portions formed on the surface thereof is etched by isotropic etching so that the valley portion (concave portion) of the substrate is rounded.

  Further, Patent Document 7 describes that after forming a concavo-convex shape on a single crystal silicon substrate, the concavo-convex shape is flattened by performing treatment with an oxidizing solution such as hydrofluoric acid and nitric acid, sulfuric acid, ozone, hydrogen peroxide and the like. Has been.

JP 60-66426 A JP 2000-58885 A JP 2011-199045 A Special table 2013-507781 gazette Japanese Patent Laid-Open No. 11-233484 WO98 / 43304 International Publication Pamphlet Special table 2011-515872 gazette

  According to the method disclosed in Patent Document 3, it is possible to form a collector electrode having a fine line pattern by plating without using an expensive resist material. However, in Patent Document 3, the side surface of the transparent electrode layer and the metal collecting electrode are in contact with each other in the groove penetrating the insulating layer and the transparent electrode layer, but the thickness of the transparent electrode layer is generally about 100 nm. The contact area between the two is small. Therefore, there is a problem that the resistance between the transparent electrode and the collector electrode is increased, and the function as the collector electrode cannot be sufficiently exhibited.

Further, according to the study by the present inventors, when forming the collecting electrode by plating, even when the surface of the photoelectric conversion part is protected by an insulating layer, the plating metal is deposited by a pinhole or the like on the surface of the insulating layer. The problem that occurred. In particular, it was revealed that the plating metal is more likely to precipitate when a surface having a concavo-convex structure is used on the surface of the photoelectric conversion portion.
However, Patent Document 4 does not describe that a texture is formed on the surface of the substrate, and does not discuss the above problems.

  Moreover, in patent document 5, although the convex part and recessed part of a concavo-convex structure remain both sharp, and patent document 6 describes that the concave part is rounded, the convex part remains sharp. Therefore, when plating is performed using a single crystal silicon substrate as in Patent Documents 5 and 6, such a problem is considered to become more prominent. Further, in Patent Document 7, it is described that the defect of the layer formed thereon can be prevented by flattening the concavo-convex structure, but no consideration is given to the influence when the collector electrode is formed by a plating method or the like. It has not been.

  An object of the present invention is to solve the problems of the prior art relating to the formation of a collector electrode of a solar cell as described above, to improve the conversion efficiency of the solar cell, and to reduce the manufacturing cost of the solar cell.

  As a result of intensive studies in view of the above problems, the present inventors have been able to improve the conversion efficiency of a crystalline silicon solar cell by using a single crystal silicon substrate having a predetermined uneven structure and a predetermined collector electrode. The inventors have found that the collector electrode can be formed at low cost, and have reached the present invention.

  That is, the present invention relates to the following.

Method for producing a crystalline silicon solar cell of the present invention, the photoelectric conversion unit preparation step for preparing a photoelectric conversion unit; and the first, first conductive layer forming step is first conductive layer is formed on the photoelectric conversion unit on A plating process in which a second conductive layer is formed on the one conductive layer by a plating method in this order, and before the plating process, an insulating layer is formed in the first conductive layer non-formation region on the photoelectric conversion portion. to have a that insulating layer forming step. The photoelectric conversion unit has a silicon-based thin film and a transparent electrode layer in this order on one main surface of a single conductivity type single crystal silicon substrate. Etching performed in the photoelectric conversion unit preparation step, the texture forming process of the concave convex structure A is formed by anisotropic etching on one main surface of the one conductivity type single crystal silicon substrate, the etching process of the concavo-convex structure A Processing steps are performed in this order . In the concavo-convex structure A, the curvature radius r1 of the convex part and the curvature radius r2 of the concave part are both less than 0.005 μm, and the curvature radius r1 of the convex part and the curvature radius r2 of the concave part are r2 < It meets r1, and is Ru is formed concavo-convex structure B satisfying 0.01μm ≦ r1 ≦ 0.5μm.

After pre-Symbol first conductive layer forming step, the even first conductive layer is performed the insulating layer forming step so that insulating layer is formed in the plating step, it is formed on the first conductive layer In addition, it is preferable that a second conductive layer electrically connected to the first conductive layer is formed through the opening provided in the insulating layer.

The first conductive layer is a low melting point material containing Mukoto is preferable that at a temperature lower than the heat resistance temperature of the heat flow temperature T1 is the photoelectric conversion unit. The opening is formed by performing a heat treatment at an annealing temperature Ta higher than the heat flow start temperature T1 of the low melting point material after the insulating layer forming step , or in the insulating layer forming step, the low temperature It is preferable that the opening is formed simultaneously with the formation of the insulating layer by forming the insulating layer at the substrate temperature Tb higher than the thermal flow start temperature T1 of the melting point material .

In the etching process, by performing an etching treatment with a mixed solution of hydrofluoric acid and ozone, the uneven structure B that is formed preferably.

  According to the present invention, by controlling the texture shape of the single crystal silicon substrate, generation of defects in the silicon-based thin film formed on the substrate can be suppressed, and the conversion efficiency of the solar cell can be improved. Further, since the collecting electrode can be formed by plating, the collecting electrode can be reduced in resistance, and the conversion efficiency of the solar cell can be improved. In addition, in the conventional method of forming a collector electrode by a plating method, a patterning process of the insulating layer is required. According to the present invention, the pattern electrode is formed by a plating method without using a mask or resist for pattern formation. Is possible. Therefore, a highly efficient solar cell can be provided at low cost.

It is typical sectional drawing which shows the heterojunction solar cell concerning one Embodiment. It is typical sectional drawing which shows the heterojunction solar cell at the time of using the board | substrate which has the conventional uneven structure. It is typical sectional drawing which shows the heterojunction solar cell concerning one Embodiment at the time of using the board | substrate which has the uneven structure of this invention. 6 is an SEM cross-sectional view of a heterojunction solar cell according to Comparative Example 2. FIG. It is SEM sectional drawing of the textured single crystal silicon substrate produced using nitric acid as the oxidizing solution in the etching treatment liquid. It is a SEM sectional view of a textured single crystal silicon substrate concerning one embodiment. It is a conceptual diagram of the manufacturing process of the solar cell by one Embodiment of this invention. It is a conceptual diagram which shows an example of the shape change at the time of the heating of a low melting-point material. It is a conceptual diagram for demonstrating the shape change at the time of the heating of low melting-point material powder, and necking. It is a SEM photograph of metal fine particles in which sintering necking has occurred. It is a structure schematic diagram of a plating apparatus. It is a figure which shows the optical characteristic of the insulating layer in an Example.

  The crystalline silicon solar cell of the present invention includes a photoelectric conversion unit having a silicon-based thin film and a transparent electrode layer in this order on one main surface of one conductivity type crystalline silicon substrate, and a collection on the one main surface of the photoelectric conversion unit. Electrode. The one-conductivity-type crystalline silicon substrate has a concavo-convex structure on the surface on one main surface side, and satisfies r2 <r1 when the radii of curvature of the concavo-convex structure are r1 and r2. The collector electrode includes a first conductive layer and a second conductive layer in order from the photoelectric conversion unit side. The first conductive layer includes an insulating layer having an opening formed between the first conductive layer and the second conductive layer, and the first conductive layer is covered with the insulating layer. It is preferable that the portion is electrically connected to the first conductive layer through the opening of the insulating layer.

  Hereinafter, the present invention will be described in more detail by taking, as an example, a heterojunction crystalline silicon solar cell (hereinafter sometimes referred to as a “heterojunction solar cell”) that is an embodiment of the present invention. A heterojunction solar cell is a crystalline silicon solar cell in which a diffusion potential is formed by having a silicon thin film having a band gap different from that of single crystal silicon on the surface of a single crystal silicon substrate of one conductivity type. The silicon-based thin film is preferably amorphous. In particular, a thin intrinsic amorphous silicon layer interposed between a conductive amorphous silicon thin film for forming a diffusion potential and a crystalline silicon substrate is a crystalline silicon solar cell with the highest conversion efficiency. It is known as one of the forms.

  FIG. 1 is a schematic cross-sectional view of a crystalline silicon solar cell according to an embodiment of the present invention. The crystalline silicon solar cell in the present invention is not limited to the following.

  The conductive silicon thin film 3a and the light incident side transparent electrode layer 6a are provided in this order on one surface (light incident side surface) of the one conductivity type single crystal silicon substrate 1. It is preferable that the other surface (opposite surface on the light incident side) of the one conductivity type single crystal silicon substrate 1 has the conductivity type silicon thin film 3b and the back surface side transparent electrode layer 6b in this order. A collecting electrode 70 including a first conductive layer 71 and a second conductive layer 72 is formed on the light incident side transparent electrode layer 6 a on the surface of the photoelectric conversion unit 50. The photoelectric conversion unit 50 has a silicon-based thin film and a transparent electrode layer in this order on one main surface of the one-conductivity-type crystalline silicon substrate. One conductivity type crystalline silicon substrate has a concavo-convex structure on the surface on one main surface side. The concavo-convex structure satisfies r2 <r1 when the radii of curvature of the convex portions and the concave portions are r1 and r2, respectively. An insulating layer 9 having an opening is formed between the first conductive layer 71 and the second conductive layer 72.

  It is preferable to have intrinsic silicon-based thin films 2a and 2b between the one-conductivity-type single crystal silicon substrate 1 and the conductive silicon-based thin films 3a and 3b. It is preferable to have the back metal electrode 8 on the back side transparent electrode layer 6b.

  First, the one conductivity type single crystal silicon substrate 1 in the crystalline silicon solar cell of the present invention will be described. In general, a single crystal silicon substrate contains an impurity that supplies electric charge to silicon in order to provide conductivity. Single crystal silicon substrates include an n-type in which atoms (for example, phosphorus) for introducing electrons into silicon atoms and a p-type in which atoms (for example, boron) for introducing holes into silicon atoms are contained. That is, “one conductivity type” in the present invention means either n-type or p-type.

  In heterojunction solar cells, electron / hole pairs are efficiently separated and recovered by providing a strong electric field with the heterojunction on the incident side where the most incident light is absorbed as the reverse junction. Can do. Therefore, the heterojunction on the light incident side is preferably a reverse junction. On the other hand, when holes and electrons are compared, electrons having smaller effective mass and scattering cross section generally have higher mobility. From the above viewpoint, the single crystal silicon substrate 1 used for the heterojunction solar cell is preferably an n-type single crystal silicon substrate. The single crystal silicon substrate 1 has an uneven (texture) structure on the surface from the viewpoint of light confinement.

Here, in general, the single crystal silicon substrate has a concavo-convex structure formed by anisotropic etching or the like, as will be described later. However, as shown in FIG. When r1 and r2, the sharp concavo-convex structure satisfying r1 <0.005 μm and r2 <0.005 μm is obtained (referred to as concavo-convex structure A). In the present invention, the “sharp concavo-convex structure” means that the curvature radius (r1 and r2) of the convex part and the concave part of the concavo-convex structure is less than 0.005 μm.

  However, according to the study by the present inventors, when such a substrate with unevenness is used, even when the surface of the photoelectric conversion part is protected by an insulating layer when forming the collector electrode by plating, the insulating layer There was a problem that the plated metal could be deposited by surface pinholes. That is, as shown in FIG. 2, since it was sharp especially in the convex part in the concavo-convex structure on the surface of the photoelectric conversion part, it became clear that precipitation of the plating metal due to the thinning of the insulating layer occurred more easily.

  On the other hand, as shown in FIG. 3, the “concavo-convex structure” according to the present invention has a plurality of concavo-convex parts satisfying r2 <r1 when the curvature radii of the convex part and the concave part are r1 and r2, respectively. B). By setting r2 <r1, it can be expected that defects in the silicon-based thin film formed on the concavo-convex structure are suppressed and that the insulating layer is prevented from being thinned.

  In the present invention, it is preferable that the radius of curvature of the convex portion of the concavo-convex structure B satisfies 0.01 μm ≦ r1 ≦ 10 μm. By setting the curvature radius r1 of the convex portion to 0.01 μm or more, defects in the silicon-based thin film generated from the convex portion when the amorphous or microcrystalline silicon thin film is formed on the substrate are suppressed. It is thought that it can be done. In addition, it is possible to prevent the insulating layer from being thinned at the convex portions, and to prevent the formation of pinholes (undesired openings). Therefore, shadow loss is reduced by preventing deposition of an undesired metal layer during plating, and as a result, solar cell characteristics can be further improved.

  Moreover, it is thought that the loss of light absorption due to the increase in surface reflectance can be further suppressed by setting the curvature radius r1 of the convex portion to 10 μm or less. Especially, it is more preferable to satisfy | fill 0.05 micrometer <= r1 <= 5micrometer, and it is still more preferable to satisfy | fill 0.07 micrometer <= r1 <= 0.4micrometer.

  In addition, the radius of curvature of the concave portion of the concavo-convex structure B in the present invention preferably satisfies r2 ≦ 5 μm, and more preferably satisfies r2 ≦ 1 μm, from the viewpoint of further suppressing light absorption loss due to an increase in surface reflectance. . Here, “the curvature radii r1 and r2 of the convex portions and the concave portions” means the average curvature radii when the curvature radii of the plurality of concave and convex portions are measured in a certain measurement range. The radius of curvature can be calculated, for example, by measuring a cross section perpendicular to the surface of the substrate in a range of 10 mm with a scanning electron microscope (SEM), and calculating an average value of the randomly extracted curvature radii at five points. it can.

  As described above, the concavo-convex structure in which r1 and r2 are both less than 0.005 μm is referred to as the concavo-convex structure A, and the concavo-convex structure of the present invention satisfying r2 <r1 is referred to as the concavo-convex structure B. The single crystal silicon substrate on which the concavo-convex structure A and the concavo-convex structure B are formed is also referred to as a substrate with the concavo-convex structure A (substrate 1A) and a substrate with the concavo-convex structure A (substrate 1A) 1B, respectively. The substrate 1A with the concavo-convex structure A can be formed by a texture forming process such as anisotropic etching.

  The concavo-convex structure B in the present invention is preferably formed by performing a separate etching treatment step after the concavo-convex structure A is formed by anisotropic etching (after the texture forming step). As anisotropic etching, for example, by immersing the substrate in an etching solution such as an alkaline solution, a uniform and fine uneven structure A can be formed on the surface of the substrate.

  Examples of the alkaline solution include an aqueous solution in which an alkali is dissolved. The alkali is preferably an alkali metal or alkaline earth metal hydroxide such as sodium hydroxide, potassium hydroxide or calcium hydroxide, particularly preferably sodium hydroxide or potassium hydroxide. These alkalis may be used alone or in combination of two or more. The alkali concentration in the etching solution is preferably 1 to 20% by weight, more preferably 2 to 15% by weight, and still more preferably 3 to 10% by weight.

  In anisotropic etching, an etching solution in which IPA or the like is added to an alkaline solution such as potassium hydroxide or sodium hydroxide is generally used. In the anisotropic etching, since the (111) plane of silicon is harder to be etched than the (100) plane, a sharp quadrangular pyramidal structure is formed.

  The concavo-convex structure B of the present invention is preferably formed by an etching process after the concavo-convex structure A by the anisotropic etching. As described above, the concave and convex portions of the concavo-convex structure after the texture forming step such as anisotropic etching usually have a sharp concavo-convex structure in which r1 and r2 both satisfy less than 0.005 μm. By performing an etching process later in the etching process, r2 <r1 can be easily achieved.

  The “etching process step” in the present invention is not particularly limited as long as a process satisfying r2 <r1 can be performed. Examples of the etching process include dry etching and mechanical polishing. Among these, from the viewpoint of damage to the single crystal silicon substrate, it is more preferable to perform etching by a wet etching method. As the wet etching method, for example, it is preferable to control the radius of curvature of the convex portion of the substrate by immersing the concave and convex substrate in a mixed solution of hydrofluoric acid and an oxidizing solution.

  The concentration of hydrofluoric acid in the etching treatment solution (mixed solution) is preferably 0.1 to 10% by weight, and more preferably 1 to 5% by weight. Since the etching rate can be improved by setting the concentration of hydrofluoric acid in the treatment liquid to 0.1% by weight or more, it is preferable from the viewpoint of productivity. Further, by setting the hydrofluoric acid concentration in the treatment liquid to 10% by weight or less, it is possible to suppress a decrease in substrate reflectivity due to extreme flattening of the texture structure.

  At this time, the oxidizing solution is not particularly limited as long as the concavo-convex structure B is formed, but it is preferable to use ozone. The concentration of ozone in the etching treatment liquid is preferably 5 ppm (parts per million) to 40 ppm, and more preferably 10 ppm to 20 ppm. By using the treatment liquid in the above range, the concavo-convex structure of the embodiment can be formed with good reproducibility, which is preferable from the viewpoint of productivity. Among these, it is more preferable to use a mixed solution of hydrofluoric acid and ozone, to set the concentration of hydrofluoric acid to 1 to 5% by weight and the concentration of ozone to 10 ppm to 20 ppm.

  Here, when nitric acid is used as the oxidizing solution, for example, as in Patent Document 6, nitrous acid, which is a reaction intermediate, stays in the recessed portion, so that the recessed portion tends to be rounded as shown in FIG. It is guessed. In this case, it is considered that the film thickness non-uniformity when forming a silicon-based thin film such as an intrinsic silicon semiconductor layer formed thereon can be suppressed. However, when plating is performed using the substrate, the pin is projected from the convex portion. Holes are likely to occur. In this case, impurities may be dissolved and impurities such as nitrogen oxides may be formed, and an additional cleaning step such as SPM (Surfur Acid Peroxide Mixture) cleaning or SC2 (Standard Clean-2) cleaning is required. Therefore, such a method has a problem that the number of steps is large and the manufacturing cost increases.

  On the other hand, for example, by using an etching solution having ozone or the like as the oxidizing solution, the concavo-convex structure B with rounded convex portions (satisfying r2 <r1) can be formed. In this case, when plating is performed It is possible to further suppress pinholes and the like to the protrusions that may occur in In particular, when ozone is used as the oxidizing solution, the product that can be generated by the etching process is generally only silicon oxide, so that an additional cleaning step is unnecessary. Therefore, it is preferable from the viewpoint of productivity because the cleaning of the substrate and the etching process of the concavo-convex portion can be performed simultaneously. Further, there is no stagnation of the chemical solution in the concave portion, and it is considered that the convex portion is selectively easily rounded as shown in FIG. For the above reasons, it is preferable to use ozone as the oxidizing solution.

A silicon-based thin film is formed on the surface of the one conductivity type single crystal silicon substrate 1 on which the concavo-convex structure B is formed. As a method for forming a silicon-based thin film, a plasma CVD method is preferable. As conditions for forming a silicon-based thin film by plasma CVD, a substrate temperature of 100 to 300 ° C., a pressure of 20 to 2600 Pa, and a high frequency power density of 0.004 to 0.8 W / cm ² are preferably used. As a source gas used for forming a silicon-based thin film, a silicon-containing gas such as SiH ₄ or Si ₂ H ₆ or a mixed gas of a silicon-based gas and H ₂ is preferably used.

The conductive silicon thin film 3 is a one-conductivity type or reverse conductivity type silicon thin film. For example, when n-type is used as the one-conductivity-type single crystal silicon substrate 1, the one-conductivity-type silicon-based thin film and the reverse-conductivity-type silicon-based thin film are n-type and p-type, respectively. B ₂ H ₆ or PH ₃ is preferably used as the dopant gas for forming the p-type or n-type silicon-based thin film. Moreover, since the addition amount of impurities such as P and B may be small, it is preferable to use a mixed gas diluted with SiH ₄ or H ₂ in advance. When forming a conductive silicon thin film, a gas containing a different element such as CH ₄ , CO ₂ , NH ₃ , GeH ₄ is added to alloy the silicon thin film, thereby reducing the energy gap of the silicon thin film. It can also be changed.

  Examples of silicon-based thin films include amorphous silicon thin films, microcrystalline silicon (thin films containing amorphous silicon and crystalline silicon), and the like. Among these, it is preferable to use an amorphous silicon thin film. For example, as a preferable configuration of the photoelectric conversion unit 50 when an n-type single crystal silicon substrate is used as the one-conductivity-type single crystal silicon substrate 1, the transparent electrode layer 6a / p-type amorphous silicon thin film 3a / i type is used. Examples include a laminated structure in the order of amorphous silicon thin film 2a / n type single crystal silicon substrate 1 / i type amorphous silicon thin film 2b / n type amorphous silicon thin film 3b / transparent electrode layer 6b. In this case, for the reason described above, it is preferable that the p-layer side be the light incident surface.

  The intrinsic silicon thin films 2a and 2b are preferably i-type hydrogenated amorphous silicon composed of silicon and hydrogen. When i-type hydrogenated amorphous silicon is deposited on a single crystal silicon substrate by CVD, surface passivation can be effectively performed while suppressing impurity diffusion into the single crystal silicon substrate. Further, by changing the amount of hydrogen in the film, it is possible to give an effective profile to the carrier recovery in the energy gap.

  The p-type silicon thin film is preferably a p-type hydrogenated amorphous silicon layer, a p-type amorphous silicon carbide layer, or a p-type amorphous silicon oxide layer. A p-type hydrogenated amorphous silicon layer is preferable from the viewpoint of suppressing impurity diffusion and reducing the series resistance. On the other hand, the p-type amorphous silicon carbide layer and the p-type amorphous silicon oxide layer are wide gap low-refractive index layers, which are preferable in terms of reducing optical loss.

  As described above, in the present invention, when an amorphous or microcrystalline silicon-based thin film is formed on the substrate, a silicon-based thin film, particularly an i-type amorphous silicon-based thin film, generated from the convex portion is used. When used, it is considered that defects can be further suppressed.

  The photoelectric conversion unit 50 of the heterojunction solar cell 101 preferably includes the transparent electrode layers 6a and 6b on the conductive silicon thin films 3a and 3b. The transparent electrode layer is formed by a transparent electrode layer forming step. The transparent electrode layers 6a and 6b are mainly composed of a conductive oxide. As the conductive oxide, for example, zinc oxide, indium oxide, or tin oxide can be used alone or in combination. From the viewpoints of conductivity, optical characteristics, and long-term reliability, an indium oxide containing indium oxide is preferable, and an indium tin oxide (ITO) as a main component is more preferably used. Here, “main component” means that the content is more than 50% by weight, preferably 70% by weight or more, and more preferably 90% by weight or more. The transparent electrode layer may be a single layer or a laminated structure composed of a plurality of layers.

  A doping agent can be added to the transparent electrode layer. For example, when zinc oxide is used as the transparent electrode layer, examples of the doping agent include aluminum, gallium, boron, silicon, and carbon. When indium oxide is used as the transparent electrode layer, examples of the doping agent include zinc, tin, titanium, tungsten, molybdenum, and silicon. When tin oxide is used as the transparent electrode layer, examples of the doping agent include fluorine.

  The doping agent can be added to one or both of the light incident side transparent electrode layer 6a and the back surface side transparent electrode layer 6b. In particular, it is preferable to add a doping agent to the light incident side transparent electrode layer 6a. By adding a doping agent to the light incident side transparent electrode layer 6a, the resistance of the transparent electrode layer itself can be reduced, and resistance loss between the transparent electrode layer 6a and the collector electrode 70 can be suppressed.

  The film thickness of the light incident side transparent electrode layer 6a is preferably 10 nm or more and 140 nm or less from the viewpoints of transparency, conductivity, and light reflection reduction. The role of the transparent electrode layer 6a is to transport carriers to the collector electrode 70, as long as it has conductivity necessary for that purpose, and the film thickness is preferably 10 nm or more. By setting the film thickness to 140 nm or less, absorption loss in the transparent electrode layer 6a is small, and a decrease in photoelectric conversion efficiency accompanying a decrease in transmittance can be suppressed. Moreover, if the film thickness of the transparent electrode layer 6a is within the above range, an increase in carrier concentration in the transparent electrode layer can also be prevented, so that a decrease in photoelectric conversion efficiency due to a decrease in transmittance in the infrared region is also suppressed.

  The method for forming the transparent electrode layer is not particularly limited, but a physical vapor deposition method such as a sputtering method, a chemical vapor deposition (MOCVD) method using a reaction between an organometallic compound and oxygen or water is preferable. In any film forming method, energy by heat or plasma discharge can be used.

  The substrate temperature at the time of producing the transparent electrode layer is appropriately set. For example, when an amorphous silicon thin film is used as the silicon thin film, the temperature is preferably 200 ° C. or lower. By setting the substrate temperature to 200 ° C. or lower, desorption of hydrogen from the amorphous silicon layer and accompanying dangling bonds to silicon atoms can be suppressed, and as a result, conversion efficiency can be improved.

  It is preferable that the back surface metal electrode 8 is formed on the back surface side transparent electrode layer 6b. As the back surface metal electrode 8, it is desirable to use a material having high reflectivity from the near infrared to the infrared region and high conductivity and chemical stability. Examples of the material satisfying such characteristics include silver and aluminum. The method for forming the back surface metal electrode layer is not particularly limited, but a physical vapor deposition method such as a sputtering method or a vacuum evaporation method, a printing method such as screen printing, or the like is applicable.

A collecting electrode 70 is formed on the transparent electrode layer 6a. The collector electrode 70 includes a first conductive layer 71 and a second conductive layer 72. The first conductive layer 71 includes a conductive material. The conductive material than the heat resistant temperature of the photoelectric conversion unit has a thermal flow temperature T ₁ of the low temperature, it is preferable to contain a low melting point material.

  In the present embodiment, the insulating layer 9 having an opening is formed between the first conductive layer 71 and the second conductive layer 72. When the collector electrode 70 of the present invention has an insulating layer having an opening on the first conductive layer as in this embodiment, a part of the second conductive layer 72 is electrically connected to the first conductive layer 71. Yes. Here, “partially conducting” means a state in which the insulating layer is typically formed with an opening and the opening is filled with the material of the second conductive layer. In addition, when the film thickness of a part of the insulating layer 9 becomes as thin as about several nm (that is, a region having a thin film thickness is locally formed), the second conductive layer 72 becomes the first conductive layer. Also included are those conducting to the layer 71. For example, when the low-melting-point material of the first conductive layer 71 is a metal material such as aluminum, the first conductive layer 71 and the second conductive layer are interposed via an oxide film (corresponding to an insulating layer) formed on the surface thereof. A state in which the gap is conducted is exemplified.

  A method for forming an opening for electrically connecting the first conductive layer and the second conductive layer in the insulating layer 9 is not particularly limited, and methods such as laser irradiation, mechanical drilling, and chemical etching can be employed. In one embodiment, a method of forming an opening in an insulating layer formed thereon by using a low-melting-point material as the conductive material in the first conductive layer and causing the low-melting-point material to heat flow. .

  As a method of forming the opening by thermal flow of the low melting point material in the first conductive layer, after forming the insulating layer 9 on the first conductive layer 71 containing the low melting point material, the heat flow start temperature of the low melting point material A method in which the surface shape of the first conductive layer is changed by heating (annealing) to T1 or more, and an opening (crack) is formed in the insulating layer 9 formed thereon; There is a method in which when the insulating layer 9 is formed on the first conductive layer 71 to be contained, the opening is formed at the same time as the formation of the insulating layer by causing the low melting point material to heat flow by heating to T1 or higher.

  Hereinafter, a method for forming an opening in the insulating layer using the heat flow of the low melting point material in the first conductive layer will be described with reference to the drawings. Note that the present invention is not limited to the following embodiment.

  FIG. 7 is a process conceptual diagram showing an embodiment of a method for forming the collector electrode 70 on the photoelectric conversion unit 50 of the solar cell. In this embodiment, first, a single conductivity type single crystal silicon substrate 1 is prepared (FIG. 7A), and a texture forming process is performed on the substrate 1 (texture forming step, FIG. 7B). Typically, anisotropic etching is preferable as the texture forming process. In this case, the concavo-convex structure A having a sharp curvature radius between the convex portion and the concave portion is formed.

Thereafter, a concavo-convex structure B having a radius of curvature satisfying r2 <r1 is formed (etching process, FIG. 7C). At this time, it is preferable to satisfy 0.01 μm ≦ r1 ≦ 10 μm.
In the case of a heterojunction solar cell as in the present invention, as described above, a photoelectric conversion unit including a silicon-based thin film and a transparent electrode layer is prepared on a one-conductivity-type silicon substrate subjected to the above-described treatment. (Photoelectric conversion part preparation process, FIG. 7D).

  A first conductive layer 71 including a low melting point material 711 is formed on one main surface of the photoelectric conversion portion (first conductive layer forming step, FIG. 7E). The insulating layer 9 is formed on the first conductive layer 71 (insulating layer forming step, FIG. 7F). The insulating layer 9 may be formed only on the first conductive layer 71, and is also formed on a region where the first conductive layer 71 of the photoelectric conversion unit 50 is not formed (first conductive layer non-formation region). It may be. In particular, when the transparent electrode layer is formed on the surface of the photoelectric conversion unit 50 as in the heterojunction solar cell in the present invention, the insulating layer 9 may be formed also on the first conductive layer non-formation region. preferable.

  After the insulating layer is formed, an annealing process by heating is performed (annealing process, FIG. 7G). Due to the annealing treatment, the first conductive layer 71 is heated to the annealing temperature Ta, and the low melting point material is heat-fluidized to change the surface shape, and accordingly, the insulating layer 9 formed on the first conductive layer 71 is deformed. Occurs. The deformation of the insulating layer 9 is typically the formation of an opening 9h in the insulating layer. The opening 9h is formed in a crack shape, for example.

  After forming an opening in the insulating layer by annealing, the second conductive layer 72 is formed by plating (plating step, FIG. 7H). Although the first conductive layer 71 is covered with the insulating layer 9, the first conductive layer 71 is exposed at a portion where the opening 9 h is formed in the insulating layer 9. Therefore, the first conductive layer is exposed to the plating solution, and metal can be deposited starting from the opening 9h. According to such a method, the second conductive layer corresponding to the shape of the collector electrode can be formed by plating without providing a resist material layer having an opening corresponding to the shape of the collector electrode.

  Further, in the present invention, as described above, by using the single crystal silicon substrate 1B having the concavo-convex structure B with rounded protrusions, it is possible to suppress defects that may occur when the silicon-based thin film formed thereon is formed. it can.

  Here, when performing normal plating, when the transparent electrode layer is provided as the outermost surface layer of the photoelectric conversion part, such as the heterojunction solar cell of the present invention, it serves as a base for plating to protect the transparent electrode layer from the plating solution. It is necessary to protect the first conductive layer non-formation region other than the region where the layer (first conductive layer) is formed with an insulating layer or the like.

  However, for example, as shown in FIG. 2, when the surface of the substrate has a sharp concavo-convex structure, the film thickness of the insulating layer in the convex part of the concavo-convex structure is smaller than the film thickness of the concave part. In this case, there is a problem that defects tend to occur on the thin convex portions, and an undesired plating layer (second conductive layer) is deposited also on the first conductive layer non-formation region.

  On the other hand, in the present invention, by forming the curvature radius of the concavo-convex structure of the substrate so as to satisfy r2 <r1, an undesired (pinhole) that may be generated from the convex portion when the second conductive layer is formed by plating. Etc.) can be suppressed. Among these, 0.01 μm ≦ r1 is preferable. In this case, in addition to the effect of suppressing defects that may occur in the silicon-based thin film, it is possible to suppress the formation of a thin film at the convex portion and to further suppress the deposition of an undesirable plating layer. Moreover, r1 ≦ 10 μm is preferable. The reflection of light incident on the light receiving surface can be reduced and the amount of light incident on the crystalline silicon solar cell can be increased, and the photoelectric conversion efficiency of the crystalline silicon solar cell can be increased.

(First conductive layer)
The first conductive layer 71 is a layer that functions as a conductive underlayer when the second conductive layer is formed by a plating method. Therefore, the first conductive layer only needs to have conductivity that can function as a base layer for electrolytic plating. In the present specification, it is defined as being conductive if the volume resistivity is 10 ⁻² Ω · cm or less. Further, if the volume resistivity is 10 ² Ω · cm or more, it is defined as insulating.

  The film thickness of the first conductive layer 71 is preferably 20 μm or less from the viewpoint of cost, and more preferably 10 μm or less. On the other hand, from the viewpoint of setting the line resistance of the first conductive layer 71 in a desired range, the film thickness is preferably 0.5 μm or more, and more preferably 1 μm or more.

  In particular, by using the substrate 1B with the convex-concave uneven structure B as in the present invention, the film thickness non-uniformity in the concave portion and the convex portion, which may occur when the first conductive layer having a thin film thickness is used, is obtained. Therefore, the thickness of the first conductive layer can be made more uniform. Therefore, it is considered that a highly efficient solar cell can be provided at low cost even when the first conductive layer is thin.

The first conductive layer 71 includes a conductive material. Conductive material preferably comprises a low melting point material of the heat flow temperature T _1. The heat flow start temperature is a temperature at which the material causes heat flow by heating and the surface shape of the layer containing the low melting point material changes, and is typically the melting point. In the case of a polymer material or glass, the material may soften at a temperature lower than the melting point to cause heat flow. In such a material, it can be defined that heat flow start temperature = softening point. The softening point is a temperature at which the viscosity becomes 4.5 × 10 ⁶ Pa · s (the same as the definition of the softening point of glass).

The low melting point material is preferably a material that causes heat flow in the annealing process and changes the surface shape of the first conductive layer 71. Therefore, the thermal flow temperature T ₁ of the low-melting material is preferred over the annealing temperature Ta is low. In the present invention, the annealing process is preferably performed at an annealing temperature Ta lower than the heat resistant temperature of the photoelectric conversion unit 50. Therefore, the heat flow temperature T ₁ of the low melting point material, it is preferred to heat the temperature of the photoelectric conversion unit is cold.

The heat-resistant temperature of the photoelectric conversion unit is irreversibly reduced in the characteristics of a solar cell including the photoelectric conversion unit (also referred to as “solar battery cell” or “cell”) or a solar battery module manufactured using the solar battery cell. Temperature. For example, in the heterojunction solar cell 101 shown in FIG. 1, the single crystal silicon substrate 1 constituting the photoelectric conversion unit 50 hardly changes its characteristics even when heated to a high temperature of 500 ° C. or higher. When the amorphous silicon-based thin films 2 and 3 are heated to about 250 ° C., thermal deterioration or diffusion of doped impurities may occur, resulting in irreversible deterioration of solar cell characteristics. Therefore, in the heterojunction solar cell, the first conductive layer 71 is preferably heat flow temperature T ₁ is comprises a low melting point material 250 ° C. or less.

The lower limit of the thermal flow temperature T ₁ of the low melting point material is not particularly limited. From the viewpoint of easily forming the opening 9h in the insulating layer 9 by increasing the amount of change in the surface shape of the first conductive layer during the annealing treatment, the low melting point material is thermally flowable in the first conductive layer forming step. It is preferable not to produce. For example, when the first conductive layer is formed by coating or printing, heating may be performed for drying. In this case, the heat flow temperature T ₁ of the low-melting material is preferred over the heating temperature for the drying of the first conductive layer is a high temperature. From this viewpoint, the heat flow temperature T ₁ of the low melting point materials is preferably at least 80 ° C., more preferably at least 100 ° C..

Low melting point material, if the heat flow temperature T ₁ is the above-mentioned range, be organic, it may be inorganic. The low melting point material may be electrically conductive or insulating, but is preferably a metal material having conductivity. If the low-melting-point material is a metal material, the resistance value of the first conductive layer can be reduced. Therefore, when the second conductive layer is formed by electroplating, the uniformity of the film thickness of the second conductive layer can be improved. it can. In addition, when the low melting point material is a metal material, the contact resistance between the photoelectric conversion unit 50 and the collector electrode 70 can be reduced.

  As the low melting point material, a simple substance or an alloy of a low melting point metal material or a mixture of a plurality of low melting point metal materials can be suitably used. Examples of the low melting point metal material include indium, bismuth, and gallium.

The first conductive layer 71, as a conductive material, in addition to the low melting point material preferably contains a refractory material having a thermal flow temperature T ₂ of the relatively high temperature than the low-melting-point material. Since the first conductive layer 71 includes the high melting point material, the first conductive layer and the second conductive layer can be efficiently conducted, and the conversion efficiency of the solar cell can be improved. For example, when a material having a large surface energy is used as the low melting point material, when the first conductive layer 71 is exposed to a high temperature by the annealing process and the low melting point material is in a liquid phase state, as conceptually shown in FIG. In some cases, the particles of the low-melting-point material are aggregated to become coarse particles, and the first conductive layer 71 may be disconnected. On the other hand, since the high melting point material does not become a liquid phase state even when heated during the annealing process, the low melting point material as shown in FIG. 8 can be obtained by including the high melting point material in the first conductive layer forming material. Disconnection of the first conductive layer due to coarsening can be suppressed.

Heat flow temperature T ₂ of the high-melting material is preferably higher than the annealing temperature Ta. That is, when the first conductive layer 71 contains a low melting point material and a high melting point material, the heat flow starting temperature T _{1 of} the low melting point material, the heat flow starting temperature T _{2 of} the high melting point material, and the annealing temperature Ta in the annealing process are: , T ₁ <Ta <T ₂ is preferably satisfied. The high melting point material may be an insulating material or a conductive material, but a conductive material is preferable from the viewpoint of reducing the resistance of the first conductive layer. When the low melting point material has low conductivity, the resistance of the first conductive layer as a whole can be reduced by using a material having high conductivity as the high melting point material. As the conductive high melting point material, for example, a single metal material such as silver, aluminum, copper, or a plurality of metal materials can be preferably used.

  When the first conductive layer 71 contains a low-melting-point material and a high-melting-point material, the content ratio is to suppress disconnection due to the coarsening of the low-melting-point material as described above, to the conductivity of the first conductive layer, to the insulating layer. From the standpoint of easiness of forming the opening (increase in the number of starting points of metal deposition of the second conductive layer) and the like, it is appropriately adjusted. The optimum value varies depending on the material used and the combination of particle sizes. For example, the weight ratio of the low melting point material to the high melting point material (low melting point material: high melting point material) is 5:95 to 67:33. It is a range. The weight ratio of the low melting point material: the high melting point material is more preferably 10:90 to 50:50, and further preferably 15:85 to 35:65.

For example, when a particulate low melting point material such as metal particles is used as the material of the first conductive layer 71, the particle size D of the low melting point material is used from the viewpoint of facilitating the formation of an opening in the insulating layer by annealing. _L is preferably 1/20 or more, more preferably 1/10 or more, of the film thickness d of the first conductive layer. Particle size _{D L} of the low-melting material, more preferably 0.25 [mu] m, more preferably not less than 0.5 [mu] m. When the first conductive layer 71 is formed by a printing method such as screen printing, the particle size of the particles can be set as appropriate according to the mesh size of the screen plate. For example, the particle size is preferably smaller than the mesh size, and more preferably ½ or less of the mesh size. When the particles are non-spherical, the particle size is defined by the diameter of a circle having the same area as the projected area of the particles (projected area circle equivalent diameter, Heywood diameter).

The shape of the particles of the low melting point material is not particularly limited, but a non-spherical shape such as a flat shape is preferable. In addition, non-spherical particles obtained by combining spherical particles by a technique such as sintering are also preferably used. Generally, when the metal particles are in a liquid phase, the surface shape tends to be spherical in order to reduce the surface energy. If low melting point material of the first conductive layer before annealing is non-spherical, the annealing is heated in heat flow starting temperature above T _1, since the particles approaches the spherical shape, the surface shape of the first conductive layer The amount of change is greater. Therefore, it is easy to form an opening in the insulating layer 9 on the first conductive layer 71.

As described above, the first conductive layer 71 is conductive, and the volume resistivity may be 10 ⁻² Ω · cm or less. The volume resistivity of the first conductive layer 71 is preferably 10 ⁻⁴ Ω · cm or less. When the first conductive layer has only the low melting point material, the low melting point material only needs to have conductivity. In the case where the first conductive layer contains a low melting point material and a high melting point material, at least one of the low melting point material and the high melting point material may be conductive. For example, the combination of low melting point material / high melting point material includes insulation / conductivity, conductivity / insulation, conductivity / conductivity. In order to make the first conductive layer have a lower resistance, Both the low melting point material and the high melting point material are preferably conductive materials.

In addition to the combination of the low-melting-point material and the high-melting-point material as described above as the material for the first conductive layer 71, by adjusting the size (for example, particle size) of the material, the first conductive layer 71 is heated by the annealing process. It is also possible to suppress disconnection of the conductive layer and improve conversion efficiency. For example, if a material having a high melting point such as silver, copper, gold or the like is fine particles having a particle size of 1 μm or less, sintering necking (particulate particles) at a temperature T ₁ ′ of about 200 ° C. or lower than the melting point Therefore, it can be used as the “low melting point material” of the present invention. When the material that causes such sintering necking is heated to the sintering necking start temperature T ₁ ′ or higher, deformation occurs in the vicinity of the outer periphery of the fine particles, so that the surface shape of the first conductive layer is changed, and the insulating layer An opening can be formed in 9. Further, even when the fine particles are heated to a temperature higher than the sintering necking start temperature, the fine particles maintain the solid state if the temperature is lower than the melting point T ₂ ′. Disconnection due to is difficult to occur. That is, it can be said that a material that causes sintering necking such as metal fine particles is a “low melting point material” in the present invention, but also has a side surface as a “high melting point material”.

In a material that causes such sintering necking, it can be defined that sintering necking start temperature T ₁ ′ = heat flow start temperature T ₁ . FIG. 9 is a diagram for explaining the sintering necking start temperature. FIG. 9A is a plan view schematically showing the particles before sintering. Since they are not sintered, the particles are in point contact with each other. FIG. 9B and FIG. 9C are cross-sectional views schematically showing the state when the particles after sintering are cut along a cross section passing through the center of each particle. FIG. 9B shows the state after the start of sintering (the initial stage of sintering), and FIG. 9C shows the state where the sintering has progressed from (B). In FIG. 9B, the grain boundary between the particle A (radius r _A ) and the particle B (radius r _B ) is indicated by a dotted line having a length a _AB .

Sintering necking onset temperature _{T 1} ', the ratio of _{r A} and _r larger value max _(r A, _{r B)} of the _B and the grain boundary between the length _{a AB, a AB / max (} r A, r _B ) is defined as the temperature at which it becomes 0.1 or more. That is, the temperature at which a _AB / max (r _A , r _B ) of at least a pair of particles is 0.1 or more is referred to as a sintering necking start temperature. In FIG. 10, for the sake of simplicity, the particles are shown as spherical, but when the particles are not spherical, the radius of curvature of the particles near the grain boundary is regarded as the radius of the particles. When the radius of curvature of the particle near the grain boundary varies depending on the location, the largest radius of curvature among the measurement points is regarded as the radius of the particle. For example, as shown in FIG. 10A, a grain boundary of length a _AB is formed between a pair of fine particles A and B that have been sintered. In this case, the shape of the particle A in the vicinity of the grain boundary is approximated by an arc of a virtual circle A indicated by a dotted line. On the other hand, the grain boundaries near the particle B, one is approximated by an arc of a virtual circle B ₁ indicated by broken lines, and the other is approximated by an arc of a virtual circle B ₂ indicated by a solid line. As shown in FIG. 10B, since r _B2 > r _B1 , r _B2 is regarded as the radius r _{B of the} particle B. Note that the above virtual circle is determined by a method in which the boundary is defined by black and white binarization processing of the observation image of the cross section or surface, and the center coordinates and radius are calculated by the least square method based on the coordinates of the boundary in the vicinity of the grain boundary. it can. If it is difficult to strictly measure the sintering necking start temperature according to the above definition, the first conductive layer containing fine particles is formed, and the temperature at which an opening (crack) is generated in the insulating layer by heating is set. It can be regarded as the sintering necking start temperature. As will be described later, when heating is performed during the formation of the insulating layer, the temperature at which an opening (crack) is generated by heating the substrate during the formation of the insulating layer can be regarded as the firing necking start temperature.

  In addition to the low melting point material (and high melting point material) described above, a paste containing a binder resin or the like can be preferably used as the first conductive layer forming material. In order to sufficiently improve the conductivity of the first conductive layer formed by the screen printing method, it is desirable to cure the first conductive layer by heat treatment. Therefore, as the binder resin contained in the paste, it is preferable to use a material that can be cured at the drying temperature, and an epoxy resin, a phenol resin, an acrylic resin, or the like is applicable. In this case, the shape of the low melting point material changes with hardening, and as shown in FIG. 7G, an opening (crack) is likely to occur in the insulating layer near the low melting point material during the annealing process. Note that the ratio between the binder resin and the conductive low melting point material may be set to be equal to or higher than a so-called percolation threshold (a critical value of the ratio corresponding to the low melting point material content at which conductivity is manifested).

  The first conductive layer 71 can be produced by a known technique such as an inkjet method, a screen printing method, a conductive wire bonding method, a spray method, a vacuum deposition method, or a sputtering method. The first conductive layer 71 is preferably patterned in a predetermined shape such as a comb shape. A screen printing method is suitable for forming the patterned first conductive layer from the viewpoint of productivity. In the screen printing method, a method of printing a collecting electrode pattern using a printing paste containing a conductive material and a screen plate having an opening pattern corresponding to the pattern shape of the collecting electrode is preferably used.

On the other hand, when a material containing a solvent is used as the printing paste, a drying step for removing the solvent is required. As described above, the drying temperature in this case is preferably lower than the heat resistant temperature of the photoelectric conversion part. For example, when the photoelectric conversion part has a transparent electrode layer or an amorphous silicon thin film, the drying temperature is preferably 250 ° C. or lower, more preferably 200 ° C. or lower, and 180 ° C. or lower. Further preferred. It is preferable than the heat flow temperature T ₁ of the low melting point material is a low temperature. The drying time can be appropriately set, for example, from about 5 minutes to 1 hour.

  The first conductive layer may be composed of a plurality of layers. For example, a laminated structure including a lower layer having a low contact resistance with the transparent electrode layer on the surface of the photoelectric conversion portion and an upper layer containing a conductive material may be used. According to such a structure, an improvement in the curve factor of the solar cell can be expected with a decrease in contact resistance with the transparent electrode layer. In addition, for example, by forming a laminated structure of a low-melting-point material-containing layer and a high-melting-point material-containing layer, a lower layer with a high content of conductive material, and an upper-layered structure with a low content of conductive material, Further reduction in resistance of the first conductive layer can be expected.

  As mentioned above, although demonstrated centering on the case where a 1st conductive layer is formed by the printing method, the formation method of a 1st conductive layer is not limited to a printing method. For example, the first conductive layer may be formed by vapor deposition or sputtering using a mask corresponding to the pattern shape. Further, the pattern may be formed by an ink jet method or the like.

(Insulating layer)
When the first conductive layer 71 is formed in a predetermined pattern (for example, a comb shape), the first conductive layer forming region in which the first conductive layer is formed on the surface of the photoelectric conversion unit 50, and the first conductive layer There is a first conductive layer non-formation region in which is not formed . Insulation layer 9, it is preferable that made form the first conductive layer non-formation region, that is formed on the entire surface of the first conductive layer non-formation region particularly preferred. If the insulating layer is made form the first conductive layer non-formation region, when the second conductive layer is formed by plating, chemical and electrical possible to protect the photoelectric conversion unit from the plating solution It becomes. In particular, when the transparent electrode layer is formed on the surface of the photoelectric conversion unit 50 as heterojunction solar cells, since the insulating layer on the surface of the transparent electrode layer is formed, a transparent electrode layer and the plating solution Is prevented, and deposition of the metal layer (second conductive layer) on the transparent electrode layer can be prevented. Also, from the viewpoint of productivity, it is more preferable that the insulating layer is formed in the entire first conductive layer formation region and the first conductive layer non-formation region.

Absolute Enso may be made of prior plating process, the insulating layer formation step, either the transparent electrode layer forming step first conductive layer forming step before or after, or before the plating step after the first conductive layer forming step May be. For example, when it is formed before the first conductive layer forming step, a method of protecting a portion corresponding to the first conductive layer with a mask and forming an insulating layer in a portion other than forming the first conductive layer can be mentioned. . Especially, it is preferable to form after a 1st conductive layer formation process. In particular, as described above, when an insulating layer having an opening is formed on the first conductive layer, the second conductive layer can be easily deposited by plating through the opening. Moreover, the photoelectric conversion part can be further protected from the plating solution by being formed so as to cover the first conductive layer. In addition, as described above, when a material having a low melting point material is used as the first conductive layer, an opening is easily formed in the insulating layer on the first conductive layer by annealing the low melting point material. Can do. In this case, an insulating layer is preferably formed on the first conductive layer non-formation region, and an insulating layer is preferably formed on the entire surface of the first conductive layer non-formation region. More preferably, an insulating layer is formed over the entire region where the first collector electrode is formed and the region where the first collector electrode is not formed.

  Further, by setting the radius of curvature r1 of the convex portion within the above range, it is possible to prevent the insulating layer from being thinned in the convex portion and to prevent the formation of pinholes. Therefore, shadow loss is reduced by preventing the deposition of an undesired metal layer, and as a result, the solar cell characteristics can be further improved.

As the material of the insulating layer 9, a material that exhibits electrical insulation is used. The insulating layer 9 is preferably a material having chemical stability with respect to the plating solution. By using a material having high chemical stability with respect to the plating solution, the insulating layer is hardly dissolved during the plating step when forming the second conductive layer, and damage to the surface of the photoelectric conversion portion is less likely to occur . Absolute Enso is preferably adhesion strength between the photoelectric conversion unit 50 is large. For example, in the heterojunction solar cell, the insulating layer 9 preferably has a high adhesion strength with the transparent electrode layer 6a on the surface of the photoelectric conversion unit 50. By increasing the adhesion strength between the transparent electrode layer and the insulating layer, it becomes difficult for the insulating layer to be peeled off during the plating step, and metal deposition on the transparent electrode layer can be prevented.

  For the insulating layer 9, it is preferable to use a material with little light absorption. Since the insulating layer 9 is formed on the light incident surface side of the photoelectric conversion unit 50, more light can be taken into the photoelectric conversion unit if light absorption by the insulating layer is small. For example, when the insulating layer 9 has sufficient transparency with a transmittance of 90% or more, the optical loss due to light absorption in the insulating layer is small, and without removing the insulating layer after forming the second conductive layer, the solar Can be used as a battery. Therefore, the manufacturing process of a solar cell can be simplified and productivity can be further improved. When the insulating layer 9 is used as it is as a solar cell without being removed, the insulating layer 9 is more preferably made of a material having sufficient weather resistance and stability against heat and humidity in addition to transparency. .

  The material of the insulating layer may be an inorganic insulating material or an organic insulating material. As the inorganic insulating material, for example, materials such as silicon oxide, silicon nitride, titanium oxide, aluminum oxide, magnesium oxide, and zinc oxide can be used. As the organic insulating material, for example, materials such as polyester, ethylene vinyl acetate copolymer, acrylic, epoxy, and polyurethane can be used. From the viewpoint of facilitating the formation of an opening in the insulating layer due to interface stress caused by the change in the surface shape of the first conductive layer in the annealing treatment, the material of the insulating layer is an inorganic material having a small breaking elongation. It is preferable.

Among these inorganic materials, from the viewpoint of plating solution resistance and transparency, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, sialon (SiAlON), yttrium oxide, magnesium oxide, barium titanate, samarium oxide, Barium tantalate _, tantalum oxide, magnesium fluoride, titanium oxide, strontium titanate and the like are preferably used. Among these, from the viewpoint of electrical properties and adhesion to the transparent electrode layer, etc., silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, sialon (SiAlON), yttrium oxide, magnesium oxide, barium titanate, samarium oxide, Barium tantalate _, tantalum oxide, magnesium fluoride, and the like are preferable, and silicon oxide, silicon nitride, and the like are particularly preferably used from the viewpoint that the refractive index can be appropriately adjusted. These inorganic materials are not limited to those having a stoichiometric composition, and may include oxygen deficiency or the like.

  The film thickness of the insulating layer 9 is appropriately set according to the material and forming method of the insulating layer. When a material containing a low-melting-point material is used as the first conductive layer, the thickness of the insulating layer 9 is such that the insulating layer 9 opens to the insulating layer due to interface stress or the like caused by a change in the surface shape of the first conductive layer in the annealing process It is preferable that the portion is thin enough to be formed. From this viewpoint, the thickness of the insulating layer 9 is preferably 1000 nm or less, and more preferably 500 nm or less. In addition, by appropriately setting the optical characteristics and film thickness of the insulating layer 9 in the first conductive layer non-forming portion, the light reflection characteristics are improved, the amount of light introduced into the crystalline silicon solar cell is increased, and the conversion is performed. Efficiency can be further improved. In order to obtain such an effect, the refractive index of the insulating layer 9 is preferably lower than the refractive index of the surface of the photoelectric conversion unit 50. Further, from the viewpoint of imparting suitable antireflection properties to the insulating layer 9, the film thickness is preferably set within a range of 30 nm to 250 nm, and more preferably within a range of 50 nm to 250 nm. In addition, when forming an insulating layer in both the first conductive layer forming region and the first conductive layer non-forming region, the thickness of the insulating layer on the first conductive layer forming region and the insulation on the first conductive layer non-forming region The layer thicknesses may be different. For example, in the first conductive layer formation region, the thickness of the insulating layer is set from the viewpoint of facilitating the formation of the opening by annealing, and in the first conductive layer non-formation region, an optical film having appropriate antireflection characteristics The film thickness of the insulating layer may be set to be thick.

  When a transparent electrode layer (generally having a refractive index of about 1.9 to 2.1) is provided on the surface of the photoelectric conversion unit 50 as in a heterojunction solar cell, the effect of preventing light reflection at the interface is enhanced and the crystalline silicon system is used. In order to increase the amount of light introduced into the solar battery cell, the refractive index of the insulating layer is preferably an intermediate value between air (refractive index = 1.0) and the transparent electrode layer. Moreover, when a photovoltaic cell is sealed and modularized, it is preferable that the refractive index of an insulating layer is an intermediate value of a sealing agent and a transparent electrode layer. From this viewpoint, the refractive index of the insulating layer 9 is preferably, for example, 1.4 to 1.9, more preferably 1.5 to 1.8, and further preferably 1.55 to 1.75. The refractive index of the insulating layer can be adjusted to a desired range depending on the material, composition, etc. of the insulating layer. For example, in the case of silicon oxide, the refractive index is increased by reducing the oxygen content. In addition, unless otherwise indicated, the refractive index in this specification is a refractive index with respect to the light of wavelength 550nm, and is a value measured by spectroscopic ellipsometry. Further, it is preferable that the optical film thickness (refractive index × film thickness) of the insulating layer is set so as to improve the antireflection characteristics according to the refractive index of the insulating layer.

  The insulating layer can be formed using a known method. For example, in the case of an inorganic insulating material such as silicon oxide or silicon nitride, a dry method such as a plasma CVD method or a sputtering method is preferably used. In the case of an organic insulating material, a wet method such as a spin coating method or a screen printing method is preferably used. According to these methods, it is possible to form a dense film with few defects such as pinholes.

  Among these, from the viewpoint of forming a film having a denser structure, the insulating layer 9 is preferably formed by a plasma CVD method. By this method, not only a thick film with a thickness of about 200 nm but also a thin insulating film with a thickness of about 30 to 100 nm can be formed.

  For example, in the case where the surface of the photoelectric conversion unit 50 has a texture structure (uneven structure), such as the crystalline silicon solar cell shown in FIG. The layer is preferably formed by a plasma CVD method. By using a highly dense insulating layer, it is possible to reduce damage to the transparent electrode layer during the plating process and to prevent metal deposition on the transparent electrode layer. Such a dense insulating film functions as a barrier layer for water, oxygen, and the like for the layers inside the photoelectric conversion unit 50 as in the silicon-based thin film 3 in the crystalline silicon-based solar cell of FIG. Therefore, the effect of improving the long-term reliability of the crystalline silicon solar cell can be expected.

  Note that the shape of the insulating layer 9 between the first conductive layer 71 and the second conductive layer 72, that is, the insulating layer 9 on the first conductive layer forming region, is not necessarily a continuous layer shape, and is an island shape. It may be. Note that the term “island” in this specification means a state in which a part of the surface has a non-formation region where the insulating layer 9 is not formed.

  In the present invention, the insulating layer 9 can also contribute to improving the adhesion between the first conductive layer 71 and the second conductive layer 72. For example, when a Cu layer is formed by plating on the Ag layer that is the base electrode layer, the adhesion between the Ag layer and the Cu layer is small, but the Cu layer is formed on an insulating layer such as silicon oxide. Therefore, it is expected that the adhesion of the second conductive layer is enhanced and the reliability of the solar cell is improved.

As described above, when the first conductive layer has, for example, a low melting point material, an annealing process is performed after the insulating layer is formed on the first conductive layer 71 and before the second conductive layer 72 is formed. During the annealing process, the first conductive layer 71 is heated to a temperature higher than the thermal flow temperature T ₁ of the low melting point material, for the low-melting-point material is fluidized state, the surface shape of the first conductive layer is changed. Along with this change, an opening 9h is formed in the insulating layer 9 formed thereon. Therefore, in a subsequent plating step, a part of the surface of the first conductive layer 71 is exposed to the plating solution and becomes conductive, so that the metal is deposited starting from this conductive portion as shown in FIG. It becomes possible.

  In this case, the opening is mainly formed on the low melting point material 711 of the first conductive layer 71. When the low melting point material is an insulating material, it is insulative immediately below the opening, but since the plating solution penetrates into the conductive high melting point material existing around the low melting point material, the first conductive layer and It is possible to conduct the plating solution.

The annealing temperature (heating temperature) Ta during the annealing treatment is preferably higher than the thermal flow start temperature T ₁ of the low melting point material, that is, T ₁ <Ta. The annealing temperature Ta preferably satisfies T ₁ + 1 ° C. ≦ Ta ≦ T ₁ + 100 ° C., and more preferably satisfies T ₁ + 5 ° C. ≦ Ta ≦ T ₁ + 60 ° C. The annealing temperature can be appropriately set according to the composition and content of the material of the first conductive layer.

Further, as described above, the annealing temperature Ta is preferably lower than the heat resistant temperature of the photoelectric conversion unit 50. The heat-resistant temperature of the photoelectric conversion unit varies depending on the configuration of the photoelectric conversion unit. For example, the heat resistant temperature in the case of having a transparent electrode layer or an amorphous silicon-based thin film, such as a heterojunction solar cell or a silicon-based thin film solar cell, is about 250 ° C. Therefore, in the case of a heterojunction solar cell in which the photoelectric conversion portion includes an amorphous silicon thin film or a silicon thin film solar cell, the annealing temperature is 250 from the viewpoint of suppressing thermal damage at the amorphous silicon thin film and its interface. It is preferable that the temperature is set to be equal to or lower. In order to realize a higher performance solar cell, the annealing temperature is more preferably 200 ° C. or less, and further preferably 180 ° C. or less. Accordingly, the heat flow temperature T ₁ of the low melting point material of the first conductive layer 71 is preferably less than 250 ° C., more preferably less than 200 ° C., more preferably less than 180 ° C..

  On the other hand, a crystalline silicon solar cell having a reverse conductivity type diffusion layer on one principal surface of a one conductivity type crystalline silicon substrate does not have an amorphous silicon thin film or a transparent electrode layer, and therefore has a heat resistance temperature of 800 ° C. It is about -900 degreeC. Therefore, the annealing process may be performed at an annealing temperature Ta higher than 250 ° C.

  Note that the method for forming the opening in the insulating layer is not limited to the method in which the annealing treatment is performed after the insulating layer is formed as described above. For example, as shown in FIG. 7 (broken arrows), the opening 9h can be formed simultaneously with the formation of the insulating layer 90.

  For example, the opening is formed substantially simultaneously with the formation of the insulating layer by forming the insulating layer while heating the substrate. Here, “substantially simultaneously with the formation of the insulating layer” means that a separate process such as annealing is not performed in addition to the insulating layer forming process, that is, during or immediately after the formation of the insulating layer. Means the state. The term “immediately after film formation” includes the period from the end of film formation of the insulating layer (after the stop of heating) to the time when the substrate is cooled and returned to room temperature. In addition, when an opening is formed in the insulating layer on the low-melting-point material, even after the insulating layer on the low-melting-point material has been formed, the insulating layer is formed around the periphery. Thus, the case where the insulating layer around the low melting point material is deformed and an opening is formed is included.

  As a method of forming the opening substantially simultaneously with the formation of the insulating layer, for example, in the insulating layer forming step, the substrate is heated to a temperature Tb higher than the thermal flow start temperature T1 of the low melting point material 711 of the first conductive layer 71. However, a method of forming the insulating layer 9 on the first conductive layer 71 is used. Since the insulating layer 9 is formed on the first conductive layer in which the low melting point material is in a fluid state, stress is generated at the film forming interface at the same time as the film formation, for example, a crack-shaped opening is formed in the insulating layer. The

  The substrate temperature Tb at the time of forming the insulating layer (hereinafter referred to as “insulating layer forming temperature”) represents the substrate surface temperature (also referred to as “substrate heating temperature”) at the time of starting the formation of the insulating layer. In general, the average value of the substrate surface temperature during the formation of the insulating layer is usually equal to or higher than the substrate surface temperature at the start of film formation. Therefore, if the insulating layer forming temperature Tb is higher than the heat flow starting temperature T1 of the low melting point material, deformation of the opening or the like can be formed in the insulating layer.

  For example, when the insulating layer 9 is formed by a dry method such as a CVD method or a sputtering method, the substrate surface temperature in the insulating layer formation is set higher than the thermal flow start temperature T1 of the low melting point material, thereby opening the opening. The part can be formed. When the insulating layer 9 is formed by a wet method such as coating, the opening is formed by setting the substrate surface temperature when drying the solvent to be higher than the thermal flow start temperature T1 of the low melting point material. be able to. Note that the “film formation start point” when the insulating layer is formed by a wet method refers to the time point when the solvent starts drying. The preferable range of the insulating layer formation temperature Tb is the same as the preferable range of the annealing temperature Ta.

  The substrate surface temperature can be measured, for example, by attaching a temperature display material (also called a thermo label or a thermo seal) or a thermocouple to the substrate surface. In addition, the temperature of the heating unit (such as a heater) can be appropriately adjusted so that the surface temperature of the substrate falls within a predetermined range.

  When annealing treatment is performed in the insulating layer forming step, the material and composition of the insulating layer, and the film forming conditions (film forming method, substrate temperature, type and amount of introduced gas, film forming pressure, power density, etc.) are adjusted as appropriate. Thus, an opening can be formed in the insulating layer.

  When the insulating layer 9 is formed by the plasma CVD method, from the viewpoint of forming a dense film, the insulating layer forming temperature Tb is preferably 130 ° C. or higher, more preferably 140 ° C. or higher, and further preferably 150 ° C. or higher. Moreover, it is preferable that the highest temperature reached on the substrate surface during the formation of the insulating layer is lower than the heat-resistant temperature of the photoelectric conversion part.

  The film deposition rate by plasma CVD is preferably 1 nm / second or less, more preferably 0.5 nm / second or less, and further preferably 0.25 nm / second or less from the viewpoint of forming a denser film. As film forming conditions when silicon oxide is formed by plasma CVD, a substrate temperature of 145 ° C. to 250 ° C., a pressure of 30 Pa to 300 Pa, and a power density of 0.01 W / cm 2 to 0.16 W / cm 2 are preferable.

  After the opening is formed substantially simultaneously with the formation of the insulating layer, when there is a portion where the opening is not sufficiently formed, the above-described annealing step may be further performed.

(Second conductive layer)
As described above, after the insulating layer 9 having the opening 9h is formed, the second conductive layer 72 is formed on the insulating layer 9 in the first conductive layer forming region by plating. At this time, the metal deposited as the second conductive layer is not particularly limited as long as it is a material that can be formed by a plating method. For example, copper, nickel, tin, aluminum, chromium, silver, gold, zinc, lead, palladium, etc. Alternatively, a mixture of these can be used.

  During operation of the solar cell (power generation), current flows mainly through the second conductive layer. Therefore, from the viewpoint of suppressing resistance loss in the second conductive layer, it is preferable that the line resistance of the second conductive layer is as small as possible. Specifically, the line resistance of the second conductive layer is preferably 1 Ω / cm or less, and more preferably 0.5 Ω / cm or less. On the other hand, the line resistance of the first conductive layer only needs to be small enough to function as a base layer during electroplating, for example, 5 Ω / cm or less.

  The second conductive layer can be formed by either an electroless plating method or an electrolytic plating method, but the electrolytic plating method is preferably used from the viewpoint of productivity. In the electroplating method, since the metal deposition rate can be increased, the second conductive layer can be formed in a short time.

  Taking the acidic copper plating as an example, a method of forming the second conductive layer by the electrolytic plating method will be described. FIG. 11 is a conceptual diagram of the plating apparatus 10 used for forming the second conductive layer. A substrate 12 on which an insulating layer having a first conductive layer and an opening is formed on a photoelectric conversion portion, and an anode 13 are immersed in a plating solution 16 in the plating tank 11. The first conductive layer 71 on the substrate 12 is connected to the power source 15 via the substrate holder 14. By applying a voltage between the anode 13 and the substrate 12, copper is selectively formed on the first conductive layer not covered with the insulating layer 9, that is, with an opening formed in the insulating layer by annealing treatment as a starting point. Can be deposited.

The plating solution 16 used for acidic copper plating contains copper ions. For example, a known composition mainly composed of copper sulfate, sulfuric acid, and water can be used, and a metal that is the second conductive layer is deposited by passing a current of 0.1 to 10 A / dm ² through this. be able to. An appropriate plating time is appropriately set according to the area of the collecting electrode, current density, cathode current efficiency, set film thickness, and the like.

  The second conductive layer may be composed of a plurality of layers. For example, after a first plating layer made of a material having high conductivity such as Cu is formed on the first conductive layer through the opening of the insulating layer, the second plating layer having excellent chemical stability is formed on the first plating layer. By forming on the surface of one plating layer, a collector electrode having low resistance and excellent chemical stability can be formed.

  It is preferable to provide a plating solution removing step after the plating step to remove the plating solution remaining on the surface of the substrate 12. By providing the plating solution removal step, it is possible to further suppress a decrease in long-term reliability.

  In general, a transparent electrode layer such as ITO or an insulating layer such as silicon oxide is hydrophilic, and a contact angle with water on the surface of the substrate 12 or the surface of the insulating layer 9 is about 10 ° or less. There are many cases. On the other hand, from the viewpoint of facilitating removal of the plating solution by air blow or the like, the contact angle with the water on the surface of the substrate 12 is preferably set to 20 ° or more. In order to increase the contact angle of the substrate surface, the surface of the substrate 12 may be subjected to water repellent treatment. The water repellent treatment is performed, for example, by forming a water repellent layer on the surface. By the water repellent treatment, the wettability of the substrate surface to the plating solution can be reduced.

  Instead of the water repellent treatment on the surface of the insulating layer 9, an insulating layer 9 having water repellency may be formed. That is, by forming the insulating layer 9 having a large contact angle θ with water (for example, 20 ° or more), a separate water-repellent treatment step can be omitted, so that the productivity of the solar cell can be further improved. As a method for imparting water repellency to the insulating layer, for example, the insulating layer is formed by a plasma CVD method in which the film forming conditions of the insulating layer (for example, the flow rate ratio of silicon source gas and oxygen source gas introduced into the film forming chamber) are changed. And a method of forming a silicon oxide layer as the above.

  In the present invention, the insulating layer removing step may be performed after the collector electrode is formed (after the plating step). In particular, when a material having a large light absorption is used as the insulating layer, it is preferable to perform an insulating layer removing step in order to suppress a decrease in solar cell characteristics due to the light absorption of the insulating layer. The method for removing the insulating layer is appropriately selected according to the characteristics of the insulating layer material. For example, the insulating layer can be removed by chemical etching or mechanical polishing. An ashing method can also be applied depending on the material. At this time, from the viewpoint of further improving the light capturing effect, it is more preferable that all of the insulating layer on the first conductive layer non-forming region is removed. When the water repellent layer 91 is formed on the insulating layer 9, it is preferable that the water repellent layer 91 is also removed together with the insulating layer 9. Note that in the case where a material with low light absorption is used for the insulating layer, the insulating layer removing step does not need to be performed.

  Although the above description has focused on the case where the collector electrode 70 is provided on the light incident side of the heterojunction solar cell, a similar collector electrode may be formed on the back surface side. Since a crystalline silicon solar cell using a crystalline silicon substrate such as a heterojunction solar cell has a large amount of current, in general, power generation loss due to loss of contact resistance between the transparent electrode layer / collector electrode tends to be significant. . On the other hand, in the present invention, since the collector electrode having the first conductive layer and the second conductive layer has a low contact resistance with the transparent electrode layer, it is possible to reduce power generation loss due to the contact resistance. .

  The solar cell of the present invention is preferably modularized for practical use. The modularization of the solar cell is performed by an appropriate method. For example, a bus bar is connected to a collector electrode via an interconnector such as a tab, so that a plurality of solar cells are connected in series or in parallel, and sealed with a sealant and a glass plate to be modularized. Done.

  Hereinafter, the present invention will be specifically described with reference to the examples of the heterojunction solar cell shown in FIG. 1, but the present invention is not limited to the following examples.

Example 1
The heterojunction solar cell of Example 1 was manufactured as follows.

  As a single conductivity type single crystal silicon substrate, an n-type single crystal silicon wafer having an incident plane of (100) and a thickness of 200 μm was used, and this silicon wafer was immersed in a 2 wt% HF aqueous solution for 3 minutes. After the silicon oxide film was removed, rinsing with ultrapure water was performed twice. This silicon substrate was immersed in a 5/15 wt% KOH / isopropyl alcohol aqueous solution maintained at 70 ° C. for 15 minutes, and the texture was formed by etching the surface of the wafer. Thereafter, rinsing with ultrapure water was performed twice. When the surface of the wafer was observed with an atomic force microscope (manufactured by AFM Pacific Nanotechnology), the surface of the wafer was most etched, and a pyramidal texture (uneven structure A with the (111) plane exposed) ) Was formed (texture forming step). The wafer after the texture treatment was immersed in a mixed solution of 0.5% by weight HF aqueous solution and 15 ppm ozone for 5 minutes to perform cleaning of the wafer surface and rounding of the textured protrusions to form an uneven structure B ( Etching process).

  The concavo-convex structures A and B are confirmed by measuring the cross section of the substrate within a range of 10 mm with a scanning electron microscope (SEM) using a single crystal silicon substrate before and after the etching treatment step, and having five curvature radii. Was calculated as the radius of curvature of each. In the concavo-convex structure A, as shown in FIG. 2, both r1 and r2 were less than 0.005 μm. On the other hand, the concavo-convex structure B after the etching treatment step was r1> r2, as shown in FIG.

The single crystal silicon substrate on which the concavo-convex structure B was formed as described above was introduced into a CVD apparatus, and an i-type amorphous silicon film having a thickness of 5 nm was formed on the light incident side as an intrinsic silicon thin film 2a. . The film formation conditions for the i-type amorphous silicon were: substrate temperature: 150 ° C., pressure: 120 Pa, SiH ₄ / H ₂ flow rate ratio: 3/10, and input power density: 0.011 W / cm ² . In addition, the film thickness of the thin film in a present Example measures the film thickness of the thin film formed on the glass substrate on the same conditions by the spectroscopic ellipsometry (brand name M2000, JA Woollam Co., Ltd. product). It is a value calculated from the film forming speed obtained by this.

On the i-type amorphous silicon layer 2a, a p-type amorphous silicon film having a thickness of 7 nm was formed as the reverse conductivity type silicon-based thin film 3a. The film forming conditions for the p-type amorphous silicon layer 3a were as follows: the substrate temperature was 150 ° C., the pressure was 60 Pa, the SiH ₄ / B ₂ H ₆ flow rate ratio was 1/3, and the input power density was 0.01 W / cm ² . . The B ₂ H ₆ gas flow rate mentioned above is the flow rate of the diluted gas diluted with H ₂ to a B ₂ H ₆ concentration of 5000 ppm.

Next, an i-type amorphous silicon layer having a thickness of 6 nm was formed as an intrinsic silicon-based thin film 2b on the back side of the wafer. The film formation conditions for the i-type amorphous silicon layer 2b were the same as those for the i-type amorphous silicon layer 2a. On the i-type amorphous silicon layer 2b, an n-type amorphous silicon layer having a thickness of 4 nm was formed as a one-conductivity-type silicon-based thin film 3b. The film forming conditions for the n-type amorphous silicon layer 3b were: substrate temperature: 150 ° C., pressure: 60 Pa, SiH ₄ / PH ₃ flow rate ratio: 1/2, input power density: 0.01 W / cm ² . The PH ₃ gas flow rate mentioned above is the flow rate of the diluted gas diluted with H ₂ to a PH ₃ concentration of 5000 ppm.

On this, as transparent electrode layers 6a and 6b, indium tin oxide (ITO, refractive index: 1.9) was formed to a thickness of 100 nm. Using indium oxide as a target, a transparent electrode layer was formed by applying a power density of 0.5 W / cm ² in an argon atmosphere at a substrate temperature of room temperature and a pressure of 0.2 Pa. On the back surface side transparent electrode layer 6b, silver was formed as a back surface metal electrode 8 with a film thickness of 500 nm by sputtering. On the light incident side transparent electrode layer 6a, a collector electrode 70 having a first conductive layer 71 and a second conductive layer 72 was formed as follows.

For the formation of the first conductive layer 71, SnBi metal powder (particle diameter D _L = 25 to 35 μm, melting point T ₁ = 141 ° C.) as a low melting point material and silver powder (particle diameter D _H = 2 to 3 μm, melting point T ₂ = 971 ° C.) at a weight ratio of 20:80, and a printing paste containing an epoxy resin as a binder resin was used. The printed paste was screen printed using a # 230 mesh (opening width: l = 85 μm) screen plate having an opening width (L = 80 μm) corresponding to the collector electrode pattern, and dried at 90 ° C. .

  The wafer on which the first conductive layer 71 is formed is put into a CVD apparatus, and a silicon oxide layer (refractive index: 1.5) is formed as an insulating layer 9 with a thickness of 80 nm on the light incident surface side by the plasma CVD method. It was.

The film forming conditions of the insulating layer 9 were: substrate temperature: 135 ° C., pressure 133 Pa, SiH ₄ / CO ₂ flow rate ratio: 1/20, input power density: 0.05 W / cm ² (frequency 13.56 MHz). The refractive index (n) and extinction coefficient (k) of the insulating layer formed on the light incident surface side under these conditions were as shown in FIG. Thereafter, the wafer after forming the insulating layer was introduced into a hot-air circulating oven, and an annealing process was performed at 180 ° C. for 20 minutes in an air atmosphere.

The substrate 12 that has been subjected to the annealing step as described above was put into the plating tank 11 as shown in FIG. In the plating solution 16, copper sulfate pentahydrate, sulfuric acid, and sodium chloride were added to a solution prepared so as to have a concentration of 120 g / l, 150 g / l, and 70 mg / l, respectively. (Product: ESY-2B, ESY-H, ESY-1A) added were used. Using this plating solution, plating is performed under conditions of a temperature of 40 ° C. and a current of 3 A / dm ² , and copper is uniformly formed as the second conductive layer 72 with a thickness of about 10 μm on the insulating layer on the first conductive layer 71. Precipitated in Almost no copper was deposited in the region where the first conductive layer was not formed.

  Thereafter, the silicon wafer on the outer periphery of the cell was removed with a width of 0.5 mm by a laser processing machine, and the heterojunction solar cell of the present invention was produced.

(Examples 2 to 5)
A heterojunction solar cell was fabricated in the same manner as in Example 1 except that the concentration of the HF aqueous solution and the ozone solution was changed as shown in Table 1 in the washing step after the texture formation.

(Comparative Example 1)
An etching process using HF and ozone is not performed after texture formation, and only anisotropic etching is performed, and a silver paste that does not contain a low-melting-point material as a printing paste for forming the first conductive layer (that is, a metal material) The first conductive layer (silver electrode) 71 was formed in the same manner as in Example 1 except that the ratio of powder to silver powder was set to 0: 100. Thereafter, none of the insulating layer forming step, the annealing step, and the second metal layer forming step was performed, and a heterojunction solar cell using this silver electrode as a collecting electrode was fabricated. In Comparative Example 1, both r1 and r2 were less than 0.005 μm.

(Comparative Example 2)
In Example 1, after forming a 1st conductive layer and an insulating layer, formation of the 2nd conductive layer by the plating method was tried without implementing an annealing process. In Comparative Example 2, copper did not deposit on the first conductive layer, and the second conductive layer was not formed. In Comparative Example 2, both r1 and r2 were less than 0.005 μm, and as shown in FIG. 4, copper was partially deposited on the insulating layer in the first conductive layer non-formation region. .

(Comparative Example 3)
In Example 1, after forming the first conductive layer, the second conductive layer was formed by plating without performing the insulating layer forming step and the annealing step. In Comparative Example 3, although the second conductive layer was able to be formed, there was a problem that the transparent electrode layer was completely etched during the plating process, and a product that functions as a solar cell was not obtained.

  The production conditions and solar cell characteristics (open circuit voltage (Voc), short circuit current density (Jsc), fill factor (FF), and conversion efficiency (Eff)) of the heterojunction solar cells of the above Examples and Comparative Examples are shown in Table 1. Shown in

  From comparison between each Example and Comparative Example 1, the crystalline silicon solar cell of the present invention has improved conversion efficiency (Eff) compared to the conventional crystalline silicon solar cell having a collector electrode made of a silver paste electrode. ing. This is presumably because the resistance of the collector electrode was lowered and the fill factor (FF) was improved in the crystalline silicon solar cell of the example.

  Moreover, in each Example, the short circuit current (Jsc) is also improved as compared with Comparative Example 1. This is presumably because the reflectance at the outermost surface (air interface of the solar cell) was lowered because the insulating layer 9 having a low refractive index was provided on the transparent electrode layer 6a having a high refractive index. This can be estimated from the fact that in FIG. 12, the insulating layer (silicon oxide) has a refractive index lower than that of the transparent electrode layer (ITO) and hardly absorbs light in the wavelength range that the solar cell can use for photoelectric conversion. . Thus, when an insulating layer having transparency and an appropriate refractive index is formed, it is understood that a solar cell having high conversion characteristics can be obtained even if the insulating layer is not removed after the formation of the second conductive layer.

  In each example, the copper was deposited as the second conductive layer by the plating step because an opening was formed in the insulating layer on the first conductive layer formation region by the annealing treatment, and the first conductive layer was in contact with the plating solution ( This is because plating was performed using the opening as a starting point for deposition.

  On the other hand, in Comparative Example 2, in the first conductive layer non-forming region, as shown in FIG. 4, some copper was deposited on the insulating layer, whereas in the example, copper was formed on the insulating layer. No precipitation was observed. This is because in Comparative Example 2, the convex portion of the concavo-convex structure of the one-conductivity type single crystal silicon substrate is sharp, so that the coating of the insulating layer on the convex portion is not sufficient, and the insulating layer becomes thin and an opening is formed. It is thought that it was because of. On the other hand, the reason why the conversion efficiency (Eff) of the example is improved is to prevent the insulating layer from being thinned at the convex portion by setting the curvature radius r1 of the convex portion at the fine concavo-convex structure to 0.01 μm or more. This is considered to be because the formation of pinholes (undesired openings) could be prevented.

  In Example 3, the short circuit current (Jsc) was improved as compared with Example 5. This is because the increase in the substrate reflectance accompanying the flattening of the convex portion in the concavo-convex structure can be suppressed by setting the curvature radius r1 to 1 μm or less. From the above, it is more preferable to satisfy r1 ≦ 1 μm.

  When Examples 1 to 4 were compared, when the concentration of ozone was the same, r1 increased as the concentration of hydrofluoric acid was increased. Further, comparing Example 4 and Example 5, when the concentration of hydrofluoric acid was the same, r1 increased as the ozone concentration was increased. Therefore, it can be seen that an uneven structure having a desired r1 can be formed by adjusting the hydrofluoric acid concentration and the ozone concentration.

  In Examples 2 to 4 and Example 6, the conversion efficiency was improved as compared with Example 1 and Example 5. This is because defects in the silicon-based thin film and pinholes on the surface of the insulating layer can be further suppressed as r1 is increased in a small range, for example, Example 1 (0.06 μm) → Example 2 (0.1 μm). it is conceivable that. On the other hand, in the range where r1 is large, the conversion efficiency decreases as it increases from Example 4 (0.5 μm) to Example 5 (0.9 μm). This is presumably because the substrate reflectivity increased with the flattening of the protrusions in the concavo-convex structure as r1 increased. From the above, from the viewpoint of plating resistance and light confinement effect, it is considered that the hydrofluoric acid concentration and the ozone concentration in the etching treatment liquid are more preferably 1 to 5% by weight and 10 ppm to 20 ppm, respectively.

  As described above with reference to the examples, according to the present invention, the collector electrode of the crystalline silicon solar cell can be produced without patterning the insulating layer. A battery can be provided at low cost.

1. One conductivity type single crystal silicon substrate 1A. Substrate with uneven structure A 1B. 1. Substrate with uneven structure B 2. Intrinsic silicon-based thin film 5. Conductive silicon thin film Transparent electrode layer 70. Collector electrode 71. First conductive layer 711. Low melting point material 72. Second conductive layer 8. Back metal electrode 9. Insulating layer 9h. Opening 50. Photoelectric conversion unit 100. Solar cell 101. Heterojunction solar cell 10. Plating apparatus 11. Plating tank 12. Substrate 13. Anode 14. Substrate holder 15. Power supply 16. Plating solution

Claims (6)

A photoelectric conversion unit having a silicon-based thin film and a transparent electrode layer in this order on one main surface of a single conductivity type single crystal silicon substrate, and a first conductive layer and a second conductive layer on one main surface of the photoelectric conversion unit A method for producing a crystalline silicon-based solar cell comprising:
A photoelectric conversion unit preparation step of preparing the photoelectric conversion unit;
A first conductive layer forming step in which a first conductive layer is formed on the photoelectric conversion portion; and a plating step in which a second conductive layer is formed on the first conductive layer by a plating method, in this order,
Before the plating step, at least an insulating layer forming step in which an insulating layer is formed in the first conductive layer non-forming region on the photoelectric conversion portion,
Performed in the photoelectric conversion unit preparation step, the texture forming process of the concave convex structure A is formed by anisotropic etching on one main surface of the one conductivity type single crystal silicon substrate, the etching process of the concavo-convex structure A Etching process steps are performed in this order,
In the concavo-convex structure A, the curvature radius r1 of the convex part and the curvature radius r2 of the concave part are both less than 0.005 μm, and the curvature radius r1 of the convex part and the curvature radius r2 of the concave part are r2 < It meets r1, and the uneven structure B satisfying 0.01μm ≦ r1 ≦ 0.5μm is formed, the manufacturing method of the crystalline silicon solar cells. After pre-Symbol first conductive layer forming step, the insulating layer forming step is performed so that also formed an insulating layer on the first conductive layer,
In the plating process, through an opening provided in the insulating layer formed on the first conductive layer, the second conductive layer conducting with said first conductive layer is formed, according to claim 1 Of manufacturing a crystalline silicon solar cell. The first conductive layer includes a low-melting-point material having a heat flow start temperature T1 lower than a heat resistant temperature of the photoelectric conversion unit,
3. The crystalline silicon solar system according to claim 2 , wherein the opening is formed by performing a heat treatment at an annealing temperature Ta higher than a thermal flow start temperature T < b > 1 of the low melting point material after the insulating layer forming step. Battery manufacturing method. The first conductive layer includes a low-melting-point material having a heat flow start temperature T1 lower than a heat resistant temperature of the photoelectric conversion unit,
In the insulating layer forming step, the opening is formed simultaneously with the formation of the insulating layer by forming the insulating layer at a substrate temperature Tb higher than the thermal flow start temperature T1 of the low melting point material. Item 3. A method for producing a crystalline silicon solar cell according to Item 2 . The method for producing a crystalline silicon-based solar cell according to claim 3 or 4, wherein the low-melting-point material has a heat flow start temperature T1 of 250 ° C or lower. In the etching process, by performing an etching treatment with a mixed solution of hydrofluoric acid and ozone, prior Symbol uneven structure B is formed, the crystalline silicon solar cell according to any one of claims 1 to 5 Production method.