JP6110417B2 - Cache memory control device and control method - Google Patents

Description

  The present invention relates to a cache memory control device and a control method for controlling a cache memory provided between a CPU (Central Processing Unit) and a main memory. In particular, the present invention relates to a cache memory control device and a control method for controlling inter-core communication using a cache memory shared among a plurality of processor cores (hereinafter referred to as cores) provided in a CPU.

  Data processing using a cache memory is known. The cache memory is provided between an arithmetic device such as a CPU and the main memory, stores part of the data in the main memory, and exchanges data with the arithmetic device. This shortens the time for the arithmetic unit to access the main memory.

  Patent Documents 1 and 2 disclose systems using such a cache memory.

  Patent Document 1 discloses a cache memory system that can avoid useless memory access that occurs when an arithmetic device writes temporary data to a cache memory.

  The cache memory system disclosed in Patent Document 1 targets a write-back cache memory that exists between a CPU including a plurality of cores and a main memory. In spite of the fact that it is not necessary, it has a mechanism to reduce the memory access that is performed to maintain the consistency of the contents of the cache memory and the main memory.

  The outline of the cache memory system will be described below with reference to the description in Patent Document 1.

  FIG. 13 is a block diagram illustrating an example of the configuration of the cache memory system described in Patent Document 1. In FIG. Referring to FIG. 13, this cache memory system has a configuration in which a cache memory 2 is arranged between a CPU 1 including a plurality of processor cores 4_0, 4_1 to 4_N−1 and a main memory 3.

  FIG. 14 is a block diagram showing a configuration of the cache memory 2 in the cache memory system described in Patent Document 1.

  Referring to FIG. 14, the cache memory 2 has an address register 7, an address array 11, a data array 12, a comparator 16, and a cache control unit 19.

  The address register 7 stores the memory address of the access destination requested by the CPU 1. The memory address stored in the address register 7 is represented by upper m bits 8, middle n bits 9, and lower k bits 10.

  The address array 11 is a memory having an address entry, and is an array having the upper m bits 13 and the state 14 as elements. The address array 11 is used as an index of the block data 15 stored in block units in the data entry of the data array 12.

  The upper m bits 8 of the memory address stored in the address register 7 are referred to as in-address tag information, the middle n bits 9 are referred to as index information, and the lower k bits 10 are referred to as byte offset information. The upper m bits 13 of the address array 11 are referred to as in-cache tag information.

  The data array 12 is an array having a plurality of block data 15 composed of a plurality of words as elements.

  FIG. 15 is a diagram showing the contents of 14 status bits stored in the address array 11.

  The state 14 includes a block state storage unit 20 and a word state storage unit 21 that indicate the state of the block data 15 stored in the data array 12. FIG. 15 shows an example in which the CPU 1 has four cores and one block data 15 stored in the data array 12 is 8 words (32 bytes).

  The word state storage unit 21 has a word state W (i) for storing word state information for specifying a word in which data from the CPU 1 is written for each word constituting the block data 15. Here, it has word states W (1) to W (8) corresponding to 8 words. Each word state W (i) has a bit corresponding to each core included in the CPU 1. Here, the word state W (i) is composed of 4 bits corresponding to the four cores.

  The word state W (i) indicates the following state of the word according to the contents. In the following description, the word state W (i) is simply referred to as W (i).

  When W (i) ≠ 0000, it indicates that data has been written from any of the cores to the i-th word, and valid data is stored in the i-th word of the block data.

  When W (i) = 0000, it indicates that no data is written in any i-th word from any core.

  Also, in W (i) where data is written from the core, the bit value at the position corresponding to the core where the writing was performed is set to 0, and the bit value at the position corresponding to the other core is set to 1. The 0 position in the 4 bits of W (i) indicates the core that performed the writing.

  The block state storage unit 20 stores BV (Block Validity) indicating whether or not the data read from the main memory 3 is stored in a word not written from the CPU 1 in the block.

  BV = 1 indicates that the entire block is valid. In this case, even if W (i) = 0000, the data read from the main memory 3 is stored in the i-th word, indicating that valid data is stored in the word.

  When BV = 0, it indicates that only the word of W (i) ≠ 0000 is valid and the word of W (i) = 0000 is invalid.

  The basic operation of the cache memory system will be described with reference to FIGS.

  When an access request to the storage device is issued from the CPU 1, the access destination memory address is stored in the address register 7 of the cache memory 2.

  The address array 11 is searched using the middle n bits 9 of the address register 7 as an index address, and the corresponding entry is obtained. In the corresponding entry, the upper m bits 13 (in-cache tag information) and the above-mentioned status 14 are stored.

  The upper m bits 13 (in-cache tag information) of the entry acquired from the address array 11 and the upper m bits 8 (in-address tag information) stored in the address register 7 are provided to the comparator 16.

  If the comparison result of the upper m bits 13 (in-cache tag information) and the upper m bits 8 (in-address tag information) by the comparator 16 match, the target data is stored in the data array 12 corresponding to the entry. (Cache hit). On the other hand, if the comparison results do not match, the target data does not exist in the cache memory 2 (cache miss), and the main memory 3 is accessed.

  The cache control unit 19 inputs the result of comparison by the comparator 16, the status 14, the core number 17, the instruction 18, etc., and controls the cache memory 2 as follows according to the content of the instruction type and the status 14. Do. Further, the cache control unit 19 receives the lower k bits 10 of the address register 7 as byte offset information for specifying the word position in the block data 15.

  The instruction 18 includes a store instruction (store), a load instruction (load), and a load and invalidate instruction (load and invalidate). The store instruction is also called a write instruction (write), and the load instruction is also called a read instruction (read).

  The operation in the case of a store instruction (store) is as follows.

  In the case of a cache hit, the cache control unit 19 specifies a word to be written in the block data 15 corresponding to the entry based on the byte offset information, and writes the write data in the word. Subsequently, information indicating the core in which the data has been written is set in W (i) corresponding to the word in which the data has been written. For example, when core 0 writes data in the first word, W (1) = 0111 is set.

  In the case of a cache miss, the cache control unit 19 allocates a new block to the data array 12 as a write block. At this time, the cache control unit 19 determines whether or not valid data remains in the allocated block based on the information set in W (i) and BV of the allocated block.

  If all the word states of the allocated block are W (i) = 0000, it means that no data has been written to the block from any core. In this case, the allocated block is used as it is without writing back to the main memory 3.

  If all the word states of the allocated block are W (i) ≠ 0000 or BV = 1, the entire block is rewritten or the entire block is valid. In this case, the data of the block is written back to the main memory 3.

  When the word state of a part of the allocated block is W (i) ≠ 0000 and BV = 0, only the word where W (i) ≠ 0000 is rewritten. In this case, only the data of the word of W (i) ≠ 0000 is written back to the main memory 3.

  Subsequently, the upper m bits 8 of the address register are set in the upper m bits 13 of the entry of the address array 11 corresponding to the newly allocated block. Then, the state 14 is cleared to zero and initialized.

  Next, the cache control unit 19 specifies a word to be written based on the byte offset information, and writes data to be written. Thereafter, information indicating the core that has written the data is set in W (i) corresponding to the word in which the data has been written. For example, when core 0 writes data in the first word, W (1) = 0111 is set.

  The operation in the case of a load instruction (load) is as follows.

  In the case of a cache hit, when the word state corresponding to the memory address indicated by the load instruction is W (i) ≠ 0000 or BV = 1, the cache control unit 19 in the data array 12 specified from the memory address Read data from the word.

  In the case of a cache hit, when the word state corresponding to the memory address indicated by the load instruction is W (i) = 0000 and BV = 0, the cache control unit 19 reads data from the main memory 3. Thereafter, the read data is written only in the word of W (i) = 0000 in the block data of the entry of the data array 12. Then, BV = 1 is set. Subsequently, the cache control unit 19 reads the accessed word from the data array 12.

  In the case of a cache miss, the cache control unit 19 allocates a new block. When valid data is contained in the allocated block, that is, when W (i) ≠ 0000 or BV = 1, the data of the target block is written back to the main memory 3.

  Subsequently, the upper m bits 8 of the address register are set in the upper m bits 13 of the entry of the address array 11 corresponding to the newly allocated block. Then, the state 14 is cleared to zero and initialized.

  Next, the cache control unit 19 reads data in the block corresponding to the memory address indicated by the load instruction from the main memory 3.

  The cache control unit 19 writes the data of the block read from the main memory 3 to the word of W (i) = 0000 in which no data is written in the block of the data array 12. Since the word state storage unit 21 has been initialized, the entire data in the block is written.

  Subsequently, the cache control unit 19 sets BV = 1 indicating that the data read from the main memory 3 is stored in a word not written from the CPU 1 in the block. Then, the cache control unit 19 reads the accessed word from the data array 12.

  The operation in the case of a load and invalidate instruction (load and invalidate) is as follows.

  In the case of a cache hit, when the word state corresponding to the memory address indicated in the load and invalidate instruction is W (i) ≠ 0000 or BV = 1, the cache control unit 19 uses the data specified from the memory address. Read data from words in array 12.

  Of the W (i) corresponding to the read word, if the bit corresponding to the core that executed the load and invalidate instruction is 1, the bit corresponding to the core that executed the load and invalidate instruction is set to 0. . Also, BV = 0 is set.

  In the case of a cache hit, when the word state corresponding to the memory address indicated in the load and invalidate instruction is W (i) = 0000 and BV = 0, the cache control unit 19 reads data from the main memory 3. Thereafter, the read data is written only in the word of W (i) = 0000 in the block data of the entry of the data array 12. Then, BV = 1 is set. This operation is the same as that in the case of a load instruction.

  The operation for a cache miss is the same as that for a load instruction.

  Patent Document 1 describes an example of communication between cores using core 0, core 1, core 2, and core 3 using the cache memory 2 using the above-described operation.

  First, the core 0 issues a store instruction to write a message to the cache memory 2. When the store instruction is completed, the word state corresponding to the corresponding word in the cache memory 2 is set to W (i) = 0111.

  Since core 1 receives the message from core 0, it issues a load and invalidate instruction. When the load and invalidate instruction is completed, the word state corresponding to the corresponding word in the cache memory 2 is set to W (i) = 0011.

  Since core 2 receives the message from core 0, it issues a load and invalidate instruction. When the load and invalidate instruction is completed, the word state corresponding to the corresponding word in the cache memory 2 is set to W (i) = 0001.

  Since core 3 receives the message from core 0, it issues a load and invalidate instruction. When the load and invalidate instruction is completed, the word state corresponding to the corresponding word in the cache memory 2 is set to W (i) = 0000.

  As described above, communication using only the cache is realized from the core 0 to the core 1, the core 2, and the core 3.

  However, such inter-core communication described in Patent Document 1 has the following problems.

  When a plurality of independent applications allocate a core and execute a program, each application cannot know which application is performing inter-core communication using a cache memory. Therefore, while an application of a certain core is performing inter-core communication using the cache memory, another core may write to the cache memory portion used for the inter-core communication. Can happen. In such a case, the communication data stored in the cache memory may be written back to the main memory. If access to the main memory, which has a slower access speed than the cache memory, occurs, the communication speed between the cores decreases.

  Patent Document 2 solves such a decrease in communication speed between cores by introducing an exclusive control device that prohibits access to a cache line (corresponding to block data in Patent Document 1) used in inter-core communication. The technology to do is disclosed.

JP 2009-157608 JP International Publication No. 2011/065492

  The exclusive control device described in Patent Document 2 which attempts to solve the decrease in the inter-core communication speed has a problem that it may not be able to cope with depending on the configuration and operation method of the multi-core processor.

  The exclusive control device described in Patent Literature 2 performs exclusive control by converting a logical address into a physical page number and managing a process ID (Identification) and a physical page number in a cache prohibition table. In this case, the user process operating independently on each core is given a unique process ID on the multi-core processor, and the logical address and the physical memory address need to be associated one-to-one. Further, in order to share the cache prohibition table among all the cores, the physical page size needs to be unified.

  In recent years, a multi-core processor may be operated in a form in which a plurality of OSs are mounted for each core, or in a form in which an OS-less application that operates based on a complete physical memory address base and an OS are operated on one processor. In such an operation, it is difficult to assign a unique process ID on the processor, and there may be a situation where the recognition of the logical address space is not unified. In such an operation method, there is a possibility that the physical page size is different between processes operating on each core.

  For the reasons described above, the exclusive control device described in Patent Document 2 may not achieve the purpose of solving the decrease in inter-core communication speed depending on the configuration and operation method of the multi-core processor.

  The present invention provides a cache memory control device and a control method for performing exclusive control by managing cache lines and word states used in inter-core communication based on physical memory addresses and solving a decrease in inter-core communication speed. The purpose is to provide.

  In order to achieve the above object, a cache memory control device according to one aspect of the present invention includes a physical memory address that is decomposed into elements that uniquely specify a cache memory area used in inter-core communication of a multi-core processor, and the physical memory address. Inter-core communication area information registration unit for registering inter-core communication area information consisting of word state storage information indicating the use state of inter-core communication in the cache memory area, and specifying the memory access destination before accessing the cache memory A decomposed element information generating means for generating decomposed element information by decomposing the input physical memory address into the elements, and comparing the decomposed element information with the inter-core communication area information; When access to the cache memory is permitted, the cache memory area used in the inter-core communication is referred to It is, and, upon obtaining a comparison result of the condition that a cache miss is determined, characterized in that it comprises a, an access exclusive control unit for notifying the access to the cache memory is determined not permitted.

  In addition, a cache memory control method according to another aspect of the present invention provides a physical memory address that is decomposed into elements that uniquely specify a cache memory area used in inter-core communication of a multi-core processor and a core between the cache memory areas. The inter-core communication area information consisting of word state storage information indicating the use state in communication is registered, the physical memory address for specifying the memory access destination is input before accessing the cache memory, and the input physical memory When the address is decomposed into the elements to generate decomposed element information, the decomposed element information is compared with the inter-core communication area information, and access to the cache memory is permitted, the inter-core communication is used. The cache memory area is referred to, and the cache memory area is referred to when a comparison result of conditions for determining a cache miss is obtained. Access to Shumemori and notifies determines disallowed.

  According to the present invention, exclusive control is performed by managing cache lines and word states used in inter-core communication based on physical memory addresses, and it is possible to solve a decrease in inter-core communication speed.

It is a block diagram which shows the structure of 1st Embodiment of the cache memory control apparatus of this invention. It is a flowchart which shows operation | movement of 1st Embodiment of the cache memory control method of this invention. It is a block diagram which shows the structure of 2nd Embodiment of the cache memory control apparatus of this invention. It is a figure which shows the format of the communication area information between cores which manages the cache memory area | region used by the communication between cores. It is a figure which shows the example of determination of the replacement | exchange presence or absence of a cache line. It is a flowchart which shows operation | movement of the communication area management part between cores of the cache memory control apparatus of 2nd Embodiment. It is a flowchart which shows operation | movement of the access exclusive control part of the cache memory control apparatus of 2nd Embodiment. It is a flowchart which shows the operation example of the transmission process of the communication between cores using the cache memory control apparatus of 2nd Embodiment. It is a flowchart which shows the operation example of the reception process of the communication between cores using the cache memory control apparatus of 2nd Embodiment. It is a block diagram which shows the structure of the cache memory control apparatus of the modification of 2nd Embodiment. It is a flowchart which shows operation | movement of the communication area management part between cores of the cache memory control apparatus of the modification of 2nd Embodiment. It is a flowchart which shows operation | movement of the access exclusive control part of the cache memory control apparatus of the modification of 2nd Embodiment. 1 is a block diagram illustrating an example of a configuration of a cache memory system described in Patent Literature 1. FIG. 2 is a block diagram illustrating a configuration of a cache memory in a cache memory system described in Patent Document 1. FIG. It is a figure which shows the status bit in the cache memory system described in patent document 1. FIG.

(Overview)
The form for implementing the cache memory control device and the control method of the present invention is based on the assumption that the cache memory system disclosed in Patent Document 1 is operated by the direct map method. Therefore, the configuration and general operation of the cache memory system described in the background art with reference to FIGS. 13 to 15 are also applied to the embodiment of the present invention.

  Embodiments of the present invention manage cache lines and word states used in inter-core communication based on physical memory addresses, perform exclusive control before accessing cache memory, and perform inter-core communication in a cache memory system. This is to prevent a decrease in speed.

  The decrease in the speed of inter-core communication in the cache memory system results from a write-back process that occurs when a cache line used in inter-core communication is replaced by another process. The exclusive control for suppressing the write-back process can be realized by specifying a cache entry used in inter-core communication and limiting access to that portion.

In the embodiment of the present invention, exclusive control focusing on cache line replacement conditions in a cache memory system is performed. Specifically, exclusive control is performed in consideration of the following technical features.
(1) The event that a cache line used in inter-core communication is replaced by another process is due to a cache allocation process performed at the time of a cache miss.
(2) The memory access is permitted only when it can be ensured that the cache line is not replaced by the memory access. On the other hand, when it is not possible to guarantee that the replacement of the cache line does not occur, the event that the cache line is replaced can be prevented by suppressing the memory access.
(3) There are various allocation methods for cache allocation that occurs at the time of a cache miss, but in the direct-mapped cache operation, the cache entry that is replaced at the time of a cache miss is uniquely determined from the physical memory address. Therefore, it is possible to verify the possibility of cache replacement by examining the access destination memory address.
(4) To determine whether or not the communication is in use between cores, the cache line and the word position used in the communication between cores are specified, and the word state W (i) of the word state storage unit being used in the cache line is monitored. It can be judged by doing. W (i) in use in inter-core communication always has a value of 1 or more, and W (i) becomes 0 when inter-core communication is completed.

  EMBODIMENT OF THE INVENTION Below, the form for implementing this invention is demonstrated with reference to drawings.

The embodiments are examples, and the disclosed apparatus and system are not limited to the configurations of the following embodiments.
(First embodiment)
FIG. 1 is a block diagram showing the configuration of the first embodiment of the cache memory control device of the present invention.

  The cache memory control device 100 according to the first embodiment includes an inter-core communication area information registration unit 110, a disassembly element information generation unit 120, and an access exclusion control unit 130.

  The inter-core communication area information registration unit 110 registers inter-core communication area information including a physical memory address indicating a cache memory area used for inter-core communication of the multi-core processor and word state storage information. The physical memory address is decomposed and registered into elements that uniquely specify a cache memory area used for inter-core communication of the multi-core processor. The word state storage information is information indicating the use state of the cache memory area in the inter-core communication.

  The disassembly element information generation means 120 inputs a physical memory address specifying a memory access destination before accessing a cache memory (not shown), disassembles the input physical memory address into the above elements, and disassembles the element. Generate information.

  The access exclusion control unit 130 compares the generated disassembly element information with the registered inter-core communication area information. When access to the cache memory is permitted, the cache memory area used for inter-core communication is referenced, and the cache memory is accessed when the comparison result of the condition for determining the cache miss is obtained. Is determined to be disapproved and notified.

  FIG. 2 is a flowchart showing the operation of the first embodiment of the cache memory control method of the present invention.

  First, inter-core communication area information including a physical memory address for specifying a cache memory area used for inter-core communication of a multi-core processor and word state storage information is registered (S101). The physical memory address is decomposed and registered into elements that uniquely specify a cache memory area used for inter-core communication of the multi-core processor. The word state storage information is information indicating the use state of the cache memory area in the inter-core communication.

  Before accessing the cache memory, a physical memory address for specifying a memory access destination is input, and the input physical memory address is decomposed into the above elements to generate decomposed element information (S102).

  The disassembly element information is compared with the inter-core communication area information (S103).

  When access to the cache memory is permitted, the cache memory area used for inter-core communication is referenced, and access to the cache memory is disabled when the comparison result of the condition for determining the cache miss is obtained. It determines with permission and notifies (S104).

  As described above, in the present embodiment, an area where inter-core communication is performed in the cache memory is registered and managed as inter-core communication area information. This inter-core communication area information is a word that is a physical memory address that is decomposed into elements that uniquely identify a cache memory area used in inter-core communication and information indicating the use state of the cache memory area in inter-core communication. Consists of state storage information.

  Therefore, before the cache memory is accessed, a physical memory address for specifying a memory access destination by the access is input, and the physical memory address is decoded to generate decomposition element information. The disassembly element information includes information of the same element as the physical memory address included in the inter-core communication area information. Therefore, by comparing the disassembly element information with the inter-core communication area information, it is possible to evaluate the influence on the cache memory area used for the inter-core communication by the access.

  Therefore, when the access is permitted, the cache memory area used in the inter-core communication is referred to, and when the comparison result of the condition for determining the cache miss is obtained, it is determined that the access is not permitted. To notify.

In this embodiment configured as described above, exclusive control is performed by managing the cache line and the word state used in inter-core communication based on the physical memory address, and the memory access accompanied by the event that the cache line is replaced Can be deterred in advance.
(Second Embodiment)
The second embodiment will be described with reference to FIGS.

  FIG. 3 is a block diagram showing the configuration of the second embodiment of the cache memory control apparatus of the present invention.

  The cache memory control device 200 according to the second embodiment functions between the CPU 1 and the cache memory 2 of the cache memory system described with reference to FIG.

  That is, whenever the application of each core of the CPU 1 accesses the memory, the CPU always accesses the cache memory control device 200 to determine whether or not the memory access is possible. The application accesses the cache memory 2 and performs normal memory access only when it is notified that memory access is possible. On the other hand, when notified that the memory access is not possible, the application executes an alternative process such as retrying the memory access or accessing another area where the access does not conflict.

  Note that the cache memory control device 200 may be implemented as hardware (HW) or software (SW). When the cache memory control device 200 is mounted by HW, it may be configured as any internal element of the CPU 1 or the cache memory 2 as long as it functions between the CPU 1 and the cache memory 2. When implemented as a SW such as a library, it is configured as a program executed by the CPU 1.

  As shown in FIG. 3, the cache memory control device 200 includes an inter-core communication area management unit 210 and an access exclusive control unit 220.

  The inter-core communication area management unit 210 includes an inter-core communication area information registration unit 211, an address resolution information generation unit 212, and a comparison determination unit 213.

  The inter-core communication area information registration unit 211 corresponds to the inter-core communication area information registration unit 110 in the first embodiment. In the inter-core communication area information registration unit 211, inter-core communication area information related to the cache memory area used for inter-core communication in the cache memory 2 is registered as a list for each inter-core communication currently being executed.

  The inter-core communication area information includes a physical memory address that identifies a cache memory area used in inter-core communication and word state storage information that indicates a use state of the cache memory area in inter-core communication. This physical memory address is divided and registered into elements that uniquely specify the cache memory area. Specifically, it is decomposed into each element of a tag, an index, and a byte offset. Details of the inter-core communication area information will be described later with reference to FIG.

  The inter-core communication area information is generated based on the inter-core communication area information registration request input from the application of each core at the start of the inter-core communication, updated during the inter-core communication, and deleted at the end of the inter-core communication. The The generation, update, and deletion of the inter-core communication area information is executed by the inter-core communication area management unit 210 according to an instruction from the access exclusive control unit 220.

  The address resolution information generation unit 212 generates address resolution information by decoding an access destination physical memory address input from an application of each core. The address decomposition information generation unit 212 corresponds to the decomposition element information generation unit 120 in the first embodiment, and the address decomposition information corresponds to the decomposition element information in the first embodiment.

  Then, the comparison / determination unit 213 performs primary comparison control by comparing the address decomposition information generated by the address decomposition information generation unit 212 with the index of the inter-core communication area information. In the primary comparison, an entry of inter-core communication area information registered in the inter-core communication area information registration unit 211 is searched to determine whether or not the memory access destination of the application is entered in the cache memory 2 It is to be. The search key used at this time is an index.

  It should be noted that instruction information indicating the type of memory access instruction and core information for specifying the core are also input from the application of each core and used in the processing described later. Further, at the start of inter-core communication, an inter-core communication area information registration request is input from the application.

  Since the actual access exclusive control is executed by the access exclusive control unit 220 as will be described later, input information (command information, core information, inter-core communication area information registration request) other than the physical memory address is used as the access exclusive control unit 220. You may comprise so that it may notify directly. Here, all information input from the application is received by the inter-core communication area management unit 210, and necessary information is notified from the inter-core communication area management unit 210 to the access exclusive control unit 220. To do.

  The inter-core communication area management unit 210 passes the comparison determination result of the primary comparison between the address resolution information and the inter-core communication area information, instruction information input from the application, core information, and the like to the access exclusive control unit 220.

  The access exclusive control unit 220 includes a comparison determination control unit 221 and executes the comparison determination result of the primary comparison and the control of the secondary comparison and the tertiary comparison described later to determine whether or not the memory access that the application intends to perform is performed. The result of the determination is notified to the application.

  If the comparison / determination control unit 221 needs to register (generate), update, or delete inter-core communication area information as a result of the control, the inter-core communication area management unit 210 is notified. In response to the notification, the inter-core communication area management unit 210 changes the contents of the inter-core communication area information registration unit 211.

  The comparison determination unit 213 and the comparison determination control unit 221 correspond to the access exclusive control unit 130 in the first embodiment.

  Here, the principle of exclusive memory access control in this embodiment will be described.

  The memory access exclusion control in this embodiment is realized by verifying two events. First, it is verified whether or not the cache memory area (cache line and word) to be accessed by the application is being used for inter-core communication. Second, it is verified whether or not the cache line used in the inter-core communication is not replaced by a memory access unrelated to the inter-core communication.

  In order to verify whether or not the cache line and the word are being used for inter-core communication, attention is paid to the following three types of information.

  Information 1: Cache line and word position used in communication between cores, Information 2: Value of word state W (i) indicating the state of word used in communication between cores, and Information 3: At cache miss The cache line and word position to be replaced.

  As for the information 1 and information 2 described above, it can be known that the information is being used by recording cache line information used for inter-core communication at the start of inter-core communication. In addition, the end of inter-core communication can be determined by referring to the word state on the cache line.

  That is, in order to satisfy the conditions of the above information 1 and information 2, it includes inter-core communication area information that is recording information for determining that inter-core communication is being performed. As described above, this inter-core communication area information is provided in the inter-core communication area management unit 210. That is, the inter-core communication area management unit 210 manages cache memory area information used for inter-core communication in the cache memory 2.

  FIG. 4 is a diagram showing a format of inter-core communication area information for managing a cache memory area used for inter-core communication.

  The inter-core communication area information has a format including information for specifying a cache line and a word position used in inter-core communication, and word state storage information indicating a use state of a word used in inter-core communication. Yes. The word state storage information is a field for storing the value of the word state W (i) described above.

  As information for specifying a cache line and a word position used in inter-core communication, a physical memory address is decomposed into elements of a tag, an index, and a byte offset. That is, the physical memory address is decomposed into elements of a tag, an index, and a byte offset, and the cache line and word position on the cache memory 2 are uniquely specified from the information of each element. For example, the index corresponds to information for searching for an entry in the address array 11 in FIG. 14, and the tag corresponds to the upper m bits 13 (in-cache tag information) input to the comparator 16 to indicate cache hit or cache miss. A comparative judgment is possible. The byte offset is information for specifying a word in the cache line.

  The word state W (i) of the word state storage information indicates the use state of the word by the value of the word state W (i) when the word of the cache line specified by the physical memory address is used for inter-core communication. It is shown. As for the value of the word state W (i), the bit corresponding to the transmission core is set to 0 at the time of transmission in inter-core communication, the bit corresponding to the reception core is set to 1, and the bit corresponding to the reception core is set to 0 at the time of reception. The Accordingly, when the reception by all the receiving cores is completed, the value of the word state W (i) becomes 0 in all bits.

  On the other hand, the information 3 can be obtained by decoding a physical memory address that is an access destination of an application operating in each core.

  Similar to the physical memory address of the inter-core communication area information, the physical memory address input from the application is address decomposition information that is decomposed into elements of a tag, an index, and a byte offset. From these elements of the address resolution information, the cache line and word position in the cache memory 2 are uniquely determined.

  In addition, whether or not the cache line used for inter-core communication is replaced by memory access unrelated to inter-core communication is determined by checking the inter-core communication area information and the physical memory address that is the access destination input from the application It is done by comparing.

  That is, by comparing the inter-core communication area information with the address resolution information of the input physical memory address, it is possible to determine in advance a cache hit / cache miss when the cache memory is accessed.

  FIG. 5 is a diagram illustrating an example of determining whether or not a cache line is replaced.

  That is, the result of comparing the inter-core communication area information and each tag, index, and byte offset of the input physical memory address and the determination of whether or not there is a cache line replacement at that time are as follows. An example is shown. For each element, a match is indicated as “◯”, and a mismatch is indicated as “x”.

  Referring to FIG. 5, the indexes of case 1, case 2, case 5, and case 6 do not match. This means that the physical memory address input from the application refers to a cache line different from the cache line used for inter-core communication. Therefore, in these cases, it can be determined that the cache line used in inter-core communication is not replaced.

  In case 7 and case 8, the index and tag match. Therefore, the cache hit is determined by the physical memory address input from the application corresponding to the cache line used in the inter-core communication. Therefore, it is possible to determine that the cache line is not replaced by processing such as a store instruction (store) and a read instruction (read) being performed on the data block on the cache line used in the inter-core communication.

  In case 3 and case 4, the indexes match and the tags do not match. Therefore, a cache miss is confirmed. Moreover, since the indexes match, it can be determined that if this memory access to the cache memory 2 is allowed, the cache line used in the inter-core communication is replaced.

  As described above, each tag, index, and byte offset of the inter-core communication area information and the input physical memory address are compared. Based on the comparison result, it is determined whether or not the cache line and the word used in the inter-core communication are overwritten when a cache miss occurs. In the example described with reference to FIG. 5, the cache lines and words used in inter-core communication may not be replaced except in cases 3 and 4 where the indexes match and the tags do not match. Guaranteed.

  Returning to FIG. 3, the description of the cache memory control device 100 of this embodiment will be continued.

  The inter-core communication area management unit 210 receives an input of a physical memory address of a memory access destination and other processing related information from an application of each core.

  The physical memory address is realized by an OS (Operating System) system call running on hardware or each core when the application is operating on a logical address basis. For example, when an OS system call is used, a physical memory address can be obtained from a logical address of a process operating on the OS using a virt_to_phys function or the like. For applications that operate on a physical memory address basis, it is not necessary to calculate the physical memory address from the logical address.

  As other processing-related information, as described above, there are command information indicating the type of memory access command, core information for specifying a core, and an inter-core communication area information registration request at the start of inter-core communication.

  As described above, the inter-core communication area management unit 210 registers and manages the inter-core communication area information as a list in the inter-core communication area information registration unit 211 as information for managing the inter-core communication area in the cache memory 2. Yes. As described with reference to FIG. 4, the inter-core communication area information includes the tag, index, byte offset information generated from the physical memory address, and the word status indicating the status of the word used in the inter-core communication. Contains the value of the word state W (i) of the stored information.

  The inter-core communication area management unit 210 decodes the physical memory address input from the application by the address resolution information generation unit 212, and acquires address resolution information decomposed into each element of a tag, an index, and a byte offset.

  In the inter-core communication area management unit 210, the comparison determination unit 213 determines the primary comparison for comparing indexes for each entry in the list of the inter-core communication area information registration unit 211. That is, the comparison / determination unit 213 searches the list of the inter-core communication area information registration unit 211 to determine whether there is an entry that matches the index obtained by decoding the input physical memory address.

  The comparison determination unit 213 notifies the access exclusive control unit 220 of the primary comparison result.

  When there is an entry with matching index, the fact that there is a matching entry, registration information of the entry, address resolution information of the input physical memory address, and other processing related information are notified as a primary comparison result. Note that the registration information of the entry is inter-core communication area information, and is information related to the cache memory area used for inter-core communication.

  If there is no entry with the matching index, the primary comparison result is notified that there is no matching entry, and the address resolution information of the input physical memory address and other processing related information. Note that the same primary comparison result is also notified to the access exclusive control unit 220 when no inter-core communication is performed and no registration entry exists in the inter-core communication area information registration unit 211.

  The access exclusion control unit 220 determines access permission and determines whether to add, update, or delete the list of inter-core communication area information based on various information of the primary comparison result notified from the inter-core communication area management unit 210. Execute exclusive control. In the access exclusion control unit 220, the comparison determination control unit 221 executes these access exclusion controls.

  First, when information indicating that an entry matching the index obtained by decoding the input physical memory address does not exist in the list of the inter-core communication area information registration unit 211 is received from the inter-core communication area management unit 210 The process will be described.

  This means that the cache line to be accessed by the application is different from the cache line currently used for inter-core communication. Therefore, the comparison determination control unit 221 determines that the area for inter-core communication is not evicted from the cache, and determines that it is accessible. This corresponds to Case 1, Case 2, Case 5, and Case 6 described with reference to FIG.

  At this time, if the access exclusion control unit 220 has received the inter-core communication area information registration request, the comparison determination control unit 221 determines that a new inter-core communication has occurred and adds a list of inter-core communication area information. Do. In this case, the access instruction is a store instruction (store).

  The comparison determination control unit 221 instructs the inter-core communication area management unit 210 to add the tag, index, and byte offset of the address resolution information of the physical memory address to the list of inter-core communication area information. Also, based on the core information, the bit corresponding to the core that requested the registration is set to 0, and the bits corresponding to other cores are set to 1 based on the core information. Instruct to do so.

  In the inter-core communication area management unit 210, the comparison / determination unit 213 receives these instructions, and adds the inter-core communication area information having the instructed contents to the inter-core communication area information registration unit 211 as a new entry.

  Next, when information indicating that an entry matching the index obtained by decoding the input physical memory address exists in the list of the inter-core communication area information registration unit 211 is received from the inter-core communication area management unit 210 Processing will be described.

  In this case, the comparison determination control unit 221 receives the primary comparison result and executes secondary comparison control.

  As a comparison of the secondary comparison, the comparison determination control unit 221 compares the address resolution information tag of the input physical memory address with the tag included in the registration information of the entry, and determines a match / mismatch between the two tags.

  As a result of the secondary comparison, if both tags match, a cache hit is determined. Therefore, even if the application accesses the area, it is determined that the area for inter-core communication is not evicted from the cache, and the access exclusive control unit 120 determines that access is possible. This corresponds to Case 7 and Case 8 described with reference to FIG.

  At this time, when the instruction information received from the inter-core communication area management unit 210 is a load and invalidate instruction (load and invalidate), the comparison determination control unit 221 further performs control of the third comparison for comparing byte offsets. Run. By this tertiary comparison, match / mismatch up to the word position to be accessed is determined.

  If the byte offsets match as a result of the third comparison, it is possible to determine that the memory access is a reception process for inter-core communication by the application. Therefore, the comparison determination control unit 221 instructs the inter-core communication area management unit 210 to update the information in the word state storage unit included in the entry registration information. At this time, as for the value of the word state W (i) of the word state storage unit information included in the registration information of the entry, the bit corresponding to the core is set to 0 based on the core information. When the value of the updated word state W (i) is all 0, the inter-core communication area management unit 210 is instructed to delete the entry from the list.

  In the inter-core communication area management unit 210, the comparison determination unit 213 receives these instructions, and updates or deletes the registration information of the corresponding entry in the inter-core communication area information registration unit 211.

  If the byte offset does not match as a result of the third comparison, nothing is done.

  As a result of the secondary comparison, if the tag of the address that the application is trying to access does not match the tag in the entry in the inter-core communication area information list, a cache miss is determined. In this case, when a memory access is performed, replacement of a cache line due to a cache miss occurs. For this reason, since this event causes a decrease in the speed of inter-core communication, the comparison determination control unit 221 determines that access is impossible. This corresponds to Case 3 and Case 4 described with reference to FIG.

  The access exclusion control unit 220 notifies the application of the above-described determination of whether access is possible or not. This notification may be notified directly to the application from the access exclusion control unit 220 or may be notified via the inter-core communication area management unit 210.

  The operation of the inter-core communication area management unit 210 having the above-described function and the operation of the access exclusive control unit 220 are shown in FIGS. 6 and 7, respectively.

  FIG. 6 is a flowchart showing the operation of the inter-core communication area management unit 210 of the cache memory control device 200 of this embodiment. FIG. 7 is a flowchart showing the operation of the exclusive access control unit 220 of the cache memory control device 200 of this embodiment.

  Referring to FIG. 6, the inter-core communication area management unit 210 receives the physical memory address of the memory access destination and other processing related information from the application, and decodes the physical memory address (S201). By decoding the physical memory address, address decomposition information decomposed into each element of tag, index, and byte offset can be obtained. As described above, the other processing related information includes command information and core information, and an inter-core communication area information registration request at the start of inter-core communication.

  The inter-core communication area management unit 210 acquires one entry of the inter-core communication area information registered and managed as a list in the inter-core communication area information registration unit 211 (S202). The entry acquired here is an untested entry that has not yet been subjected to the primary comparison.

  At this time, if the inter-core communication is not performed at all and the entry to be acquired is not registered in the inter-core communication area information registration unit 211, the determination in step S203 determines that there is no acquired entry, and the process of step S205 is performed. move on.

  The inter-core communication area management unit 210 notifies the access exclusion control unit 220 of the absence of entry as a primary comparison result as a process when there is no registered entry in the inter-core communication area information registration unit 211 (S205). At this time, the address resolution information of the input physical memory address and other processing related information are also notified to the access exclusion control unit 220 (S206).

  On the other hand, if one uninspected entry can be acquired from the inter-core communication area information registration unit 211 (Yes in S203), does the index included in the registration information of the entry match the index included in the address resolution information? It is determined whether or not (S204).

  If the index does not match in the determination in step S204, the process returns to step S202, and another uninspected entry is acquired from the inter-core communication area information registration unit 211, and the processes in steps S203 and S204 are performed. repeat.

  As a result of repeating the processes of steps S202, S203, and S204, when there are no unexamined entries that can be acquired from the inter-core communication area information registration unit 211 (S203, none), the process proceeds to step S205.

  The inter-core communication area management unit 210 notifies the access exclusion control unit 220 that there is no entry as a primary comparison result as a process when it is determined that there is no entry with the matching index in the inter-core communication area information registration unit 211. (S205). At this time, the address resolution information of the input physical memory address and other processing related information are also notified to the access exclusion control unit 220 (S206).

  If there is an entry with the matching index in the determination in step S204, the inter-core communication area management unit 210 notifies the access exclusion control unit 220 of the determination that there is an entry as the primary comparison result (S207). At this time, the registration information of the entry with the matching index, the address resolution information of the input physical memory address, and other processing related information are also notified to the access exclusive control unit 220 (S208).

  The above is the operation of the inter-core communication area management unit 210 of the present embodiment.

  Next, the operation of the access exclusive control unit 220 will be described.

  Referring to FIG. 7, the access exclusive control unit 220 first performs processing based on the entry presence / absence determination, which is the primary comparison result notified from the inter-core communication area management unit 210.

  That the entry with the matching index is not registered in the inter-core communication area information registration unit 211 means that the cache memory area that the application is trying to access is not currently used for inter-core communication. Therefore, if the determination in step S211 is no entry, the process in step S212 is executed, and it is determined that access is possible. The determination result is notified to the application.

  Subsequently, it is determined whether or not the access exclusive control unit 220 has received the inter-core communication area information registration request (S213).

  When the inter-core communication area information registration request has been received (S213, yes), a new inter-core communication has occurred, so the inter-core communication area information is used as management information for the cache memory area used by the inter-core communication. Needs to be added to the list. Therefore, the access exclusion control unit 220 instructs the inter-core communication area management unit 210 to additionally register an entry in the inter-core communication area information registration unit 211 (S214).

  Specifically, an instruction is given to add the tag, index, and byte offset of the address resolution information of the physical memory address as a new entry to the list. Then, based on the core information, the bit corresponding to the core that requested registration is set to 0, and the bits corresponding to other cores are set to 1 based on the core information. Instruct to do so. Although the processing flow is not shown, the inter-core communication area management unit 210 receives these instructions and adds the inter-core communication area information having the instructed contents to the inter-core communication area information registration unit 211 as a new entry.

  When it is confirmed in step S213 that an inter-core communication area information registration request has been received, a process for confirming that a store instruction (store) has been received as instruction information may be added. If the instruction information is not a store instruction (store) while receiving the inter-core communication area information registration request, illegal processing is performed.

  Next, when an entry with the matching index is registered in the inter-core communication area information registration unit 211 (Yes in S211), the address resolution information tag is compared with the tag included in the entry registration information. Tag match / mismatch is determined (S215). The process of step S215 is referred to as secondary comparison.

  If both tags match as a result of the secondary comparison (S215, match), a cache hit is determined. Also, if the result of the secondary comparison does not match the address resolution information tag and the tag included in the entry registration information (S215, mismatch), a cache miss is determined.

  If a cache miss with a mismatched tag is determined in step S215, a cache line replacement due to a cache miss occurs when a memory access is performed. For this reason, since this event causes a decrease in the speed of inter-core communication, it is determined that access is impossible (S216), and that is notified to the application.

  If a matching cache hit is confirmed in step S215, it is determined that the inter-core communication area is not evicted from the cache even if the application accesses the area. Therefore, it is determined that access is possible in step S217. The determination result is notified to the application.

  If it is determined that access is possible due to a cache hit, it is determined whether the access instruction type is a load and invalidate instruction (load and invalidate) (S218). If the instruction is a load and invalidate instruction (load and invalidate), it is determined that the process is a reception process for inter-core communication (S218, Yes), and a third-order comparison control for comparing byte offsets is further executed ( S219). By this tertiary comparison, match / mismatch up to the word position to be accessed is determined.

  As a result of the third comparison, if the byte offsets match, it can be determined that the memory access is a reception process of communication between the cores using the cache memory area by the application. Therefore, the access exclusion control unit 220 instructs the inter-core communication area management unit 210 to update the information in the word state storage unit included in the entry registration information.

  Specifically, the bit corresponding to the core based on the core information is set to 0 in the value of the word state W (i) of the word state storage unit information field included in the registration information of the entry. When the value of the updated word state W (i) is all 0, the inter-core communication area management unit 210 is instructed to delete the entry from the list.

  If the access instruction type is not a load and invalidate instruction (load and invalidate), or if the byte offset does not match in the third comparison, nothing is done and the application is notified that access is possible.

  The above is the operation of the exclusive access control unit 220 of this embodiment.

  Next, an operation example of inter-core communication by a multi-core processor having four cores using the cache memory control device described above will be described.

  First, an operation when data is transmitted from the core 0 to the cores 1, 2, and 3 will be described.

  FIG. 8 is a flowchart illustrating an operation example of transmission processing of inter-core communication using the cache memory control device 200 according to the second embodiment.

  When an application running on core 0 tries to send an inter-core communication message, it controls the physical memory address, core ID (Identification), store instruction (store), and inter-core communication area information registration request. Pass to device 200. (S221).

  In the cache memory control device 200, the physical memory address of the access destination passed from the application is decoded by the inter-core communication area management unit 210, and is decomposed into tag, index, and byte offset information to obtain address decomposition information (S222). ).

  Next, the inter-core communication area management unit 210 searches the list of the inter-core communication area information registration unit 211 for an entry with the matching index, and as a result, detects that no entry with the matching index is registered (S223). ).

  As a result of the search, when it is detected that the entry with the matching index is not registered, the inter-core communication area management unit 210 notifies the access exclusion control unit 220 to that effect. At that time, the store command received from the application and the inter-core communication area information registration request are also passed.

  The access exclusion control unit 220 determines whether access is possible based on the above information, and further receives a store instruction and a request for registering the inter-core communication area information. It is determined that it is used (S224).

  Therefore, the access exclusion control unit 220 instructs the inter-core communication area management unit 210 to register a new entry in the inter-core communication area information registration unit 211. The inter-core communication area management unit 210 registers the tag, index, and byte offset address resolution information obtained by decoding the physical memory address input from the application as a new entry in the list of the inter-core communication area information registration unit 211. (S225). Further, the value of the word state W (i) in the word state storage section information field of the entry is set to 0 for the bit corresponding to the core 0 and to 1 for the other bits corresponding to the cores 1, 2, and 3.

  The access exclusive control unit 220 notifies the application of the core 0 of the accessibility determination (S226).

  As described above, the application of the core 0 that has received the notification of access permission from the cache memory control device 200 accesses the cache memory 2 using the same information input to the cache memory control device 200. Therefore, the memory area used for the inter-core communication in the cache memory 2 and the entry registered in the inter-core communication area information registration unit 211 of the cache memory control device 200 are managed in a consistent manner.

  Next, the operation when the cores 1, 2, and 3 receive the inter-core communication data sent from the core 0 will be described.

  FIG. 9 is a flowchart illustrating an operation example of reception processing of inter-core communication using the cache memory control device 200 of the second embodiment.

  When an application operating on the cores 1, 2, and 3 tries to receive an inter-core communication message, the cache memory control device 200 receives a physical memory address, a core ID, and a load and invalidate instruction (load and invalidate). (S231).

  In the cache memory control device 200, the physical memory address of the access destination passed from the application is decoded by the inter-core communication area management unit 210, and is decomposed into tag, index, and byte offset information to obtain address decomposition information (S232). ).

  Next, the inter-core communication area management unit 210 searches for an entry with the matching index from the list of the inter-core communication area information registration unit 211, and as a result, detects that an entry with the matching index is registered (S233). ).

  As a result of the search, when it is detected that an entry with the matching index is registered, the inter-core communication area management unit 210 notifies the access exclusion control unit 220 to that effect. At that time, entry registration information, physical memory address address resolution information received from the application, a core ID, and a load and invalidate command (load and invalidate) are also passed.

  The access exclusion control unit 220 compares the address resolution information tag with the tag included in the entry registration information, and detects that the two tags match and a cache hit occurs (S234).

  Subsequently, the access exclusive control unit 220 confirms that the memory access is a read and invalidate instruction (load and invalidate) that is read, and is a reception process of inter-core communication (S235).

  The access exclusive control unit 220 that has confirmed that it is the inter-core communication reception process compares the byte offset of the address resolution information with the byte offset included in the registration information of the entry and confirms that they match (S236). ).

  With the above operation, since the memory access can be determined as a reception process of communication between cores using the cache memory area by the application, the access exclusive control unit 220 updates the information in the word state storage unit included in the registration information of the entry. This is performed (S237).

  Specifically, the bit corresponding to the core that performs the reception process is set to 0 in the value of the word state W (i) of the word state storage unit information field included in the registration information of the entry.

  As a result of the above update, when the value of the updated word state W (i) is all 0 (S238, Yes), the entry is deleted from the list (S239).

  The update of steps S237 and S239 described above is executed when the access exclusive control unit 220 instructs the inter-core communication area management unit 210.

  Then, the access exclusion control unit 220 notifies the core application that performs the reception process of the determination that access is possible (S240).

  As described above, the core application that performs the reception process in response to the access permission notification from the cache memory control device 200 accesses the cache memory 2 using the same information as that input to the cache memory control device 200. Therefore, the memory area used for the inter-core communication in the cache memory 2 and the entry registered in the inter-core communication area information registration unit 211 of the cache memory control device 200 are managed in a consistent manner.

  As described above, in the present embodiment, an area where inter-core communication in the cache memory is performed is registered and managed in the inter-core communication area information registration unit. Each entry in the inter-core communication area information registration unit indicates a physical memory address that is decomposed into elements that uniquely identify a cache memory area used in inter-core communication and a use state of the cache memory area in inter-core communication. It consists of word state storage information which is information.

  Therefore, before the cache memory is accessed, a physical memory address for specifying a memory access destination by the access is input, and the physical memory address is decoded to generate address resolution information. The address decomposition information includes information decomposed into the same elements as the physical memory address included in each entry of the inter-core communication area information registration unit. Therefore, by comparing the address resolution information with each entry in the inter-core communication area information registration unit, it is possible to evaluate the influence of the access on the cache memory area used in the inter-core communication.

  Therefore, when the access is permitted, the cache memory area used in the inter-core communication is referred to, and when the comparison result of the condition for determining the cache miss is obtained, it is determined that the access is not permitted. To notify. Further, when the comparison result of the condition for determining the cache hit is obtained or when the corresponding entry does not exist, it is determined that the access does not affect the cache memory area used in the inter-core communication.

In this embodiment configured as described above, exclusive control is performed by managing the cache line and the word state used in inter-core communication based on the physical memory address, and the memory access accompanied by the event that the cache line is replaced Can be deterred in advance.
(Modification of the second embodiment)
Next, a cache memory control apparatus according to a modification of the second embodiment will be described with reference to FIGS.

  In the cache memory control device 200 of the second embodiment, the inter-core communication area information registration unit 211 is included in the inter-core communication area management unit 210, and the update is performed based on an instruction from the access exclusive control unit 220. It was broken.

  FIG. 10 is a block diagram illustrating a configuration of a cache memory control device 300 according to a modification of the second embodiment.

  In the cache memory control device 300 according to the modification of the second embodiment, an inter-core communication area information registration unit 330 corresponding to the inter-core communication area information registration unit 211 is installed as an independent configuration. Therefore, the inter-core communication area information registration unit 330 can be updated from either the inter-core communication area management unit 310 or the access exclusive control unit 320.

  In the cache memory control device 300 according to the modification of the second embodiment, the inter-core communication area management unit 310 updates the inter-core communication area information registration unit 330 without receiving an instruction from the access exclusive control unit 320. be able to. Further, the access exclusion control unit 320 can directly update the inter-core communication area information registration unit 330 without instructing the inter-core communication area management unit 310.

  FIG. 11 is a flowchart illustrating the operation of the inter-core communication area management unit 310 of the cache memory control device 300 according to the modification of the second embodiment. The operation of the inter-core communication area management unit 310 will be described with reference to FIG. Only differences from the processing flow in the operation of the inter-core communication area management unit 210 of the second embodiment described with reference to FIG. 6 will be described.

  The processes in steps S301 to S303 and steps S307 to S309 in FIG. 11 are the same as the processes in steps S201 to S204 and steps S207 and S208 in FIG.

  The different processing is that there are no steps S205 and S206 in FIG. 6 and steps S304 to S306 in FIG. 11 are performed.

  In the second embodiment, when an entry having an index that matches the index of the address resolution information is not registered in the inter-core communication area information registration unit 211 (No in S203), the subsequent processing is performed by the access exclusive control unit 220. To ask.

  On the other hand, in the modified example of the second embodiment, when the entry having the same index is not registered in the inter-core communication area information registration unit 330 (S303, none), the inter-core communication area management unit 310 performs access exclusion. The determination control is performed.

  That is, that the entry with the matching index is not registered in the inter-core communication area information registration unit 330 means that the cache memory area that the application is trying to access is not currently used for inter-core communication. Therefore, the inter-core communication area management unit 310 determines that access is possible and notifies the application to that effect (S304). Further, it is determined whether or not an inter-core communication area information registration request has been received (S305).

  When an inter-core communication area information registration request has been received (S305, yes), a new inter-core communication has occurred, so an additional entry is registered as management information for the cache memory area used by the inter-core communication. It performs (S306).

  Therefore, when it is found that the entry with the matching index is not registered in the inter-core communication area information registration unit 330, the inter-core communication area management unit 310 does not request the access exclusive control unit 320 and the access exclusive control The determination control is performed.

  Steps S304 to S306 in FIG. 11 correspond to steps S212 to S214 of the processing of the exclusive access control unit 220 of the second embodiment described with reference to FIG.

  FIG. 12 is a flowchart illustrating the operation of the access exclusive control unit 320 of the cache memory control device 300 according to the modification of the second embodiment.

  As described above, when the entry with the matching index is not registered in the inter-core communication area information registration unit 330, the inter-core communication area management unit 310 performs access exclusion determination control.

  Therefore, in the exclusive access control unit 320 of the cache memory control device 300 according to the modified example of the second embodiment, the processing when the entry with the matching index is not registered in the inter-core communication area information registration unit 330 is unnecessary. Become. That is, as shown in FIG. 12, in the modified example of the second embodiment, the processes in steps S211 to S214 described with reference to FIG.

  On the other hand, the access exclusive control unit 320 updates the entry content in step S315 without instructing the inter-core communication area management unit 310.

  Specifically, in the value of the word state W (i) of the word state storage unit information field included in the registration information of the entry, the bit corresponding to the core that performs the reception process is set to 0. If the updated word state W (i) is all 0 as a result of the update, the entry is deleted from the list of the inter-core communication area information registration unit 330.

  The cache memory control device 300 according to the modification of the second embodiment configured as described above reduces the transfer information between the inter-core communication area management unit 310 and the access exclusive control unit 320, which are constituent elements, and performs processing. The operation can be speeded up.

  As described above, the cache memory control device and the control method of each embodiment perform access exclusive control that suppresses write-back processing by focusing on the access destination cache line, the cache line used in inter-core communication, and the word state. Do. In other words, the cache memory control device and the control method of each embodiment can perform exclusive access control without using process IDs, logical addresses, physical page sizes, etc., and without depending on the configuration and operation method of the multi-core processor. Therefore, without depending on the configuration and operation method of the multi-core processor, the write-back processing that occurs when the cache line used for inter-core communication is replaced is suppressed, and the inter-core communication speed is prevented from decreasing. Can do.

1 CPU
2 Cache memory 3 Main memory 4_0, 4_1, 4_N-1 Core 7 Address register 8, 13 Upper m bits 9 n bits 10 Lower k bits 11 Address array 12 Data array 14 State and others 15 Block data 16 Comparison unit 17 Core number 18 Instruction 19 Cache control unit 20 Block state storage unit 21 Word state storage unit 22 For core 0 23 For core 1 24 For core 2 25 For core 3 100, 200, 300 Cache memory control device 110, 211, 330 Inter-core communication area information registration Unit 120 decomposition element information generation unit 130 access exclusion control unit 210, 310 inter-core communication area management unit 212, 312 address decomposition information generation unit 213, 313 comparison determination unit 220, 320 access exclusion control unit 221, 321 comparison determination Control unit

Claims (10)

Between cores consisting of a physical memory address that is decomposed into elements that uniquely identify a cache memory area used in inter-core communication of a multi-core processor and word state storage information that indicates the use state of the cache memory area in inter-core communication An inter-core communication area information registration unit for registering communication area information;
Decomposition element information generating means for inputting a physical memory address for specifying a memory access destination before accessing the cache memory and decomposing the input physical memory address into the elements to generate decomposition element information;
When the decomposition element information is compared with the inter-core communication area information and access to the cache memory is permitted, the cache memory area used in the inter-core communication is referred to and a cache miss is determined. A cache memory control device comprising: an access exclusive control unit that determines that access to the cache memory is not permitted when a comparison result of conditions is obtained and notifies the result. The physical memory address is decomposed into elements of a tag, an index, and a byte offset, and the index corresponds to information used for searching an entry of an address array that registers a cache line registered in the cache memory. Corresponding to information used for cache hit or cache miss comparison determination together with the index, the byte offset corresponds to information identifying a word in the cache line that hit the cache,
The word state storage information includes information indicating, for each core, transmission access status and reception access status of each core in the cache memory area of each core performing inter-core communication. The cache memory control device described. The access exclusive control means includes:
As a primary comparison, the presence / absence of the inter-core communication area information having an index that matches the index of the decomposition element information generated by the decomposition element information generation unit is determined and matched. Permit access to the cache memory when there is no inter-core communication area information having an index to
When an inter-core communication area information registration request for requesting registration of the inter-core communication area information is input together with the input of the physical memory address, the disassembly element information generating means is provided in the inter-core communication area information registration unit. 3. The cache memory control device according to claim 2, wherein new inter-core communication area information having the disassembled element information generated by is registered. When the inter-core communication area information having a matching index exists as a result of the primary comparison, the access exclusive control means performs a secondary comparison on the inter-core communication area information having a matching index. Determining whether or not the tag of the decomposition element information generated by the decomposition element information generation means matches,
The access to the cache memory is not permitted if the tag does not match in the secondary comparison, and the access to the cache memory is permitted if the tag matches in the secondary comparison. Item 4. The cache memory control device according to Item 3. The access exclusive control means is a case where the inter-core communication area information with the matching tag exists as a result of the secondary comparison, and the access instruction type input together with the input of the physical memory address indicates reception processing. As a third comparison, for the inter-core communication area information having a matching tag and index, determine whether or not the byte offset of the decomposition element information generated by the decomposition element information generation means,
5. The cache memory control device according to claim 4, wherein when the byte offsets match in the tertiary comparison, the word state storage information included in the inter-core communication area information is updated. The access exclusive control means updates the information corresponding to the core that performs the reception processing of the word state storage information to be set to 0 indicating that the reception access has been executed,
6. The inter-core communication area information is deleted from the inter-core communication area information registration unit when information corresponding to all the cores that perform the reception process becomes 0. 6. Cache memory controller. Between cores consisting of a physical memory address that is decomposed into elements that uniquely identify a cache memory area used in inter-core communication of a multi-core processor and word state storage information that indicates the use state of the cache memory area in inter-core communication Register communication area information in the inter-core communication area information registration unit,
Before accessing the cache memory, input a physical memory address for specifying a memory access destination, decompose the input physical memory address into the elements, and generate decomposed element information.
When the decomposition element information is compared with the inter-core communication area information and access to the cache memory is permitted, the cache memory area used in the inter-core communication is referred to and a cache miss is determined. A cache memory control method comprising: notifying that access to the cache memory is not permitted when a comparison result of conditions is obtained. The physical memory address is decomposed into elements of a tag, an index, and a byte offset, and the index corresponds to information used for searching an entry of an address array that registers a cache line registered in the cache memory. Corresponding to information used for cache hit or cache miss comparison determination together with the index, the byte offset corresponds to information identifying a word in the cache line that hit the cache,
The word state storage information includes information indicating the transmission access status and reception access status of each core of the cache memory area of each core performing inter-core communication for each core,
The presence or absence in the inter-core communication area information registration unit of the inter-core communication area information having an index that matches the index of the decomposition element information is determined as a primary comparison,
When the inter-core communication area information having a matching index does not exist as the determination result of the primary comparison, access to the cache memory is permitted, and the inter-core communication area information is registered together with the input of the physical memory address. When the inter-core communication area information registration request for requesting is input, new inter-core communication area information having the disassembly element information is registered in the inter-core communication area information registration unit. The cache memory control method according to claim 7. If the inter-core communication area information having a matching index exists as a determination result of the primary comparison, the tag of the decomposition element information is compared with the inter-core communication area information having a matching index. Determine whether there is a match as a secondary comparison,
If the tag does not match as the determination result of the secondary comparison, access to the cache memory is disallowed,
9. The cache memory control method according to claim 8, wherein access to the cache memory is permitted when the tags match as a determination result of the secondary comparison. If the inter-core communication area information that matches the tag exists as the determination result of the secondary comparison, and the access instruction type input together with the input of the physical memory address indicates reception processing, the matching tag and For the inter-core communication area information having an index, the presence or absence of matching of the byte offset of the disassembly element information is determined as a third comparison,
As a result of the tertiary comparison, when the byte offsets match, the information corresponding to the core that performs the reception processing of the word state storage information included in the inter-core communication area information is received. Update to 0 to indicate that
The information of the inter-core communication area is deleted from the inter-core communication area information registration unit when the information corresponding to all the cores performing the reception process becomes 0. Cache memory control method.

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