JPH10207767A - Cache memory with lock function and microprocessor equipped with cache memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a cache memory with a lock function and a microprocessor equipped with the cache memory in which a CPU cycle to be spent on data transfer to a locked area can be reduced. SOLUTION: A microprocessor incorporating a cache memory equipped with a lock function is provided with an index register 6 which sets an index address for designating the cache line of a lock area for operating writing independently of an address register 1 which sets an operand address. A block transferring instruction for directly transferring data from a main memory to the locked set of the cache line is executed, and writing is operated to the locked set.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory having a cache line locking function and a microprocessor having the cache memory.

[0002]

2. Description of the Related Art In a microprocessor incorporating a cache memory adopting a set associative method, one of a plurality of sets is locked for each cache line to reduce a penalty due to a cache miss, and is replaced from a replacement target. There is a method of using the locked portion of the cache memory as if it were removed, as if it were a built-in RAM that can be accessed at high speed.

For example, a 1-Kbyte, 2-way set associative data cache is built in, and for each line of the data cache, an LRU replacement bit indicating a set to be replaced next and an indication that the cache line is locked. By providing a lock bit,
A processor realizing a cache line locking function has been commercialized.

The LRU replacement bit indicates set 1 when set 0 of the cache line is accessed, and indicates set 0 when set 1 is accessed, so that when a cache miss occurs and the cache line is replaced, The recently accessed set is controlled to remain in the cache memory.

On the other hand, when locking the set 0 of the cache line, the LRU replacement bit is set to 1, and when locking the set 1, the LRU replacement bit is set to 0 and then the lock bit is set to 1. In the cache line in which the lock bit is set to 1, the update of the LRU replacement bit due to access to the cache line is suppressed, so that the locked set is excluded from the replacement target.

FIG. 2 shows a conventional microprocessor data cache control mechanism using a two-way set associative cache memory as an example.

In the data cache shown in FIG. 2, when a load instruction and a store instruction are executed and an operand read request or an operand write request is issued, an operand address is set in the address register 100. Using the lower address of the address register 100 as an index, a replacement bit, a lock bit, and two sets of valid bits and a tag address of the corresponding cache line are read from the cache storage unit 101. The upper address of the address register 100 and the read tag address of the cache line are
If the valid bit is 1 and the upper address matches the tag address, a cache hit is determined.

In the case of operand read, data of a set that has been hit using the lower address of the address register 100 as an index is selected and read by the selector 103 and output as operand read data. In the case of operand write, address register 1
Operand write data is selected by the selector 104 and written to the hit set using the lower address of 00 as an index.

If no hit is determined for any of the sets, a replacement request is output from the cache control circuit 105 as a cache miss. At this time, the value of the address register 100 is output as a replacement address. Also, the set indicated by the replacement bit read from the cache line is to be replaced. When the data of the replacement address is read from the main memory, the replacement acknowledgment is input to the cache control circuit 105, the replacement data is written in the data of the set to be replaced using the lower address of the address register 100 as an index, and the address register is stored in the tag address. Is written, and 1 is written to the valid bit. When the replacement of the cache line is completed, in the operand read, the replaced set of data is read using the lower address of the address register 100 as an index, and output as operand read data. On the other hand, in the operand write, the operand write data is written in the replaced set using the lower address of the address register 100 as an index.

When a cache hit occurs due to an operand read request or an operand write request, if the read lock bit is not 1, the replacement bit is updated so as to indicate the set in which the replacement bit did not hit. In the case of a cache miss, if the read lock bit is not 1, the replacement bit is updated so as to indicate the set in which the replacement bit has not been replaced. On the other hand, when the lock bit is 1
In the case of, the replacement bit is not updated, and the replacement bit always indicates the unlocked set, so that the locked set is prevented from being replaced.

By such control, a part of the cache memory, that is, a locked part can be used as if it were a built-in RAM which can be accessed at a high speed.

In such a usage form, when data in the main memory is transferred to the locked set of the cache memory, a load instruction for transferring data from the main memory to the register and a lock instruction of the cache memory from the register are used. It had to be performed in combination with a store instruction to transfer data to the set.

[0013]

As described above,
A conventional microprocessor with a cache memory having a lock function, when transferring data from main memory to a locked set of cache lines,
Two instructions, a load instruction and a store instruction, had to be executed. For this reason, data transfer takes time and CPU cycles for executing two instructions are spent.

Accordingly, the present invention has been made in view of the above, and has as its object to reduce the number of CPU cycles spent for transferring data to a locked area and shorten the write time in a locked area. It is an object of the present invention to provide a cache memory with a lock function and a microprocessor having the cache memory.

[0015]

According to an aspect of the present invention, there is provided a cache memory with a lock function for prohibiting and locking replacement in the event of a mishit in a data storage area designated in advance. When performing normal cache access, the first operand address for accessing data is set and held, and when writing to a locked data storage area, the second operand address for specifying write data is used for block transfer. An operand address holding means which is set and held by execution of an instruction, and an index which sets and holds an index address designating a data storage area to be written among the locked data storage areas by executing a block transfer instruction Address holding means and normal cache access When performing a write operation, an operand address held in the operand address holding means is selected to designate a data storage area, or when writing is performed in a locked storage area, an index held in the index address holding means is used. Selecting means for selecting a data storage area by selecting an address; receiving a block transfer request by executing a block transfer instruction for writing to the locked data storage area; The area is provided with control means for controlling writing of write data specified by the operand address held in the operand address holding means and directly transferred from the transfer source.

According to a second aspect of the present invention, in the cache memory with the lock function according to the first aspect, the index address held in the index address holding means is incremented, and the incremented index address is selectively selected as the index address. An increment means for setting the data in the holding means is provided, and writing is continuously performed on the data storage area locked by the incremented index address.

According to a third aspect of the present invention, in the cache memory with the lock function according to the first or second aspect, the control means locks the data storage area specified by the index address held in the index address holding means. It is determined whether or not the data has been locked, and if the data is not locked, the writing to the data storage area specified by the index address held by the index address holding means is stopped and controlled.

According to a fourth aspect of the present invention, there is provided the cache memory with a lock function according to the first, second or third aspect, wherein the block transfer instruction is included in an instruction set, the block transfer instruction is executed, and the operand address holding means is executed. , An index address is set in the index address holding means by executing a block transfer instruction, and a block transfer instruction is executed to give the block transfer request to the control means. The data to be written to the data storage area locked according to the held operand address is directly transferred to the cache memory with lock function.

[0019]

FIG. 1 is a diagram showing the configuration of a cache memory with a lock function according to an embodiment of the present invention, and a microprocessor provided with the cache memory.

In FIG. 1, the cache memory with a lock function according to the present embodiment has the above-described lock function.
An address register 1 having the same functions as those of the address register 100, the cache storage unit 101, the comparator 102, and the selectors 103 and 104 constituting the cache memory with a lock function shown in FIG. In addition to the cache storage unit 2, the comparator 3, and the selectors 4 and 5, an index address specifying a cache line to be written in the locked cache line of the cache storage unit 2 is set and held by executing the block transfer instruction. Index register 6, an incrementer 7 for incrementing the index address held in the index register 6, and an index address incremented by the incrementer 7 or the execution of the block transfer instruction. And a selector 8 for selecting an index address given by the formula (1) and giving the index address to the index register 6, and selecting a lower address of the operand address held in the address register 1 or an index address held in the index register 6, and A selector 9 for specifying a locked cache line to be written, and a cache control circuit 10 for controlling a normal cache access operation and a replace operation and a write operation of a locked cache line
It is comprised including.

In such a configuration, ordinary cache access operation and replacement operation are performed in the same manner as the configuration shown in FIG. When a load instruction and a store instruction are executed by the microprocessor and there is an operand read request or an operand write request,
An operand address is set in the address register 1. The lower address of the address register 1 is selected as an index, and the cache line specified by this address is accessed. The cache miss / hit determination, operand read data read, operand write data write, and cache miss replacement are performed in the same manner as in the related art. In an operand read request or an operand write request, the lower address of the address register is used as a cache index.

Next, an operation of transferring data from an arbitrary address of a main memory (not shown) to a locked set of a cache line will be described.

First, a block transfer instruction is executed using the address of the main memory of the transfer source of the write data as the operand address and the address of the cache line of the transfer destination as the index address, the operand address is set in the address register 1, and the index address is set. Is set in the index register 6. The block transfer instruction is an instruction for directly transferring write data from the main memory and performing an operation of writing the transferred data to a set of locked cache lines, and a microprocessor including the cache memory according to the present embodiment. Included in the instruction set. The index address and the operand address are set as values of the address field of the block transfer instruction.

When the block transfer instruction is executed, a block transfer request is given from the microprocessor to the cache control circuit 10, and the index address held in the index register 6 is selected by the selector 9 as an index. The replacement bit and the lock bit of the designated cache line, the valid bits for two sets, and the tag address are read.

In the block transfer, a replacement request is output from the cache control circuit 10 to the processor irrespective of the result of comparison between the upper address of the address register 1 and the tag address. At this time, the address held in the address register 1 is output to the processor as a replacement address. In the block transfer, set 1 is set when the read replacement bit is 0, and set 0 when the read replacement bit is 1.
Are replaced. When the data of the replacement address is read from the main memory, the replacement acknowledgment is input to the cache control circuit 10 from the processor side, the output of the index register 6 is selected as an index, and the cache line of the set to be replaced is selected via the selector 5. The given replacement data is written.

In the block transfer, the tag address, the valid bit, and the replacement bit are not updated. The index address held in the index register 6 is incremented and updated by the incrementer 7.

As described above, in the block transfer instruction, the data of the main memory specified by the operand address is transferred to the cache using the index address set in the index register 6 as the cache index. Further, since the index address held in the index register 6 is incremented, the block transfer instruction is continuously executed, and the index address incremented by the incrementer 7 is selected by the selector 8 and set in the index register 6, thereby enabling the cache to be executed. The data in the main memory can be continuously transferred to the continuous data storage area locked in the storage unit 2. This is effective for replacing a group of data in a continuously locked area.

The block transfer instruction assumes that the lock bit of the cache line specified by the index address held in the index register 6 has been set to 1. Since the locked set of cache lines is used as a built-in RAM that can be accessed at a high speed, it is not necessary to maintain coherency of data in the main memory and the cache memory. On the other hand, if a block transfer instruction is executed for a cache line in which the lock bit is set to 0, data consistency between the main memory and the cache memory cannot be guaranteed. Therefore, the present invention is particularly effective in a microprocessor having a cache memory having a lock function. The cache control circuit 10 determines whether or not the cache line specified by the index address held in the index register 6 is locked by reading the lock bit, and if not locked, stops writing. You may make it have the function to make it. In such a case, it is possible to prevent writing into an unlocked area.

The present invention is not limited to a data cache, but is also effective for an instruction cache. For example, a routine that requires high-speed execution may be resident in the instruction cache by locking a part of the instruction cache. According to the present invention, when switching the routine resident in the instruction cache, a new routine is used. It is possible to load the instruction cache at high speed.

As described above, in the above-described embodiment, in the cache memory having the lock function and the microprocessor incorporating the cache memory, the index for setting the index address of the cache independently of the address register 1 for setting the operand address. By providing the register 6, it is possible to execute a block transfer instruction for transferring data from an arbitrary address of the main memory to the locked set of the cache line,
By combining a load instruction and a store instruction in the past, unnecessary CPU cycles can be reduced. Also,
By adding the increment function to the index register 6, continuous execution of the block transfer instruction becomes possible,
Block transfer to a continuous lock area of the cache memory becomes possible.

[0031]

As described above, according to the present invention, data written in a locked area by executing a block transfer instruction is directly transferred from a transfer source.
Since the transferred data is written to the locked area specified by the index address set in the index address holding means, CPU cycles spent for transferring data to the locked area are reduced,
It is possible to provide a cache memory with a lock function in which the write time in the lock area is reduced, and a microprocessor including the cache memory.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a cache memory with a lock function and a microprocessor including the cache memory according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a conventional cache memory with a lock function and a microprocessor provided with the cache memory.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Address register 2 Cache storage unit 3 Comparator 4, 5, 8, 9 Selector 6 Index register 7 Incrementer 10 Cache control circuit

Claims (4)

[Claims] In a cache memory with a lock function for inhibiting replacement and locking when a mishit occurs in a data storage area designated in advance, a first operand address for accessing data is set when performing normal cache access. An operand address holding means for setting and holding a second operand address designating write data when writing to a locked data storage area by executing a block transfer instruction; Among the storage areas, an index address for designating a data storage area to be written is set and held by execution of a block transfer instruction, and the operand address holding means is used for performing normal cache access. Operation Selecting a land address to specify a data storage area, or, when writing to a locked storage area, selecting an index address held by the index address holding means and specifying a data storage area; Receiving a block transfer request by executing a block transfer instruction for writing to the locked data storage area, and storing the operand address stored in the operand address storage means in the locked data storage area specified by the selection means. And a control means for controlling writing of the write data specified directly by the transfer source and transferred from the transfer source. 2. An index address holding means for incrementing an index address held by the index address holding means, and selectively setting the incremented index address in the index address holding means, wherein the incremented index address is continuously set by the incremented index address. 2. The cache memory with a lock function according to claim 1, wherein data is written to the locked data storage area. 3. The control means determines whether or not a data storage area specified by an index address held by the index address holding means is locked. If the data storage area is not locked, the control means determines whether the data storage area is locked. 3. The cache memory with a lock function according to claim 1, wherein writing control to the data storage area specified by the index address stored in the cache memory is stopped. 4. A cache memory with a lock function according to claim 1, wherein said block transfer instruction is included in an instruction set, said block transfer instruction is executed, and an operand address is set in said operand address holding means. Executing a block transfer instruction to set an index address in the index address holding means, executing the block transfer instruction and giving the block transfer request to the control means, and setting the operand address held in the operand address holding means to Therefore, a microprocessor provided with a cache memory with a lock function, which directly transfers data written in a locked data storage area to the cache memory with a lock function.