JP6109186B2 - 状態機械格子におけるカウンタ動作 - Google Patents
状態機械格子におけるカウンタ動作 Download PDFInfo
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- G—PHYSICS
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
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- G05B19/045—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using logic state machines, consisting only of a memory or a programmable logic device containing the logic for the controlled machine and in which the state of its outputs is dependent on the state of its inputs or part of its own output states, e.g. binary decision controllers, finite state controllers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17724—Structural details of logic blocks
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
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Description
Claims (10)
- デバイスであって、
ブロックのそれぞれが複数の列を備える複数の前記ブロックを備える、有限状態機械(FSM)格子を備え、
前記列のそれぞれが、複数のプログラム可能な要素を備え、前記複数のプログラム可能な要素のそれぞれは、条件の検出に基づいて信号を出力するように構成され、
前記ブロックの特定の1つの前記列の少なくとも1つが、前記ブロックの前記特定の1つの前記複数の列のいずれかにおいて前記複数のプログラム可能な要素のいずれかに選択的に結合するように構成されたカウンタを更に備え、前記カウンタは、前記条件が選択的に結合されたいずれかの前記複数のプログラム可能な要素から一定回数検出されたカウンティングに応答して出力するように構成される、デバイス。 - 前記カウンタは、デクリメントカウンタを備える、請求項1に記載のデバイス。
- 前記カウンタは、
ゼロにデクリメントする前記カウンタに応答して前記カウンタがリセットされるまで、前記カウンタをゼロに保持するためにアサートされるように構成された保持入力と、
前記保持入力がアサートされないときに前記カウンタの初期値をロードするためにアサートされるように構成されたロール入力と、を備える、請求項1に記載のデバイス。 - カウンタを備えない前記ブロックの前記特定の1つの前記複数の列の特定の1つは、ブール論理セルを備え、前記ブール論理セルは、列内回路およびブロック内回路経由で前記カウンタに選択的に結合する、請求項1に記載のデバイス。
- 前記FSM格子を備えるサーバ、パーソナルコンピュータ、ワークステーション、ルータ、ネットワークスイッチ、チップテスト装置、ラップトップ、携帯電話、メディアプレーヤー、ゲームコンソール、またはメインフレームコンピュータを備える、請求項1に記載のデバイス。
- デバイスであって、
少なくとも第1の列及び第2の列を備える第1のブロックを備える、有限状態機械(FSM)格子を備え、
前記第1の列及び前記第2の列のそれぞれが、条件の検出に基づいて信号を出力するように構成される複数のプログラム可能な要素を備え、
前記第1の列が、前記第1の列に含まれる前記複数のプログラム可能な要素及び前記第2の列に含まれる前記複数のプログラム可能な要素と選択的に結合するように構成された第1のカウンタを更に備え、前記第1のカウンタは、前記条件が前記第1の列及び前記第2の列に含まれる前記複数のプログラム可能な要素から一定回数検出されたカウンティングに応答して出力するように構成される、デバイス。 - 前記第1のブロックは、前記第1の列及び前記第2の列にそれぞれ対応して設けられた第1のブロック内回路及び第2のブロック内回路を備え、前記第1のカウンタは前記第1のブロック内回路及び前記第2のブロック内回路を介して前記第2の列に含まれる前記複数のプログラム可能な要素と結合する請求項6に記載のデバイス。
- 前記格子は、条件の検出に基づいて信号を出力するように構成される複数のプログラム可能な要素を含む第3の列及び前記第3の列に対応して設けられた第3のブロック内回路を備える第2のブロックと、前記第1のブロック及び前記第2のブロックを結合するように構成されたブロック間回路を更に備え、前記第1のカウンタは、前記第1のブロック内回路、前記ブロック間回路及び前記第3のブロック内回路を介して前記第2のブロックに含まれる前記複数のプログラム可能な要素と結合される請求項7に記載のデバイス。
- 前記第1のブロックは、第2のカウンタを含む第3の列及び前記第3の列に対応して設けられた第3のブロック内回路を更に備え、前記第1のカウンタは前記第1のブロック内回路及び前記第3のブロック内回路を介して前記第2のカウンタと結合し、前記第2のカウンタから受ける受信繰上げ信号に応じてカウント動作を行う請求項7に記載のデバイス。
- 前記第1のカウンタ及び前記第2のカウンタは共にデクリメントカウンタである請求項9に記載のデバイス。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/327,499 US8648621B2 (en) | 2011-12-15 | 2011-12-15 | Counter operation in a state machine lattice |
US13/327,499 | 2011-12-15 | ||
PCT/US2012/067988 WO2013090091A2 (en) | 2011-12-15 | 2012-12-05 | Counter operation in a state machine lattice |
Publications (2)
Publication Number | Publication Date |
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JP2015505399A JP2015505399A (ja) | 2015-02-19 |
JP6109186B2 true JP6109186B2 (ja) | 2017-04-05 |
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JP2014547287A Active JP6109186B2 (ja) | 2011-12-15 | 2012-12-05 | 状態機械格子におけるカウンタ動作 |
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Country | Link |
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US (4) | US8648621B2 (ja) |
EP (1) | EP2791854B1 (ja) |
JP (1) | JP6109186B2 (ja) |
KR (1) | KR101840905B1 (ja) |
CN (2) | CN104067282B (ja) |
TW (1) | TWI486810B (ja) |
WO (1) | WO2013090091A2 (ja) |
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WO2013090091A2 (en) | 2013-06-20 |
CN107608750A (zh) | 2018-01-19 |
TWI486810B (zh) | 2015-06-01 |
TW201342110A (zh) | 2013-10-16 |
US20130159670A1 (en) | 2013-06-20 |
KR20140103143A (ko) | 2014-08-25 |
KR101840905B1 (ko) | 2018-05-04 |
CN107608750B (zh) | 2020-05-08 |
US8648621B2 (en) | 2014-02-11 |
US20170261956A1 (en) | 2017-09-14 |
EP2791854B1 (en) | 2019-01-23 |
WO2013090091A3 (en) | 2014-07-24 |
US20140115299A1 (en) | 2014-04-24 |
US20150253755A1 (en) | 2015-09-10 |
JP2015505399A (ja) | 2015-02-19 |
CN104067282A (zh) | 2014-09-24 |
US9058465B2 (en) | 2015-06-16 |
US9886017B2 (en) | 2018-02-06 |
US9665083B2 (en) | 2017-05-30 |
CN104067282B (zh) | 2017-08-22 |
EP2791854A2 (en) | 2014-10-22 |
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