JP6094130B2 - PWM signal generator - Google Patents

Description

  The present invention relates to a PWM signal generation device, for example, a technique effective when applied to a PWM signal generation device that generates a PWM signal in a digital manner.

  For example, Patent Document 1 discloses a PWM generator using a delay locked loop (DLL). Patent Document 2 discloses a digital PWM signal generation circuit. Specifically, the PWM signal corresponding to the register value is selected by selecting whether or not to output a pulse signal having a different phase generated by the ring counter by using a register value and an AND operation circuit, and performing an OR operation on the selected pulse signal. Is generated. At this time, the OR operation is realized by a plurality of OR operation circuits appropriately divided by flip-flops. Patent Document 3 shows a PWM signal generation circuit similar to Patent Document 2. However, in Patent Document 3, the ring counter operates at both edges of the clock signal, and generates a pulse signal whose phase differs by a half cycle of the clock signal.

JP-T-2006-527569 JP 2004-345280 A Japanese Patent Laid-Open No. 2005-5770

  In recent years, digital PWM signal generators have attracted attention in place of analog PWM signal generators that generate PWM (Pulse Width Modulation) signals using triangular waves, sawtooth waves, or the like. FIG. 16 is a block diagram showing a schematic configuration example of a PWM signal generation device studied as a premise of the present invention. The PWM signal generation device shown in FIG. 16 is a digital system, and includes a counter unit CUNTc, a plurality of register units REG, a comparison circuit unit CMPc, and a PWM output generation unit PWMGc.

  The comparison circuit unit CMPc compares the counter value from the counter unit CUNTc with the set values of the counters by the plurality of register units REG, and outputs a compare match signal if they match. When the compare match signal is output, the PWM output generation unit PWMGc generates the PWM signal PWMOUT according to the corresponding output level setting signal (eg, “H” → “L” level, “L” → “H” level). . When using such a PWM signal generation device, CUNTc and PWMGc need to operate with a master clock signal CLKm having a period (frequency) corresponding to the minimum resolution. For example, when the minimum resolution is 1.0 ns, it is necessary to operate at 1 GHz CLKm.

  However, depending on the semiconductor manufacturing process, it may be difficult to realize a PWM signal generation device that operates with a clock signal of 1 GHz, for example, due to timing constraints. For example, the counter unit or the like is usually configured by a plurality of flip-flops and a combinational logic circuit provided between the plurality of flip-flops, and data transfer between the flip-flops via such a combinational logic circuit is 1 GHz. It may be difficult to perform at a frequency of. Further, even if it can be realized, a state-of-the-art manufacturing process is required to operate with a high-speed clock signal, leading to an increase in cost and an increase in power consumption. Therefore, it is conceivable to use techniques as disclosed in Patent Documents 1 to 3 as a technique for generating a high-resolution PWM signal while satisfying such timing constraints.

  However, for example, when the PWM generator disclosed in Patent Document 1 is used, a delay locked loop (DLL) needs to be mounted, which may increase the circuit scale. In addition, since the DLL needs to be redesigned when changing the semiconductor manufacturing process, there is a concern about an increase in design cost. Furthermore, when using DLL, there are concerns that there are many restrictions such as the minimum operation clock frequency and setting procedure.

  Further, when the PWM signal generation circuit of Patent Document 2 is used, there is a possibility that a glitch of a very short time may occur in the PWM signal by the AND-OR operation circuit in the output unit. Note that such glitch may be prevented if the OR operation is realized by a plurality of OR operation circuits appropriately divided by flip-flops. However, in this case, it is necessary to transfer data between flip-flops sandwiching the OR operation circuit with a high-speed clock signal (for example, 1 GHz), and there is a possibility that the timing constraint described above cannot be satisfied.

  On the other hand, the PWM signal generation circuit of Patent Document 3 operates the ring counter at both edges of the clock signal in order to obtain twice the resolution of the clock signal. Thereby, for example, when a 1 GHz clock signal is used, the pulse width of 1.0 ns can be minimized, and thereafter the pulse width can be set in 0.5 ns increments. When a 500 MHz clock signal is used, 2.0 ns The pulse width can be set in increments of 1.0 ns. However, since the minimum pulse width is 2.0 ns when realizing the minimum resolution of 1.0 ns in this way, the application range may be limited. Further, in common with Patent Document 2 and Patent Document 3, due to the timing relationship between the digital data for setting the pattern of the PWM signal and the AND-OR operation circuit, the pulse width of the PWM signal is set. There is a risk that high accuracy (high resolution) cannot be achieved.

  The present invention has been made in view of the above, and other problems and novel features will become apparent from the description of the present specification and the accompanying drawings.

  Of the means for solving the problems disclosed in the present application, the outline of typical ones will be briefly described as follows.

  Of the inventions disclosed in the present application, the outline of a typical embodiment will be briefly described as follows.

  The PWM signal generation device according to the present embodiment includes a signal generation circuit, first pattern data, a phase adjustment circuit, a first AND operation circuit unit, and an OR operation circuit. Each of the signal generation circuits includes N first pulses having the same pulse width, a second period N (N is an integer of 2 or more) times the first period, and phases that are sequentially different in units of the first period. A signal [n] (n = 1, 2,..., N) is generated. The first pattern data is N-bit parallel data updated every second period, and sets the logical level of the PWM signal in the N section in the second period. The phase adjustment circuit receives the first pattern data, adjusts the phase of each bit, and then outputs N-bit second pattern data. The first AND operation circuit unit includes N AND operation circuits to which the second pattern data and the N first pulse signals [n] are input, and each of the N first pulse signals [n] is supplied to the first AND operation circuit unit. Selectively output based on the two pattern data. The OR operation circuit performs an OR operation using the output from the first AND operation circuit unit as an input, and outputs a PWM signal corresponding to the first pattern data. Here, in detail, the phase adjustment circuit outputs a part of the bits of the second pattern data in the first phase, and outputs the other part of the bits of the second pattern data based on the first phase. A second phase having a phase difference M times the period (M is an integer of 1 to (N-1)) is output.

  The effects obtained by the representative embodiments of the invention disclosed in this application will be briefly described. In the PWM signal generation apparatus, timing design can be facilitated and a high-resolution PWM signal can be generated. It becomes.

1 is a block diagram illustrating a schematic configuration example of a semiconductor device including the PWM signal generation device according to Embodiment 1 of the present invention. FIG. FIG. 2 is a block diagram illustrating a schematic configuration example of a PWM signal generation unit in the semiconductor device of FIG. 1. FIG. 3 is a circuit diagram illustrating a detailed configuration example of a clock / pulse signal generation unit in FIG. 2. FIG. 4 is a waveform diagram showing an example of a signal generated by a clock / pulse signal generation unit in FIG. 3. FIG. 2 is a circuit diagram illustrating a detailed configuration example of a PWM output generation unit in FIG. 1. FIG. 6 is a waveform diagram illustrating an operation example of a PWM output generation unit in FIG. 5. (A) is a figure which shows an example of the effect of the pulse selection circuit part (AND operation circuit part) for interpolation in FIG. 5, (b) is a pulse selection circuit part for interpolation as a comparative example of (a). It is a figure which shows an example of the problem in case there is no (AND operation circuit part). (A), (b), and (c) are figures which show the typical operation example of each pulse selection circuit part (AND operation circuit part) and OR operation circuit in FIG. FIG. 3 is a circuit block diagram illustrating a detailed configuration example of a PWM output pattern generation unit in FIG. 2. 3 is a circuit diagram illustrating a detailed configuration example of a clock / pulse signal generation unit in FIG. 2 in a PWM signal generation device according to a second embodiment of the present invention. FIG. FIG. 5 is a circuit diagram showing a detailed configuration example of a clock / pulse signal generation unit of FIG. 2 in a PWM signal generation device according to Embodiment 3 of the present invention; (A) is the circuit diagram which shows the detailed structural example of the clock pulse signal generation part of FIG. 2 in the PWM signal generation apparatus by Embodiment 4 of this invention, (b) is one of (a). It is a wave form diagram which shows the operation example of a part. FIG. 10 is a circuit diagram illustrating a detailed configuration example of a PWM output generation unit in FIG. 1 in a PWM signal generation device according to a fifth embodiment of the present invention. FIG. 10 is a circuit diagram illustrating a detailed configuration example of a PWM output generation unit in FIG. 1 in a PWM signal generation device according to a sixth embodiment of the present invention. FIG. 15 is a waveform diagram illustrating a main operation example in a part of the PWM output generation unit of FIG. 14. 1 is a block diagram illustrating a schematic configuration example of a PWM signal generation device studied as a premise of the present invention.

  In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant, and one is the other. Some or all of the modifications, details, supplementary explanations, and the like are related. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  The circuit elements constituting each functional block of the embodiment are not particularly limited, but are formed on a semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as a CMOS (complementary MOS transistor). . Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
<< Overall configuration of semiconductor device >>
FIG. 1 is a block diagram illustrating a schematic configuration example of a semiconductor device including the PWM signal generation device according to the first embodiment of the present invention. The semiconductor device MCU shown in FIG. 1 is realized by a single semiconductor chip, for example, and serves as a microcontroller for performing power supply control in a digital manner. The semiconductor device (microcontroller) MCU of FIG. 1 includes an analog bus ABUS, a digital bus DBUS, a plurality of functional units appropriately coupled to these buses, and an interface unit GPIO that performs communication between the outside.

  An operational amplifier unit OPAMP, an analog / digital conversion unit ADC, a digital / analog conversion unit DAC, an analog voltage comparison unit ACMP, a reference voltage generation unit VREF, and a temperature sensor unit TJSEN are coupled to the analog bus ABUS. In addition to ADC and DAC, the digital bus DBUS includes a central processing unit CPU, a digital signal processor unit DSP, a debug unit DBG, a PWM signal generation unit (PWM signal generation device) PWMU, a direct memory access control unit DMAC, and a timer. Unit TMR is connected. Further, a memory unit MEMU, a serial communication unit SCU, a system control unit SYSC, and a chip control unit CPC are connected to DBUS.

  The memory unit MEMU includes a flash memory FLASH, a RAM (Random Access Memory), and the like. The serial communication unit SCU includes an SPI (Serial Peripheral Interface), a UART (Universal Asynchronous Receiver Transmitter), an I2C (Inter-Integrated Circuit), and the like. The system control unit SYSC includes an interrupt control circuit INTC, a watchdog timer WDT, and the like. The chip control unit CPC includes a power-on reset circuit POR, a voltage drop detection circuit LVD, an oscillation circuit OSC, a PLL (Phase Locked Loop) circuit, and the like.

  The power supply control using such a semiconductor device (microcontroller) MCU is typically performed as follows, for example. First, the analog / digital conversion unit ADC measures the voltage or current in an external switching power supply circuit (switching transistor, inductor, capacitor, etc.). Next, the digital signal processor unit DSP performs filtering processing of the measurement result. Subsequently, the central processing unit CPU compares the digital data after the filter processing with a predetermined expected value, determines the duty of the PWM signal based on the comparison result, and sets the counter value corresponding to the duty Determine. The PWM signal generation unit (PWM signal generation device) PWMU stores the set value of the counter in a register, and generates a PWM signal for controlling on / off of the switching transistor based on the stored value.

  At this time, in order to control the output power supply voltage generated by the switching power supply circuit with high accuracy, for example, 1.0 ns may be required as the setting resolution of the duty (pulse width) of the PWM signal. On the other hand, depending on the semiconductor manufacturing process of the semiconductor device (microcontroller) MCU, as described above, it is difficult to transfer data between flip-flops via a combinational logic circuit at a frequency of 1 GHz, for example, due to timing constraints. There is. Therefore, it is beneficial to use a PWM signal generation device according to this embodiment to be described later.

<< Overall configuration of PWM signal generator >>
FIG. 2 is a block diagram illustrating a schematic configuration example of a PWM signal generation unit in the semiconductor device of FIG. The PWM signal generation unit (PWM signal generation device) PWMU shown in FIG. 2 includes a clock / pulse signal generation unit CPG, a counter unit CUNT, a plurality (two in this case) of register units REG1 and REG2, and a comparison circuit unit CMP. , A PWM output pattern generation unit PWMPTG and a PWM output generation unit PWMG. The CPG includes a frequency dividing circuit NDIV and a pulse signal generating circuit PGEN. The NDIV receives, for example, a 1 GHz master clock signal CLKm generated by the PLL circuit of FIG. 1, and divides it by N (for example, by 8). Since NDIV does not include a combinational logic circuit in particular, it can operate at CLKm. The PGEN generates a plurality of pulse signals using the clock signal divided by N (for example, divided by 8).

  The counter unit CUNT performs a counting operation in synchronization with the N-divided clock signal (for example, divided by 8) from the frequency dividing circuit NDIV, and outputs the counter value CT. The CUNT is constituted by using, for example, a flip-flop and a combinational logic circuit (one-increment circuit), and here, operates with a clock signal divided by N. As a result, it is possible to relax the timing constraint (simplify timing design). In the register units REG1 and REG2, counter setting values CTH1 and CTH2 for designating the timing at which an event is to be generated, and the event type at that time (for example, transition from 'H' to 'L' level, in the opposite direction) Event setting values EVNT1 and EVNT2 that specify the transition of the The set values of REG1 and REG2 are appropriately updated by the central processing unit CPU in the example of FIG.

  The comparator circuit CMP compares the counter value CT with the counter set values CTH1 and CTH2, and outputs a match signal MT1 when CT and CTH1 match, and outputs a match signal MT2 when CT and CTH2 match. Output. At this time, the counter unit CUNT performs a count operation in units of a cycle N (for example, N = 8) times the master clock signal CLKm, whereas CTH1 and CTH2 have a cycle that is 1 time CLKm. It can be set as a unit. Therefore, CMP subtracts CTH1 (or CT2) from CT, for example, and outputs MT1 (or MT2) including information on the lower 3 bits when the result is zero other than the lower 3 bits. . The information of the lower 3 bits represents which timing among the N timings when a cycle N times (for example, N = 8) times CLKm is divided into N.

  The PWM output pattern generation unit PWMPTG generates PWM pattern data nxpat [n: 0] which is parallel data of (n + 1) bits (for example, (n + 1) = 8) based on the match signals MT1 and MT2 and the event set values EVNT1 and EVNT2. Is generated. The PWM output pattern generation unit PWMPTG uses the N-divided clock signal from the frequency dividing circuit NDIV and a plurality of pulse signals from the pulse signal generating circuit PGEN to generate a PWM signal PWMOUT corresponding to nxpat [n: 0]. Is generated. Schematically, PWMOUT is generated such that nxpat [n: 0] is parallel-serial converted at a cycle of the master clock signal CLKm (for example, 1.0 ns).

  As described above, the PWM signal generation unit (PWM signal generation device) PWMU in FIG. 2 is approximately 1.0 ns in a clock cycle of 1 / N (for example, N = 8) of the master clock signal CLKm of 1 GHz, for example. A system is used in which PWM pattern data for N cycles are collectively generated and this pattern data is serially output with a resolution of 1.0 ns. As a result, only the frequency divider NDIV operates in synchronism with 1.0 GHz CLKm, so that timing constraints can be relaxed (timing design can be facilitated).

<Details of clock / pulse signal generator>
FIG. 3 is a circuit diagram showing a detailed configuration example of the clock / pulse signal generator in FIG. FIG. 4 is a waveform diagram showing an example of a signal generated by the clock / pulse signal generation unit of FIG. In the clock pulse signal generation unit CPG1 of FIG. 3, the frequency divider NDIV1 includes eight stages of flip-flop circuits FF1 cascaded in a ring shape, and each FF1 has one edge (here, the master clock signal CLKm). Operates in synchronization with the rising edge. That is, NDIV1 is an 8-bit cyclic shift register. In this example, as the initial value, one of the “H” level (“1” level) and the “L” level (“0” level) is set in the first four stages of the 8-stage FF1, and the other one is set. The latter four stages are set.

  As a result, as shown in FIG. 4, the master clock signal CLKm having a duty of 50% is divided by 8 (a period (second period) that is eight times the period of CLKm (first period)). Clock signals C [0] to C [7] are generated. C [0], C [1],..., C [7] are output signals of the first, second,..., Eighth stage of the cascaded eight stages of FF1, respectively. Correspondingly, they have different phases in order with the period (first period) of CLKm as a unit.

  In the clock / pulse signal generation unit CPG1 of FIG. 3, the pulse signal generation circuit PGEN1 includes eight AND operation circuits AD1 [n] (n is an integer of 0 to 7) and eight AND operation circuits AD2 [n]. Prepare. Eight AD1 [n] both have two inputs, and the AND of the clock signal C [n] and the inverted signal of C [n + 1] (when (n + 1) ≧ 8, (n + 1) is the remainder of 8). By performing the calculation, a pulse signal S [n] (S [0] to S [7]) is generated. For example, AD1 [0] generates S [0] by performing an AND operation on C [0] and the inverted signal of C [1]. Thereby, as shown in FIG. 4, S [n] (S [0] to S [7]) has the same pulse width as the period (first period) of the master clock signal CLKm, and 8 of CLKm. A period that is twice as long (second period) and a phase that is sequentially different in units of CLKm period (first period).

  The eight AND operation circuits AD2 [n] both have two inputs, and are inverted signals of the clock signal C [n] and C [n + 2] (when (n + 2) ≧ 8, (n + 2) is a remainder of 8). The AND signal is then used to generate a pulse signal S [n, n + 1] (S [0,1], S [1,2],..., S [7,0]). For example, AD2 [0] generates S [0, 1] by performing an AND operation on the inverted signal of C [0] and C [2]. As a result, S [n, n + 1] (S [0, 1], S [1, 2],..., S [7, 0]) is set to the master clock signal CLKm as shown in FIG. It has a pulse width that is twice the period (first period), a period that is eight times CLKm (second period), and the same phase as the pulse signal S [n].

  Here, for example, as shown in Patent Document 2 and the like, by using a circuit similar to the frequency divider NDIV1 in FIG. 3, the pulse signals S [0] to S [7 are obtained by circulating a pulse of 1.0 ns. ] Can also be generated. However, it may be difficult to cycle the 1.0 ns pulse due to the semiconductor manufacturing process. In such a case, it is useful to generate S [0] to S [7] using an AND operation circuit AD1 [n] as shown in FIG.

<< Details of PWM output generator >>
FIG. 5 is a circuit diagram showing a detailed configuration example of the PWM output generation unit in FIG. The PWM output generation unit PWMG1 shown in FIG. 5 includes two pattern data generation circuits PDG1 and PDG2, a phase adjustment circuit PHCTL, two pulse selection circuit units (AND operation circuit units) PSEL1 and PSEL2, and an OR operation circuit. OR1 is provided. PDG1 includes eight flip-flop circuits FF2. Each of the eight FFs 2 has the PWM signal data nxpat [7: 0] (nxpat [0] to nxpat [7]) from the PWM output pattern generation unit PWMPTG of FIG. ] To output pattern data pat [0] to pat [7].

  The pattern data generation circuit PDG2 includes eight AND operation circuits AD3 [n] (n is an integer of 0 to 7) and seven flip-flop circuits FF3. AD3 [x] (x is an integer of 0 to 6) performs an AND operation on the PWM pattern data nxpat [x] and nxpat [x + 1]. For example, AD3 [0] performs an AND operation on nxpat [0] and nxpat [1]. Each of the seven FFs 3 latches the outputs of AD3 [0] to AD3 [6] with the clock signal C [4] shown in FIG. 4, and receives the interpolation pattern data hpat [0] to hpat [6]. Output. Further, AD3 [7] performs an AND operation on the pattern data pat [7] (that is, nxpat [7] one cycle before) and nxpat [0], and outputs the pattern data hpat [7] for interpolation.

  The seven flip-flop circuits FF3 in the pattern data generation circuit PDG2 can prevent glitches that may occur in the outputs of the AND operation circuits AD3 [0] to AD3 [6]. Further, a glitch that may occur at the output of AD3 [7] can be prevented by a flip-flop circuit FF5 [7] in the phase adjustment circuit PHCTL described later. As described above, since the FF3 is provided in the PDG2, the flip-flop circuit FF2 is also provided in the pattern data generation circuit PDG1 in order to align the clock cycles.

  Here, the phase adjustment circuit PHCTL includes five flip-flops FF4 [i] (i is an integer of 3 to 7) and six flip-flops FF5 [j] (j is an integer of 2 to 7). The PHCTL adjusts each phase of the pattern data pat [n] (n is an integer of 0 to 7) using FF4 [i], then outputs the pattern data P [n], and interpolates using FF5 [j]. After adjusting each phase of the pattern data hpat [n] for interpolation, pattern data PH [n, n + 1] for interpolation is output (when (n + 1) ≧ 8, (n + 1) is a remainder of 8).

  Here, the flip-flop FF4 ([3], [4], [5]) has the pattern data pat ([3], [4], [5]) as the clock signal C [0] shown in FIG. ] Is latched (retimed) at the rising edge of the signal and pattern data P ([3], [4], [5]) is output. FF4 ([6], [7]) latches (retiming) pat ([6], [7]) at the rising edge of the clock signal C [4] shown in FIG. , [7]). On the other hand, the flip-flop FF5 ([2], [3], [4], [5]) receives the pattern data hpat ([2], [3], [4], [5]) for interpolation, respectively. Latch (retiming) at the rising edge of C [0], and output pattern data PH ([2, 3], [3,4], [4, 5], [5, 6]) for interpolation. FF5 ([6], [7]) latches (retimates) hpat ([6], [7]) at the rising edge of C [4], and PH ([6, 7], [7 , 0]). The phase adjustment circuit PHCTL outputs pat ([0], [1], [2]) as P ([0], [1], [2]) as it is, and outputs hpat ([0], [1] ]) As it is as PH ([0, 1], [1, 2]).

  The pulse selection circuit unit (AND operation circuit unit) PSEL1 includes eight AND operation circuits AD4 [n] (n is an integer of 0 to 7). AD4 [n] performs an AND operation on the pattern data P [n] and the pulse signal S [n] shown in FIG. 4, and outputs an output pulse signal Sp [n]. For example, AD4 [0] performs an AND operation on P [0] and S [0] and outputs Sp [0]. The pulse selection circuit unit (AND operation circuit unit) PSEL2 includes eight AND operation circuits AD5 [n] (n is an integer of 0 to 7). AD5 [n] is the interpolated pattern data PH [n, n + 1] (when (n + 1) ≧ 8, (n + 1) is a remainder of 8) and the pulse signal S [n, n + 1] shown in FIG. An AND operation is performed to output an output pulse signal Sc [n]. For example, AD5 [0] performs an AND operation on PH [0,1] and S [0,1] and outputs Sc [0].

  Thus, the pulse selection circuit unit (AND operation circuit unit) PSEL1 has a function of selectively outputting the pulse signal S [n] based on the pattern data P [n], and the pulse selection circuit unit (AND operation circuit unit). ) PSEL2 has a function of selectively outputting the pulse signal S [n, n + 1] based on the interpolation pattern data PH [n, n + 1]. The OR operation circuit OR1 includes output pulse signals Sp [0] to Sp [7] selectively output from PSEL1 and output pulse signals Sc [0] to Sc [7] selectively output from PSEL2. An OR operation is performed to generate a PWM signal PWMOUT.

  FIG. 6 is a waveform diagram showing an operation example of the PWM output generation unit of FIG. In the example of FIG. 6, the operation of the clock cycle T = T0 to T3 accompanying the clock signal (C [4]) divided by 8 is shown. Here, “00011111” is input as PWM pattern data nxpat ([0] [1]... [7]) that is parallel data at T = T0, and “11111000” is input at T = T1. The nxpat ([0] [1]... [7]) at T = T0 becomes the pattern data pat ([0] [1]... [7]) at T = T1, and the nxpat ([0] at T = T1). [1]... [7]) becomes pat ([0] [1]... [7]) at T = T2.

  On the other hand, for example, the interpolation pattern data hpat ([0] [1]... [6]) in the clock cycle T = T1 is the PWM pattern data nxpat ([0] [1]... [7] in the clock cycle T = T0. ]) Are determined by successive 2-bit AND operation results. Since nxpat ([0] [1]... [7]) at T = T0 is “00011111”, the AND of the first value (“0”) and the second value (“0”) from the left. Hpat [0] ('0') at T = T1 is determined by the calculation result. Similarly, hpat [1] ('0') is determined by the AND operation result of the second value ('0') and the third value ('0') from the left. Hpat [6] ('1') is determined by the AND operation result of the eighth value ('1') and the eighth value ('1'). Further, the value ('1') of hpat [7] at T = T1 is nxpat [0] ('1') at T = T1 and nxpat [7] at T = T0 (pat [7] at T = T1). ) ('1') is determined by the AND operation result. As described above, the pattern data generation circuit PDG2 shown in FIG. 5 operates when the two consecutive bits (nxpat [n], nxpat [n + 1]) in nxpat are both at the “1” level (“H” level). Output “1” level (“H” level) as [n].

  Here, as shown in FIG. 6, for example, the pattern data pat ([0] [1] [2]) in the clock cycle T = T1 is converted into the clock signal in T = T1 by the phase adjustment circuit PHCTL in FIG. Pattern data P ([0] [1] [2]) is output at the timing of the rising edge of C [4]. Further, pat ([3] [4] [5]) at T = T1 is the rising edge of the clock signal C [0] which is a half cycle after the output timing of P ([0] [1] [2]). Pattern data P ([3] [4] [5]) is output at the edge timing. Further, pat ([6] [7]) at T = T1 is a pattern at the timing of the rising edge of C [4], which is one cycle after the output timing of P ([0] [1] [2]). It is output as data P ([6] [7]).

  In the pattern data P ([0] to [7]) in FIG. 6, the output pulse signal Sp ([0] to [7]) from the pulse selection circuit unit (AND operation circuit unit) PSEL1 in FIG. ) Output timing is shown. For example, Sp [0] is a result of selecting whether or not the pulse signal S [0] is output based on P [0] using the AND operation circuit AD4 [0], and is thus output at the timing of S [0]. Is done. For example, in clock cycle T = T1, since P [0] is “0”, S [0] is not output to Sp [0], and Sp [0] is at the “0” level (“L” level). It becomes. As can be seen from FIG. 6, by using the phase adjustment circuit PHCTL of FIG. 5, the AND operation of S [n] and P [n] is performed by the AND operation circuit AD4 [n] (n is an integer of 0 to 7). A sufficient setup margin / hold margin can be secured. For example, even in the case of Sp [2] in FIG. 6, a hold margin with a pulse width of S [n] (that is, one period (eg, 1.0 ns) of the master clock signal CLKm) is secured.

  Thereby, the timing design of the output pulse signal Sp [n] (n is an integer of 0 to 7) can be facilitated, and Sp [n] can be generated with high accuracy (high resolution). As a comparative example, for example, in the configurations of Patent Document 2 and Patent Document 3, the output timing of the pulse signal S [0] and the output timing of the pattern data P ([0] to [7]) are the same. In this case, for example, if the output timing of P ([0] to [7]) is too early, P ([0] for determining whether or not S ([0] to [7]) is output in the clock cycle T originally. ] To [7]) may cause a problem that a part of whether or not S [7] is output in the previous clock cycle (T-1) is determined. On the other hand, if the output timing of P ([0] to [7]) is too late, P ([0] to [7]) for determining whether or not S ([0] to [7]) is output in the clock cycle T is essentially used. [7]) may cause a problem that a part of whether or not S [0] is output in the subsequent clock cycle (T + 1) is determined.

  On the other hand, by using the phase adjustment circuit PHCTL of FIG. 5, the pattern data P [n is obtained in a state where a sufficient setup time is secured with respect to the output timing of the output pulse signal Sp [n] (n is an integer of 0 to 7). ] Is output, and the output of P [n] is closed while a sufficient hold time is secured. Therefore, as a result, the timing design of Sp [n] can be facilitated, and Sp [n] can be generated with high accuracy (high resolution).

  The interpolation pattern data PH ([0, 1], [1, 2],..., [7, 0] in FIG. 6 is similar to the pattern data P ([0] to [7]). In addition, the output timing of the output pulse signal Sc ([0] to [7]) from the pulse selection circuit unit (AND operation circuit unit) PSEL2 of Fig. 5 is shown. By using this, a setup margin / hold margin when performing an AND operation between the pulse signals S [n, n + 1] and PH [n, n + 1] by the AND operation circuit AD5 [n] (n is an integer of 0 to 7) is used. As a result, the timing design of Sc [n] (n is an integer of 0 to 7) can be facilitated, and Sc [n] can be generated with high accuracy (high resolution). It becomes possible to do.

  In this way, the phase adjustment circuit PHCTL gives the first phase to some bits of the input pattern data, and sets the period of the master clock signal CLKm (reference to the first phase to the other bits). This is to secure a setup margin / hold margin by providing a second phase having a phase difference that is an integral multiple of (first period). Therefore, it is not necessarily limited to the configuration example of FIG. That is, the PHCTL has a configuration in which a setup margin / hold margin of at least one cycle of the master clock signal CLKm is secured by the combination of the flip-flop and the clock signals C [0] to C [7] shown in FIG. If it is.

  For example, the pattern data P ([0], [1]) is used as it is (corresponding to C [4]), and the pattern data P ([2], [3]) is used as the clock signal C [6] and P ([ 4], [5]) can be retimed with C [0], and P ([6], [7]) can be retimed with C [2]. However, when the number of clock signals used is large, control becomes complicated, and for example, setup margin / hold margin when latching pattern data pat [n] and outputting P [n] becomes a problem. There is a fear. From this point of view, it is beneficial to use a configuration using two types of clock signals (C [0], C [4]) as shown in PHCTL in FIG.

  In FIG. 6, the PWM signal PWMOUT output from the OR operation circuit OR1 in FIG. 5 is output by the pulse selection circuit unit (AND operation circuit unit) PSEL1 to the output pulse signal Sp [3] (' Transition to the “H” level at the output timing of 1 ′). Thereafter, the signal transits to the “L” level at the output timing of Sp [5] (“0”) in the clock cycle T = T3. In this PWMOUT 'H' level period, for example, when both Sp [3] and Sp [4] are at '1' level, the output pulse signal Sc [3 is output by the pulse selection circuit unit (AND operation circuit unit) PSEL2. ] Is also at the “1” level. As a result, as will be described below, it is possible to prevent glitches of a minute time that may occur in PWMOUT due to the configuration of PSEL1.

<< Details of pulse selection circuit section (AND operation circuit section) for interpolation >>
FIG. 7A is a diagram illustrating an example of the effect of the pulse selection circuit unit (AND operation circuit unit) for interpolation in FIG. 5, and FIG. 7B is an interpolation example as a comparative example of FIG. 7A. It is a figure which shows an example of a problem in case there is no pulse selection circuit part (AND operation circuit part) for an operation. First, as shown in FIG. 7B, when there is no interpolation pulse selection circuit unit (AND operation circuit unit) PSEL2 in FIG. 5, the pulse selection circuit unit (AND operation circuit unit) PSEL1 is input. Assume that continuous pattern data P [n], P [n + 1] (n is an integer of 0 to 7, and (n + 1) ≧ 8, where (n + 1) is a remainder of 8) are both at the “H” level. To do.

  In this case, the pulse signals S [n] and S [n + 1] are sequentially output by the pulse selection circuit unit (AND operation circuit unit) PSEL1, and the OR operation of the S [n] and S [n + 1] is performed by the OR operation circuit OR1. A PWM signal PWMOUT is generated. However, in this case, for example, when the falling timing of S [n] is earlier than the rising timing of S [n + 1], PSEL1 is in an unselected period between S [n] and S [n + 1]. L 'level is output. As a result, in the PWMOUT, an “L” level glitch occurs when an “H” level output is expected even during the unselected period.

  On the other hand, when the pulse selection circuit unit (AND operation circuit unit) PSEL2 for interpolation is provided, as shown in FIG. 7A, the PSEL2 is accompanied with the 'H' level of the pattern data P [n], P [n + 1]. The pattern data PH [n, n + 1] for interpolation input to is at the “H” level. In this case, the PSEL2 is a pulse signal S [n, n + 1] for interpolation over a period in which the pulse signals S [n] and S [n + 1] are sequentially output by the pulse selection circuit unit (AND operation circuit unit) PSEL1. Is output. As a result, as described in FIG. 7B, even when an unselected period exists between S [n] and S [n + 1], an interpolating pulse signal S for interpolating the unselected period. Since [n, n + 1] is input to the OR operation circuit OR1, it is possible to prevent the occurrence of glitches in the PWM signal PWMOUT. This also reduces the influence of the unselected period between S [n] and S [n + 1], and facilitates timing design.

  FIG. 8A, FIG. 8B, and FIG. 8C are diagrams showing schematic operation examples of each pulse selection circuit unit (AND operation circuit unit) and OR operation circuit in FIG. FIG. 8A shows a case where the PWM signal PWMOUT becomes the “L” level, and FIG. 8B shows a case where the PWMOUT transitions from the “L” level to the “H” level. (C) shows a case where PWMOUT changes from the “H” level to the “L” level.

  In FIG. 8A, the continuous pattern data P [n], P [n + 1] (n is an integer of 0 to 7, and when (n + 1) ≧ 8, (n + 1) is a remainder of 8) are both 'L'. Since it is a level, the pattern data P [n, n + 1] for interpolation is at the “L” level. Accordingly, neither the pulse signals S [n], S [n + 1] and the interpolating pulse signal S [n, n + 1] are input to the OR operation circuit OR1, and the PWM signal PWMOUT is set to the 'L' level. In FIG. 8B, since P [n] is at the 'L' level and P [n + 1] is at the 'H' level, P [n, n + 1] is at the 'L' level. As a result, only S [n + 1] is input to OR1, and PWMOUT transitions from the ‘L’ level to the ‘H’ level at the rising edge of S [n + 1].

  In FIG. 8C, since the pattern data P [n] is at the “H” level and the pattern data P [n + 1] is at the “L” level, the pattern data P [n, n + 1] for interpolation is at the “L” level. It becomes. As a result, only the pulse signal S [n] is input to the OR operation circuit OR1, and the PWM signal PWMOUT changes from the ‘H’ level to the ‘L’ level at the falling timing of the S [n]. As shown in FIG. 7A, when continuous P [n] and P [n + 1] are both at the “H” level, P [n, n + 1] is at the “H” level, and PWMOUT is also set. Becomes 'H' level.

<< Details of PWM output pattern generator >>
FIG. 9 is a circuit block diagram showing a detailed configuration example of the PWM output pattern generation unit in FIG. The PWM output pattern generation unit PWMPTG illustrated in FIG. 9 includes a decoder circuit DEC, a flip-flop circuit FFa, and selection circuits SEL [0] to SEL [7]. SEL [n] (n is an integer of 0 to 7) selects one output from four inputs based on a 2-bit selection signal SE [n] and outputs it as PWM pattern data nxpat [n]. . The output of SEL [0] (nxpat [0]) is two of the four inputs in SEL [1], one of which is the non-inverted data of the output of SEL [0] and the other is the output of SEL [0]. Inverted data. Similarly, the output of SEL [1] (nxpat [1]) is two of the four inputs in SEL [2]. Similarly, the output of SEL [6] (not shown) (nxpat [6]) Becomes two of the four inputs in SEL [7].

  On the other hand, the output (nxpat [7]) of the selection circuit SEL [7] becomes two of the four inputs in the selection circuit SEL [0] via the flip-flop circuit FFa. As described above, the selection circuits SEL [0] to SEL [7] are cascaded, and the output of the final stage (SEL [7]) is the first stage (SEL [0]) via the FFa. It is configured to be returned to. In each SEL [n] (n is an integer of 0 to 7), the output from the previous SEL [n−1] is connected to the two inputs of the four inputs as described above, and the remaining two inputs are A “0” level (“L” level) and a “1” level (“H” level) are input.

  As shown in FIG. 2, the decoder circuit DEC receives the match signals MT1 and MT2 and the 2-bit event setting values EVNT1 and EVNT2, performs decoding, and respectively selects 2-bit selection signals SE [0] to SE [7]. Is output. MT1 includes a flag signal FLG1 and a counter set value CTH1 '. Here, for example, the comparator circuit CMP shown in FIG. 2 subtracts the counter set value CTH1 from the counter value CT, and outputs FLG1 when the other than the lower 3 bits of the result becomes zero. The bit value is output as CTH1 ′. Similarly, via CMP, MT2 also includes a flag signal FLG2 based on the subtraction result of CT and the counter setting value CTH2, and the counter setting value CTH2 ′ that is the value of the lower 3 bits at this time. .

  The decoder circuit DEC receives the position of the selection signals SE [0] to SE [7] that generate an event based on the set value CTH1 ′ (or CTH2 ′) of the counter when the flag signal FLG1 (or FLG2) is input. Determine. For example, SE [0] is targeted when CTH1 ′ = “000”, SE [1] is targeted when CTH1 ′ = “001”, and SE [7] when CTH1 ′ = “111”. Is targeted. Then, the DEC determines the type of event in the target based on the event set value EVNT1 (or EVNT2).

  In the event set value EVNT1 (or EVNT2), as can be understood from the four inputs of the selection circuit SEL [n], the logic level of the previous nxpat [n-1] is set as the logic level of the PWM pattern data nxpat [n]. Can be set (SE [n] = “00”) or the logic level of nxpat [n−1] is inverted (SE [n] = “11”). Further, in EVNT1 (or EVNT2), whether the logic level of nxpat [n] is forcibly set to 'H' level (SE [n] = "10") or forcibly set to 'L' level ( SE [n] = “01”) can be set.

  By using such a PWM output pattern generation unit PWMPTG, it is possible to flexibly set the PWM pattern data nxpat [0] to nxpat [7]. For example, assuming that the default value of the PWM signal PWMOUT is 'L' level, the setting values CTH1 and CTH2 of the counter in FIG. 2 are “x... X001” and “x... X111” (“x. ), And the event set values EVNT1 and EVNT2 are both set to "logical level inversion (toggle)". In this case, the selection signals SE [1] and SE [7] are set to “11” via the decoder circuit DEC of FIG. 9, and the remaining selection signals SE ([0], [2] to [6]). Is set to “00”. As a result, “011... 10” is generated as nxpat ([0] [1] [2]... [6] [7]). For example, PWMOUT having a ‘H’ pulse width of 6.0 ns is generated. For example, if CTH2 is set to “x... X010”, PWMOUT having a ‘H’ pulse width with a minimum resolution (for example, 1.0 ns) can be generated. SE [n] = “01” or “10” can be used, for example, when it is desired to set the logic level of the default value of PWMOUT for the convenience of the user.

  As described above, according to the first embodiment, for example, when the minimum resolution is 1.0 ns, the minimum pulse width is set to 1.0 ns, and the pulse width can be set in increments of 1.0 ns. A signal generation device can be realized, and the timing design at this time can be facilitated. This effect can be achieved, for example, by using a circuit configuration that does not transfer data between flip-flops via a combinational logic circuit at the minimum resolution cycle, by providing a phase adjustment circuit PHCTL, and for interpolation. It is obtained by providing a pulse selection circuit part (AND operation circuit part) PSEL2.

  Further, by using such a PWM signal generation device, it is possible to generate a high-resolution PWM signal without using a state-of-the-art semiconductor manufacturing process, so that it is possible to reduce costs. Further, in FIG. 2, since the circuit other than the frequency divider NDIV operates with a substantially low speed (1 / N) clock signal, power consumption can be reduced. In FIG. 3, the configuration example of the clock / pulse signal generation unit CPG is shown. Of course, the configuration is not limited to the configuration example. The pulse signal S [k] and the interpolation pulse shown in FIG. The signal S [n, n + 1] can be generated using various circuit methods.

(Embodiment 2)
<< Details of Clock / Pulse Signal Generator (Modification [1]) >>
FIG. 10 is a circuit diagram showing a detailed configuration example of the clock / pulse signal generation unit of FIG. 2 in the PWM signal generation device according to the second embodiment of the present invention. In the clock pulse signal generation unit CPG2 of FIG. 10, the frequency divider NDIV2 has the same circuit configuration as the frequency divider NDIV1 shown in FIG. However, in NDIV2, the initial value of the 8-stage flip-flop circuit FF1 is different from NDIV1, and the 'L' level ('0' level) is set in the first to sixth stages, and the seventh and eighth stages. The “H” level (“1” level) is set in the stage.

  Thus, as shown in FIG. 4, the same pulse width (pulse width twice as long as the period of the master clock signal CLKm (first period)) and the same period (period as much as eight times as long as CLKm (second period)). ) And pulse signals S [n, n + 1] (n is an integer of 0 to 7 and (n + 1) ≧ 8 is a remainder of 8 when n is 1) ≧ 8) having different phases in units of the first period. Is done. That is, S [n, n + 1] having a duty of 25% and sequentially having different phases is generated. S [0,1], S [1,2],..., S [7,0] are the first, second,..., Eighth stage of the cascaded 8-stage FF1, respectively. Corresponds to the output signal.

  In the clock / pulse signal generation unit CPG2 of FIG. 10, the pulse signal generation circuit PGEN2 includes eight AND operation circuits AD6 [n] (n is an integer of 0 to 7). Eight AD6 [n] have two inputs, and when the pulse signals S [n, n + 1] and S [n + 1, n + 2] ((n + 1) and (n + 2) are 8 or more, (n + 1) and ( n + 2) performs an AND operation with an inverted signal of the remainder of 8) to generate a pulse signal S [n] (S [0] to S [7]). For example, AD6 [0] generates S [0] by performing an AND operation on S [0,1] and an inverted signal of S [1,2].

  When the clock / pulse signal generation unit CPG2 as shown in FIG. 10 is used, the number of AND operation circuits is reduced as compared with the case where the clock / pulse signal generation unit CPG1 of FIG. 3 is used, so that the circuit scale can be reduced. As a result, the load connected to the node C [n] in FIG. 3 (S [n, n + 1] in FIG. 10) is reduced, so that the waveform quality of the pulse signals S [0] to S [7] is reduced. It becomes easy to secure. However, in the configuration example of FIG. 10, there is a possibility that a skew is generated between the pulse signal S [n, n + 1] for interpolation and the pulse signal S [n] by the delay of the AND operation circuit AD6 [n]. . From the viewpoint of reducing the skew, a configuration example as shown in FIG. 3 is desirable. In the configuration example of FIG. 10, unlike the case of FIG. 3, the clock signal C [n] is not generated, but C [n] can be substituted by, for example, S [n, n + 1].

(Embodiment 3)
<< Details of Clock / Pulse Signal Generation Unit (Modification [2]) >>
FIG. 11 is a circuit diagram showing a detailed configuration example of the clock / pulse signal generation unit of FIG. 2 in the PWM signal generation device according to Embodiment 3 of the present invention. The clock / pulse signal generation unit CPG3 of FIG. 11 has a configuration in which eight flip-flop circuits FF6 are added to the pulse signal generation circuit PGEN3 as compared with the clock / pulse signal generation unit CPG2 of FIG. The eight FFs 6 respectively output the pulse signals S [0] to S [7] by latching the output signals of the AND operation circuits AD6 [0] to AD6 [7] at the rising edge of the master clock signal CLKm. .

  Compared to the configuration example of FIG. 10, the configuration example of FIG. 11 is easier to secure the waveform quality of the pulse signals S [0] to S [7] through the flip-flop circuit FF6. The skew between [0] and S [7] is also easily reduced. However, the configuration example of FIG. 11 is based on the premise that data transfer between flip-flop circuits via a small-scale combinational logic circuit (here, an AND operation circuit) can be performed at high speed (for example, at 1 GHz). When it is difficult, the configuration example as shown in FIG. 10 or FIG. 3 is more desirable.

(Embodiment 4)
<< Details of Clock / Pulse Signal Generation Unit (Modification [3]) >>
FIG. 12A is a circuit diagram showing a detailed configuration example of the clock / pulse signal generation unit of FIG. 2 in the PWM signal generation device according to the fourth embodiment of the present invention, and FIG. It is a wave form diagram which shows a part of operation example of 12 (a). The clock / pulse signal generation unit CPG4 shown in FIG. 12A includes two frequency dividing circuits NDIV4a and NDIV4b and a pulse signal generation circuit PGEN4.

  The frequency divider NDIV4a includes four stages of flip-flop circuits FF7 cascaded in a ring shape, and each FF7 is synchronized with the falling edge of the master clock signal CLKm2 (the rising edge of the inverted signal (/ CLKm2) of CLKm2). Works. On the other hand, the frequency dividing circuit NDIV4b also includes four stages of flip-flop circuits FF8 cascaded in a ring shape, and each FF8 operates in synchronization with the rising edge of CLKm2 unlike the FF7. Also, as the initial value of FF7, 'L' level ('0' level) is set to the first to third stages of the four stages of FF7, and 'H' level ('1' is set to the fourth stage. 'Level) is set. Similarly, 'L' level ('0' level) is set to the first to third stages of the four stages of FF8 as the initial value of FF8, and 'H' level (' 1 'level) is set.

  Here, the master clock signal CLKm2 has, for example, a half frequency of the master clock signal CLKm described in each of the embodiments so far. For example, when CLKm is 1 GHz, CLKm2 has a frequency of 500 MHz. Accordingly, the interpolation pulse signals S [1,2], S shown in FIG. 4 are respectively obtained from the first stage, the second stage, the third stage, and the fourth stage of the flip-flop circuit FF7 in the frequency divider NDIV4a. [3,4], S [5,6], S [7,0] can be generated. Further, the interpolation pulse signals S [0, 1] and S [shown in FIG. 4 are respectively shown from the first stage, the second stage, the third stage, and the fourth stage of the flip-flop circuit FF8 in the frequency divider NDIV4b. 2,3], S [4,5], S [6,7] can be generated.

  The pulse signal generation circuit PGEN4 includes eight AND operation circuits AD7 [0] to AD7 [7]. AD7 [k] (k = 1, 3, 5, 7) is the case where the inverted signal (/ CLKm2) of the master clock signal CLKm2 and the interpolating pulse signal S [k, k + 1] ((k + 1) ≧ 8, respectively) And (k + 1) is a remainder of 8) to generate the pulse signal S [k]. For example, AD7 [1] generates S [1] by performing an AND operation on / CLKm2 and S [1,2] as shown in FIG. On the other hand, each of AD7 [m] (m = 0, 2, 4, 6) performs an AND operation on CLKm2 and the interpolating pulse signal S [m, m + 1] to obtain the pulse signal S [m]. Generate. For example, AD7 [0] generates S [0] by performing an AND operation on CLKm2 and S [0, 1] as shown in FIG.

  In the configuration example of FIG. 12A, compared with the configuration examples as shown in FIGS. 3, 10, and 11, the pulse signal S [n] and the interpolation signal are used by using half the frequency (for example, 500 MHz). Since the pulse signal S [n, n + 1] can be generated, the timing design can be simplified and the power consumption can be reduced. However, the configuration example of FIG. 12A is based on the premise that the duty of the master clock signal CLKm2 is 50%. Otherwise, as shown in FIG. 3, FIG. 10, and FIG. The configuration example is preferable.

(Embodiment 5)
<< Details of PWM Output Generator (Modification [1]) >>
FIG. 13 is a circuit diagram showing a detailed configuration example of the PWM output generation unit in FIG. 1 in the PWM signal generation device according to the fifth embodiment of the present invention. The PWM output generation unit PWMG2 shown in FIG. 13 includes two pattern data generation circuits PDG3 and PDG4, a phase adjustment circuit PHCTL, two pulse selection circuit units (AND operation circuit units) PSEL1 and PSEL2, and an OR operation circuit OR1 is provided. Among these, the configuration of PHCTL, PSEL1, PSEL2, and OR1 is the same as that of the PWM output generation unit PWMG1 of FIG.

  The pattern data generation circuit PDG3 includes eight AND operation circuits AD8 [n] (n is an integer of 0 to 7), seven flip-flop circuits FF9, and two flip-flop circuits FF2 [6] and FF2 [ 7]. FF2 [6] and FF2 [7] latch the PWM pattern data nxpat [6] and nxpat [7] at the rising edge of the clock signal C [4], respectively, and the pattern data pat [6] and pat [7]. Is output. AD8 [0] performs an AND operation on the inverted data of pat [7], nxpat [0], and the inverted data of nxpat [1]. AD8 [p] (p is an integer of 1 to 6) performs an AND operation on the inverted data of nxpat [p-1], nxpat [p], and inverted data of nxpat [p + 1]. For example, AD8 [1] performs an AND operation on the inverted data of nxpat [0], the inverted data of nxpat [1], and the inverted data of nxpat [2]. AD8 [7] performs an AND operation on the inverted data of pat [6], pat [7], and the inverted data of nxpat [0] to generate pattern data patA [7]. The seven FFs 9 latch the outputs of AD8 [0] to AD8 [6] at the rising edge of C [4], and generate pattern data patA [0] to patA [6].

  The pattern data generation circuit PDG4 includes eight AND operation circuits AD9 [n] (n is an integer of 0 to 7) and six flip-flop circuits FF3. AD9 [q] (q is an integer of 0 to 5) performs an AND operation on the PWM pattern data nxpat [q] and nxpat [q + 1]. For example, AD9 [0] performs an AND operation on nxpat [0] and nxpat [1]. Each of the six FFs 3 latches the outputs of AD9 [0] to AD9 [5] at the rising edge of the clock signal C [4], and generates pattern data for interpolation hpat [0] to hpat [5]. . AD9 [6] performs an AND operation on the pattern data pat [6] and pat [7] to generate hpat [6]. AD9 [7] performs an AND operation on pat [7] and nxpat [0] to generate hpat [7]. The phase adjustment circuit PHCTL receives the pattern data patA [0] to patA [7] from the pattern data generation circuit PDG3 and the pattern data hpat [0] to hpat [7] for interpolation from the PDG4. Works as well.

  Thus, in the pattern data generation circuit PDG3, the PWM pattern data of interest (for example, nxpat [1]) is at the “1” level, and the PWM pattern data before and after that (nxpat [0], nxpat [2]) are both “ When the level is 0, the pattern data (patA [1]) corresponding to the PWM pattern data of interest is driven to the level “1”. That is, when the PDG 3 receives the adjacent 3-bit “010” in the PWM pattern data and outputs the PWM signal PWMOUT having the pulse width of the minimum resolution (for example, 1.0 ns), the PDG 3 corresponds to the output timing. The pattern data patA [n] is driven to the “1” level.

  On the other hand, in the pattern data generation circuit PDG4, similarly to the PDG2 in FIG. 5, the PWM pattern data of interest (for example, nxpat [0]) is at the “1” level, and the subsequent PWM pattern data (nxpat [1]) is also “1”. When it is at the “level”, the pattern data (hpat [0]) corresponding to the PWM pattern data of interest is driven to the “1” level. That is, the PDG 4 receives the adjacent two bits “11” in the PWM pattern data and outputs a PWM signal PWMOUT having a pulse width (for example, 2.0 ns or more) that is twice or more the minimum resolution. The interpolation pattern data hpat [n] corresponding to the timing to be driven is driven to the “1” level. The PDG4 differs from the PDG2 in that it generates hpat [6] directly from the output of the AND operation circuit AD9 [6], but it is a difference between latching after the AND operation and performing AND operation after the latch. Substantial operation is the same.

  By using such a PWM output generation unit PWMG2, as in the case of the PWM output generation unit PWMG1 of FIG. 5, a PWM signal PWMOUT having a minimum resolution pulse width can be generated, and the pulse width can be set in increments of the minimum resolution. It becomes possible to set with. In this case, as in the case of FIG. 5, for example, high resolution (for example, 1.0 ns) can be achieved without using a state-of-the-art semiconductor manufacturing process. Further simplification may be achieved.

  That is, in the configuration example of FIG. 5, it is necessary to consider the skew between the pulse signal S [n] and the pulse signal S [n, n + 1] for interpolation. Specifically, in FIG. 5, for example, when generating a PWM signal PWMOUT having a pulse width of 2.0 ns or more, interpolation is performed using S [0, 1] for S [0], S [1]. Therefore, it is necessary to suppress the skew of S [0, 1] with respect to S [0], S [1] within, for example, half of the minimum resolution (for example, 0.5 ns). On the other hand, in the configuration example of FIG. 13, for example, when generating PWMOUT having a pulse width of 2.0 ns or more, only S [n, n + 1] whose half cycle originally overlapped (already in an interpolation relationship) Is used to generate PWMOUT. For this reason, from the viewpoint of interpolation, the skew between S [n] and S [n, n + 1] is not particularly affected, and adjacent S [n, n + 1] need only overlap. , S [n, n + 1] can tolerate a skew of up to 1.0 ns, for example. Note that the effect of providing the phase adjustment circuit PHCTL and the effect of interpolating the pulse signal are the same as in the case of FIG.

(Embodiment 6)
<< Details of PWM Output Generator (Modification [2]) >>
FIG. 14 is a circuit diagram showing a detailed configuration example of the PWM output generation unit in FIG. 1 in the PWM signal generation apparatus according to the sixth embodiment of the present invention. The PWM output generation unit PWMG3 shown in FIG. 14 includes two pattern data generation circuits PDG1 and PDG5, a phase adjustment circuit PHCTL ′, two pulse selection circuit units (AND operation circuit units) PSEL3 and PSEL4, and a pulse width. A change circuit PCL and an OR operation circuit OR2 are provided. Among these, the configuration of the PDG 1 is the same as in FIG.

  The pattern data generation circuit PDG5 includes eight AND operation circuits AD10 [n] (n is an integer of 0 to 7) and seven flip-flop circuits FF10. AD10 [x] (x is an integer of 0 to 6) performs an AND operation on the PWM pattern data nxpat [x] and the inverted data of nxpat [x + 1]. For example, AD10 [0] performs an AND operation on nxpat [0] and the inverted data of nxpat [1]. Each of the seven FFs 10 latches the outputs of AD10 [0] to AD10 [6] with the clock signal C [4] shown in FIG. 4, and changes pattern data cpat [0] to cpat [6]. Output. Further, AD10 [7] performs an AND operation on the pattern data pat [7] (that is, nxpat [7] one cycle before) from the pattern data generation circuit PDG1 and the inverted data of nxpat [0] for change. Pattern data cpat [7] is output.

  The phase adjustment circuit PHCTL ′ includes six flip-flops FF4 [i] (i is an integer of 2 to 7) and seven flip-flops FF5 [j] (j is an integer of 1 to 7). PHCTL ′ uses FF4 [i] to adjust each phase of the pattern data pat [n] (n is an integer of 0 to 7) from the pattern data generation circuit PDG1, and then outputs the pattern data P [n]. In addition, PHCTL ′ adjusts each phase of the pattern data cpat [n] for change using FF5 [j] and then changes pattern data PC [n, n + 1] ((n + 1) ≧ 8 when ( n + 1) outputs a remainder of 8).

  In the flip-flop FF4 ([2], [3], [4], [5]), the pattern data pat ([2], [3], [4], [5]) is shown in FIG. Latching (retiming) is performed at the rising edge of the clock signal C [0], and pattern data P ([2], [3], [4], [5]) is output. FF4 ([6], [7]) latches (retiming) pat ([6], [7]) at the rising edge of the clock signal C [4] shown in FIG. , [7]). On the other hand, the flip-flop FF5 ([1], [2], [3], [4]) receives the change pattern data cpat ([1], [2], [3], [4]), respectively. Latch (retiming) at the rising edge of C [0], and change pattern data PC ([1,2], [2,3], [3,4], [4,5]) is output. FF5 ([5], [6], [7]) latches (retimates) cpat ([5], [6], [7]) at the rising edge of C [4], and PC ( [5, 6], [6, 7], [7, 0]) are output. The phase adjustment circuit PHCTL ′ outputs pat ([0], [1]) as it is as P ([0], [1]), and outputs cpat [0] as it is as PC [0, 1]. .

  The function of the phase adjustment circuit PHCTL 'is the same as that of the phase adjustment circuit PHCTL in FIG. However, the PHCTL in FIG. 5 sets up a setup margin for each pulse signal for the pulse signal S [n] having a pulse width with the minimum resolution and the pulse signal S [n, n + 1] having a pulse width twice that of the pulse signal S [n]. / PHmar 'has been defined, but PHCTL' covers only S [n, n + 1], as will be described in detail later. Further, for example, the pulse signal corresponding to the pattern data pat [0] is S [0,1], whereas the pulse signal corresponding to the pattern data cpat [0] for change is S [1,2]. As described above, the correspondence (phase relationship) between the pattern data and the pulse signal is also different.

  Therefore, the phase adjustment circuit PHCTL ′ uses the same number of clock signals (two C [0] and C [4]) as compared with the phase adjustment circuit PHCTL in FIG. A circuit is added or a part of a clock signal assigned to the flip-flop circuit is changed. As a result, both the minimum resolution (for example, 1.0 ns) or more are secured as the setup margin / hold margin. As described above, the configuration of the phase adjustment circuit can be changed as appropriate according to the phase, pulse width, and the like of the target pulse signal.

  The pulse selection circuit unit (AND operation circuit unit) PSEL3 includes eight AND operation circuits AD11 [n] (n is an integer of 0 to 7). AD11 [n] performs an AND operation on the pattern data P [n] and the pulse signal S [n, n + 1] (when (n + 1) ≧ 8, (n + 1) is a remainder of 8). In other words, PSEL3 selectively outputs S [n, n + 1] based on P [n]. For example, AD11 [0] selectively outputs S [0,1] based on P [0] by performing an AND operation on P [0] and S [0,1].

  The pulse selection circuit unit (AND operation circuit unit) PSEL4 includes eight AND operation circuits AD12 [n] (n is an integer of 0 to 7). AD12 [n] is a pattern data for change PC [n, n + 1] (when (n + 1) ≧ 8, (n + 1) is a remainder of 8) and pulse signal S [n + 1, n + 2] ((n + 2) ≧ 8 (N + 2) is a remainder of 8). In other words, the PSEL 4 selectively outputs S [n + 1, n + 2] based on PC [n, n + 1]. For example, AD12 [0] selectively outputs S [1,2] based on PC [0,1] by performing an AND operation between PC [0,1] and S [1,2]. To do.

  The pulse width changing circuit PCL includes eight AND operation circuits AD13 [n] (n is an integer of 0 to 7). AD13 [n] performs an AND operation on the output signal of the AND operation circuit AD11 [n] and the inverted output signal of the AND operation circuit AD12 [n], and outputs an output pulse signal So [n]. For example, AD13 [0] performs an AND operation on the output signal of AD11 [0] and the inverted output signal of AD12 [0], and outputs So [0]. The OR operation circuit OR2 generates the PWM signal PWMOUT by performing an OR operation of So [0] to So [7].

  In such a configuration example, the pulse selection circuit unit (AND operation circuit unit) PSEL3 differs from PSEL1 in FIG. 5 based on the pattern data P [n], for example, twice the minimum resolution (for example, 2.0 ns). A pulse signal S [n, n + 1] having a pulse width is selectively output. Here, as in the case of the fifth embodiment, S [n, n + 1] originally has a half cycle overlapping (already in an interpolating relationship), so that interpolation is performed as in the case of FIG. There is no need to provide a separate circuit. Further, since adjacent S [n, n + 1] have a phase difference with a minimum resolution, the pulse width of the PWM signal PWMOUT is set to the minimum resolution based on P [n] (PWM pattern data nxpat [n]). It is possible to vary. However, in this case, the pulse width is always expanded by an extra 1.0 ns, and the minimum pulse width that can be set is also twice the minimum resolution (for example, 2.0 ns).

  Therefore, by providing the pulse selection circuit unit (AND operation circuit unit) PSEL4 and the pulse width change circuit PCL, an excessive expansion (for example, 1.0 ns) of the pulse width is cut, and the minimum value of the pulse width is minimized. The resolution (for example, 1.0 ns) can be set. FIG. 15 is a waveform diagram showing a main operation example in a part of the PWM output generation unit of FIG. In the example of FIG. 15, “110...” Is input as the PWM pattern data nxpat ([0] [1] [2]...) At the clock cycle T = T0, and the pattern data pat ([[ 0] [1] [2] ...) is "110 ...". In accordance with “110...” Of the pat ([0] [1] [2]...), AND operation circuits AD11 [0] and AD11 [1] in the pulse selection circuit unit (AND operation circuit unit) PSEL3 are Pulse signals S [0, 1] and S [1, 2] are output, respectively.

  On the other hand, in response to “110...” Of the PWM pattern data nxpat ([0] [1] [2]...) In the clock cycle T = T0, the pattern data cpat ([0] for change is used in the clock cycle T = T1. [010] is output as [1] [2]. In response to this, the AND operation circuit AD12 [0] in the pulse selection circuit unit (AND operation circuit unit) PSEL4 outputs the '0' level, and AD12 [1] outputs the pulse signal S [2, 3]. . As a result, the AND operation circuit AD13 [0] in the pulse width changing circuit PCL outputs the pulse signal S [0, 1] as the output pulse signal So [0]. On the other hand, since AD13 [1] in the PCL performs an AND operation on S [1,2] and the inverted signal of S [2,3], as shown in FIG. An output pulse signal So [1] having a pulse width of the minimum resolution (for example, 1.0 ns) is generated after the latter half (for example, 1.0 ns) of the pulses are deleted.

  As described above, the pulse width changing circuit PCL receives the pulse signal S [n, n + 1] selectively output from the pulse selection circuit unit (AND operation circuit unit) PSEL3 and receives a predetermined S [u, u + 1] therein. ], It has a function of reducing the pulse width of S [u, u + 1] in half by performing a logical operation with S [u + 1, u + 2] whose phase is different by half of the pulse width. Then, a pulse signal excluding S [u, u + 1] as a target from pulse signals S [n, n + 1] selectively output from PSEL3, and S [u, u + 1] whose pulse width is reduced. Output toward the OR operation circuit OR2.

  As a result, when the PWM signal PWMOUT falls in accordance with the PWM pattern data nxpat [n] (that is, when the value of two adjacent bits in nxpat [n] becomes “10”), as shown in FIG. This makes it possible to cut off an excessively enlarged pulse width (for example, 1.0 ns). Further, as can be seen from FIG. 15, if “010...” Is input as PWM pattern data nxpat ([0] [1] [2]...), Only the output pulse signal So [1] is output as PWMOUT. Therefore, the minimum value of the pulse width can be set to the minimum resolution (for example, 1.0 ns).

  By using such a PWM output generation unit PWMG3, as in the case of the PWM output generation unit PWMG1 in FIG. 5 and the like, a PWM signal PWMOUT having a minimum resolution pulse width can be generated, and the pulse width can be reduced to a minimum resolution. It becomes possible to set in increments. In this case, as in the case of FIG. 5 and the like, for example, high resolution (for example, 1.0 ns) can be achieved without using a state-of-the-art semiconductor manufacturing process, and the phase adjustment circuit PHCTL ′ and the mechanism of the interpolation This facilitates the timing design.

  Furthermore, in the configuration example of FIG. 14, compared with the configuration examples of FIG. 5 and FIG. 13, a pulse signal (that is, pulse signal S [n]) having a pulse width of the minimum resolution (for example, 1.0 ns) is not used. The setting with the minimum resolution can be realized using only a pulse signal having a pulse width twice as large as the minimum resolution (for example, 2.0 ns) (that is, pulse signal S [n, n + 1]). As a result, the number of pulse signals to be used is reduced, and the pulse width of the pulse signals is increased, so that the timing design can be further facilitated. Further, there is a case where the circuit area can be reduced in the PWM signal generation device because S [n] becomes unnecessary.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. For example, the above-described embodiment has been described in detail for easy understanding of the present invention, and is not necessarily limited to one having all the configurations described. Further, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. . In addition, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.

  For example, FIG. 1 shows an example in which the PWM signal generation device according to the present embodiment is applied for control of a switching power supply device. However, for example, for control of a motor device or for dimming control of an LED device. The present invention can be widely applied to all products using PWM signals. Further, the present invention is not limited to the application to the PWM signal, but can be applied as a technique for performing parallel / serial conversion with high accuracy in some cases.

  In addition, here, an example of generating the PWM signal of the “H” pulse has been shown, but it is of course applicable to the case of generating the PWM signal of the “L” pulse. In this case, for example, the type and polarity of the logic operation circuit (AND operation circuit or OR operation circuit) shown in each embodiment may be changed as appropriate. Further, here, an example of 8 is shown as the number of bits of the PWM pattern data nxpat [n: 0] and the frequency division number “N” of the frequency divider NDIV. However, of course, the value is not limited to this value, and may be a value of 2 or more in principle, and is typically a power of 2 such as 2, 4, 8, 16,.

ABUS Analog bus ACMP Analog voltage comparison unit AD AND operation circuit ADC Analog / digital conversion unit C Clock signal CLKm Master clock signal CMP Comparison circuit unit CPC Chip control unit CPG Clock / pulse signal generation unit CPU Central processing unit CT Counter value CTH , CTH 'counter setting value CUNT counter unit DAC digital / analog conversion unit DBG debug unit DBUS digital bus DEC decoder circuit DMAC direct memory access control unit DSP digital signal processor unit EVNT event setting value FF flip-flop circuit GPIO interface unit INTC interrupt control Circuit LVD Voltage drop detection circuit MCU Semiconductor equipment (Microcontroller)
MEMU Memory Unit MT Match Signal NDIV Divider Circuit OPAMP Operational Amplifier Unit OR OR Operation Circuit OSC Oscillator Circuit PCL Pulse Width Change Circuit PDG Pattern Data Generation Circuit PGEN Pulse Signal Generation Circuit PHCTL, PHCTL 'Phase Adjustment Circuit POR Power On Reset Circuit PSEL Pulse Select Circuit part (AND operation circuit part)
PWMG PWM output generation unit PWMOUT PWM signal PWMPTG PWM output pattern generation unit PWMU PWM signal generation unit (PWM signal generation device)
REG register section S pulse signal SCU serial communication unit SEL selection circuit SE selection signal SYSC system control unit TJSEN temperature sensor unit TMR timer unit VREF reference voltage generation unit WDT watchdog timer cpat, pat, patA, hpat, P, PH, PC pattern Data nxpat PWM pattern data

Claims (12)

N first pulse signals [n] each having the same pulse width, a second period N (N is an integer greater than or equal to 2) times the first period, and phases sequentially different in units of the first period. A signal generation circuit for generating (n = 1, 2,..., N);
N-bit parallel data that is updated every second period, and first pattern data that respectively sets the logic level of the PWM signal in the N interval in the second period;
A phase adjustment circuit that receives the first pattern data, adjusts the phase of each bit, and then outputs N-bit second pattern data;
N AND operation circuits to which the second pattern data and the N first pulse signals [n] are input are included, and each of the N first pulse signals [n] is used as the second pattern data. A first AND operation circuit portion that selectively outputs based on the first AND operation circuit portion;
An OR operation circuit that performs an OR operation using the output from the first AND operation circuit unit as an input, and outputs the PWM signal according to the first pattern data;
The phase adjustment circuit outputs a part of the bits of the second pattern data in a first phase, and outputs the other part of the bits of the second pattern data in the first period with reference to the first phase. A PWM signal generation device that outputs in a second phase having a phase difference of M (M is an integer of 1 to (N-1)) times. The PWM signal generation device according to claim 1,
The N first pulse signals [n] have a pulse width of the first period,
The PWM signal generation device further includes a second AND operation circuit unit,
In addition to the output of the first AND operation circuit unit, the OR operation circuit further performs an OR operation using the output of the second AND operation circuit unit as an input,
The signal generation circuit further includes N second pulses having a pulse width twice as long as the first period, and the second period, each having the same phase as the N first pulse signals [n]. Generating a pulse signal [n],
The second AND operation circuit unit includes N AND operation circuits to which the N second pulse signals [n] are input, and the first AND operation circuit unit includes the first pulse signal [k] (k Is an integer from 1 to N) and a PWM signal generator that outputs the second pulse signal [k] when the first pulse signal [k + 1] is sequentially output. The PWM signal generation device according to claim 2,
A first pattern data generation circuit for detecting a case in which two adjacent bits in the first pattern data are both at the first logic level and generating N-bit third pattern data based on the detection result;
The phase adjustment circuit further receives the third pattern data, adjusts the phase of each bit, and then outputs N-bit fourth pattern data,
The fourth pattern data is a PWM signal generation device that is input to the N AND operation circuits in the second AND operation circuit unit. The PWM signal generation device according to claim 3, wherein
The second phase and the first phase have a phase difference corresponding to a half cycle of the second cycle,
The PWM signal generation device, wherein the phase adjusting circuit gives the first phase to some bits of the second pattern data and gives the second phase to all the remaining bits except the some bits. The PWM signal generation device according to claim 1,
The N first pulse signals [n] are PWM signal generation devices having a pulse width twice as large as the first period. The PWM signal generation device according to claim 5, wherein
A third AND operation circuit unit;
In addition to the output of the first AND operation circuit unit, the OR operation circuit further performs an OR operation using the output of the third AND operation circuit unit as an input,
The signal generation circuit may further include N third pulse signals [having a pulse width of the first period, a second period, and the same phase as the N first pulse signals [n], respectively. n],
The first AND operation circuit unit is configured to select a predetermined one of the N first pulse signals [n] when causing the OR operation circuit to output the PWM signal having a pulse width more than twice the first period. The first pulse signal [n] of
The third AND operation circuit unit includes N AND operation circuits to which the N third pulse signals [n] are input, and the PWM signal having the pulse width of the first period in the OR operation circuit. A PWM signal generation device that outputs a predetermined one of the N third pulse signals [n]. The PWM signal generation device according to claim 6, wherein
The case where the adjacent three bits in the first pattern data are sequentially the first logic level, the second logic level, and the first logic level is detected, and N-bit fifth pattern data is generated based on the detection result. A second pattern data generation circuit;
The phase adjustment circuit further receives the fifth pattern data, adjusts the phase of each bit, and then outputs N-bit sixth pattern data,
The sixth pattern data is a PWM signal generation device that is input to the N AND operation circuits in the third AND operation circuit unit. The PWM signal generation device according to claim 5, further comprising:
A fourth AND operation circuit unit;
The first pulse signal [k] in the first pulse signal [n] inserted between the first AND operation circuit unit and the OR operation circuit and selectively output from the first AND operation circuit unit. (K is an integer of 1 to N), the pulse width is reduced, the first pulse signal [n] excluding the first pulse signal [k], and the first pulse signal [ k] and a pulse width changing circuit for outputting to the OR operation circuit,
The fourth AND operation circuit unit includes N AND operation circuits to which the N first pulse signals [n] are input, and the pulse width changing circuit has a pulse width of the first pulse signal [k]. The first pulse signal [k + 1] is output when
The pulse width changing circuit performs a logical operation on the first pulse signal [k] from the first AND operation circuit unit and the first pulse signal [k + 1] from the fourth AND operation circuit unit. A PWM signal generator for reducing a pulse width of the first pulse signal [k]. The PWM signal generation device according to claim 8, wherein
A third pattern data generation circuit that detects a case where two adjacent bits in the first pattern data are sequentially at a first logic level and a second logic level, and generates N-bit seventh pattern data based on the detection result Further comprising
The phase adjustment circuit further receives the seventh pattern data, adjusts the phase of each bit, and then outputs N-bit eighth pattern data,
The eighth pattern data is a PWM signal generation device that is input to the N AND operation circuits in the fourth AND operation circuit unit. N pieces each having a second period N (N is an integer greater than or equal to 2) times the first period, a pulse width twice the first period, and different phases in order of the first period. A signal generation circuit for generating a first pulse signal [n] (n = 1, 2,..., N);
N-bit parallel data that is updated every second period, and first pattern data that respectively sets the logic level of the PWM signal in the N interval in the second period;
A pattern data generation circuit for detecting a case where two adjacent bits in the first pattern data are sequentially at a first logic level and a second logic level, and generating N-bit third pattern data based on the detection result;
After receiving the first pattern data and adjusting the phase of each bit, the second pattern data of N bits is output, and after receiving the third pattern data and adjusting the phase of each bit, the fourth pattern data of N bits A phase adjustment circuit that outputs
A first selection circuit that selectively outputs each of the N first pulse signals [n] based on the second pattern data;
A second selection circuit unit that selectively outputs each of the N first pulse signals [n] based on the fourth pattern data;
The first pulse signal [n] selectively output from the first selection circuit unit is received, and the first pulse signal [k] (k is an integer of 1 to N) in the first pulse signal [n]. ), By performing a logical operation using the first pulse signal [k + 1] from the second selection circuit unit , the pulse width of the first pulse signal [k] is reduced from twice the first period. A pulse width change circuit that outputs the first pulse signal [n] except for the first pulse signal [k], and the first pulse signal [k] with the pulse width reduced, which is reduced in the first period. When,
OR operation with the output from the pulse width changing circuit as input, and OR operation circuit for outputting the PWM signal according to the first pattern data;
Equipped with a,
The phase adjustment circuit outputs a part of the bits of the second pattern data in a first phase, and outputs the other part of the bits of the second pattern data in the first period with reference to the first phase. M (M is an integer of 1 to (N-1)) times as a second phase having a phase difference, a part of bits of the fourth pattern data is output in the first phase, and the fourth pattern Outputting some other bits of data in the second phase;
PWM signal generator. N first pulses each having a pulse width of the first period, a second period N (N is an integer greater than or equal to 2) times the first period, and different phases in order of the first period. The same as the signal [n] (n = 1, 2,..., N), the pulse width twice the first period, the second period, and the N first pulse signals [n], respectively. A signal generation circuit for generating N second pulse signals [n] having a phase;
N-bit parallel data that is updated every second period, and first pattern data that respectively sets the logic level of the PWM signal in the N interval in the second period;
A pattern data generation circuit that detects a case in which two adjacent bits in the first pattern data are both at the first logic level, and generates N-bit second pattern data based on the detection result;
The first pattern data is received, the phase of each bit is adjusted, N-bit third pattern data is output, the second pattern data is received, the phase of each bit is adjusted, and then the N-bit fourth pattern data A phase adjustment circuit that outputs
A first selection circuit that selectively outputs each of the N first pulse signals [n] based on the second pattern data;
Second selection for outputting the second pulse signal [k] when the first selection circuit unit sequentially outputs the first pulse signal [k] (k is an integer of 1 to N) and the first pulse signal [k + 1]. A circuit section;
An OR operation circuit that performs an OR operation using outputs from the first and second selection circuit units as inputs, and outputs the PWM signal according to the first pattern data ;
With
The phase adjustment circuit outputs a part of the bits of the third pattern data in a first phase, and outputs the other part of the bits of the third pattern data in the first period based on the first phase. M (M is an integer of 1 to (N-1)) times as a second phase having a phase difference, a part of bits of the fourth pattern data is output in the first phase, and the fourth pattern Outputting some other bits of data in the second phase;
PWM signal generator. The PWM signal generation device according to claim 11 ,
The second phase and the first phase have a phase difference corresponding to a half cycle of the second cycle,
The phase adjusting circuit gives the first phase to a part of the bits of the third pattern data, and gives the second phase to all the remaining bits except the part of the fourth pattern data. A part of the bits having the first phase, and the remaining bits other than the part of the bits have the second phase.

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