JP6085460B2 - Hall element and manufacturing method thereof - Google Patents

Description

  The present invention relates to a Hall element and a manufacturing method thereof, and more particularly, to a Si monolithic Hall element having a low systematic offset voltage and a manufacturing method thereof.

  The Hall element is a magnetoelectric conversion element that detects a magnetic field and converts the intensity of the magnetic field into an electric signal, that is, a kind of magnetic sensor. The Hall element used as the magnetic field sensor is mounted on the Hall IC. For example, it is used for an azimuth angle sensor that detects geomagnetism and obtains an azimuth.

  In this type of conventional Hall IC, a signal processing IC to be formed is manufactured by using a CMOS process, a bipolar process, or the like on Si such as a bulk Si substrate or an SOI (silicon on insulator) substrate. The Hall IC structure uses Si for the Hall element operating layer and operates a monolithic Hall IC that is connected monolithically on the same substrate as the signal processing IC and a compound semiconductor that is more sensitive than the Si Hall element. There is a hybrid Hall IC in which the Hall element used for the layer and the two chips of the signal processing IC are housed and connected in one package.

  As a general Hall element, a horizontal Hall element that detects a magnetic field component perpendicular to the substrate surface is known. This Hall element is an element that outputs a voltage proportional to a magnetic field, and ideally the output voltage is zero when there is no magnetic field. However, in reality, a voltage called an offset voltage is generated in the output even when there is no magnetic field, resulting in an error in the measurement magnetic field.

  FIGS. 1A and 1B are configuration diagrams showing the correspondence between a Hall element that does not generate an offset voltage and a Wheatstone bridge circuit that is a model circuit thereof. FIG. 1A is a schematic diagram showing deviations 17a to 17d from the actual layout of the n-type impurity region 12, the n-type region 14a, and the n-type impurity region 12 of the Hall element. The n-type region 14a is a terminal, and there are four terminals A to D in the Hall element. Terminals A and C are terminals for driving a voltage. Vbias “V” is applied to the terminal A, and 0 [V] is applied to the terminal B. Terminals B and D are terminals for extracting an output voltage, and VS1 [V] and VS2 [V] are output, respectively.

  In FIG. 1B, when the resistance components R1 to R4 satisfy the relationship “R1 × R3 = R2 × R4”, the output of the Hall element = VS1-VS2 [V] is 0 [V]. The resistance components R1 to R4 change due to the deformation of the n-type impurity region 12. Therefore, if the deviations 17a to 17d between the actual n-type impurity region 12 and the layout are equal on the four sides of the Hall element, the resistance components R1 to R4 are all the same, and no offset voltage is generated.

  2A and 2B are configuration diagrams showing the correspondence between the Hall element in which the offset voltage is generated and the Wheatstone bridge circuit that is a model circuit thereof. In FIG. 2A, only 17c out of the deviations 17a to 17d between the actual n-type impurity region 12 and the layout is reduced. At this time, the bridge circuit is expressed as R1 = R2 = R4 = R, R3 = R + ΔR, and a systematic offset voltage is generated.

As a method for preventing the occurrence of such an offset voltage, a method is disclosed in which a resistance distribution is changed by applying a voltage to an electrode material through an insulating film provided between the contact regions (for example, Patent Documents). 1).
3A and 3B are configuration diagrams of the horizontal Hall element described in Patent Document 1, FIG. 3A is a top view, and FIG. 3B is L1- It is L1 sectional view taken on the line.

  A semiconductor layer (P-SUB) 1 made of P-type silicon and a semiconductor region 2 made of a diffusion layer (well) formed in such a manner that N-type conductive impurities are introduced into this surface are shared. Has been. Contact regions 3a to 3d are formed on the surface of the semiconductor region 2 so as to selectively increase the impurity concentration of the surface. Insulating electrode materials G1 and G3 are formed between the contact regions 3a and 3c, 3a and 3d, respectively. A nonvolatile memory, more specifically, an EEPROM (Electrically Erasable Programmable Read-Only Memory) is formed by using G1 and G3 as floating electrodes.

The EEPROM includes N type diffusion layers (N + layers) MD1 and MD3, an electron trapping floating gate electrode (electrode materials G1 and G3) formed thereon via a tunnel insulating film TW, and an insulating film 4 and control gate electrodes CG1 and CG3 which are superposed via 4 and used for writing and access.
In such a structure, if the offset voltage is adjusted by applying a voltage to the electrodes G1 and G3 by the CG1 and CG3, the charges at that time are held in the electrode materials G1 and G3. For this reason, even if the application of the voltage to CG1 and CG3 is stopped, the voltage is continuously applied by the electric charge held in the electrode materials G1 and G3, and the resistance distribution is fixed and maintained.

JP 2006-179594 A

However, in the configuration disclosed in Patent Document 1 described above, in order to maintain the voltage of the electrode material, there arises a problem that the charge of the electrode material must be retained using a nonvolatile memory. In view of the above problems, the object is to realize a Hall element structure having a small offset voltage without using a nonvolatile memory, and a Si monolithic Hall element having a small systematic offset voltage and its It is to provide a manufacturing method.

The present invention has been made in order to achieve the above object, a first aspect of the present invention, p-type semiconductor substrate layer made of p-type silicon (11), said p-type semiconductor substrate An n-type impurity region (12) provided on the surface of the layer (11), a first p-type region (13a) provided on the surface of the n-type impurity region (12), and the n-type impurity region ( 12) and n-type regions (14a) provided on both sides of each of two opposing sides of the first p-type region (13a), and on the surface of the p-type semiconductor substrate layer , A p-type impurity region (15a) provided so as to surround the n-type impurity region (12), and a second p-type region (13b) provided on the surface of the p-type impurity region (15a). When, on the surface of the p-type semiconductor substrate layer, enclose the periphery of the p-type impurity region (15a) Wherein the distance between the n-type impurity region and a provided so as to be uniform dummy patterns n-type impurity region (19).

According to a second aspect of the present invention, in the first aspect of the present invention, the first p-type region (13a), the n-type region (14a), the n-type region (14a), and the second characterized in that it comprises the provided device isolation oxide film (16) between the p-type region (13b).
According to a third aspect of the present invention, in the first or second aspect of the present invention, the dummy pattern n-type impurity region (19) suppresses non-uniform deformation of the n-type impurity region (12). It is characterized by having.
The invention according to claim 4 is the invention according to claim 1, 2 or 3, characterized in that the p-type impurity region (15a) is the p-type semiconductor substrate layer (11). To do.

The invention described in Claim 5, by injecting n-type impurities on the surface of the p-type semiconductor substrate layer made of p-type silicon (11), n-type impurity region (12) and the dummy pattern n-type forming an impurity region, forming a first p-type region (13a) on the surface of the n-type impurity region (12), the surface of the n-type impurity region (12), and first A step of forming an n-type region (14a) on both sides of two opposing sides of the p-type region (13a) of the p-type region (13a), and between the n-type impurity region and the dummy pattern n-type impurity region, forming a p-type impurity region (15a) so as to surround the n-type impurity region (12), and forming a second p-type region (13b) on the surface of the p-type impurity region (15a). When, was perforated, the n-type impurity region and the dummy In the step of forming the pattern n-type impurity region, the n-type impurity region and the dummy pattern n-type are formed in a region excluding the n-type impurity region and the dummy pattern n-type impurity region on the surface of the p-type semiconductor substrate layer. A resist having a uniform width between the impurity regions is formed and n-type impurities are implanted .

The invention according to claim 6 is the invention according to claim 5, wherein the first p-type region (13a), the n-type region (14a), the n-type region (14a), and the second An element isolation oxide film (16) is sequentially formed between the p-type region (13b).
According to a seventh aspect of the invention, in the invention of the fifth or sixth aspect, the dummy pattern n-type impurity region (19) has a function of suppressing uneven deformation of the n-type impurity region (12). It is characterized by forming so that it may have.
The invention according to claim 8 is characterized in that, in the invention according to claim 5, 6 or 7, the p-type impurity region (15a) is formed by the p-type semiconductor substrate layer (11). To do.

According to the present invention, a Hall element structure with a small offset voltage can be realized without using a nonvolatile memory, and a Hall element with a small offset voltage can be used even in a process in which a nonvolatile memory is not mounted.
Moreover, the systematic offset voltage of a Hall element manufactured under standard conditions is reduced from 112 uV to 30 uV by introducing a dummy pattern, and a Si monolithic Hall element having a low systematic offset voltage and a method for manufacturing the same are realized. Can do.

(A) And (b) is a block diagram which shows a response | compatibility with the Wheatstone bridge circuit which is the model element circuit and Hall element which an offset voltage does not generate | occur | produce. (A) And (b) is a block diagram which shows a response | compatibility with the Wheatstone bridge circuit which is the model circuit of the Hall element in which the offset voltage has generate | occur | produced. (A) And (b) is a block diagram of the horizontal Hall element described in patent document 1. FIG. (A) And (b) is a block diagram for demonstrating the resist deformation | transformation by baking. It is a block diagram for demonstrating that N well deformation | transformation generate | occur | produces by deformation | transformation of a resist. (A) And (b) is a figure which shows the relationship between a resist deformation amount and a resist width. It is a block diagram for demonstrating the condition where the nonuniformity of a resist deformation amount generate | occur | produces. (A) And (b) is a block diagram for demonstrating the Example of the Hall element based on this invention. (A) thru | or (d) are the block diagrams for demonstrating the effect of a dummy pattern.

In order to solve the above-mentioned problems, the present inventor considered the cause of the occurrence of offset, and found that this is a non-uniform deformation of the resist on each side of the Hall element.
FIGS. 4A and 4B are configuration diagrams for explaining resist deformation by baking (heat treatment), in which reference numeral 21 denotes a resist and 22 denotes an opening. 4A is a cross-sectional view of the resist before baking, and FIG. 4B is a cross-sectional view after baking. The cross-section of the resist is deformed to have a taper by baking.

FIG. 5 is a configuration diagram for explaining that N well deformation occurs due to deformation of a resist. As shown in FIG. 5, the N-well implant 23 penetrates a part of the tapered portion, and an n-type impurity region 25 not intended in the layout is formed in addition to the n-type impurity region 24 intended in the layout. Therefore, N well deformation occurs.
6A and 6B are diagrams showing the relationship between the resist deformation amount and the resist width. When a resist width 32 and a resist deformation amount 33 are defined for the resist 31 as shown in FIG. 6A, when the resist width is small as shown in FIG. The amount of deformation increases, and the resist deformation amount does not change when the resist width exceeds a certain value.

  FIG. 7 is a configuration diagram for explaining a situation where non-uniformity in resist deformation amount occurs. The n-type impurity region 12 and the n-type impurity region 12 in the case where two Hall elements 1 and 2 are arranged vertically are shown. The deviations 17a to 17d and the resist widths 18a to 18d between the actual product and the layout are shown. Of the resist widths 18a to 18d, only the resist element 18c is adjacent to the Hall element, so that the resist width is small. For the resist elements 18a, 18b, and 18d, the resist deformation amount is equal because the adjacent Hall element is sufficiently far away. .

Under such circumstances, the area where the implanter penetrates the resist in the Hall element 1 is reduced only on the lower side, that is, the deformation amount of the N-well is reduced only on the lower side, so that FIGS. As described in the above, a systematic offset voltage is generated. This situation is likely to occur when a plurality of Hall elements are used.
The present invention provides a Hall element having a small offset without using a non-volatile memory by suppressing a non-uniform deformation of a resist that causes an offset by inserting a dummy pattern.

Embodiments of the present invention will be described below with reference to the drawings.
FIGS. 8A and 8B are configuration diagrams for explaining an embodiment of the Hall element according to the present invention. FIG. 8A is a top view and FIG. 8B is a diagram of FIG. It is an AB sectional view. In the figure, reference numeral 10 denotes a Hall element, 11 denotes a semiconductor substrate layer (p substrate), 12 denotes an n-type impurity region (N well), 13a and 13b denote a p-type region (p + diffusion layer), and 14a and 14b denote an n-type region ( n + diffusion layer), 15a and 15b are p-type impurity regions (p-wells), 16 is an element isolation oxide film (LOCOS), and 19 is a dummy pattern n-type impurity region.

The Hall element 10 of the present invention is a Hall element configured to detect a magnetic field using the Hall effect and reduce an offset voltage. A p-type semiconductor substrate layer 11 made of p-type silicon , an n-type impurity region 12 provided on the surface of the p-type semiconductor substrate layer 11, and a first provided on the surface of the n-type impurity region 12. P-type region 13a, n-type region 14a provided on both sides of the two opposite sides of first p-type region 13a on the surface of n-type impurity region 12, and a p-type semiconductor substrate A p-type impurity region 15a provided on the surface of the layer so as to surround the periphery of the n-type impurity region 12, a second p-type region 13b provided on the surface of the p-type impurity region 15a, and a p-type semiconductor A dummy pattern n-type impurity region 19 is provided on the surface of the conductive substrate layer so as to surround the p-type impurity region 15a and to have a uniform distance from the n-type impurity region.

An n-type region 14 b is provided on the surface of the dummy pattern n-type impurity region 19. A p-type impurity region 15 b is provided in the dummy pattern n-type impurity region 19. Further, a first p-type region 13a and the n-type region 14a and the element isolation oxide film provided between the n-type region 14a and the second p-type region 13b (LOCOS) 16. This LOCOS (Local Oxidation of Silicon) is an element isolation technique, in which a mask such as a nitride film is formed on a Si substrate and thermally oxidized to form an oxide film for element isolation. Since diffusion occurs during thermal oxidation, the side surface of the oxide film is difficult to be sharp.

The dummy pattern n-type impurity region 19 has a function of suppressing non-uniform deformation of the n-type impurity region 12. The p-type impurity region 15 a may be a p-type semiconductor substrate layer (P substrate) 11.
9A to 9D are configuration diagrams for explaining the effect of the dummy pattern, FIG. 9A is a top view of the conventional layout, and FIG. 9B is a top view of the dummy pattern layout. In both cases, it is assumed that another Hall element 2 exists next to the Hall element 1. 9C is a cross-sectional view taken along line A1-B1 in FIG. 9A, and FIG. 9D is a cross-sectional view taken along line A2-B2 in FIG. 9B.

9A to 9D show the Hall element after the Hall element NWELL process, and the semiconductor substrate layer 11, the n-type impurity region 12, and the deviation 17 a from the actual layout of the n-type impurity region 12. 17d, a dummy pattern n-type impurity region 19 is shown.
In the conventional layout of FIG. 9A, the resist width 18c of the side facing the adjacent Hall element 2 is smaller than the resist widths 18a, 18b, 18d of the other sides. Deviation 17c from the actual layout is smaller than the other 17a, 17b, 17d. Therefore, systematic offset occurs due to non-uniform deformation of the N well.

In the dummy pattern layout of FIG. 9B, since the dummy pattern n-type impurity region 19 is provided around the n-type impurity region 12, the resist widths 18a to 18d are uniform on each side of the Hall element 1. Therefore, since the region penetrating the implant is also uniform on each side, the deviations 17a to 17d from the actual layout of the n-type impurity region 12 are uniform, and systematic offset can be suppressed.
As described above, according to the Hall element of the present invention, it is possible to realize a Hall element structure with a small offset voltage without using a non-volatile memory and to realize a Si monolithic Hall element with a small systematic offset voltage.

Next, a method for manufacturing the Hall element of the present invention will be described.
The method for manufacturing the Hall element 10 of the present invention is a method for manufacturing a Hall element that is formed so as to reduce the offset voltage by detecting a magnetic field using the Hall effect.
First, an n-type impurity region (12) and a dummy pattern n-type impurity region are formed by implanting an n-type impurity into the surface of the p-type semiconductor substrate layer 11 made of p-type silicon. Next, a first p-type region 13 a is formed on the surface of the n-type impurity region 12. Next, the n-type region 14a is formed on the surface of the n-type impurity region 12 and on both sides of the two opposing sides of the first p-type region 13a. Next, a p-type impurity region 15 a is formed between the n-type impurity region and the dummy pattern n-type impurity region so as to surround the periphery of the n-type impurity region 12. Next, in the step of forming the second p-type region 13b on the surface of the p-type impurity region 15a and forming the n-type impurity region and the dummy pattern n-type impurity region, the n-type of the surface of the p-type semiconductor substrate layer is formed. A resist having a uniform width between the n-type impurity region and the dummy pattern n-type impurity region is formed in a region excluding the impurity region and the dummy pattern n-type impurity region, and n-type impurity implantation is performed .

Further, an element isolation oxide film 16 is sequentially formed between the first p-type region 13a and the n-type region 14a and between the n-type region 14a and the second p-type region 13b. Further, the dummy pattern n-type impurity region 19 is formed so as to have a function of suppressing non-uniform deformation of the n-type impurity region 12. Further, the p-type impurity region 15 a may be formed of the p-type semiconductor substrate layer 11.
Thus, according to the Hall element manufacturing method of the present invention, there is provided a method for manufacturing a Si monolithic Hall element having a small systematic offset voltage while realizing a Hall element structure having a small offset voltage without using a nonvolatile memory. Can be realized.

1 Semiconductor layer 2, 2a Semiconductor region 3a to 3c Contact region (N ^- layer)
4 Insulating film G1, G3 Electrode material CG1, CG3 Control gate electrode MD1, MD3 Diffusion layer 10 Hall element 11 Semiconductor substrate layer 12 n-type impurity region (N well)
13a, 13b p-type region (p + diffusion layer)
14a, 14b n-type region (n + diffusion layer)
15a, 15b p-type impurity region (p-well)
16 Oxide film for element isolation (LOCOS)
17a, 17b, 17c, 17d Deviation from actual layout of n-type impurity region 12 18a, 18b, 18c, 18d Resist width 19 Dummy pattern n-type impurity region 21 Resist 22 N well opening 23 N well implant 24 Intended in layout N-type impurity region 25 n-type impurity region 31 not intended in layout Resist 32 Resist width 33 Resist deformation amount

Claims (8)

a p -type semiconducting substrate layer made of p-type silicon;
And n-type impurity region provided on the surface of the p-type semiconductor substrate layer,
A first p-type region provided on the surface of the n-type impurity region;
N-type regions provided on the surface of the n-type impurity region and on both sides of each of two opposing sides of the first p-type region;
A p-type impurity region provided on the surface of the p-type semiconductor substrate layer so as to surround the periphery of the n-type impurity region;
A second p-type region provided on the surface of the p-type impurity region;
A dummy pattern n-type impurity region provided on the surface of the p-type semiconductor substrate layer so as to surround the p-type impurity region and to have a uniform distance from the n-type impurity region; Characteristic hall element. According to claim 1, characterized in that it comprises an element isolation oxide film provided between the first p-type region and the n-type region and said n-type region and the second p-type region Hall element.   The Hall element according to claim 1, wherein the dummy pattern n-type impurity region has a function of suppressing non-uniform deformation of the n-type impurity region.   The Hall element according to claim 1, wherein the p-type impurity region is the p-type semiconductor substrate layer. by implanting an n-type impurity on the surface of the p-type semiconductor substrate layer made of p-type silicon, forming an n-type impurity regions and the dummy patterns n-type impurity regions,
Forming a first p-type region in a surface of the n-type impurity regions,
Forming an n-type region on the surface of the n-type impurity region and on both sides of each of two opposing sides of the first p-type region;
Forming a p-type impurity region between the n-type impurity region and the dummy pattern n-type impurity region so as to surround the n-type impurity region;
Forming a second p-type region on the surface of the p-type impurity region;
I have a,
In the step of forming the n-type impurity region and the dummy pattern n-type impurity region, the n-type impurity region and the dummy pattern n-type impurity region except for the n-type impurity region and the dummy pattern n-type impurity region are formed on the surface of the p-type semiconductor substrate layer. A method of manufacturing a Hall element, comprising forming a resist having a uniform width between an impurity region and the dummy pattern n-type impurity region and implanting n-type impurities .   6. The hole according to claim 5, wherein an element isolation oxide film is sequentially formed between the first p-type region, the n-type region, and the n-type region and the second p-type region. Device manufacturing method.   7. The Hall element manufacturing method according to claim 5, wherein the dummy pattern n-type impurity region is formed to have a function of suppressing non-uniform deformation of the n-type impurity region.   8. The method of manufacturing a Hall element according to claim 5, wherein the p-type impurity region is formed by the p-type semiconductor substrate layer.

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