JP6080933B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device.

In recent years, semiconductor integrated circuits have been increased in scale, and in the state-of-the-art MPU (Micro-processing Unit), a semiconductor chip whose number of transistors has reached 1 G (giga) has been developed. The so-called planar transistor needs to completely separate the N-well region forming the PMOS and the P-type silicon substrate (or P-well region) forming the NMOS, as shown in Non-Patent Document 1. In addition, the N-well region and the P-type silicon substrate each require a body terminal for applying a potential, which is a factor that further increases the area.

As a means for solving this problem, a Surrounding Gate Transistor (SGT) having a structure in which a source, a gate, and a drain are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-like semiconductor layer has been proposed. A CMOS inverter, a NAND circuit, or an SRAM cell using the above is disclosed. For example, see Patent Document 1, Patent Document 2, Patent Document 3, and Patent Document 4.

Yoshizawa Hirokazu, Basics of CMOS OP Amplifier Circuit Practical Design, CQ Publishing Company, August 1, 2007, p. 23

Japanese Patent No. 5130596 Japanese Patent No. 5031809 Japanese Patent No. 4756221 International Publication No. 2009/096465

21, 22, and 23 show circuit diagrams and layout diagrams of inverters using SGTs.
FIG. 21 is a circuit diagram of an inverter, Qp is a P-channel MOS transistor (hereinafter referred to as a PMOS transistor), Qn is an N-channel MOS transistor (hereinafter referred to as an NMOS transistor), IN is an input signal, OUT is an output signal, Vcc Is a power source, and Vss is a reference power source.

FIG. 22 is a plan view of a layout in which the inverter of FIG. 21 is configured by SGT. FIG. 23 is a cross-sectional view in the cut line AA ′ direction in the plan view of FIG.
22 and 23, planar silicon layers 2p and 2n are formed on an insulating film such as a buried oxide film layer (BOX) 1 formed on the substrate, and the planar silicon layers 2p and 2n are impurity implanted or the like. Thus, a p + diffusion layer and an n + diffusion layer are formed. Reference numeral 3 denotes a silicide layer formed on the surface of the planar silicon layer (2p, 2n), which connects the planar silicon layers 2p, 2n. 4n is an n-type silicon pillar, 4p is a p-type silicon pillar, 5 is a gate insulating film surrounding the silicon pillars 4n and 4p, 6 is a gate electrode, and 6a is a gate wiring. A p + diffusion layer 7p and an n + diffusion layer 7n are respectively formed on the uppermost portions of the silicon pillars 4n and 4p by impurity implantation or the like. 8 is a silicon nitride film for protecting the gate insulating film 5, etc., 9p and 9n are p + diffusion layers 7p, silicide layers connected to the n + diffusion layers 7n, 10p and 10n are silicide layers 9p and 9n and metal wiring 13a. , 13b, and 11 are contacts for connecting the gate wiring 6a and the metal wiring 13c, respectively.

The silicon pillar 4n, the diffusion layer 2p, the diffusion layer 7p, the gate insulating film 5, and the gate electrode 6 constitute a PMOS transistor Qp. The silicon pillar 4p, the diffusion layer 2n, the diffusion layer 7n, the gate insulating film 5 and the gate electrode 6 constitute the PMOS transistor Qp. The NMOS transistor Qn is configured. Diffusion layers 7p and 7n serve as sources, and diffusion layers 2p and 2n serve as drains. A power supply Vcc is supplied to the metal wiring 13a, a reference power supply Vss is supplied to the metal wiring 13b, and an input signal IN is connected to the metal wiring 13c. Further, the silicide layer 3 connecting the drain diffusion layer 2p of the PMOS transistor Qp and the drain diffusion layer 2n of the NMOS transistor Qn becomes the output OUT.

In the inverter using SGT shown in FIG. 21, FIG. 22 and FIG. 23, the PMOS transistor and the NMOS transistor are completely separated from each other in structure, and no well separation is required unlike the planar transistor. Since it becomes a floating body, there is no need for a body terminal for supplying a potential to the well unlike a planar transistor, and the layout (arrangement) can be very compact.

An object of the present invention is to provide a semiconductor device that uses the feature of SGT to provide a decoder having a minimum area by arranging NAND type decoders and inverters using a three-input NAND circuit in one column. It is.

(1) In the semiconductor device according to the present invention for achieving the above object, six transistors in which sources, drains and gates are arranged hierarchically in a direction perpendicular to the substrate are arranged in a first direction on the substrate. A semiconductor device that constitutes a NAND decoder by arranging in a column,
Each of the transistors is
Silicon pillars,
An insulator surrounding a side surface of the silicon pillar;
A gate surrounding the insulator;
A source region disposed above or below the silicon pillar;
A drain region disposed above or below the silicon pillar, the drain region disposed opposite to the source region with respect to the silicon pillar;
The six transistors are:
A first P-channel MOS transistor;
A second P-channel MOS transistor;
A third P-channel MOS transistor;
A first N-channel MOS transistor;
A second N-channel MOS transistor;
A third N-channel MOS transistor;
Consists of
The gates of the first P-channel MOS transistor and the first N-channel MOS transistor are connected to each other,
The gates of the second P-channel MOS transistor and the second N-channel MOS transistor are connected to each other.
The gates of the third P-channel MOS transistor and the third N-channel MOS transistor are connected to each other.
The drain regions of the first P-channel MOS transistor, the second P-channel MOS transistor, the third P-channel MOS transistor, and the first N-channel MOS transistor are disposed on the substrate side from the silicon pillar, and silicide each other. Connected through the region to become the output terminal (DEC1),
The source region of the second N-channel MOS transistor and the drain region of the third N-channel MOS transistor are disposed on the substrate side from the silicon pillar,
A source region of the first N-channel MOS transistor is connected to a drain region of the second N-channel MOS transistor via a contact;
The source region of the second N-channel MOS transistor is connected to the drain region of the third N-channel MOS transistor via a lower diffusion layer and a silicide layer,
Source regions of the first P-channel MOS transistor, the second P-channel MOS transistor, and the third P-channel MOS transistor are connected to a power supply line through contacts,
The source region of the third N-channel MOS transistor is connected to a reference power line through a contact,
The decoder
A first address signal line;
A second address signal line;
A second address signal line;
Have
The gates of the first P-channel MOS transistor and the first N-channel MOS transistor connected to each other are connected to the first address signal line,
The gates of the second P-channel MOS transistor and the second N-channel MOS transistor connected to each other are connected to the second address signal line,
The gates of the third P-channel MOS transistor and the third N-channel MOS transistor connected to each other are connected to the third address signal line,
The power supply line, the reference power supply line, the first address signal line, the second address signal line, and the third address signal line extend in a second direction perpendicular to the first direction. It is characterized by being arranged.

  (2) In a preferred aspect of the present invention, the six transistors include the third P-channel MOS transistor, the second P-channel MOS transistor, the first P-channel MOS transistor, and the first N-channel MOS. The transistors, the second N-channel MOS transistor, and the third N-channel MOS transistor are arranged in one row in the order.

  (3) In another aspect, the gates of the first P-channel MOS transistor and the first N-channel MOS transistor, or the second P-channel MOS transistor and the second N-channel MOS transistor At least one of the gates or the gates of the third P-channel MOS transistor and the third N-channel MOS transistor is at least via a wiring of a first metal wiring layer arranged to extend in the first direction. And connected to address signal lines corresponding to the first to third address signal lines constituted by the wiring of the second metal wiring layer arranged to extend in the second direction.

(4) In the semiconductor device according to the present invention, six transistors in which sources, drains, and gates are arranged hierarchically in a direction perpendicular to the substrate are arranged in a row in the first direction on the substrate. A semiconductor device constituting a NAND decoder,
Each of the transistors is
Silicon pillars,
An insulator surrounding a side surface of the silicon pillar;
A gate surrounding the insulator;
A source region disposed above or below the silicon pillar;
A drain region disposed above or below the silicon pillar, the drain region disposed opposite to the source region with respect to the silicon pillar;
The six transistors are at least
A first P-channel MOS transistor;
A second P-channel MOS transistor;
A third P-channel MOS transistor;
A first N-channel MOS transistor;
A second N-channel MOS transistor;
A third N-channel MOS transistor;
Consists of
The gates of the first P-channel MOS transistor and the first N-channel MOS transistor are connected to each other,
The gates of the second P-channel MOS transistor and the second N-channel MOS transistor are connected to each other.
The gates of the third P-channel MOS transistor and the third N-channel MOS transistor are connected to each other.
The drain regions of the first P-channel MOS transistor, the second P-channel MOS transistor, the third P-channel MOS transistor, and the first N-channel MOS transistor are arranged on the substrate side from the silicon pillar, and The output terminal (DEC1) is connected through the silicide region,
The source region of the second N-channel MOS transistor and the drain region of the third N-channel MOS transistor are disposed on the substrate side from the silicon pillar,
A source region of the first N-channel MOS transistor is connected to a drain region of the second N-channel MOS transistor via a contact;
The source region of the second N-channel MOS transistor is connected to the drain region of the third N-channel MOS transistor via a lower diffusion layer and a silicide layer,
Source regions of the first P-channel MOS transistor, the second P-channel MOS transistor, and the third P-channel MOS transistor are connected to a power supply line through contacts,
The source region of the third N-channel MOS transistor is connected to a reference power line through a contact,
The semiconductor device includes:
A first a address signal lines;
A second b address signal lines;
A third c address signal lines;
a × b × c NAND-type decoders;
Have
In each of the a × b × c NAND decoders,
The gates of the first P-channel MOS transistor and the first N-channel MOS transistor connected to each other are connected to any one of the first a address signal lines,
The gates of the second P-channel MOS transistor and the second N-channel MOS transistor connected to each other are connected to any one of the second b address signal lines,
The gates of the third P-channel MOS transistor and the third N-channel MOS transistor connected to each other are connected to any one of the third c address signal lines,
The power supply line, the reference power supply line, the first a address signal lines, the second b address signal lines, and the third c address signal lines are perpendicular to the first direction. It is arranged to extend in a second direction.

  (5) In a preferred aspect of the present invention, the six transistors include the third P-channel MOS transistor, the second P-channel MOS transistor, the first P-channel MOS transistor, and the first N-channel MOS. Transistors, the second N-channel MOS transistor, and the third N-channel MOS transistor are arranged in one row in the order.

  (6) In another aspect, the gates of the first P-channel MOS transistor and the first N-channel MOS transistor, or the second P-channel MOS transistor and the second N-channel MOS transistor At least one of the gates or the gates of the third P-channel MOS transistor and the third N-channel MOS transistor is at least via a wiring of a first metal wiring layer arranged to extend in the first direction. And connected to address signal lines corresponding to the first to third address signal lines constituted by the wiring of the second metal wiring layer arranged to extend in the second direction.

(7) In the semiconductor device according to the present invention, six transistors in which sources, drains, and gates are arranged hierarchically in a direction perpendicular to the substrate are arranged in a row in the first direction on the substrate. A semiconductor device constituting a NAND decoder,
Each of the transistors is
Silicon pillars,
An insulator surrounding a side surface of the silicon pillar;
A gate surrounding the insulator;
A source region disposed above or below the silicon pillar;
A drain region disposed above or below the silicon pillar, the drain region disposed opposite to the source region with respect to the silicon pillar;
The six transistors are:
A first P-channel MOS transistor;
A second P-channel MOS transistor;
A third P-channel MOS transistor;
A first N-channel MOS transistor;
A second N-channel MOS transistor;
A third N-channel MOS transistor;
Consists of
The gates of the first P-channel MOS transistor and the first N-channel MOS transistor are connected to each other,
The gates of the second P-channel MOS transistor and the second N-channel MOS transistor are connected to each other.
The gates of the third P-channel MOS transistor and the third N-channel MOS transistor are connected to each other.
Source regions of the first P-channel MOS transistor, the second P-channel MOS transistor, the third P-channel MOS transistor, and the first N-channel MOS transistor are disposed on the substrate side from the silicon pillar. ,
The drain region of the second N-channel MOS transistor and the source region of the third N-channel MOS transistor are disposed on the substrate side from the silicon pillar,
The drain regions of the first P-channel MOS transistor, the second P-channel MOS transistor, the third P-channel MOS transistor, and the first N-channel MOS transistor are connected to each other through a contact and output terminals (DEC1)
Source regions of the first P-channel MOS transistor, the second P-channel MOS transistor, and the third P-channel MOS transistor are connected to a power supply line through a lower diffusion layer and a silicide region,
The source region of the first N-channel MOS transistor is connected to the drain region of the second N-channel MOS transistor via a lower diffusion layer and a silicide region,
The source region of the second N-channel MOS transistor is connected to the drain region of the third N-channel MOS transistor through a contact, and the source region of the third N-channel MOS transistor includes a lower diffusion layer and Connected to the reference power line through the silicide region,
The NAND decoder is
A first address signal line;
A second address signal line;
A third address signal line;
Have
The gates of the first P-channel MOS transistor and the first N-channel MOS transistor connected to each other are connected to the first address signal line,
The gates of the second P-channel MOS transistor and the second N-channel MOS transistor connected to each other are connected to the second address signal line,
The gates of the third P-channel MOS transistor and the third N-channel MOS transistor connected to each other are connected to the third address signal line,
The power supply line, the reference power supply line, the first address signal line, the second address signal line, and the third address signal line extend in a second direction perpendicular to the first direction. It is characterized by being arranged.

  (8) In a preferred aspect of the present invention, the six transistors include the third P-channel MOS transistor, the second P-channel MOS transistor, the first P-channel MOS transistor, and the first N-channel MOS transistor. The second N-channel MOS transistor and the third N-channel MOS transistor are arranged in one row in order.

  (9) In another aspect, the gates of the first P-channel MOS transistor and the first N-channel MOS transistor, or the second P-channel MOS transistor and the second N-channel MOS transistor At least one of the gates or the gates of the third P-channel MOS transistor and the third N-channel MOS transistor is at least via a wiring of a first metal wiring layer arranged to extend in the first direction. And connected to address signal lines corresponding to the first to third address signal lines constituted by the wiring of the second metal wiring layer arranged to extend in the second direction.

(10) A semiconductor device according to the present invention includes six transistors in which sources, drains, and gates are arranged hierarchically in a direction perpendicular to the substrate, arranged in a row in the first direction on the substrate. A semiconductor device constituting a NAND decoder,
Each of the transistors is
Silicon pillars,
An insulator surrounding a side surface of the silicon pillar;
A gate surrounding the insulator;
A source region disposed above or below the silicon pillar;
A drain region disposed above or below the silicon pillar, the drain region disposed opposite to the source region with respect to the silicon pillar;
The six transistors are at least
A first P-channel MOS transistor;
A second P-channel MOS transistor;
A third P-channel MOS transistor;
A first N-channel MOS transistor;
A second N-channel MOS transistor;
A third N-channel MOS transistor;
Consists of
The gates of the first P-channel MOS transistor and the first N-channel MOS transistor are connected to each other,
The gates of the second P-channel MOS transistor and the second N-channel MOS transistor are connected to each other.
The gates of the third P-channel MOS transistor and the third N-channel MOS transistor are connected to each other.
Source regions of the first P-channel MOS transistor, the second P-channel MOS transistor, the second P-channel MOS transistor, and the first N-channel MOS transistor are disposed on the substrate side from the silicon pillar. ,
The drain region of the second N-channel MOS transistor and the source region of the third N-channel MOS transistor are disposed on the substrate side from the silicon pillar,
The drain regions of the first P-channel MOS transistor, the second P-channel MOS transistor, the third P-channel MOS transistor, and the first N-channel MOS transistor are connected to each other through a contact and output terminals (DEC1)
Source regions of the first P-channel MOS transistor, the second P-channel MOS transistor, and the third P-channel MOS transistor are connected to a power supply line through a lower diffusion layer and a silicide layer,
The source region of the first N-channel MOS transistor is connected to the drain region of the second N-channel MOS transistor via a lower diffusion layer and a silicide layer,
The source region of the second N-channel MOS transistor is connected to the drain region of the third N-channel MOS transistor through a contact, and the source region of the third N-channel MOS transistor is a lower diffusion layer and Connected to the reference power line through the silicide layer,
The semiconductor device includes:
A first a address signal lines;
A second b address signal lines;
A third c address signal lines;
a × b × c NAND-type decoders;
Have
In each of the a × b × c NAND decoders,
The gates of the first P-channel MOS transistor and the first N-channel MOS transistor connected to each other are connected to any one of the first a address signal lines,
The gates of the second P-channel MOS transistor and the second N-channel MOS transistor connected to each other are connected to any one of the second b address signal lines,
The gates of the third P-channel MOS transistor and the third N-channel MOS transistor connected to each other are connected to any one of the third c address signal lines,
The power supply line, the reference power supply line, the first a address signal lines, the second b address signal lines, and the third c address signal lines are perpendicular to the first direction. It is arranged to extend in a second direction.

  (11) In a preferred aspect of the present invention, the six transistors include the third P-channel MOS transistor, the second P-channel MOS transistor, the first P-channel MOS transistor, and the first N-channel MOS. Transistors, the second N-channel MOS transistor, and the third N-channel MOS transistor are arranged in one row in the order.

(12) In another aspect, the first P-channel MOS transistor, the second P-channel MOS transistor, and the third P-channel MOS transistor constituting the a × b × c NAND decoders These source regions are commonly connected via a silicide layer.

  (13) In another aspect, the gates of the first P-channel MOS transistor and the first N-channel MOS transistor, or the gates of the second P-channel MOS transistor and the second N-channel MOS transistor. Or at least one of the gates of the third P-channel MOS transistor and the third N-channel MOS transistor via at least a wiring of a first metal wiring layer arranged to extend in the first direction. Connected to the corresponding address signal lines of the first to third address signal lines constituted by the wiring of the second metal wiring layer arranged to extend in the second direction.

(14) In the semiconductor device according to the present invention, eight transistors in which sources, drains, and gates are arranged hierarchically in a direction perpendicular to the substrate are arranged in a row in the first direction on the substrate. A semiconductor device constituting a NAND decoder and an inverter,
Each of the transistors is
Silicon pillars,
An insulator surrounding a side surface of the silicon pillar;
A gate surrounding the insulator;
A source region disposed above or below the silicon pillar;
A drain region disposed above or below the silicon pillar, the drain region disposed opposite to the source region with respect to the silicon pillar;
The eight transistors are:
A first P-channel MOS transistor;
A second P-channel MOS transistor;
A third P-channel MOS transistor;
A fourth P-channel MOS transistor;
A first N-channel MOS transistor;
A second N-channel MOS transistor;
A third N-channel MOS transistor;
A fourth N-channel MOS transistor;
Consists of
The NAND decoder is
A first P-channel MOS transistor;
A second P-channel MOS transistor;
A third P-channel MOS transistor;
A first N-channel MOS transistor;
A second N-channel MOS transistor;
A third N-channel MOS transistor;
Consists of
The inverter is
A fourth P-channel MOS transistor;
A fourth N-channel MOS transistor;
Consists of
The gates of the first P-channel MOS transistor and the first N-channel MOS transistor are connected to each other,
The gates of the second P-channel MOS transistor and the second N-channel MOS transistor are connected to each other.
The gates of the third P-channel MOS transistor and the third N-channel MOS transistor are connected to each other.
The drain regions of the first P-channel MOS transistor, the second P-channel MOS transistor, the third P-channel MOS transistor, and the first N-channel MOS transistor are arranged on the substrate side from the silicon pillar, and The first output terminal (DEC1) is connected through the silicide layer,
The source region of the second N-channel MOS transistor and the drain region of the third N-channel MOS transistor are disposed on the substrate side from the silicon pillar,
Source regions of the first P-channel MOS transistor, the second P-channel MOS transistor, and the third P-channel MOS transistor are connected to a power supply line through contacts,
A source region of the first N-channel MOS transistor is connected to a drain region of the second N-channel MOS transistor via a contact;
The source region of the second N-channel MOS transistor is connected to the drain region of the third N-channel MOS transistor via a silicide layer,
The source region of the third N-channel MOS transistor is connected to a reference power line through a contact,
The gates of the fourth P-channel MOS transistor and the fourth N-channel MOS transistor are connected to each other and connected to the first output terminal (DEC1),
The drain region of the fourth P-channel MOS transistor and the drain region of the fourth N-channel MOS transistor are connected to each other to become a second output terminal (SEL1),
The source region of the fourth P-channel MOS transistor and the source region of the fourth N-channel MOS transistor are connected to a power supply line and a reference power supply line, respectively.
The NAND decoder is
A first address signal line;
A second address signal line;
A third address signal line;
Have
The gates of the first P-channel MOS transistor and the first N-channel MOS transistor connected to each other are connected to the first address signal line,
The gates of the second P-channel MOS transistor and the second N-channel MOS transistor connected to each other are connected to the second address signal line,
The gates of the third P-channel MOS transistor and the third N-channel MOS transistor connected to each other are connected to the third address signal line,
The power supply line, the reference power supply line, the first address signal line, the second address signal, and the third address signal line are arranged to extend in a second direction perpendicular to the first direction. It is characterized by being.

  (15) In a preferred aspect of the present invention, the eight transistors are one of the fourth N-channel MOS transistor or the fourth P-channel MOS transistor, the fourth N-channel MOS transistor or the fourth P-channel MOS transistor. The other of the channel MOS transistors, the third P channel MOS transistor, the second P channel MOS transistor, the first P channel MOS transistor, the first N channel MOS transistor, the second N channel MOS transistor The third N-channel MOS transistors are arranged in a row in the order of the third N-channel MOS transistors.

  (16) In another aspect, the gates of the first P-channel MOS transistor and the first N-channel MOS transistor, or the second P-channel MOS transistor and the second N-channel MOS transistor At least one of the gates or the gates of the third P-channel MOS transistor and the third N-channel MOS transistor is at least via a wiring of a first metal wiring layer arranged to extend in the first direction. And connected to address signal lines corresponding to the first to third address signal lines constituted by the wiring of the second metal wiring layer arranged to extend in the second direction.

(17) In the semiconductor device according to the present invention, eight transistors in which sources, drains, and gates are arranged hierarchically in a direction perpendicular to the substrate are arranged on the substrate in one row in the first direction. A semiconductor device constituting a NAND decoder and an inverter,
Each of the transistors is
Silicon pillars,
An insulator surrounding a side surface of the silicon pillar;
A gate surrounding the insulator;
A source region disposed above or below the silicon pillar;
A drain region disposed above or below the silicon pillar, the drain region disposed opposite to the source region with respect to the silicon pillar;
The eight transistors are:
A first P-channel MOS transistor;
A second P-channel MOS transistor;
A third P-channel MOS transistor;
A fourth P-channel MOS transistor;
A first N-channel MOS transistor;
A second N-channel MOS transistor;
A third N-channel MOS transistor;
A fourth N-channel MOS transistor;
Consists of
The decoder is at least
A first P-channel MOS transistor;
A second P-channel MOS transistor;
A third P-channel MOS transistor;
A first N-channel MOS transistor;
A second N-channel MOS transistor;
A third N-channel MOS transistor;
Consists of
The inverter is
A fourth P-channel MOS transistor;
A fourth N-channel MOS transistor;
Consists of
The gates of the first P-channel MOS transistor and the first N-channel MOS transistor are connected to each other,
The gates of the second P-channel MOS transistor and the second N-channel MOS transistor are connected to each other.
The gates of the third P-channel MOS transistor and the third N-channel MOS transistor are connected to each other.
The drain regions of the first P-channel MOS transistor, the second P-channel MOS transistor, the third P-channel MOS transistor, and the first N-channel MOS transistor are disposed on the substrate side from the silicon pillar, and are mutually connected. The first output terminal (DEC1) is connected through the silicide layer,
The source region of the second N-channel MOS transistor and the drain region of the third MOS transistor are disposed on the substrate side from the silicon pillar,
Source regions of the first P-channel MOS transistor, the second P-channel MOS transistor, and the third P-channel MOS transistor are connected to a power supply line through contacts,
A source region of the first N-channel MOS transistor is connected to a drain region of the second N-channel MOS transistor via a contact;
The source region of the second N-channel MOS transistor is connected to the drain region of the third N-channel MOS transistor via a silicide layer,
The source region of the third N-channel MOS transistor is connected to a reference power line through a contact,
The gates of the fourth P-channel MOS transistor and the fourth N-channel MOS transistor are connected to each other and connected to the first output terminal (DEC1),
The drain region of the fourth P-channel MOS transistor and the drain region of the fourth N-channel MOS transistor are connected to each other to become a second output terminal (SEL1),
The source region of the fourth P-channel MOS transistor and the source region of the fourth N-channel MOS transistor are connected to a power supply line and a reference power supply line, respectively.
The semiconductor device includes:
A first a address signal lines;
A second b address signal lines;
A third c address signal lines;
a × b × c NAND decoders and inverters;
Have
In each of the a × b × c NAND decoders and inverters,
The gates of the first P-channel MOS transistor and the first N-channel MOS transistor connected to each other are connected to any one of the first a address signal lines,
The gates of the second P-channel MOS transistor and the second N-channel MOS transistor connected to each other are connected to any one of the second b address signal lines,
The gates of the third P-channel MOS transistor and the third N-channel MOS transistor connected to each other are connected to any one of the third c address signal lines,
The power supply line, the reference power supply line, the first a address signal lines, the second b address signal lines, and the third c address signal lines are perpendicular to the first direction. And extending in the second direction.

  (18) In a preferred aspect of the present invention, the eight transistors are one of the fourth N-channel MOS transistor or the fourth P-channel MOS transistor, the fourth N-channel MOS transistor or the fourth P-channel MOS transistor. The other of the channel MOS transistors, the third P channel MOS transistor, the second P channel MOS transistor, the first P channel MOS transistor, the first N channel MOS transistor, and the second N channel MOS transistor The third N-channel MOS transistors are arranged in one row in the order.

  (19) In another aspect, the gates of the first P-channel MOS transistor and the first N-channel MOS transistor, or the second P-channel MOS transistor and the second N-channel MOS transistor At least one of the gates or the gates of the third P-channel MOS transistor and the third N-channel MOS transistor is at least via a wiring of a first metal wiring layer arranged to extend in the first direction. And connected to address signal lines corresponding to the first to third address signal lines constituted by the wiring of the second metal wiring layer arranged to extend in the second direction.

(20) In the semiconductor device according to the present invention, eight transistors in which sources, drains, and gates are arranged hierarchically in a direction perpendicular to the substrate are arranged in a row in the first direction on the substrate. A semiconductor device constituting a NAND decoder and an inverter,
Each of the transistors is
Silicon pillars,
An insulator surrounding a side surface of the silicon pillar;
A gate surrounding the insulator;
A source region disposed above or below the silicon pillar;
A drain region disposed above or below the silicon pillar, the drain region disposed opposite to the source region with respect to the silicon pillar;
The eight transistors are:
A first P-channel MOS transistor;
A second P-channel MOS transistor;
A third P-channel MOS transistor;
A fourth P-channel MOS transistor;
A first N-channel MOS transistor;
A second N-channel MOS transistor;
A third N-channel MOS transistor;
A fourth N-channel MOS transistor;
Consists of
The NAND decoder is
A first P-channel MOS transistor;
A second P-channel MOS transistor;
A third P-channel MOS transistor;
A first N-channel MOS transistor;
A second N-channel MOS transistor;
A third N-channel MOS transistor;
Consists of
The inverter is
A third P-channel MOS transistor;
A third N-channel MOS transistor;
Consists of
The gates of the first P-channel MOS transistor and the first N-channel MOS transistor are connected to each other,
The gates of the second P-channel MOS transistor and the second N-channel MOS transistor are connected to each other.
The gates of the third P-channel MOS transistor and the third N-channel MOS transistor are connected to each other.
Source regions of the first P-channel MOS transistor, the second P-channel MOS transistor, the third P-channel MOS transistor, and the first N-channel MOS transistor are disposed on the substrate side from the silicon pillar. ,
The drain region of the second N-channel MOS transistor and the source region of the third N-channel MOS transistor are disposed on the substrate side from the silicon pillar,
The drain regions of the first P-channel MOS transistor, the second P-channel MOS transistor, the third P-channel MOS transistor, and the first N-channel MOS transistor are connected to each other via a contact and Output terminal (DEC1),
Source regions of the first P-channel MOS transistor, the second P-channel MOS transistor, and the third P-channel MOS transistor are connected to a power supply line through a silicide region,
The source region of the first N-channel MOS transistor is connected to the drain region of the second N-channel MOS transistor via a silicide layer,
The source region of the second N channel MOS transistor is connected to the drain region of the third N channel MOS transistor via a contact,
The source region of the third N-channel MOS transistor is connected to a reference power source through a silicide layer,
The gates of the fourth P-channel MOS transistor and the fourth N-channel MOS transistor are connected to each other and connected to the first output terminal (DEC1),
The drain region of the fourth P-channel MOS transistor and the drain region of the fourth N-channel MOS transistor are connected to each other to become a second output terminal (SEL1),
The source region of the fourth P-channel MOS transistor and the source region of the fourth N-channel MOS transistor are connected to a power supply line and a reference power supply line, respectively.
The NAND decoder is
A first address signal line;
A second address signal line;
A third address signal line;
Have
The gates of the first P-channel MOS transistor and the first N-channel MOS transistor connected to each other are connected to the first address signal line,
The gates of the second P-channel MOS transistor and the second N-channel MOS transistor connected to each other are connected to the second address signal line,
The gates of the third P-channel MOS transistor and the third N-channel MOS transistor connected to each other are connected to the third address signal line,
The power supply line, the reference power supply line, the first address signal line, the second address signal line, and the third address signal line extend in a second direction perpendicular to the first direction. It is characterized by being arranged.

  (21) In a preferred aspect of the present invention, the eight transistors are one of the fourth N-channel MOS transistor or the fourth P-channel MOS transistor, the fourth N-channel MOS transistor, or the fourth P-channel MOS transistor. The other of the channel MOS transistors, the third P channel MOS transistor, the second P channel MOS transistor, the first P channel MOS transistor, the first N channel MOS transistor, the second N channel MOS transistor The third N-channel MOS transistors are arranged in one row in the order.

(22) In another aspect, source regions of the fourth P-channel MOS transistor and the fourth N-channel MOS transistor are disposed closer to the substrate side than the silicon pillar,
The eight transistors include the fourth N-channel MOS transistor, the fourth P-channel MOS transistor, the third P-channel MOS transistor, the second P-channel MOS transistor, and the first P-channel MOS transistor. The first N-channel MOS transistor, the second N-channel MOS transistor, and the third N-channel MOS transistor are arranged in one row in this order.

  (23) In another aspect, the gates of the first P-channel MOS transistor and the first N-channel MOS transistor, or the second P-channel MOS transistor and the second N-channel MOS transistor At least one of the gates or the gates of the third P-channel MOS transistor and the third N-channel MOS transistor is at least via a wiring of a first metal wiring layer arranged to extend in the first direction. And connected to address signal lines corresponding to the first to third address signal lines constituted by the wiring of the second metal wiring layer arranged to extend in the second direction.

(24) In the semiconductor device according to the present invention, eight transistors in which sources, drains, and gates are arranged hierarchically in a direction perpendicular to the substrate are arranged in a line in the first direction on the substrate. A semiconductor device constituting a NAND decoder and an inverter,
Each of the transistors is
Silicon pillars,
An insulator surrounding a side surface of the silicon pillar;
A gate surrounding the insulator;
A source region disposed above or below the silicon pillar;
A drain region disposed above or below the silicon pillar, the drain region disposed opposite to the source region with respect to the silicon pillar;
The eight transistors are:
A first P-channel MOS transistor;
A second P-channel MOS transistor;
A third P-channel MOS transistor;
A fourth P-channel MOS transistor;
A first N-channel MOS transistor;
A second N-channel MOS transistor;
A third N-channel MOS transistor;
A fourth N-channel MOS transistor;
Consists of
The NAND decoder is
A first P-channel MOS transistor;
A second P-channel MOS transistor;
A third P-channel MOS transistor;
A first N-channel MOS transistor;
A second N-channel MOS transistor;
A third N-channel MOS transistor;
Consists of
The inverter is
A fourth P-channel MOS transistor;
A fourth N-channel MOS transistor;
Consists of
The gates of the first P-channel MOS transistor and the first N-channel MOS transistor are connected to each other,
The gates of the second P-channel MOS transistor and the second N-channel MOS transistor are connected to each other.
The gates of the third P-channel MOS transistor and the third N-channel MOS transistor are connected to each other.
Source regions of the first P-channel MOS transistor, the second P-channel MOS transistor, the third P-channel MOS transistor, and the first N-channel MOS transistor are disposed on the substrate side from the silicon pillar. ,
The drain region of the second N-channel MOS transistor and the source region of the third N-channel MOS transistor are disposed on the substrate side from the silicon pillar,
The drain regions of the first P-channel MOS transistor, the second P-channel MOS transistor, the third P-channel MOS transistor, and the first N-channel MOS transistor are connected to each other via a contact and Output terminal (DEC1),
Source regions of the first P-channel MOS transistor, the second P-channel MOS transistor, and the third P-channel MOS transistor are connected to a power supply line through a silicide region,
The source region of the first N-channel MOS transistor is connected to the drain region of the second N-channel MOS transistor via a silicide layer,
The source region of the second N channel MOS transistor is connected to the drain region of the third N channel MOS transistor via a contact,
The source region of the third N-channel MOS transistor is connected to a reference power source through a silicide layer,
The gates of the fourth P-channel MOS transistor and the fourth N-channel MOS transistor are connected to each other and connected to the first output terminal (DEC1),
The drain region of the fourth P-channel MOS transistor and the drain region of the fourth N-channel MOS transistor are connected to each other to become a second output terminal (SEL1),
The source region of the fourth P-channel MOS transistor and the source region of the fourth N-channel MOS transistor are connected to a power supply line and a reference power supply line, respectively.
The semiconductor device includes:
A first a address signal lines;
A second b address signal lines;
A third c address signal lines;
a × b × c NAND decoders and inverters;
Have
In each of the a × b × c NAND decoders and inverters,
The gates of the first P-channel MOS transistor and the first N-channel MOS transistor connected to each other are connected to any one of the first a address signal lines,
The gates of the second P-channel MOS transistor and the second N-channel MOS transistor connected to each other are connected to any one of the second b address signal lines,
The gates of the third P-channel MOS transistor and the third N-channel MOS transistor connected to each other are connected to any one of the third c address signal lines,
The power supply line, the reference power supply line, the first a address signal lines, the second b address signal lines, and the third c address signal lines are perpendicular to the first direction. And extending in the second direction.

  (25) In a preferred aspect of the present invention, the eight transistors are one of the fourth N-channel MOS transistor or the fourth P-channel MOS transistor, the fourth N-channel MOS transistor, or the fourth P-channel MOS transistor. The other of the channel MOS transistors, the third P channel MOS transistor, the second P channel MOS transistor, the first P channel MOS transistor, the first N channel MOS transistor, the second N channel MOS transistor The third N-channel MOS transistors are arranged in one row in the order.

(26) In another aspect, source regions of the fourth P-channel MOS transistor and the fourth N-channel MOS transistor are disposed closer to the substrate than the silicon pillar,
The eight transistors include the fourth N-channel MOS transistor, the fourth P-channel MOS transistor, the third P-channel MOS transistor, the second P-channel MOS transistor, and the first P-channel MOS transistor. The first N-channel MOS transistor, the second N-channel MOS transistor, and the third N-channel MOS transistor are arranged in one row in this order.

  (27) In another aspect, the first P-channel MOS transistor, the second P-channel MOS transistor, and the third P-channel MOS constituting the a × b × c NAND decoders and inverters The transistor and the source region of the fourth P-channel MOS transistor are commonly connected via a silicide layer.

  (28) In another aspect, the gates of the first P-channel MOS transistor and the first N-channel MOS transistor, or the second P-channel MOS transistor and the second N-channel MOS transistor At least one of the gates or the gates of the third P-channel MOS transistor and the third N-channel MOS transistor is at least via a wiring of a first metal wiring layer arranged to extend in the first direction. And connected to address signal lines corresponding to the first to third address signal lines constituted by the wiring of the second metal wiring layer arranged to extend in the second direction.

FIG. 3 is an equivalent circuit diagram illustrating the decoder according to the first embodiment of the present invention. It is a top view of the decoder of Example 1 of this invention. It is a top view of the decoder of Example 1 of this invention. It is sectional drawing of the decoder of Example 1 of this invention. It is sectional drawing of the decoder of Example 1 of this invention. It is sectional drawing of the decoder of Example 1 of this invention. It is sectional drawing of the decoder of Example 1 of this invention. It is sectional drawing of the decoder of Example 1 of this invention. It is sectional drawing of the decoder of Example 1 of this invention. It is sectional drawing of the decoder of Example 1 of this invention. It is sectional drawing of the decoder of Example 1 of this invention. It is an equivalent circuit schematic which shows the decoder of Example 2 of this invention. It is a top view of the decoder of Example 2 of this invention. It is sectional drawing of the decoder of Example 2 of this invention. It is an equivalent circuit diagram which shows the decoder of Example 3 of this invention. It is an address map of the decoder of Example 3 of this invention. It is a top view of the decoder of Example 3 of this invention. It is a top view of the decoder of Example 3 of this invention. It is a top view of the decoder of Example 3 of this invention. It is a top view of the decoder of Example 3 of this invention. It is sectional drawing of the decoder of Example 3 of this invention. It is sectional drawing of the decoder of Example 3 of this invention. It is sectional drawing of the decoder of Example 3 of this invention. It is sectional drawing of the decoder of Example 3 of this invention. It is sectional drawing of the decoder of Example 3 of this invention. It is sectional drawing of the decoder of Example 3 of this invention. It is sectional drawing of the decoder of Example 3 of this invention. It is sectional drawing of the decoder of Example 3 of this invention. It is sectional drawing of the decoder of Example 3 of this invention. It is sectional drawing of the decoder of Example 3 of this invention. It is sectional drawing of the decoder of Example 3 of this invention. It is sectional drawing of the decoder of Example 3 of this invention. It is sectional drawing of the decoder of Example 3 of this invention. It is an equivalent circuit diagram which shows the decoder of Example 4 of this invention. It is a top view of the decoder of Example 4 of this invention. It is a top view of the decoder of Example 4 of this invention. It is sectional drawing of the decoder of Example 4 of this invention. It is sectional drawing of the decoder of Example 4 of this invention. It is sectional drawing of the decoder of Example 4 of this invention. It is sectional drawing of the decoder of Example 4 of this invention. It is sectional drawing of the decoder of Example 4 of this invention. It is sectional drawing of the decoder of Example 4 of this invention. It is sectional drawing of the decoder of Example 4 of this invention. It is sectional drawing of the decoder of Example 4 of this invention. It is sectional drawing of the decoder of Example 4 of this invention. It is sectional drawing of the decoder of Example 4 of this invention. It is an equivalent circuit diagram which shows the decoder of Example 5 of this invention. It is a top view of the decoder of Example 5 of this invention. It is a top view of the decoder of Example 5 of this invention. It is sectional drawing of the decoder of Example 5 of this invention. It is sectional drawing of the decoder of Example 5 of this invention. It is sectional drawing of the decoder of Example 5 of this invention. It is an equivalent circuit diagram which shows the decoder of Example 6 of this invention. It is an equivalent circuit diagram which shows the decoder of Example 6 of this invention. It is an address map of the decoder of Example 6 of this invention. It is an address map of the decoder of Example 6 of this invention. It is a top view of the decoder of Example 6 of this invention. It is a top view of the decoder of Example 6 of this invention. It is a top view of the decoder of Example 6 of this invention. It is a top view of the decoder of Example 6 of this invention. It is a top view of the decoder of Example 6 of this invention. It is sectional drawing of the decoder of Example 6 of this invention. It is sectional drawing of the decoder of Example 6 of this invention. It is sectional drawing of the decoder of Example 6 of this invention. It is sectional drawing of the decoder of Example 6 of this invention. It is sectional drawing of the decoder of Example 6 of this invention. It is sectional drawing of the decoder of Example 6 of this invention. It is sectional drawing of the decoder of Example 6 of this invention. It is sectional drawing of the decoder of Example 6 of this invention. It is sectional drawing of the decoder of Example 6 of this invention. It is sectional drawing of the decoder of Example 6 of this invention. It is sectional drawing of the decoder of Example 6 of this invention. It is sectional drawing of the decoder of Example 6 of this invention. It is sectional drawing of the decoder of Example 6 of this invention. It is sectional drawing of the decoder of Example 6 of this invention. It is sectional drawing of the decoder of Example 6 of this invention. It is sectional drawing of the decoder of Example 6 of this invention. It is sectional drawing of the decoder of Example 6 of this invention. It is sectional drawing of the decoder of Example 6 of this invention. It is the equivalent circuit of the inverter which shows a prior art example. It is a top view of the conventional inverter comprised by SGT. It is sectional drawing of the conventional inverter comprised by SGT.

Example 1
(Equivalent circuit applied to the embodiment of the present invention)
FIG. 1 shows a circuit diagram in which transistors constituting a three-input NAND type decoder constituted by a three-input NAND circuit applied to the present invention are arranged corresponding to the arrangement of the embodiment. Tp11, Tp12, and Tp13 are PMOS transistors composed of SGT, and Tn11, Tn12, and Tn13 are NMOS transistors that are also composed of SGT. The sources of the PMOS transistors Tp11, Tp12, and Tp13 are connected to the power supply Vcc, and the drains are commonly connected to the output terminal DEC1. The drain of the NMOS transistor Tn11 is connected to the output terminal DEC1, the source is connected to the drain of the NMOS transistor Tn12, the source of the NMOS transistor Tn12 is connected to the drain of the NMOS transistor Tn13, and the source of the NMOS transistor Tn13 is the reference Connected to the power supply Vss. The address signal line A1 is connected to the gates of the PMOS transistor Tp11 and NMOS transistor Tn11, the address signal line A2 is connected to the gates of the PMOS transistor Tp12 and NMOS transistor Tn12, and the gates of the PMOS transistor Tp13 and NMOS transistor Tn13. Is connected to the address signal line A3.

A PMOS transistor Tp11, Tp12, Tp13 and NMOS transistors Tn11, Tn12 and Tn13 constitute a 3-input NAND decoder 101. The NAND decoder 101 is a decoder having a negative logic output (the output of the selected decoder is logic “0”). When a positive logic output (the output of the selected decoder becomes logic “1”) is required, an inverter may be combined as will be described later.

As an embodiment in which the equivalent circuit of FIG. 1 is applied to the present invention, Embodiment 1 is shown in FIGS. 2a, 2b, and 3a to 3h. FIG. 2A is a plan view of the layout (arrangement) of the 3-input NAND decoder 101 of this embodiment. FIG. 2B is a plan view of the transistor and the gate wiring, and shows the connection relationship between the address signal and the gate wiring. 3a is a cross-sectional view along the cut line AA ′ in FIG. 2a, FIG. 3b is a cross-sectional view along the cut line BB ′ in FIG. 2a, and FIG. 3c is a cut line CC in FIG. 3d is a cross-sectional view along the cut line DD ′ in FIG. 2a, FIG. 3e is a cross-sectional view along the cut line EE ′ in FIG. 2a, and FIG. 2a is a cross-sectional view taken along the cut line FF ′ in FIG. 2a, FIG. 3g is a cross-sectional view taken along the cut line GG ′ in FIG. 2a, and FIG. 3h is a cross-sectional view taken along the cut line HH ′ in FIG. The figure is shown.
In FIGS. 2a, 2b, and 3a to 3h, portions having the same structure as those in FIGS. 21, 22, and 23 are indicated by equivalent symbols in the 100s.

In FIG. 2a, PMOS transistors Tp13, Tp12, Tp11, NMOS transistors Tn11, Tn12, and Tn13, which are six SGTs constituting the NAND decoder 101 of FIG. Are defined in a direction).
Further, in the vertical direction of the figure (this is defined as a second direction perpendicular to the first direction), wirings 115a, 115b, 115d, 115e, 115g, 115h, and 115j of a second metal wiring layer to be described later are provided. The power supply line Vcc, the power supply line Vcc, the power supply line Vcc, the address signal line A1, the address signal line A2, the address signal line A3, and the reference power supply line Vss are arranged extending in the vertical direction (second direction). The feature of this embodiment is that the six transistors constituting the three-input NAND decoder are arranged in one row, and the circuit is efficiently connected so that the arrangement area is minimized. 2A and 2B, the gate electrodes 106 of the PMOS transistor Tp11 and the NMOS transistor Tn11 are directly connected by the gate wiring 106a, and the gate electrodes 106 of the PMOS transistor Tp12 and the NMOS transistor Tn12 are directly connected by the gate wiring 106b. Then, the gate electrodes 106 of the PMOS transistor Tp13 and NMOS transistor Tn13 are directly connected by the gate wiring 106c (disposed on the lower side of the figure), thereby arranging the three-input NAND decoders in one column. It is possible. Further, the address signal line is supplied to the gate wiring by using the wiring of the second metal wiring layer arranged to extend vertically (second direction). That is, the address signal A1 supplied to the wiring 115e of the second metal wiring layer is connected to the gate wiring 106a by the A1 contact portion including the contact 111k, the wiring 113k of the first metal wiring layer, and the contact 114k. The address signal A2 supplied to the wiring 115g of the second metal wiring layer is connected to the gate wiring 106b by the A2 contact portion including the wiring 113m of the first metal wiring layer and the contact 114m, and the wiring of the contact 111n and the wiring of the first metal wiring layer The address signal A3 supplied to the wiring 115h of the second metal wiring layer is connected to the gate wiring 106c by the A3 contact portion consisting of 113n and contact 114n.

In this embodiment, one NAND type decoder with three inputs is used, but the repetition pitch (dimension) when a plurality of NAND decoders are arranged in the vertical direction is Ly. The reason why the pitch can be set to Ly is that, as will be described later, the upper gate wiring 106b is shared with a decoder disposed adjacent to the upper side, and the lower gate wiring 106c is shared with a decoder disposed adjacent to the lower side. It is to be done. That is, the upper and lower decoders can minimize the layout area by inverting the 3-input NAND type decoder of this embodiment. Hereinafter, this embodiment will be described in detail.

Planar silicon layers 102pa, 102na and 102nb are formed on an insulating film such as a buried oxide film layer (BOX) 101 formed on the substrate, and the planar silicon layers 102pa, 102na and 102nb are formed by impurity implantation or the like, respectively. A p + diffusion layer, an n + diffusion layer, and an n + diffusion layer are formed. 103 is a silicide layer formed on the surface of the planar silicon layers (102pa, 102na and 102nb), and connects the planar silicon layers 102pa and 102na. 104n11, 104n12, 104n13 are n-type silicon pillars, 104p11, 104p12, 104p13 are p-type silicon pillars, 105 is a gate insulating film surrounding the silicon pillars 104n11, 104n12, 104n13, 104p11, 104p12, 104p13, 106 is a gate electrode, 106a, 106b and 106c are gate wirings. The gate insulating film 105 is also formed under the gate electrode 106 and the gate wirings 106a, 106b, and 106c.
P + diffusion layers 107p11, 107p12, and 107p13 are respectively formed on the uppermost portions of the silicon pillars 104n11, 104n12, and 104n13 by impurity implantation or the like, and n + diffusion layers 107n11 and 107n12 are formed on the uppermost parts of the silicon pillars 104p11, 104p12, and 104p13, respectively. And 107n13 are formed by impurity implantation or the like. 108 is a silicon nitride film for protecting the gate insulating film 105, 109p11, 109p12, 109p13, 109n11, 109n12 and 109n13 are silicides connected to p + diffusion layers 107p11, 107p12 and 107p13 and n + diffusion layers 107n11, 107n12 and 107n13, respectively. Is a layer.

110p11, 110p12, 110p13, 110n11, 110n12, and 110n13 are contacts that connect the silicide layers 109p11, 109p12, 109p13, 109n11, 109n12, and 109n13 and the wirings 113c, 113b, 113a, 113d, 113d, and 113e of the first metal wiring layer, respectively. It is. 111k is a contact for connecting the gate wiring 106a and the wiring 113k of the first metal wiring layer, 111m is a contact for connecting the gate wiring 106b and the wiring 113m of the first metal wiring layer, 111n is a contact of the gate wiring 106c and the first metal wiring layer. It is a contact for connecting the wiring 113n. 114p11 is a contact connecting the wiring 113c of the first metal wiring layer and the wiring 115d of the second metal wiring layer, 114p12 is a contact connecting the wiring 113b of the first metal wiring layer and the wiring 115b of the second metal wiring layer, and 114p13 is A contact connecting the wiring 113a of the first metal wiring layer and the wiring 115a of the second metal wiring layer, 114n13 is a contact connecting the wiring 113e of the first metal wiring layer and the wiring 115j of the second metal wiring layer, and 114k is the first. A contact connecting the wiring 113k of the metal wiring layer and the wiring 115e of the first metal wiring layer, 114m is a contact connecting the wiring 113m of the first metal wiring layer and the wiring 115g of the second metal wiring layer, and 114n is the first metal wiring layer. To connect the wiring 113n and the wiring 115n of the second metal wiring layer It is a door.

The silicon pillar 104n11, the lower diffusion layer 102pa, the upper diffusion layer 107p11, the gate insulating film 105, and the gate electrode 106 constitute a PMOS transistor Tp11.
The silicon pillar 104n12, the lower diffusion layer 102pa, the upper diffusion layer 107p12, the gate insulating film 105, and the gate electrode 106 constitute a PMOS transistor Tp12.
The silicon pillar 104n13, the lower diffusion layer 102pa, the upper diffusion layer 107p13, the gate insulating film 105, and the gate electrode 106 constitute a PMOS transistor Tp13.
The silicon pillar 104p11, the lower diffusion layer 102na, the upper diffusion layer 107n11, the gate insulating film 105, and the gate electrode 106 constitute an NMOS transistor Tn11.
The silicon pillar 104p12, the lower diffusion layer 102nb, the upper diffusion layer 107n12, the gate insulating film 105, and the gate electrode 106 constitute an NMOS transistor Tn12,
The silicon pillar 104p13, the lower diffusion layer 102nb, the upper diffusion layer 107n13, the gate insulating film 105, and the gate electrode 106 constitute an NMOS transistor Tn13.
The gate wiring 106a is connected to the gate electrodes 106 of the PMOS transistor Tp11 and NMOS transistor Tn11, the gate wiring 106b is connected to the gate electrodes 106 of the PMOS transistor Tp12 and NMOS transistor Tn12, and the PMOS transistor Tp13 and the NMOS transistor Tn13 are connected. A gate wiring 106 c is connected to the gate electrode 106.

The lower diffusion layers 102pa and 102na are connected by the silicide layer 103 to be a common drain of the PMOS transistor Tp11, the PMOS transistor Tp12, the PMOS transistor Tp13, and the NMOS transistor Tn11, and are connected to the output DEC1. The upper diffusion layer 107p11 which is the source of the PMOS transistor Tp11 is connected to the wiring 113c of the first metal wiring layer through the silicide 109p11 and the contact 110p11, and the wiring 113c of the first metal wiring layer is connected to the second metal wiring through the contact 114p11. The power supply Vcc is supplied to the wiring 115d of the second metal wiring layer.
The upper diffusion layer 107p12 that is the source of the PMOS transistor Tp12 is connected to the wiring 113b of the first metal wiring layer through the silicide 109p12 and the contact 110p12, and the wiring 113b of the first metal wiring layer is connected to the second metal wiring through the contact 114p12. The power supply Vcc is supplied to the wiring 115b of the second metal wiring layer.
The upper diffusion layer 107p13 which is the source of the PMOS transistor Tp13 is connected to the wiring 113a of the first metal wiring layer through the silicide 109p13 and the contact 110p13, and the wiring 113a of the first metal wiring layer is connected to the second metal wiring through the contact 114p13. The power supply Vcc is supplied to the wiring 115a of the second metal wiring layer.
The upper diffusion layer 107n11 which is the source of the NMOS transistor Tn11 is connected to the wiring 113d of the first metal wiring layer via the silicide 109n11 and the contact 110n11, and the upper diffusion layer 107n12 which is the drain of the NMOS transistor Tn12 is connected to the silicide 109n12 and the contact 110n12. To the wiring 113d of the first metal wiring layer. Here, the source of the NMOS transistor Tn11 and the drain of the NMOS transistor Tn12 are connected through the wiring 113d of the first metal wiring layer. The lower diffusion layer 102nb covered with the silicide layer 103 becomes the source region of the NMOS transistor Tn12 and the drain region of the NMOS transistor Tn13, and the source of the NMOS transistor Tn12 and the drain of the NMOS transistor Tn13 are connected. The source region 107n13 of the NMOS transistor Tn13 is connected to the wiring 115j of the second metal wiring layer via the contact 110n13, the wiring 113e of the first metal wiring layer, and the contact 114n13, and the reference power supply is connected to the wiring 115j of the second metal wiring layer. Vss is supplied.

The address signal A1 is supplied to the wiring 115e of the second metal wiring layer, and is connected to the gate wiring 106a via the contact 114k, the wiring 113k of the first metal wiring layer, and the contact 111k, and the PMOS transistor Tp11 and the NMOS transistor Tn11 Supplied to the gate electrode.
The address signal A2 is supplied to the wiring 115g of the second metal wiring layer, and is connected to the gate wiring 106b through the contact 114m, the wiring 113m of the first metal wiring layer, and the contact 111m, and the PMOS transistor Tp12 and the NMOS transistor Tn12 Supplied to the gate electrode.
The address signal A3 is supplied to the wiring 115h of the second metal wiring layer, and is connected to the gate wiring 106c through the contact 114n, the wiring 113n of the first metal wiring layer, and the contact 111n, and the PMOS transistor Tp13 and the NMOS transistor Tn13 Supplied to the gate electrode.
In FIG. 2a, the dimension in the vertical direction (second direction) is the minimum processing dimension determined by the dimension of the SGT, the margin between the SGT and the lower diffusion layer, and the distance between the diffusion layers, and is defined as Ly. That is, a plurality of the three-input NAND decoders 101 according to the present embodiment can be arranged adjacent to each other with a minimum pitch (minimum interval) Ly in the vertical direction.

According to this embodiment, six SGTs constituting a three-input NAND decoder are arranged in one column in the first direction, and the power supply line Vcc, the reference power supply line Vss, the address signal lines A1, A2, and A3 are By disposing and extending in the second direction perpendicular to the first direction, it is possible to provide a semiconductor device that constitutes a three-input NAND decoder with a reduced area without providing unnecessary wiring and contact regions.

(Example 2)
(Equivalent circuit applied to the embodiment of the present invention)
FIG. 4 shows a circuit diagram in which a 3-input NAND decoder applied to the present invention and a decoder constituting the inverter are arranged corresponding to the arrangement of the embodiment.
In FIG. 4, a three-input NAND decoder 101 is the same as FIG. The decoder 100 is configured by adding an inverter 102 including a PMOS transistor Tp14 and an NMOS transistor Tn14 to FIG. The gates of the PMOS transistor Tp14 and the NMOS transistor Tn14 are commonly connected to the output DEC1 of the three-input NAND type decoder 101, the drains of the PMOS transistor Tp14 and the NMOS transistor Tn14 are commonly connected to form the decoder output SEL1, and the PMOS transistor Tp14. And the source of the NMOS transistor Tn14 are connected to the power supply Vcc and the reference power supply Vss, respectively.
As described above, by adding the inverter 102 to the NAND-type decoder 101 having the negative logic output, the output SEL1 of the decoder 100 becomes a positive logic output (the output of the selected decoder is logic “1”). Here, the inverter 102 has both a logic inversion function and a buffer function (amplifying the driving capability of the NAND decoder 101).

As an embodiment in which the equivalent circuit of FIG. 4 is applied to the present invention, a second embodiment is shown in FIGS. FIG. 5 is a plan view of the layout (arrangement) of the 3-input NAND decoder 101 and the inverter 102 of this embodiment. 6 is a cross-sectional view taken along the cut line BB ′ in FIG. 5 and corresponds to FIG. 3b.
In FIGS. 5 and 6, portions having the same structure as in FIGS. 2a and 3b are indicated by equivalent symbols in the 100s.
5, PMOS transistors Tp13, Tp12, Tp11, NMOS transistors Tn11, Tn12 and Tn13, which are six SGTs constituting the NMOS transistor Tn14, the PMOS transistor Tp14, and the 3-input NAND decoder 101 constituting the inverter 102, They are arranged in a row in the horizontal direction (first direction) from the right side of the figure.
The 3-input NAND decoder 101 of FIG. 5 is the same as FIG. 2a, and the inverter 102 not shown in FIG. 2a will be described in detail.

Planar silicon layers 102pb and 102nc are formed on an insulating film such as a buried oxide film layer (BOX) 101 formed on the substrate, and the planar silicon layers 102pb and 102nc are respectively formed as p + diffusion layers by impurity implantation or the like. , N + diffusion layers are formed. Reference numeral 103 denotes a silicide layer formed on the surface of the planar silicon layers (102pb, 102nc), which connects the planar silicon layers 102pb and 102nc. 104n14 is an n-type silicon pillar, 104p14 is a p-type silicon pillar, 105 is a gate insulating film surrounding the silicon pillars 104n14 and 104p14, 106 is a gate electrode, and 106d is a gate wiring.
A p + diffusion layer 107p14 is formed on the uppermost part of the silicon pillar 104n14 by impurity implantation or the like, and an n + diffusion layer 107n14 is formed on the uppermost part of the silicon pillar 104p14 by impurity implantation or the like. Reference numeral 108 denotes a silicon nitride film for protecting the gate insulating film 105, and reference numerals 109p14 and 109n14 denote silicide layers connected to the p + diffusion layer 107p14 and the n + diffusion layer 107n14, respectively.
110p14 and 110n14 are contacts for connecting the silicide layers 109p14 and 109n14 and the wirings 113g and 113f of the first metal wiring layer, respectively. 111a is a contact for connecting the gate wiring 106d and the wiring 113h of the first metal wiring layer, and 112a is a contact for connecting the silicide layer 103 which is the output DEC1 of the 3-input NAND decoder and the wiring 113h of the first metal wiring layer. 114p14 is a contact for connecting the wiring 113g of the first metal wiring layer and the wiring 115l of the second metal wiring layer, and 114n14 is a contact for connecting the wiring 113f of the first metal wiring layer and the wiring 115k of the second metal wiring layer.

The silicon pillar 104n14, the lower diffusion layer 102pb, the upper diffusion layer 107p14, the gate insulating film 105, and the gate electrode 106 constitute a PMOS transistor Tp14.
The silicon pillar 104p14, the lower diffusion layer 102nc, the upper diffusion layer 107n14, the gate insulating film 105, and the gate electrode 106 constitute an NMOS transistor Tn14.
Further, the gate electrodes 106 of the PMOS transistor Tp14 and the NMOS transistor Tn14 are connected in common and the gate wiring 106d is connected.
The lower diffusion layers 102pb and 102nc are connected by the silicide layer 103, become the common drain of the PMOS transistor Tp14 and the NMOS transistor Tn14, and are connected to the output SEL1.
The upper diffusion layer 107p14 which is the source region of the PMOS transistor Tp14 is connected to the wiring 113g of the first metal wiring layer via the silicide layer 109p14 and the contact 110p14, and the wiring 113g of the first metal wiring layer is connected to the second metal via the contact 114p14. The power supply Vcc is supplied to the wiring 115l of the second metal wiring layer connected to the wiring 115l of the metal wiring layer.
The upper diffusion layer 107n14 that is the source region of the NMOS transistor Tn14 is connected to the wiring 113f of the first metal wiring layer via the silicide layer 109n14 and the contact 110n14, and the wiring 113f of the first metal wiring layer is connected to the second metal via the contact 114n14. The reference power supply Vss is supplied to the wiring 115k of the second metal wiring layer, which is connected to the wiring 115k of the metal wiring layer.

The address signal A1 is supplied to the wiring 115e of the second metal wiring layer, and is connected to the gate wiring 106a via the contact 114k, the wiring 113k of the first metal wiring layer, and the contact 111k, and the PMOS transistor Tp11 and the NMOS transistor Tn11 Supplied to the gate electrode.
The address signal A2 is supplied to the wiring 115g of the second metal wiring layer, and is connected to the gate wiring 106b through the contact 114m, the wiring 113m of the first metal wiring layer, and the contact 111m, and the PMOS transistor Tp12 and the NMOS transistor Tn12 Supplied to the gate electrode.
The address signal A3 is supplied to the wiring 115h of the second metal wiring layer, and is connected to the gate wiring 106c through the contact 114n, the wiring 113n of the first metal wiring layer, and the contact 111n, and the PMOS transistor Tp13 and the NMOS transistor Tn13 Supplied to the gate electrode.
In FIG. 5a, as in FIG. 2a, the dimension in the vertical direction (second direction) is the minimum processing dimension determined by the dimension of the SGT, the margin between the SGT and the lower diffusion layer, and the distance between the diffusion layers, and is defined as Ly. To do. That is, a plurality of decoders 100 (three-input NAND decoder 101 and inverter 102) of the present embodiment can be arranged adjacent to each other with a minimum pitch (minimum interval) Ly in the vertical direction.

According to this embodiment, six SGTs constituting a three-input NAND decoder and two SGTs constituting an inverter are arranged in one column in the first direction, and a power supply line Vcc, a reference power supply line Vss, By arranging the address signal lines A1, A2 and A3 in a second direction perpendicular to the first direction, a decoder (3-input NAND) having a reduced area without providing unnecessary wiring and contact regions is provided. A semiconductor device constituting a type decoder and an inverter) can be provided.

(Example 3)
(Equivalent circuit applied to the embodiment of the present invention)
FIG. 7 shows an equivalent circuit diagram in which a plurality of 3-input NAND decoders and inverters applied to the present invention are arranged to constitute the decoder.
Six address signal lines A1, A2, A3, A4, A5, and A6 are provided. A1 and A2 are selectively connected to the gates of the PMOS transistor Tpk1 (k is a natural number) and the NMOS transistor Tnk1, and A3 and A4 is selectively connected to the gates of PMOS transistor Tpk2 and NMOS transistor Tnk2, and A5 and A6 are selectively connected to the gates of PMOS transistor Tpk3 and NMOS transistor Tnk3. Eight address signals A1 to A6 constitute eight decoders 100-1 to 100-8.
Address signal lines A1, A3 and A5 are connected to the decoder 100-1,
Address signal lines A2, A3 and A5 are connected to the decoder 100-2,
Address signal lines A1, A4 and A5 are connected to the decoder 100-3,
Address signal lines A2, A4 and A5 are connected to the decoder 100-4.
Address signal lines A1, A3 and A6 are connected to the decoder 100-5,
Address signal lines A2, A3 and A6 are connected to the decoder 100-6.
Address signal lines A1, A4 and A6 are connected to the decoder 100-7,
Address signal lines A2, A4 and A6 are connected to the decoder 100-8.
A location where the address signal line is connected is indicated by a dotted circle.
As will be described later, the address signal line A3 is commonly connected to the decoders 100-1 and 100-2, and is commonly connected to the decoders 100-5 and 100-6. The address signal line A4 is commonly connected to the decoders 100-3 and 100-4, and is commonly connected to the decoders 100-7 and 100-8. Address signal line A5 is commonly connected to decoders 100-1 to 100-4, and address signal line A6 is commonly connected to decoders 100-5 to 100-8.

FIG. 8 shows an address map of the eight decoders of FIG. Address signals connected to the decoder outputs DEC1 / SEL1 to DEC8 / SEL8 are indicated by circles. As will be described later, a contact is provided and connected.

Example 3 is shown in FIGS. 9a to 9d and FIGS. 10a to 10m. This embodiment implements the equivalent circuit of FIG. 7, and is adjacent to the upper and lower sides (second direction) of the figure with eight decoders 100 and 100-1 to 100-8 in FIG. 5 with the minimum pitch Ly. Are arranged. In the arrangement, 100-1, 100-3, 100-5, 100-7 are arranged upside down in FIG. 5, and 100-2, 100-4, 100-6, 100-8 are arranged in the normal direction. It is. As a result, the gate wiring 106c or the gate wiring 106d of the adjacent decoders can be shared, and the vertical pitch can be minimized. 9a and 9b are plan views of the layout (arrangement) of the three-input NAND decoder and inverter of the present invention. FIGS. 9c and 9d are the bottom diffusion layer, each transistor and each of the plan views of FIGS. 9a and 9b. FIG. 5 is a diagram showing only the gate wiring and showing the connection between the address signal and the gate wiring in an easily understandable manner.
10a is a cross-sectional view along the cut line AA ′ in FIG. 9a, FIG. 10b is a cross-sectional view along the cut line BB ′ in FIG. 9a, and FIG. 10c is along the cut line CC ′ in FIG. 10d is a cross-sectional view taken along the cut line DD ′ in FIG. 9a, FIG. 10e is a cross-sectional view taken along the cut line EE ′ in FIG. 9b, and FIG. 10f is a cut line F− in FIG. Fig. 10g is a cross-sectional view taken along the cut line GG 'in Fig. 9a, Fig. 10h is a cross-sectional view taken along the cut line HH' in Fig. 9a, and Fig. 10i is shown in Fig. 9a. FIG. 10j is a cross-sectional view along the cut line JJ ′ in FIG. 9a, FIG. 10k is a cross-sectional view along the cut line KK ′ in FIG. 9a, and FIG. Figure 9a 'Cross-sectional view taken along, FIG 10m is cut line M-M in FIG. 9a' cut line L-L that shows a cross-sectional view taken along.
9a corresponds to the decoder block 110a in FIG. 7, and FIG. 9b corresponds to the decoder block 110b in FIG. Although FIGS. 9a and 9b are continuous drawings, in order to enlarge the drawings, the drawings are divided into FIGS. 9a and 9b for convenience.

9a, the NMOS transistor Tn14, the PMOS transistors Tp14, Tp13, Tp12, Tp11, and the NMOS transistors Tn11, Tn12, and Tn13 that form the decoder 100-1 of FIG. 7 are arranged in the lateral direction (first direction) from the right in the drawing. One row is arranged in the top row of the figure.
The NMOS transistor Tn24, the PMOS transistors Tp24, Tp23, Tp22, Tp21, and the NMOS transistors Tn21, Tn22, and Tn23 constituting the decoder 100-2 are arranged in one column in the horizontal direction (first direction) from the right side of the figure, It is arranged in the second column from. Similarly, the decoder 100-3 and the decoder 100-4 are sequentially arranged from the top of FIG. 9a.
The gate electrodes 106 of the PMOS transistors Tp12 and Tp22 and the NMOS transistors Tn12 and Tn22 are commonly connected by a gate wiring 106c. Since the gate wiring 106c is disposed in the gap (dead space) between the lower diffusion layers of the decoder 100-1 and the decoder 100-2, the size in the vertical direction (second direction) can be minimized, and the gate wiring is shared. By doing so, the parasitic capacitance of the wiring can be reduced, and high-speed operation becomes possible.
Similarly, the gate electrodes 106 of the PMOS transistors Tp32 and Tp42 and the NMOS transistors Tn32 and Tn42 are commonly connected by a gate wiring 106c. The gate wiring 106c is disposed in a gap (dead space) between the lower diffusion layers of the decoder 100-3 and the decoder 100-4.
The gate electrodes 106 of the PMOS transistors Tp13, Tp23, Tp33, Tp43, and the NMOS transistors Tn13, Tn23, Tn33, and Tn34 are connected in common by gate wirings 106d, 106d1, 106d2, 106d3, 106d4. Since the gate wiring 106d is disposed in the gap (dead space) between the lower diffusion layers of the decoder 100-2 and the decoder 100-3, the size in the vertical direction (second direction) can be minimized, and the gate wiring is shared. By doing so, the parasitic capacitance of the wiring can be reduced, and high-speed operation becomes possible.

Similarly in FIG. 9b, the NMOS transistor Tn54, the PMOS transistors Tp54, Tp53, Tp52, Tp51, and the NMOS transistors Tn51, Tn52, and Tn53 constituting the decoder 100-5 in FIG. (Direction) in one row and the top row in the figure.
The NMOS transistor Tn64, the PMOS transistors Tp64, Tp63, Tp62, Tp61, and the NMOS transistors Tn61, Tn62, and Tn63 constituting the decoder 100-6 are arranged in one column in the horizontal direction (first direction) from the right side of the drawing, It is arranged in the second column from. Similarly, a decoder 100-7 and a decoder 100-8 are sequentially arranged from the top of FIG. 9b.
The gate electrodes 106 of the PMOS transistors Tp52 and Tp62 and the NMOS transistors Tn52 and Tn62 are connected in common by a gate wiring 106c. Since the gate wiring 106c is disposed in the gap (dead space) between the lower diffusion layers of the decoder 100-5 and the decoder 100-6, the vertical dimension (second direction) can be minimized and the gate wiring can be shared. By doing so, the parasitic capacitance of the wiring can be reduced, and high-speed operation becomes possible.
Similarly, the gate electrodes 106 of the PMOS transistors Tp72 and Tp82 and the NMOS transistors Tn72 and Tn82 are commonly connected by a gate wiring 106c. The gate wiring 106c is disposed in a gap (dead space) between the lower diffusion layers of the decoder 100-7 and the decoder 100-8.
The gate electrodes 106 of the PMOS transistors Tp53, Tp63, Tp73, Tp83, and the NMOS transistors Tn53, Tn63, Tn73, and Tn83 are connected in common by gate wirings 106d, 106d1, 106d2, 106d3, and 106d4. Since the gate wiring 106d is disposed in the gap (dead space) between the lower diffusion layers of the decoder 100-6 and the decoder 100-7, the size in the vertical direction (second direction) can be minimized and the gate wiring can be shared. By doing so, the parasitic capacitance of the wiring can be reduced, and high-speed operation becomes possible.

9a and 9b, the wirings 115k, 115l, 115a, 115b, 115c, 115d, 115e, 115f, 115g, 115h, 115i, and 115j of the second metal wiring layer are arranged in the vertical direction (second direction) from the right side. The reference power supply line Vss, power supply line Vcc, power supply line Vcc, power supply line Vcc, address signal line A1, power supply line Vcc, address signal line A2, A3, A4, A5, A6, reference power supply line Vss, respectively. Configure. Since the wirings 115a to 115l of the second metal wiring layer are arranged at the minimum pitch (minimum wiring width and minimum wiring interval) of the second metal wiring layer, the horizontal dimension can be arranged at the minimum.
In FIGS. 9a to 9d and FIGS. 10a to 10m, portions having the same structure as those in FIGS. 2a, 2b, and 3a to 3h are indicated by equivalent symbols in the 100s.

NMOS transistors Tn14, which are eight SGTs constituting the decoder 100-1, PMOS transistors Tp14, Tp13, Tp12, Tp11, NMOS transistors Tn11, Tn12, Tn13, and NMOSs which are eight SGTs constituting the decoder 110-8 The arrangement of the transistors Tn84, PMOS transistors Tp84, Tp83, Tp82, Tp81, NMOS transistors Tn81, Tn82, Tn83 are NMOS transistors Tn14, PMOS transistors Tp14, Tp13, Tp12, Tp11 which are eight SGTs in FIG. The arrangement of the NMOS transistors Tn11, Tn12, and Tn13 is the same. 9a and 9b differ from FIG. 5 in that the arrangement position and connection location of the wiring of the second metal wiring layer for supplying the address signal are changed as the address signal increases from A1 to A3 to A1 to A6. That is.

9a and 9b,
The wiring 115k of the second metal wiring layer that supplies the reference power supply Vss extends in the second direction and is connected to the sources of the NMOS transistors Tn14 and Tn24 to Tn84.
The wiring 115l of the second metal wiring layer for supplying the power supply Vcc extends in the second direction and is connected to the sources of the PMOS transistors Tp14 and Tp24 to Tp84.
The wiring 115a of the second metal wiring layer for supplying the power supply Vcc extends in the second direction and is connected to the sources of the PMOS transistors Tp13 and Tp23 to Tp83.
The wiring 115b of the second metal wiring layer for supplying the power supply Vcc extends in the second direction and is connected to the sources of the PMOS transistors Tp12, Tp22 to Tp82.

The wiring 115c of the second metal wiring layer that supplies the address signal A1 extends in the second direction, and is connected to the gate wiring 106b via the contact 114k1, the wiring 113k1 of the first metal wiring layer, and the contact 111k1, and the PMOS The gate electrodes 106 of the transistors Tp11, Tp31, Tp51, and Tp71 are connected to the gate electrodes 106 of the NMOS transistors Tn11, Tn31, Tn51, and Tn71 through the gate wiring 106a.
The wiring 115d of the second metal wiring layer for supplying the power supply Vcc extends in the second direction and is connected to the sources of the PMOS transistors Tp11, Tp21 to Tp81.
The second metal wiring layer wiring 115e for supplying the address signal A2 extends in the second direction and is connected to the gate wiring 106a via the contact 114k2, the first metal wiring layer wiring 113k2, and the contact 111k2, respectively. The gate electrodes of the PMOS transistor Tp21 and NMOS transistor Tn21, the gate electrodes of the PMOS transistor Tp41 and NMOS transistor Tn41, the gate electrodes of the PMOS transistor Tp61 and NMOS transistor Tn61, and the gate electrodes of the PMOS transistor Tp81 and NMOS transistor Tn81 are connected.

The wiring 115f of the second metal wiring layer that supplies the address signal A3 extends in the second direction, and is connected to the gate wiring 106c via the contact 114m1, the wiring 113m1 of the first metal wiring layer, and the contact 111m1, and the PMOS The transistors Tp12 and Tp22 are connected to the gate electrodes 106 of the NMOS transistors Tn12 and Tn22, and are also connected to the gate wiring 106c through the contact 114m1, the first metal wiring layer wiring 113m1 and the contact 111m1, and the PMOS transistors Tp52 and Tp62. Are connected to the gate electrodes 106 of the NMOS transistors Tn52 and Tn62.
The wiring 115g of the second metal wiring layer for supplying the address signal A4 extends in the second direction, and is connected to the gate wiring 106c via the contact 114m2, the wiring 113m2 of the first metal wiring layer, and the contact 111m2, and the PMOS The transistors Tp32 and Tp42 are connected to the gate electrodes 106 of the NMOS transistors Tn32 and Tn42, and are also connected to the gate wiring 106c through the contact 114m2, the first metal wiring layer wiring 113m2, and the contact 111m2, and the PMOS transistors Tp72 and Tp82. Are connected to the gate electrodes 106 of the NMOS transistors Tn72 and Tn82.

The second metal wiring layer 115h for supplying the address signal A5 extends in the second direction, and is connected to the gate wiring 106d through the contact 114n1, the first metal wiring layer 113n1, and the contact 111n1, and is connected to the PMOS. The gate electrodes of the transistors Tp23 and Tp33 and the NMOS transistors Tn23 and Tn33 are connected to the gate electrodes of the PMOS transistors Tp13 and Tp43 and the NMOS transistors Tn13 and Tn43 through the gate wirings 106d1 to 106d4, respectively.
The wiring 115i of the second metal wiring layer that supplies the address signal A6 extends in the second direction, and is connected to the gate wiring 106d via the contact 114n2, the wiring 113n2 of the first metal wiring layer, and the contact 111n2, and the PMOS The gate electrodes of the transistors Tp63 and Tp73 and the NMOS transistors Tn63 and Tn73 are connected to the gate electrodes of the PMOS transistors Tp53 and Tp83 and the NMOS transistors Tn53 and Tn83 through the gate wirings 106d1 to 106d4, respectively.
The wiring 115j of the second metal wiring layer that supplies the reference power supply Vss extends in the second direction and is connected to the sources of the NMOS transistors Tn13, Tn23 to Tn83.

With such arrangement and connection, eight decoders can be realized with a minimum pitch and a minimum area in both the horizontal and vertical directions.
In this embodiment, the address signals are set to A1 to A6 and eight decoders are provided. However, increasing the number of decoders by increasing the address signals is included in the scope of the present invention.

According to this embodiment, a three-input NAND type decoder and a plurality of decoders in which eight SGTs constituting an inverter are arranged in a line in the first direction are arranged adjacent to each other, and the power supply line Vcc and the reference power supply line Vss are arranged. By arranging the address signal lines (A1 to A6) in the second direction perpendicular to the first direction, the first direction and the second direction can be provided without providing unnecessary wiring and contact regions. Both can be arranged with a minimum pitch, and a semiconductor device that constitutes a 3-input NAND decoder and inverter with a minimum area can be provided.

Example 4
(Equivalent circuit applied to the embodiment of the present invention)
FIG. 11 shows an equivalent circuit diagram of a three-input NAND decoder 201 applied to the present invention. FIG. 11 shows a transistor arrangement and circuit connection method corresponding to an embodiment described later. This embodiment differs from the first embodiment described above in that the source and drain directions of the PMOS transistors Tp11, Tp12, Tp13, and the NMOS transistors Tn11, Tn12, and Tn13 are arranged upside down. As a result, the wiring connecting the drain, source and gate of each transistor is different. In order to clarify the wiring means, the types of wiring are shown in FIG.

In FIG. 11, Tp11, Tp12, and Tp13 are PMOS transistors configured by SGT, and Tn11, Tn12, and Tn13 are NMOS transistors also configured by SGT. The sources of the PMOS transistors Tp11, Tp12 and Tp13 serve as a lower diffusion layer, connected to the wiring of the first metal wiring layer through the wiring of the silicide layer, and further connected to the wiring of the second metal wiring layer. Supplied. The drains of the PMOS transistors Tp11, Tp12, Tp13 and the NMOS transistor Tn11 are commonly connected to the output line DEC1 formed by the wiring of the first metal wiring layer. The source of the NMOS transistor Tn11 is connected to the drain of the NMOS transistor Tn12 through the lower diffusion layer and the silicide layer, and the source of the NMOS transistor Tn12 is connected to the drain of the NMOS transistor Tn13 through the wiring of the first metal wiring layer. The source of the transistor Tn13 is connected to the wiring of the second metal wiring layer through the lower silicide layer, and the reference power supply Vss is supplied.
The address signal line A1 is connected to the gates of the PMOS transistor Tp11 and the NMOS transistor Tn11 via the wiring of the second metal wiring layer, the wiring of the first metal wiring layer, and the gate wiring, and the PMOS transistor Tp12 and the NMOS transistor Tn12. The gate is connected to the address signal line A2 via the wiring of the second metal wiring layer, the wiring of the first metal wiring layer, and the gate wiring. The gates of the PMOS transistor Tp13 and the NMOS transistor Tn13 are connected to the second metal wiring layer. Address signal line A3 is connected through this wiring, the first metal wiring layer wiring and the gate wiring.

As an embodiment in which the equivalent circuit of FIG. 11 is applied to the present invention, Embodiment 4 is shown in FIGS. 12a, 12b, and 13a to 13j. FIG. 12 a is a plan view of the layout (arrangement) of the 3-input NAND decoder of the present invention. FIG. 12B is a diagram showing the lower diffusion layer, each transistor, and the gate wiring in the plan view of FIG.
13a is a cross-sectional view along the cut line AA ′ in FIG. 12a, FIG. 13b is a cross-sectional view along the cut line BB ′ in FIG. 12a, and FIG. 13c is a cut line CC in FIG. FIG. 3d is a cross-sectional view taken along the cut line DD ′ in FIG. 12a, FIG. 13e is a cross-sectional view taken along the cut line EE ′ in FIG. 12a, and FIG. 12a is a cross-sectional view taken along the cut line FF ′ in FIG. 12a, FIG. 13g is a cross-sectional view taken along the cut line GG ′ in FIG. 12a, and FIG. 13h is a cross-sectional view taken along the cut line HH ′ in FIG. FIGS. 13a and 13i are cross-sectional views taken along the cut line II ′ in FIG. 12a, and FIGS. 13j are cross-sectional views taken along the cut line JJ ′ in FIG. 12a.
In FIGS. 12a, 12b, and 13a to 13j, parts having the same structure as those in FIGS. 2 and 3a to 3h are indicated by equivalent symbols in the 200s.

In FIG. 12a, PMOS transistors Tp13, Tp12, Tp11, NMOS transistors Tn11, Tn12, and Tn13 constituting the NAND decoder 201 of FIG. 11 are arranged in a row in the horizontal direction (first direction) from the right in the figure. Yes.
Also, wirings 215a, 215c, 215e, 215g, and 215j, which will be described later, extend in the vertical direction (second direction perpendicular to the first direction) in the figure, and are arranged to extend to the power supply lines Vcc, Address signal lines A3, A2, A1, and a reference power supply line Vss are configured.
The feature of the present embodiment is that the address signal A1 supplied to the wiring 215g of the second metal wiring layer is temporarily replaced with the wiring 213k of the first metal wiring layer through the contact 214k, and extended through the contact 211k. And connecting to the gate wiring 206b. The reason for this is that when a plurality of embodiments are arranged, as shown in other embodiments described later, a plurality of address signal lines are necessary for easily arranging without increasing the area. is there.

Planar silicon layers 202pa, 202na, 202nb are formed on an insulating film such as a buried oxide film layer (BOX) 201 formed on the substrate, and these planar silicon layers 202pa, 202na, 202nb are respectively formed by impurity implantation or the like. It comprises a p + diffusion layer, an n + diffusion layer, and an n + diffusion layer. Reference numeral 203 denotes a silicide layer formed on the surface of the planar silicon layer (202pa, 202na, 202nb). 204n11, 204n12, 204n13 are n-type silicon pillars, 204p11, 204p12, 204p13 are p-type silicon pillars, 205 is a gate insulating film surrounding the silicon pillars 204n11, 204n12, 204n13, 204p11, 204p12, 204p13, 206 is a gate electrode, 206a, 206b, 206c and 206d are gate wirings. The gate insulating film 205 is also formed under the gate electrode 206 and the gate wirings 206a, 206b, 206c and 206d.
P + diffusion layers 207p11, 207p12, and 207p13 are formed on the uppermost portions of the silicon pillars 204n11, 204n12, and 204n13, respectively, by impurity implantation or the like. And 207n13 are formed by impurity implantation or the like. 208 is a silicon nitride film for protecting the gate insulating film 205, 209p11, 209p12, 209p13, 209n11, 209n12 and 209n13 are silicides connected to the p + diffusion layers 207p11, 207p12 and 207p13 and n + diffusion layers 207n11, 207n12 and 207n13, respectively. Is a layer.

210p11, 210p12, 210p13, 210n11, 210n12 and 210n13 are contacts connecting the silicide layers 209p11, 209p12, 209p13, 209n11, 209n12 and 209n13 and the wirings 213b, 213b, 213b, 213b, 213c and 213c of the first metal wiring layer, respectively. It is. 211k is a contact connecting the gate wiring 206b and the first metal wiring layer 213k, 211m is a contact connecting the gate wiring 206c and the first metal wiring layer 213m, 211n is the gate wiring 206d and the first metal wiring layer This is a contact for connecting the wiring 213n. 212a is a contact connecting the silicide layer 203 connected to the p + diffusion layer 202pa and the wiring 213a of the first metal wiring layer, and 212b (two are arranged in FIG. 13a) is a silicide layer 203 connected to the n + diffusion layer 202nb. And a contact for connecting the wiring 213d of the first metal wiring layer.
214a is a contact connecting the wiring 213a of the first metal wiring layer and the wiring 215a of the second metal wiring layer, 214b is a contact connecting the wiring 213d of the first metal wiring layer and the wiring 215j of the second metal wiring layer, and 214k is A contact connecting the wiring 213k of the first metal wiring layer and the wiring 215g of the second metal wiring layer, 214m is a contact connecting the wiring 213m of the first metal wiring layer and the wiring 215e of the second metal wiring layer, and 214n is the first This is a contact for connecting the wiring 213n of the metal wiring layer and the wiring 215c of the second metal wiring layer.

The silicon pillar 204n11, the lower diffusion layer 202pa, the upper diffusion layer 207p11, the gate insulating film 205, and the gate electrode 206 constitute a PMOS transistor Tp11.
The silicon pillar 204n12, the lower diffusion layer 202pa, the upper diffusion layer 207p12, the gate insulating film 205, and the gate electrode 206 constitute a PMOS transistor Tp12.
The silicon pillar 204n13, the lower diffusion layer 202pa, the upper diffusion layer 207p13, the gate insulating film 205, and the gate electrode 206 constitute a PMOS transistor Tp13.
The silicon pillar 204p11, the lower diffusion layer 202na, the upper diffusion layer 207n11, the gate insulating film 205, and the gate electrode 206 constitute an NMOS transistor Tn11.
The silicon pillar 204p12, the lower diffusion layer 202na, the upper diffusion layer 207n12, the gate insulating film 205, and the gate electrode 206 constitute an NMOS transistor Tn12.
The silicon pillar 204p13, the lower diffusion layer 202nb, the upper diffusion layer 207n13, the gate insulating film 205, and the gate electrode 206 constitute an NMOS transistor Tn13.
Further, the gate wiring 206a is connected to the gate electrode 206 of the PMOS transistor Tp11 and the NMOS transistor Tn11, and the gate wiring 206b is connected to the gate electrode 206 of the NMOS transistor Tn11. A gate wiring 206c is connected to the gate electrodes 206 of the PMOS transistor Tp12 and the NMOS transistor Tn12, and a gate wiring 206d is commonly connected to the gate electrodes 206 of the PMOS transistor Tp13 and the NMOS transistor Tn13.

P ⁺ diffusion layer 207p11 is the drain of the PMOS transistor Tp11, p ⁺ diffusion layer 207p12, n ⁺ diffusion layer and p ⁺ drain diffusion layer 207p13 and NMOS transistors Tn11 is the drain of the PMOS transistor Tp13 is the drain of the PMOS transistor Tp12 207n11 is commonly connected via the wiring 213b of the first metal wiring layer and becomes the output line DEC1. The lower diffusion layer 202pa, which is the source of the PMOS transistor Tp11, the PMOS transistor Tp12, and the PMOS transistor Tp13, is commonly connected by the silicide layer 203. The silicide layer 203 is connected via the contact 212a, the wiring 213a of the first metal wiring layer, and the contact 214a. Are connected to the wiring 215a of the second metal wiring layer, and the power source Vcc is supplied to the wiring 215a of the second metal wiring layer. The lower diffusion layer 202na which is the source region of the NMOS transistor Tn11 is connected to the drain region of the NMOS transistor Tn12 via the silicide layer 203, and the upper diffusion layer 207n12 which is the source region of the NMOS transistor Tn12 is connected via the silicide layer 209n12 and the contact 210n12. To the wiring 213c of the first metal wiring layer. The drain region of the NMOS transistor Tn13 is connected to the wiring 213c of the first metal wiring layer through the upper diffusion layer 207n13, the silicide layer 209n13, and the contact 210n13. Here, the source of the NMOS transistor Tn12 and the drain of the NMOS transistor Tn13 are connected via the wiring 213c of the first metal wiring layer. The lower diffusion layer 202nb which is the source region of the NMOS transistor Tn13 is connected to the wiring 215j of the second metal wiring layer via the silicide layer 203, the contact 212b, the wiring 213d of the first metal wiring layer, and the contact 214b. The reference power source Vss is supplied to the wiring 215j of the two metal wiring layer. Note that the contact 212b, the wiring 213d of the first metal wiring layer, and the contact 214b are arranged at two positions on the upper and lower sides in the drawing.

The address signal A1 is supplied to the wiring 215g of the second metal wiring layer, and 215g is connected to the wiring 213k of the first metal wiring layer arranged to extend through the contact 214k, and further to the gate wiring 206b through the contact 211k. Are connected to the gate electrode 206 of the NMOS transistor Tn11 and supplied to the gate electrode 206 of the PMOS transistor Tp11 via the gate wiring 206a.
The address signal A2 is supplied to the wiring 215e of the second metal wiring layer and is connected to the gate wiring 206c through the contact 214m, the wiring 213m of the first metal wiring layer, and the contact 211m, and the gates of the PMOS transistor Tp12 and the NMOS transistor Tn12 Supplied to the electrode 206.
The address signal A3 is supplied to the wiring 215c of the second metal wiring layer and is connected to the gate wiring 206d through the contact 214n, the wiring 213n of the first metal wiring layer and the contact 211n, and the gates of the PMOS transistor Tp13 and the NMOS transistor Tn13 Supplied to the electrode 206.
In FIG. 13a, the dimension in the vertical direction (second direction) is the minimum processing dimension determined by the dimension of the SGT, the margin between the SGT and the lower diffusion layer, and the distance between the diffusion layers, and is defined as Ly. That is, the three-input NAND decoder 201 in this embodiment can be shared with the adjacent three-input NAND decoder 201 by inverting and arranging in the vertical direction, so that the minimum pitch (minimum) A plurality can be arranged adjacent to each other at an interval (Ly).
Since the address signal A1 is connected to the gate wiring 206b by replacing the wiring 215g of the second metal wiring layer with the wiring 213k of the first metal wiring layer, the arrangement position of the wiring 215g of the second metal wiring layer is shown in FIG. In 12a, it can be moved to an appropriate position between the wiring 215e of the second metal wiring layer and the wiring 215j of the second metal wiring layer. In this case, the wiring 213k of the first metal wiring layer is made possible by extending in the lateral direction (first direction).
Further, in the present embodiment, the wiring 213k of the first metal wiring layer is extended and arranged in the connection of the address signal A1, but it may be applied to the address signal A2 or A3.

According to this embodiment, six SGTs constituting a three-input NAND type decoder are arranged in a line in the first direction, and the source regions of the PMOS transistors Tp11, Tp12 and Tp13 are formed as a lower diffusion layer (202pa) and a silicide. By connecting the power source line Vcc, the reference power source line Vss, and the address signal lines A1, A2, and A3 in a second direction perpendicular to the first direction, they are connected in common by the layer 203, so that unnecessary wiring and contacts are provided. A semiconductor device that constitutes a three-input NAND decoder with a minimum area without providing a region can be provided. Furthermore, by replacing the address signal supplied to the wiring of the second metal wiring layer with the wiring of the first metal wiring layer extended to connect to the gate wiring, the flexibility of the address signal supply method can be increased. it can.

(Example 5)
(Equivalent circuit applied to the embodiment of the present invention)
FIG. 14 shows a circuit diagram in which a three-input NAND type decoder applied to the present invention and a decoder constituting an inverter are arranged corresponding to the arrangement of the embodiment.
In FIG. 14, the 3-input NAND decoder 201 is the same as FIG. In contrast to FIG. 11, an inverter 202 composed of a PMOS transistor Tp14 and an NMOS transistor Tn14 is added to form a decoder 200. The gates of the PMOS transistor Tp14 and the NMOS transistor Tn14 are commonly connected to the output DEC1 of the three-input NAND decoder 201. The drains of the PMOS transistor Tp14 and the NMOS transistor Tn14 are commonly connected to form the decoder output SEL1, and the PMOS transistor Tp14. And the source of the NMOS transistor Tn14 are connected to the power supply Vcc and the reference power supply Vss, respectively.
Here, the source of the PMOS transistor Tp14 is arranged and connected in common with the PMOS transistors Tp11, Tp12, Tp13 by the lower silicide layer.
As described above, by adding the inverter 102 to the NAND-type decoder 101 having the negative logic output, the output SEL1 of the decoder 100 becomes a positive logic output (the output of the selected decoder is logic “1”). Here, the inverter 102 has both a logic inversion function and a buffer function (amplifying the driving capability of the NAND decoder 101).

As an embodiment in which the equivalent circuit of FIG. 14 is applied to the present invention, FIG. 15a, FIG. 15b, FIG. 16a, FIG. FIG. 15A is a plan view of the layout (arrangement) of the 3-input NAND decoder 201 and the inverter 202 of this embodiment.
FIG. 15B is a diagram showing the connection between the address signal and the gate wiring in an easy-to-understand manner by showing the lower diffusion layer, each transistor, and the gate wiring in the plan view of FIG. 15A.
16a is a cross-sectional view along the cut line AA ′ in FIG. 15a, FIG. 16b is a cross-sectional view along the cut line BB ′ in FIG. 15a, and FIG. 16c is a cut line CC in FIG. It is sectional drawing along '.

FIG. 15a is obtained by adding an inverter 202 composed of a PMOS transistor Tp14 and an NMOS transistor Tn14 to FIG. 12a, but differs in the method of connecting the gate electrodes of the PMOS transistor Tp13 and the NMOS transistor Tn13. That is, in FIG. 12a (Embodiment 4), the gate electrode 206 of the PMOS transistor Tp13 and the NMOS transistor Tn13 is directly connected using the gate wiring 206d, but in FIG. 206d and 206e are separated by using the wiring 213n of the first metal wiring layer. The wiring 213n of the first metal wiring layer extends in the lateral direction (first direction) in FIG. 15a. With such an arrangement, as described later, the degree of freedom of arrangement of the wiring 215p of the second metal wiring layer that supplies the address signal A3 is increased.
In addition, in FIG. 15a, FIG. 15b, FIG. 16a, FIG. 16b, and FIG. 16c, the same structure as FIG. 12a and FIG.

15a, the NMOS transistor Tn14, the PMOS transistor Tp14, the PMOS transistors Tp13, Tp12, Tp11, and the NMOS transistors Tn11, Tn12, and Tn13 that form the NAND decoder 201 and the inverter 202 in FIG. 1 direction).
In addition, wirings 215k, 215p, 215a, 215e, 215g, and 215j in the second metal wiring layer are arranged to extend in the vertical direction (second direction perpendicular to the first direction), and are respectively connected to the reference power supply line Vss and the address. The signal line A3, the power supply line Vcc, the address signal lines A2 and A1, and the reference power supply line Vss are configured.
As in FIG. 12a, the present embodiment is characterized in that the address signal A1 supplied to the wiring 215g of the second metal wiring layer is temporarily replaced with the wiring 213k of the first metal wiring layer through the contact 214k. In addition to being connected to the gate wiring 206b via the contact 211k, the address signal A3 supplied to the wiring 215p of the second metal wiring layer is temporarily supplied to the wiring 213n of the first metal wiring layer via the contact 214n. The replacement wiring is extended and connected to the gate wiring 206d through the contact 211a. The reason for this is that when a plurality of the present embodiments are arranged, as shown in other embodiments described later, a plurality of address signal lines are required to be easily arranged without increasing the area. . Further, the feature of this embodiment is that the lower diffusion layer (202pa) which is the source region of the PMOS transistor Tp14 constituting the inverter 202 is changed to the lower region which is the source region of the PMOS transistors Tp11, Tp12 and Tp13 of the three-input NAND decoder 201. By sharing the diffusion layer (202pa) with the common wiring (215a) of the second metal wiring layer that supplies the power Vcc, the number of wirings of the second metal wiring layer can be reduced.
The configuration will be described in detail below.

Planar silicon layers 202pa, 202na, 202nb, and 202nc are formed on an insulating film such as a buried oxide film layer (BOX) 201 formed on the substrate. The planar silicon layers 202pa, 202na, 202nb, and 202nc are impurity-implanted. The p + diffusion layer, the n + diffusion layer, the n + diffusion layer, and the n + diffusion layer are respectively configured. Reference numeral 203 denotes a silicide layer formed on the surface of the planar silicon layer (202pa, 202na, 202nb, 202nc). 204n11, 204n12, 204n13, 204n14 are n-type silicon pillars, 204p11, 204p12, 204p13, 204p14 are p-type silicon pillars, 205 is a silicon pillar 204n11, 204n12, 204n13, 204n14, 204p11, 204p12, 204p13, 204p14. , 206 are gate electrodes, and 206a, 206b, 206c, 206d, 206e, 206f and 206g are gate wirings. The gate insulating film 205 is also formed under the gate electrode 206 and the gate wirings 206a, 206b, 206c, 206d, 206e, 206f and 206g.
P + diffusion layers 207p11, 207p12, 207p13, and 207p14 are formed by impurity implantation or the like on the uppermost portions of the silicon pillars 204n11, 204n12, 204n13, and 204n14, respectively. N + diffusion layers 207n11, 207n12, 207n13, and 207n14 are formed by impurity implantation or the like. 208 is a silicon nitride film for protecting the gate insulating film 205. It is a silicide layer connected to 207n13 and 207n14.

210p11, 210p12, 210p13, 210p14, 210n11, 210n12, 210n13 and 210n14 are silicide layers 209p11, 209p12, 209p13, 209p14, 209n11, 209n12, 209n13 and 209n14 and the first metal wiring layers 213b, 213b, 213b, 213f, Contacts 213b, 213c, 213c, and 213f are connected to each other. 211k is a contact connecting the gate wiring 206b and the first metal wiring layer 213k, 211m is a contact connecting the gate wiring 206c and the first metal wiring layer 213m, 211n is the gate wiring 206e and the first metal wiring layer This is a contact for connecting the wiring 213n. 211a is a contact for connecting the gate wiring 206d and the wiring 213n of the first metal wiring layer, and 211b is a contact for connecting the gate wiring 206g and the wiring 213b of the first metal wiring layer. 212a is a contact connecting the silicide layer 203 connected to the p + diffusion layer 202pa and the wiring 213a of the first metal wiring layer, and 212b (two pieces arranged in the upper and lower sides in FIG. 15a) is a silicide connected to the n + diffusion layer 202nb. The contact connecting the layer 203 and the wiring 213d of the first metal wiring layer, and 212c (arranged in the upper and lower portions in FIG. 15a) connect the silicide layer 203 connected to the n + diffusion layer 202nc and the wiring 213e of the first metal wiring layer. It is a contact to be connected.
214a is a contact connecting the wiring 213a of the first metal wiring layer and the wiring 215a of the second metal wiring layer, 214b is a contact connecting the wiring 213d of the first metal wiring layer and the wiring 215j of the second metal wiring layer, and 214c is This is a contact for connecting the wiring 213e of the first metal wiring layer and the wiring 215k of the second metal wiring layer. 214k is a contact for connecting the wiring 213k of the first metal wiring layer and the wiring 215g of the second metal wiring layer, 214m is a contact for connecting the wiring 213m of the first metal wiring layer and the wiring 215e of the second metal wiring layer, 214n is a contact for connecting the wiring 213n of the first metal wiring layer and the wiring 215p of the second metal wiring layer.

The silicon pillar 204n11, the lower diffusion layer 202pa, the upper diffusion layer 207p11, the gate insulating film 205, and the gate electrode 206 constitute a PMOS transistor Tp11.
The silicon pillar 204n12, the lower diffusion layer 202pa, the upper diffusion layer 207p12, the gate insulating film 205, and the gate electrode 206 constitute a PMOS transistor Tp12.
The silicon pillar 204n13, the lower diffusion layer 202pa, the upper diffusion layer 207p13, the gate insulating film 205, and the gate electrode 206 constitute a PMOS transistor Tp13.
The silicon pillar 204n14, the lower diffusion layer 202pa, the upper diffusion layer 207p14, the gate insulating film 205, and the gate electrode 206 constitute a PMOS transistor Tp14.
The silicon pillar 204p11, the lower diffusion layer 202na, the upper diffusion layer 207n11, the gate insulating film 205, and the gate electrode 206 constitute an NMOS transistor Tn11.
The silicon pillar 204p12, the lower diffusion layer 202na, the upper diffusion layer 207n12, the gate insulating film 205, and the gate electrode 206 constitute an NMOS transistor Tn12.
The silicon pillar 204p13, the lower diffusion layer 202nb, the upper diffusion layer 207n13, the gate insulating film 205, and the gate electrode 206 constitute an NMOS transistor Tn13,
The silicon pillar 204p14, the lower diffusion layer 202nc, the upper diffusion layer 207n14, the gate insulating film 205, and the gate electrode 206 constitute an NMOS transistor Tn14.
Further, the gate wiring 206a is connected to the gate electrode 206 of the PMOS transistor Tp11 and the NMOS transistor Tn11, and the gate wiring 206b is connected to the gate electrode 206 of the NMOS transistor Tn11. A gate wiring 206c is connected to the gate electrodes 206 of the PMOS transistor Tp12 and the NMOS transistor Tn12. A gate wiring 206e is connected to the gate electrode of the PMOS transistor Tp13, and a gate wiring 206d is connected to the gate electrode 206 of the NMOS transistor Tn13. A gate wiring 206f is connected to the gate electrode 206 of the PMOS transistor Tp14 and the NMOS transistor Tn14, and a gate wiring 206g is connected to the gate electrode 206 of the PMOS transistor Tp14.

P ⁺ diffusion layer 207p11 is the drain of the PMOS transistor Tp11, p ⁺ diffusion layer 207p12, n ⁺ diffusion layer and p ⁺ drain diffusion layer 207p13 and NMOS transistors Tn11 is the drain of the PMOS transistor Tp13 is the drain of the PMOS transistor Tp12 207n11 is commonly connected via the wiring 213b of the first metal wiring layer and becomes the output line DEC1. The lower diffusion layer 202pa, which is the source of the PMOS transistor Tp11, the PMOS transistor Tp12, the PMOS transistor Tp13, and the PMOS transistor Tp14, is commonly connected by the silicide layer 203. The silicide layer 203 includes the contact 212a, the wiring 213a of the first metal wiring layer, The contact 214a is connected to the wiring 215a of the second metal wiring layer, and the power Vcc is supplied to the wiring 215a of the second metal wiring layer. The lower diffusion layer 202na which is the source region of the NMOS transistor Tn11 is connected to the drain region of the NMOS transistor Tn12 via the silicide layer 203, and the upper diffusion layer 207n12 which is the source region of the NMOS transistor Tn12 is connected via the silicide layer 209n12 and the contact 210n12. To the wiring 213c of the first metal wiring layer. The drain region of the NMOS transistor Tn13 is connected to the wiring 213c of the first metal wiring layer through the upper diffusion layer 207n13, the silicide layer 209n13, and the contact 210n13. Here, the source of the NMOS transistor Tn12 and the drain of the NMOS transistor Tn13 are connected via the wiring 213c of the first metal wiring layer. The lower diffusion layer 202nb which is the source region of the NMOS transistor Tn13 is connected to the wiring 215j of the second metal wiring layer via the silicide layer 203, the contact 212b, the wiring 213d of the first metal wiring layer, and the contact 214b. The reference power source Vss is supplied to the wiring 215j of the two metal wiring layer. Note that the contact 212b, the wiring 213d of the first metal wiring layer, and the contact 214b are arranged at two locations on the upper and lower sides in FIG. 15a. The lower diffusion layer 202nc, which is the source region of the NMOS transistor Tn14, is connected to the second metal wiring layer wiring 215k via the silicide layer 203, the contact 212c, the first metal wiring layer wiring 213e, and the contact 214c. A reference power source Vss is supplied to the wiring 215p of the wiring layer. Note that the contact 212c, the wiring 213e of the first metal wiring layer, and the contact 214c are arranged at two locations on the upper and lower sides in FIG. 15a. The drains of the PMOS transistor Tp14 and the NMOS transistor Tn14 are commonly connected to the wiring 213f of the first metal wiring layer via the upper diffusion layer 207p14, the silicide layer 209p14, the contact 210p14, or the upper diffusion layer 207n14, the silicide layer 209n14, and the contact 210n14, respectively. And becomes the output SEL1 of the decoder 200.

The address signal A1 is supplied to the wiring 215g of the second metal wiring layer, and 215g is connected to the wiring 213k of the first metal wiring layer arranged to extend through the contact 214k, and further to the gate wiring 206b through the contact 211k. Are connected to the gate electrode 206 of the NMOS transistor Tn11 and supplied to the gate electrode 206 of the PMOS transistor Tp11 via the gate wiring 206a.
The address signal A2 is supplied to the wiring 215e of the second metal wiring layer and is connected to the gate wiring 206c through the contact 214m, the wiring 213m of the first metal wiring layer, and the contact 211m, and the gates of the PMOS transistor Tp12 and the NMOS transistor Tn12 Supplied to the electrode 206.
The address signal A3 is supplied to the wiring 215p of the second metal wiring layer, connected to the gate wiring 206e via the contact 214n, the wiring 213n of the first metal wiring layer, and the contact 211n, and connected to the gate electrode 206 of the PMOS transistor Tp13. At the same time, the wiring 213n of the first metal wiring layer is arranged to extend to the left side and is connected to the gate wiring 206d through the contact 211a, and the gate wiring 206d is connected to the gate electrode 206 of the NMOS transistor Tn13.
In FIG. 15a, the dimension in the vertical direction (second direction) is the minimum processing dimension determined by the dimension of the SGT, the margin between the SGT and the lower diffusion layer, and the distance between the diffusion layers, and is defined as Ly. That is, the decoder 200 constituted by the 3-input NAND decoder 201 and the inverter 202 in the present embodiment can share the gate wirings 206c, 206d, and 206e with the adjacent decoder 200 by being inverted in the vertical direction. Therefore, a plurality can be arranged adjacent to each other with the minimum pitch (minimum interval) Ly.

Since the address signal A1 is connected to the gate wiring 206b by replacing the wiring 215g of the second metal wiring layer with the wiring 213k of the first metal wiring layer, the arrangement position of the wiring 215g of the second metal wiring layer is shown in FIG. In 15a, it can be moved to an appropriate position between the wiring 215e of the second metal wiring layer and the wiring 215j of the second metal wiring layer. In this case, the wiring 213k of the first metal wiring layer is made possible by extending in the lateral direction (first direction).
Further, since the address signal A3 is connected to the gate wiring 206e or the gate wiring 206d by replacing the wiring 215p of the second metal wiring layer with the wiring 213n of the first metal wiring layer, the address signal A3 is connected to the wiring 215p of the second metal wiring layer. In FIG. 15a, the arrangement position can be moved to an appropriate position between the wiring 215k of the second metal wiring layer and the wiring 215a of the second metal wiring layer.
Further, in this embodiment, the address signal A2 is not particularly arranged to extend the wiring 213m of the first metal wiring layer, but may be arranged to extend like the A1 or A3.

According to the present embodiment, six SGTs constituting the 3-input NAND decoder (201) and two SGT transistors constituting the inverter (202) are arranged in a line in the first direction, and the PMOS transistor Tp11 is arranged. , Tp12, Tp13, and Tp14 are connected in common by the lower diffusion layer (202pa) and the silicide layer 203, and the power supply line Vcc, the reference power supply line Vss, and the address signal lines A1, A2, and A3 are perpendicular to the first direction. By extending and arranging in the second direction, it is possible to provide a semiconductor device constituting a decoder (200) including a three-input NAND decoder and an inverter with a minimum area without providing useless wiring and contact regions. . Furthermore, by replacing the address signal supplied to the wiring of the second metal wiring layer with the wiring of the first metal wiring layer extended to connect to the gate wiring, the flexibility of the address signal supply method can be increased. it can.

(Example 6)
(Equivalent circuit applied to the embodiment of the present invention)
17a and 17b show an equivalent circuit diagram in which a plurality of three-input NAND type decoders and inverters applied to the present invention are arranged to constitute a decoder. It is described corresponding to the arrangement and connection method of the embodiment. Similarly to FIG. 14, the wiring by the silicide layer, the gate wiring, the wiring of the first metal wiring layer, and the wiring of the second metal wiring layer are distinguished from each other.
Twelve address signal lines A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, and A12 are provided, and A1 to A4 are PMOS transistors Tpk1 (k is a natural number). A5 to A8 are selectively connected to the gates of the PMOS transistor Tpk2 and NMOS transistor Tnk2, and A9 to A12 are selectively connected to the gates of the PMOS transistor Tpk3 and NMOS transistor Tnk3. Connected to. Twelve address signals A1 to A12 constitute 64 decoders 200-1 to 200-64.
However, since it is difficult to describe all 64 decoders on the drawing, as a representative, 8 decoders 200-1 to 200-8 are displayed in FIG. 17a, and FIG. Eight of 57-200-64 are described.
In FIG. 17a,
Address signal lines A1, A5 and A9 are connected to the decoder 200-1,
Address signal lines A2, A5 and A9 are connected to the decoder 200-2,
Address signal lines A3, A5 and A9 are connected to the decoder 200-3.
Address signal lines A4, A5 and A9 are connected to the decoder 200-4.
Address signal lines A1, A6 and A9 are connected to the decoder 200-5,
Address signal lines A2, A6 and A9 are connected to the decoder 200-6,
Address signal lines A3, A6 and A9 are connected to the decoder 200-7,
Address signal lines A4, A6 and A9 are connected to the decoder 200-8.
In FIG. 17b,
Address signal lines A1, A7 and A12 are connected to the decoder 200-57,
Address signal lines A2, A7 and A12 are connected to the decoder 200-58,
Address signal lines A3, A7 and A12 are connected to the decoder 200-59,
Address signal lines A4, A7 and A12 are connected to the decoder 200-60,
Address signal lines A1, A8 and A12 are connected to the decoder 200-61,
Address signal lines A2, A8 and A12 are connected to the decoder 200-62,
Address signal lines A3, A8 and A12 are connected to the decoder 200-63,
Address signal lines A4, A8 and A12 are connected to the decoder 200-64.
A location where the address signal line is connected is indicated by a dotted circle.

As will be described later, in FIG. 17a, the address signal line A5 is connected in common to the decoders 200-1 and 200-2, and is further connected in common to the decoders 200-3 and 200-4, and the address signal line A6 is connected to the decoder. It is commonly connected to 200-5 and 200-6, and further commonly connected to decoders 200-7 and 200-8. In FIG. 17b, the address signal A7 is commonly connected to the decoders 200-57 and 200-58, and is further commonly connected to the decoders 200-59 and 200-60, and the address signal line A8 is connected to the decoders 200-61. Are connected in common to decoders 200-63 and 200-64.
Although details will be described later in FIGS. 17A and 17B, the address signal lines A1 to A4 are temporarily connected to the first metal wiring layer from the wiring of the second metal wiring layer arranged to extend in the vertical direction (second direction). Connected to wiring and connected to gate wiring. In FIG. 17b, the address signal A12 is also connected to the wiring of the first metal wiring layer from the wiring of the second metal wiring layer arranged to extend in the vertical direction (second direction). Connected to gate wiring.

18a and 18b show address maps of 64 decoders of this embodiment. Address signals connected to the decoder outputs DEC1 / SEL1 to DEC64 / SEL64 are indicated by circles. As will be described later, a contact is provided and connected.

Example 6 is shown in FIGS. 19a to 19e and FIGS. 20a to 20s. This embodiment implements the equivalent circuit of FIGS. 17a and 17b. Based on the decoder of the embodiment 5 (FIG. 15a), 16 decoders (200-1 to 200-) are provided according to FIGS. 17a and 17b. 8 and 200-57 to 200-64) are arranged adjacent to each other with the minimum pitch Ly. 19a to 19d are plan views of the layout (arrangement) of the 3-input NAND decoder 201 and the inverter 202 of the present invention, and FIG. 19e is the SGT, gate wiring, and address signals A1, A2, A3, and A4 of FIG. 19d. FIG. 20A is a cross-sectional view taken along the cut line AA ′ in FIG. 19A, and FIG. 20B is a cut line B− in FIG. 19A. 20c is a cross-sectional view along the cut line CC ′ in FIG. 19a, FIG. 20d is a cross-sectional view along the cut line DD ′ in FIG. 19a, and FIG. 20e is in FIG. 19a. Cross-sectional view along cut line EE ′, FIG. 20f is a cross-sectional view along cut line FF ′ in FIG. 19b, and FIG. 20g is a cut line GG ′ in FIG. 19c. 20h is a sectional view taken along the cut line HH ′ in FIG. 19c, FIG. 20i is a sectional view taken along the cut line II ′ in FIG. 19d, and FIG. 20j is a cut line in FIG. 19a. 20K is a cross-sectional view along the cut line KK ′ in FIG. 19A, FIG. 20L is a cross-sectional view along the cut line LL ′ in FIG. 19A, and FIG. 19a is a cross-sectional view along the cut line MM ′, FIG. 20n is a cross-sectional view along the cut line NN ′ in FIG. 19a, and FIG. 20p is a cross-sectional view along the cut line PP ′ in FIG. 20q is a cross-sectional view along the cut line QQ 'in FIG. 19a, FIG. 20r is a cross-sectional view along the cut line RR' in FIG. 19a, and FIG. 20s is a cut line SS in FIG. A cross-sectional view along 'is shown.
19a corresponds to the decoder block 210a in FIG. 17a, FIG. 19b corresponds to the decoder block 210b in FIG. 17a, FIG. 19c corresponds to the decoder block 210c in FIG. 17b, and FIG. 19d corresponds to FIG. Corresponds to the decoder block 210d in FIG. FIGS. 19a and 19b and FIGS. 19c and 19d are continuous drawings, but are shown separately in FIGS. 19a to 19d for convenience of illustration.

In FIG. 19a, the NMOS transistor Tn14, the PMOS transistors Tp14, Tp13, Tp12, Tp11, and the NMOS transistors Tn11, Tn12, and Tn13 constituting the decoder 200-1 in FIG. 17a are laterally (first direction) from the right in the drawing. One row is arranged in the top row of the figure.
The NMOS transistor Tn24, the PMOS transistors Tp24, Tp23, Tp22, Tp21, and the NMOS transistors Tn21, Tn22, and Tn23 constituting the decoder 200-2 are arranged in the first row in the horizontal direction from the right side of the drawing in the second row from the top of the drawing. ing. Similarly, a decoder 200-3 and a decoder 200-4 are sequentially arranged from above in FIG. 19a.
The decoders 200-1 and 200-3 are normally arranged based on the decoder of FIG. 15a, and the decoders 200-2 and 200-4 are arranged upside down.
As a result, the gate wiring 206c connecting the PMOS transistors Tp12 and Tp22 and the NMOS transistors Tn12 and Tn22 is provided in common, and is disposed in the gap (dead space) between the lower diffusion layers of the decoder 200-1 and the decoder 200-2. In addition to minimizing the size in the vertical direction (second direction), by using a common gate wiring, the parasitic capacitance of the wiring can be reduced, and high-speed operation is possible. Similarly, the gate wiring 206c that connects the PMOS transistors Tp32 and Tp42 and the NMOS transistors Tn32 and Tn42 is provided in common.

The gate electrodes 206 of the PMOS transistors Tp13, Tp23, Tp33, and Tp43 are connected by gate wirings 206e1, 206e, and 206e2, respectively. The gate electrodes 206 of the NMOS transistors Tn13, Tn23, Tn33, and Tn43 are commonly connected by a gate wiring 206d, and the gate wiring 206d extends through a gap between the lower diffusion layers of the decoders 200-2 and 200-3. It is arranged in the horizontal direction. The gate wiring 206d and the gate wiring 206e are commonly connected by the wiring 213n1 of the first metal wiring layer through the contact 211a and the contact 211n1. That is, in FIG. 19a, the wiring 215p of the second metal wiring layer to which the address signal A9 is supplied is a gate wiring from one place of the contact 214n1 via the wiring 213n1, the contact 211n1 or the contact 211a of the first metal wiring layer. The gate electrode 206 is connected to the gate electrode 206 of the PMOS transistors Tp13, Tp23, Tp33, Tp43, and the NMOS transistors Tn13, Tn23, Tn33, Tn43. With such an arrangement, the area of the wiring region can be reduced, the parasitic capacitance of the wiring can be reduced, and high-speed operation is possible.

It should be noted that the decoders 200-2 and 200-4 are inverted, but the contacts 211k1 to 211k4 for supplying the address signals A1 to A4, the wirings 213k1 to 213k4 of the first metal wiring layer, and The contacts 214k1 to 214k4 are arranged in the normal direction without being inverted. Thus, the address signals A1 to A4 can be independently supplied to the gate wirings 206b of the decoders 200-1, 200-2, 2003, and 200-4.
19b, 19c, and 19d, decoders 200-5 to 200-8, decoders 200-57 to 200-60, and decoders 200-61 to 200-64 are arranged in the same manner.

19a to 19d, the wirings 215k, 215l, 215m, 215n, 215p, 215a, 215b, 215c, 215d, 215e, 215f, 215g, 215h, 215i and 215j in the second metal wiring layer are in the vertical direction (second The reference power supply Vss, the address signals A12, A11, A10, A9, the power supply Vcc, the address signal lines A8, A7, A6, A5, A4, A3, A2, A1, and the reference power supply Vss, respectively. Supply. Since the wirings 215a to 215p of the second metal wiring layer are arranged at the minimum pitch (minimum wiring width and minimum wiring interval) of the second metal wiring layer, the horizontal dimension can be arranged at the minimum.
In FIGS. 19a to 19e and FIGS. 20a to 20s, portions having the same structure as those of FIGS. 15a, 15b, and 16a to 16c are indicated by equivalent symbols in the 200s.

19a to 19d and 20a to 20s, the wiring 215k of the second metal wiring layer that supplies the reference power source Vss is arranged to extend in the second direction, and the contact 214c, the wiring 213e of the first metal wiring layer, and The contact 212c is connected to the silicide layer 203 that commonly connects the lower diffusion layer 202nc, which is the source region of the NMOS transistors Tn14 to Tn84 and Tn574 to Tn644. Note that a plurality of connection locations (214c, 213e, 212c) are provided. Further, the silicide layer 203 covering the lower diffusion layers 202nc and 202nc is shared and connected by vertically adjacent decoders.

The wiring 215l of the second metal wiring layer for supplying the address signal A12 extends in the vertical direction (second direction), and as shown in FIGS. 19c and 20h, the contact 214n4 and the horizontal direction (first direction). Is connected to the gate wiring 206e via the wiring 213n4 and the contact 211n4 of the first metal wiring layer extended to the gate electrode 206, and is connected to the gate electrode 206 of the PMOS transistors Tp573, Tp583, Tp593, Tp603 and via the contact 211a. And connected to the gate electrode 206 of the NMOS transistors Tn573, Tn583, Tn593, and Tn603.
In FIG. 19d, the contact 214n4 is connected to the gate wiring 206e via the first metal wiring layer wiring 213n1 extended in the lateral direction (first direction) and the contact 211n1, and the PMOS transistors Tp613, Tp623, The gate electrode 206 is connected to the gate electrodes 206 of Tp633 and Tp643, is connected to the gate wiring 206d through the contact 211a, and is connected to the gate electrode 206 of the NMOS transistors Tn613, Tn623, Tn633, and Tn643.
Although not shown, according to the address map FIG. 18b, the address signal A12 is sent to 16 decoders 200-49 to 200-64 by the contact 214n4, the first metal wiring layer wiring 213n4, and the contact 211n4 as described above. Supply.

The wiring 215m of the second metal wiring layer for supplying the address signal A11 extends in the vertical direction (second direction) and is not shown, but, like the address A12, the contact 214n3 not shown and the horizontal direction (first direction) Are connected to the gate wiring 206e and the gate wiring 206d through the wiring 213n3 and the contact 211n3 of the first metal wiring layer extending in the direction), and according to the address map FIG. The address signal A11 is supplied to each.

The wiring 215n of the second metal wiring layer for supplying the address signal A10 extends in the vertical direction (second direction) and is not shown. However, like the address A12, the contact 214n2 not shown and the horizontal direction (first direction) Are connected to the gate wiring 206e and the gate wiring 206d through the wiring 213n2 and the contact 211n2 of the first metal wiring layer arranged extending in the direction), and according to the address map FIG. 18a, 16 to the decoders 200-17 to 200-32 are connected. The address signal A10 is supplied to each.

The wiring 215p of the second metal wiring layer for supplying the address signal A9 extends in the vertical direction (second direction), and as shown in FIGS. 19a and 20d, the contact 214n1 and the horizontal direction (first direction) Is connected to the gate wiring 206e via the wiring 213n1 and the contact 211n1 of the first metal wiring layer extending to the gate electrode 206, and is connected to the gate electrode 206 of the PMOS transistors Tp13, Tp23, Tp33, Tp43 and via the contact 211a. The gate wiring 206d is connected to the gate electrode 206 of the NMOS transistors Tn13, Tn23, Tn33, Tn43.
Further, in FIG. 19b, the contact 214n1, the wiring 213n1 of the first metal wiring layer arranged to extend in the lateral direction (first direction), and the gate wiring 206e via the contact 211n1 are connected to the PMOS transistors Tp53, Tp63, The gate electrode 206 is connected to the gate electrodes 206 of Tp73 and Tp83, is connected to the gate wiring 206d through the contact 211a, and is connected to the gate electrode 206 of the NMOS transistors Tn53, Tn63, Tn73, and Tn83.

The wiring 215a of the second metal wiring layer for supplying the power source Vcc is extended and arranged in the second direction, and the PMOS transistors Tp11 of all the decoders are connected via the contact 214a, the wiring 213a of the first metal wiring layer, and the contact 212a. Tp12, Tp13, Tp14 to Tp641, Tp642, Tp643, and Tp644 are connected to the silicide layer 203 that commonly connects the lower diffusion layer 202pa, which is the source region. Note that a plurality of connection locations (214a, 213a, 212a) are provided. The first metal wiring 213a extends in the lateral direction (first direction), and by disposing a plurality of contacts 212a, the resistance of the silicide layer 203 is reduced, and the power source Vcc is supplied to the source of each PMOS transistor. Can be supplied efficiently.

The second metal wiring layer wiring 215b for supplying the address signal A8 extends in the vertical direction (second direction). As shown in FIGS. 19d and 20i, the contact 214m4 and the first metal wiring layer wiring 213m4 are arranged. Are connected to the gate wiring 206c through the contact 211m4, and are connected to the gate electrodes of the PMOS transistors Tp612 and Tp622 and the NMOS transistors Tn612 and Tn622. Similarly, it is connected to the gate wiring 206c through the contact 214m4, the first metal wiring layer wiring 213m4, and the contact 211m4, and is connected to the gate electrodes of the PMOS transistors Tp632 and Tp642 and the NMOS transistors Tn632 and Tn642.

The second metal wiring layer wiring 215c for supplying the address signal A7 extends in the vertical direction (second direction). As shown in FIGS. 19c and 20g, the contact 214m3 and the first metal wiring layer wiring 213m3 are provided. Are connected to the gate wiring 206c through the contact 211m3, and are connected to the gate electrodes of the PMOS transistors Tp572 and Tp582 and the NMOS transistors Tn572 and Tn582. Similarly, it is connected to the gate wiring 206c through the contact 214m3, the first metal wiring layer wiring 213m3, and the contact 211m3, and is connected to the gate electrodes of the PMOS transistors Tp592, Tp602, NMOS transistors Tn592, Tn602.

The wiring 215d of the second metal wiring layer that supplies the address signal A6 extends in the vertical direction (second direction). As shown in FIGS. 19b and 20f, the contact 214m2 and the wiring 213m2 of the first metal wiring layer are arranged. Are connected to the gate wiring 206c through the contact 211m2, and are connected to the gate electrodes of the PMOS transistors Tp52 and Tp62 and the NMOS transistors Tn52 and Tn62. Similarly, it is connected to the gate wiring 206c through the contact 214m2, the first metal wiring layer wiring 213m2, and the contact 211m2, and is connected to the gate electrodes of the PMOS transistors Tp72 and Tp82 and the NMOS transistors Tn72 and Tn82.

The second metal wiring layer wiring 215e for supplying the address signal A5 extends in the vertical direction (second direction), and as shown in FIGS. 19a and 20c, the contact 214m1 and the first metal wiring layer wiring 213m1. Are connected to the gate wiring 206c through the contact 211m1, and are connected to the gate electrodes of the PMOS transistors Tp12 and Tp22 and the NMOS transistors Tn12 and Tn22. Similarly, as shown in FIG. 20e, it is connected to the gate wiring 206c via the contact 214m1, the first metal wiring layer wiring 213m1, and the contact 211m1, and is connected to the gate electrodes of the PMOS transistors Tp32 and Tp42 and the NMOS transistors Tn32 and Tn42. Is done.

The wiring 215f of the second metal wiring layer that supplies the address signal A4 extends in the vertical direction (second direction), and as shown in FIGS. 19a and 20e, the contact 214k4 and the horizontal direction (first direction). Is connected to the gate wiring 206b through the wiring 213k4 of the first metal wiring layer and the contact 211k4, and is connected to the gate electrode of the NMOS transistor Tn41, and is connected to the gate of the PMOS transistor Tp41 through the gate wiring 206a. Connected to the electrode.
Similarly, as shown in FIG. 19b, the contact 214k4 is connected to the gate wiring 206b via the first metal wiring layer wiring 213k4 extending in the lateral direction (first direction), the contact 211k4, and the NMOS. The gate electrode of the transistor Tn81 is connected to the gate electrode of the PMOS transistor Tp81 via the gate wiring 206a.
Further, as shown in FIG. 19c, the contact 214k4, the wiring 213k4 of the first metal wiring layer arranged to extend in the lateral direction (first direction), and the gate wiring 206b through the contact 211k4 are connected to the NMOS transistor Tn601. Are connected to the gate electrode of the PMOS transistor Tp601 through the gate wiring 206a.
Further, as shown in FIG. 19d, the contact 214k4, the wiring 213k4 of the first metal wiring layer arranged to extend in the lateral direction (first direction), and the gate wiring 206b through the contact 211k4 are connected to the NMOS transistor Tn641. Are connected to the gate electrode of the PMOS transistor Tp641 through the gate wiring 206a.

The wiring 215g of the second metal wiring layer that supplies the address signal A3 extends in the vertical direction (second direction), and as shown in FIGS. 19a and 20d, the contact 214k3 and the vertical direction (second direction) Is connected to the gate wiring 206b through the wiring 213k3 of the first metal wiring layer and the contact 211k3, and is connected to the gate electrode of the NMOS transistor Tn31, and is connected to the gate of the PMOS transistor Tp31 through the gate wiring 206a. Connected to the electrode.
Similarly, as shown in FIG. 19b, the contact 214k3 is connected to the gate wiring 206b via the first metal wiring layer wiring 213k3 extending in the vertical direction (second direction), the contact 211k3, and the NMOS. It is connected to the gate electrode of the transistor Tn71 and is connected to the gate electrode of the PMOS transistor Tp71 via the gate wiring 206a.
Further, as shown in FIG. 19c, the contact 214k3 is connected to the gate wiring 206b via the first metal wiring layer wiring 213k3 extending in the lateral direction (first direction) and the contact 211k3, and the NMOS transistor Tn591. Are connected to the gate electrode of the PMOS transistor Tp591 through the gate wiring 206a.
Further, as shown in FIG. 19d, the contact 214k3 is connected to the gate wiring 206b via the first metal wiring layer wiring 213k3 extending in the vertical direction (second direction) and the contact 211k3, and the NMOS transistor Tn631. Are connected to the gate electrode of the PMOS transistor Tp631 through the gate wiring 206a.

The wiring 215h of the second metal wiring layer for supplying the address signal A2 extends in the vertical direction (second direction), and as shown in FIGS. 19a and 20c, contacts 214k2 and the horizontal direction (first direction). Is connected to the gate wiring 206b through the wiring 213k2 and the contact 211k2 of the first metal wiring layer extended to the gate electrode of the NMOS transistor Tn21 and is connected to the gate of the PMOS transistor Tp21 through the gate wiring 206a. Connected to the electrode.
Similarly, as shown in FIG. 19b, the contact 214k2, the wiring 213k2 of the first metal wiring layer extending in the lateral direction (first direction), and the gate wiring 206b via the contact 211k2 are connected to the NMOS. The gate electrode of the transistor Tn61 is connected to the gate electrode of the PMOS transistor Tp61 through the gate wiring 206a.
Further, as shown in FIG. 19c, the contact 214k2, the first metal wiring layer wiring 213k2 extending in the lateral direction (first direction), and the contact 211k2 are connected to the gate wiring 206b to be connected to the NMOS transistor Tn581. Are connected to the gate electrode of the PMOS transistor Tp581 through the gate wiring 206a.
Further, as shown in FIG. 19d, the contact 214k2, the wiring 213k2 of the first metal wiring layer arranged in the lateral direction (first direction), the gate 211b2 are connected to the gate wiring 206b, and the NMOS transistor Tn621 is connected. Are connected to the gate electrode of the PMOS transistor Tp621 through the gate wiring 206a.

The wiring 215i of the second metal wiring layer for supplying the address signal A1 extends in the vertical direction (second direction), and as shown in FIGS. 19a and 20a, the contact 214k1 and the horizontal direction (first direction). Is connected to the gate wiring 206b through the wiring 213k1 and the contact 211k1 of the first metal wiring layer extended to the gate electrode of the NMOS transistor Tn11, and is connected to the gate of the PMOS transistor Tp11 through the gate wiring 206a. Connected to the electrode.
Similarly, as shown in FIG. 19b, the contact 214k1, the wiring 213k1 of the first metal wiring layer extending in the lateral direction (first direction), and the gate wiring 206b via the contact 211k1 are connected to the NMOS. The gate electrode of the transistor Tn51 is connected to the gate electrode of the PMOS transistor Tp51 through the gate wiring 206a.
Further, as shown in FIG. 19c, the contact 214k1, the first metal wiring layer wiring 213k1 extending in the lateral direction (first direction), and the contact 211k1 are connected to the gate wiring 206b to be connected to the NMOS transistor Tn571. Are connected to the gate electrode of the PMOS transistor Tp571 via the gate wiring 206a.
Further, as shown in FIG. 19d, the contact 214k1, the first metal wiring layer wiring 213k1 extended in the lateral direction (first direction), the gate 211b1 is connected to the gate wiring 206b via the contact 211k1, and the NMOS transistor Tn611. Are connected to the gate electrode of the PMOS transistor Tp611 via the gate wiring 206a.

The wiring 215j of the second metal wiring layer that supplies the reference power supply Vss is arranged to extend in the second direction in FIGS. 19a to 19d, and is connected via the contact 214b, the wiring 213d of the first metal wiring layer, and the contact 212b. The NMOS transistors Tn13 to Tn83 and Tn573 to Tn643 are connected to the silicide layer 203 that commonly connects the lower diffusion layer 202nb which is the source region. Note that a plurality of connection locations (214b, 213d, 212b) are provided. Further, the silicide layer 203 covering the lower diffusion layers 202nb and 202nb is shared and connected by the decoders vertically adjacent to each other.

With such an arrangement and connection, 64 decoders can be realized with a minimum pitch and a minimum area in both the horizontal and vertical directions.
In this embodiment, the address signal is set to A1 to A12 and 64 decoders are provided. However, it is easy to increase the number of decoders by increasing the address signals. As with the address signals A1 to A12, the address signal to be increased is arranged by extending the wiring of the second metal wiring layer in the vertical direction (second direction) and extending in the horizontal direction (first direction). If the first metal wiring layer is connected to the gate wirings 206b, 206c or 206d or 206e, the added second metal wiring layer wiring can also be arranged with the minimum pitch determined by processing, so that the minimum area is reduced. Thus, a large-scale decoder can be provided.
In Example 3 (FIG. 9a), since the address signals are set to A1 to A6, the number is as small as six. In particular, when connecting from the wiring of the second metal wiring layer extending in the vertical direction to the gate wiring, Although the wiring of the first metal wiring layer extending in the horizontal direction is not required, when the address signal is set to 12 or more as in the sixth embodiment (FIG. 19a), Similarly, if the wiring of the second metal wiring layer extending in the vertical direction is replaced with the wiring of the first metal wiring layer extending in the horizontal direction and connected to the gate wiring, the address signal can be easily increased. Can do.

According to this embodiment, a plurality of decoders (200) in which eight SGTs constituting a three-input NAND decoder (201) and an inverter (202) are arranged in a line in the first direction are arranged adjacent to each other. , The power supply line Vcc, the reference power supply line Vss, and the address signal lines (A1 to A12) extend in a second direction perpendicular to the first direction and any one of the address signal lines (A1 to A12). In this case, by connecting to the gate wiring of the three-input NAND type decoder through the wiring of the first metal wiring layer arranged extending at least in the first direction, the number of input address signals is not limited and is useless. Without providing a wiring or a contact region, the semiconductor device can be provided with a minimum pitch in both the first direction and the second direction, and a 3-input NAND decoder and inverter can be provided with a minimum area.

In this embodiment, the arrangement of 8 SGTs is the NMOS transistor Tn14, the PMOS transistors Tp14, Tp13, Tp12, Tp11, and the NMOS transistors Tn11, Tn12, and Tn13 from the right side. The eight SGTs constituting the inverter are arranged in one row, and the connection to the lower diffusion layer wiring (silicide layer), the upper metal layer wiring, and the gate wiring is connected to the second metal wiring and the first metal wiring. The present invention is to provide a decoder that can be effectively used to minimize the area, and in accordance with the arrangement method of the present invention, the arrangement of SGT, the wiring method of the gate wiring, the wiring position, the wiring method of the metal wiring, and the wiring position Those other than those shown in the drawings of this embodiment belong to the technical scope of the present invention.

In the present embodiment, a NAND-type decoder composed of 6 SGTs and an inverter composed of 2 SGTs also serving as buffers are combined to provide a positive logic decoder composed of 8 SGTs. However, the essence of the present invention is composed of 6 SGTs. The three-input NAND decoder is arranged efficiently with the wiring area being minimized, and includes a layout arrangement of NAND decoders composed of six SGTs. In this case, the decoder has a negative logic output (the output of the selected decoder becomes logic “0”).

Although all the embodiments have been described using the BOX structure, the present embodiment can be easily realized even with a normal CMOS structure and is not limited to the BOX structure.

In the description of this embodiment, the silicon column of the PMOS transistor is defined as N-type silicon and the NMOS silicon column is defined as a P-type silicon layer for convenience. However, it is difficult to control the concentration by impurity implantation in a miniaturized process. Therefore, both the PMOS transistor and the NMOS transistor use a so-called neutral semiconductor that does not inject impurities into the silicon pillar, and the channel control, that is, the threshold values of the PMOS and NMOS are specific to the metal gate material. In some cases, the difference in work function (Work Function) is used.

In this embodiment, the lower diffusion layer or the upper diffusion layer is covered with the silicide layer. However, silicide is used to reduce the resistance, and other low-resistance materials may be used. A generic term for metal compounds is defined as silicide.

Tp11, Tp12, Tp13, Tp14 to Tp641, Tp642, Tp643, Tp644: PMOS transistors Tn11, Tn12, Tn13, Tp14 to Tn641, Tn642, Tn643, Tn644: NMOS transistors 101, 201: buried oxide film layers 102pa, 102pb, 102na, 102nb, 102nc, 202pa, 202na, 202nb, 202nc: planar silicon layer 103, 203: silicide layer 104p, 204p: p-type silicon pillar 104n, 204n: n-type silicon pillar 105, 205: gate insulating film 106, 206: gate Electrodes 106a, 106b, 106c, 106d, 206a, 206b, 206c, 206d, 206e, 206f, 206g: gate wiring 107p, 207p: p + Diffusion layers 107n, 207n: n + diffusion layers 108, 208: silicon nitride films 109p, 109n, 209p, 209n: silicide layers 110p, 110n, 210p, 210n: contacts 111, 211: contacts 112, 212: contacts 113, 213: first 1 metal wiring layer wiring 114, 214: contact 115, 215: second metal wiring layer wiring

Claims (28)

A semiconductor device that constitutes a NAND-type decoder by arranging six transistors whose sources, drains, and gates are arranged hierarchically in a direction perpendicular to the substrate in a row in the first direction on the substrate. And
Each of the transistors is
Silicon pillars,
An insulator surrounding a side surface of the silicon pillar;
A gate surrounding the insulator;
A source region disposed above or below the silicon pillar;
A drain region disposed above or below the silicon pillar, the drain region disposed opposite to the source region with respect to the silicon pillar;
The six transistors are:
A first P-channel MOS transistor;
A second P-channel MOS transistor;
A third P-channel MOS transistor;
A first N-channel MOS transistor;
A second N-channel MOS transistor;
A third N-channel MOS transistor;
Consists of
The gates of the first P-channel MOS transistor and the first N-channel MOS transistor are connected to each other,
The gates of the second P-channel MOS transistor and the second N-channel MOS transistor are connected to each other.
The gates of the third P-channel MOS transistor and the third N-channel MOS transistor are connected to each other.
The drain regions of the first P-channel MOS transistor, the second P-channel MOS transistor, the third P-channel MOS transistor, and the first N-channel MOS transistor are arranged on the substrate side from the silicon pillar and are connected to each other. Becomes the output terminal (DEC1),
The source region of the second N-channel MOS transistor and the drain region of the third N-channel MOS transistor are disposed on the substrate side from the silicon pillar,
A source region of the first N-channel MOS transistor is connected to a drain region of the second N-channel MOS transistor;
A source region of the second N-channel MOS transistor is connected to a drain region of the third N-channel MOS transistor;
The source regions of the first P-channel MOS transistor, the second P-channel MOS transistor, and the third P-channel MOS transistor are connected to a power line, and the source region of the third N-channel MOS transistor Is connected to the reference power line,
The decoder
A first address signal line;
A second address signal line;
A third address signal line;
Have
The gates of the first P-channel MOS transistor and the first N-channel MOS transistor connected to each other are connected to the first address signal line,
The gates of the second P-channel MOS transistor and the second N-channel MOS transistor connected to each other are connected to the second address signal line,
The gates of the third P-channel MOS transistor and the third N-channel MOS transistor connected to each other are connected to the third address signal line,
The power supply line, the reference power supply line, the first address signal line, the second address signal line, and the third address signal line extend in a second direction perpendicular to the first direction. A semiconductor device which is arranged.   The six transistors include the third P channel MOS transistor, the second P channel MOS transistor, the first P channel MOS transistor, the first N channel MOS transistor, and the second N channel MOS transistor. 2. The semiconductor device according to claim 1, wherein the third N-channel MOS transistors are arranged in a line in the order of the third N-channel MOS transistors.   The gates of the first P-channel MOS transistor and the first N-channel MOS transistor, or the gates of the second P-channel MOS transistor and the second N-channel MOS transistor, or the third P-channel MOS transistor At least one of the transistor and the gate of the third N-channel MOS transistor extends in the second direction via a wiring of a first metal wiring layer extending in the first direction at least. 3. The semiconductor device according to claim 1, wherein the semiconductor device is connected to a corresponding address signal line of the first to third address signal lines configured by wiring of the second metal wiring layer formed. apparatus. A semiconductor device in which a NAND-type decoder is configured by arranging six transistors whose sources, drains and gates are arranged hierarchically in a direction perpendicular to a substrate in a row in a first direction on the substrate. ,
Each of the transistors is
Silicon pillars,
An insulator surrounding a side surface of the silicon pillar;
A gate surrounding the insulator;
A source region disposed above or below the silicon pillar;
A drain region disposed above or below the silicon pillar, the drain region disposed opposite to the source region with respect to the silicon pillar;
The six transistors are at least
A first P-channel MOS transistor;
A second P-channel MOS transistor;
A third P-channel MOS transistor;
A first N-channel MOS transistor;
A second N-channel MOS transistor;
A third N-channel MOS transistor;
Consists of
The gates of the first P-channel MOS transistor and the first N-channel MOS transistor are connected to each other,
The gates of the second P-channel MOS transistor and the second N-channel MOS transistor are connected to each other.
The gates of the third P-channel MOS transistor and the third N-channel MOS transistor are connected to each other.
The drain regions of the first P-channel MOS transistor, the second P-channel MOS transistor, the third P-channel MOS transistor, and the first N-channel MOS transistor are arranged on the substrate side from the silicon pillar, and Connected to output terminal (DEC1),
The source region of the second N-channel MOS transistor and the drain region of the third N-channel MOS transistor are disposed on the substrate side from the silicon pillar,
A source region of the first N-channel MOS transistor is connected to a drain region of the second N-channel MOS transistor;
A source region of the second N-channel MOS transistor is connected to a drain region of the third N-channel MOS transistor;
Source regions of the first P-channel MOS transistor, the second P-channel MOS transistor, and the third P-channel MOS transistor are connected to a power supply line,
A source region of the third N-channel MOS transistor is connected to a reference power line;
The semiconductor device includes:
A first a address signal lines;
A second b address signal lines;
A third c address signal lines;
a × b × c NAND-type decoders;
Have
In each of the a × b × c NAND decoders,
The gates of the first P-channel MOS transistor and the first N-channel MOS transistor connected to each other are connected to one of the first a address signal lines, and the second P-channel MOS transistor connected to each other. The gates of the P-channel MOS transistor and the second N-channel MOS transistor are connected to any one of the second b address signal lines, and the third P-channel MOS transistor connected to each other and the gate The gate of the third N-channel MOS transistor is connected to any one of the third c address signal lines, the power supply line, the reference power supply line, the first a address signal lines, The second b address signal lines and the third c address signal lines are arranged to extend in a second direction perpendicular to the first direction. The semiconductor device according to symptoms.   The six transistors include the third P channel MOS transistor, the second P channel MOS transistor, the first P channel MOS transistor, the first N channel MOS transistor, and the second N channel MOS transistor. 5. The semiconductor device according to claim 4, wherein the semiconductor devices are arranged in a line in the order of the third N-channel MOS transistors.   The gates of the first P-channel MOS transistor and the first N-channel MOS transistor, or the gates of the second P-channel MOS transistor and the second N-channel MOS transistor, or the third P-channel MOS transistor At least one of the transistor and the gate of the third N-channel MOS transistor extends in the second direction via a wiring of a first metal wiring layer extending in the first direction at least. 6. The semiconductor device according to claim 4, wherein the semiconductor device is connected to an address signal line corresponding to the first to third address signal lines configured by wiring of the second metal wiring layer formed. apparatus. A semiconductor device in which a NAND-type decoder is configured by arranging six transistors whose sources, drains and gates are arranged hierarchically in a direction perpendicular to a substrate in a row in a first direction on the substrate. ,
Each of the transistors is
Silicon pillars,
An insulator surrounding a side surface of the silicon pillar;
A gate surrounding the insulator;
A source region disposed above or below the silicon pillar;
A drain region disposed above or below the silicon pillar, the drain region disposed opposite to the source region with respect to the silicon pillar;
The six transistors are:
A first P-channel MOS transistor;
A second P-channel MOS transistor;
A third P-channel MOS transistor;
A first N-channel MOS transistor;
A second N-channel MOS transistor;
A third N-channel MOS transistor;
Consists of
The gates of the first P-channel MOS transistor and the first N-channel MOS transistor are connected to each other,
The gates of the second P-channel MOS transistor and the second N-channel MOS transistor are connected to each other.
The gates of the third P-channel MOS transistor and the third N-channel MOS transistor are connected to each other.
Source regions of the first P-channel MOS transistor, the second P-channel MOS transistor, the third P-channel MOS transistor, and the first N-channel MOS transistor are disposed on the substrate side from the silicon pillar. ,
The drain region of the second N-channel MOS transistor and the source region of the third N-channel MOS transistor are disposed on the substrate side from the silicon pillar,
The drain regions of the first P-channel MOS transistor, the second P-channel MOS transistor, the third P-channel MOS transistor and the first N-channel MOS transistor are connected to each other to serve as an output terminal (DEC1). ,
Source regions of the first P-channel MOS transistor, the second P-channel MOS transistor, and the third P-channel MOS transistor are connected to a power supply line,
A source region of the first N-channel MOS transistor is connected to a drain region of the second N-channel MOS transistor;
The source region of the second N channel MOS transistor is connected to the drain region of the third N channel MOS transistor, the source region of the third N channel MOS transistor is connected to a reference power supply line,
The NAND decoder is
A first address signal line;
A second address signal line;
A third address signal line;
Have
The gates of the first P-channel MOS transistor and the first N-channel MOS transistor connected to each other are connected to the first address signal line,
The gates of the second P-channel MOS transistor and the second N-channel MOS transistor connected to each other are connected to the second address signal line,
The gates of the third P-channel MOS transistor and the third N-channel MOS transistor connected to each other are connected to the third address signal line,
The power supply line, the reference power supply line, the first address signal line, the second address signal line, and the third address signal line extend in a second direction perpendicular to the first direction. A semiconductor device which is arranged.   The six transistors include the third P-channel MOS transistor, the second P-channel MOS transistor, the first P-channel MOS transistor, the first N-channel MOS transistor, the second N-channel MOS transistor, and 8. The semiconductor device according to claim 7, wherein the third N-channel MOS transistors are arranged in a line in the order of the third N-channel MOS transistors.   The gates of the first P-channel MOS transistor and the first N-channel MOS transistor, or the gates of the second P-channel MOS transistor and the second N-channel MOS transistor, or the third P-channel MOS transistor At least one of the transistor and the gate of the third N-channel MOS transistor extends in the second direction via a wiring of a first metal wiring layer extending in the first direction at least. 9. The semiconductor device according to claim 7, wherein the semiconductor device is connected to address signal lines corresponding to the first to third address signal lines configured by wiring of the second metal wiring layer formed. apparatus. A semiconductor device in which a NAND-type decoder is configured by arranging six transistors whose sources, drains and gates are arranged hierarchically in a direction perpendicular to a substrate in a row in a first direction on the substrate. ,
Each of the transistors is
Silicon pillars,
An insulator surrounding a side surface of the silicon pillar;
A gate surrounding the insulator;
A source region disposed above or below the silicon pillar;
A drain region disposed above or below the silicon pillar, the drain region disposed opposite to the source region with respect to the silicon pillar;
The six transistors are at least
A first P-channel MOS transistor;
A second P-channel MOS transistor;
A third P-channel MOS transistor;
A first N-channel MOS transistor;
A second N-channel MOS transistor;
A third N-channel MOS transistor;
Consists of
The gates of the first P-channel MOS transistor and the first N-channel MOS transistor are connected to each other,
The gates of the second P-channel MOS transistor and the second N-channel MOS transistor are connected to each other.
The gates of the third P-channel MOS transistor and the third N-channel MOS transistor are connected to each other.
Source regions of the first P-channel MOS transistor, the second P-channel MOS transistor, the third P-channel MOS transistor, and the first N-channel MOS transistor are disposed on the substrate side from the silicon pillar. ,
The drain region of the second N-channel MOS transistor and the source region of the third N-channel MOS transistor are disposed on the substrate side from the silicon pillar,
The drain regions of the first P-channel MOS transistor, the second P-channel MOS transistor, the third P-channel MOS transistor and the first N-channel MOS transistor are connected to each other to serve as an output terminal (DEC1). ,
Source regions of the first P-channel MOS transistor, the second P-channel MOS transistor, and the third P-channel MOS transistor are connected to a power supply line,
A source region of the first N-channel MOS transistor is connected to a drain region of the second N-channel MOS transistor;
The source region of the second N channel MOS transistor is connected to the drain region of the third N channel MOS transistor, the source region of the third N channel MOS transistor is connected to a reference power supply line,
The semiconductor device includes:
A first a address signal lines;
A second b address signal lines;
A third c address signal lines;
a × b × c NAND-type decoders;
Have
In each of the a × b × c NAND decoders,
The gates of the first P-channel MOS transistor and the first N-channel MOS transistor connected to each other are connected to one of the first a address signal lines, and the second P-channel MOS transistor connected to each other. The gates of the P-channel MOS transistor and the second N-channel MOS transistor are connected to any one of the second b address signal lines, and the third P-channel MOS transistor connected to each other and the gate The gate of the third N-channel MOS transistor is connected to any one of the third c address signal lines, the power supply line, the reference power supply line, the first a address signal lines, The second b address signal lines and the third c address signal lines are arranged to extend in a second direction perpendicular to the first direction. A featured semiconductor device.   The six transistors include the third P channel MOS transistor, the second P channel MOS transistor, the first P channel MOS transistor, the first N channel MOS transistor, and the second N channel MOS transistor. 11. The semiconductor device according to claim 10, wherein the semiconductor devices are arranged in a line in the order of the third N-channel MOS transistors. Source regions of the first P-channel MOS transistor, the second P-channel MOS transistor, and the third P-channel MOS transistor constituting the a × b × c NAND decoders are connected in common. The semiconductor device according to claim 10, wherein:   The gate of the first P-channel MOS transistor and the first N-channel MOS transistor, or the gate of the second P-channel MOS transistor and the second N-channel MOS transistor, or the third P-channel MOS transistor And at least one of the gates of the third N-channel MOS transistor is arranged to extend in the second direction via a wiring of a first metal wiring layer extended in at least the first direction. 13. The semiconductor device according to claim 10, further comprising a second metal wiring layer connected to an address signal line corresponding to the first to third address signal lines configured by wiring of the second metal wiring layer. A semiconductor device according to 1. A semiconductor device that constitutes a NAND-type decoder and an inverter by arranging eight transistors whose sources, drains and gates are arranged hierarchically in a direction perpendicular to the substrate in a first direction on the substrate. There,
Each of the transistors is
Silicon pillars,
An insulator surrounding a side surface of the silicon pillar;
A gate surrounding the insulator;
A source region disposed above or below the silicon pillar;
A drain region disposed above or below the silicon pillar, the drain region disposed opposite to the source region with respect to the silicon pillar;
The eight transistors are:
A first P-channel MOS transistor;
A second P-channel MOS transistor;
A third P-channel MOS transistor;
A fourth P-channel MOS transistor;
A first N-channel MOS transistor;
A second N-channel MOS transistor;
A third N-channel MOS transistor;
A fourth N-channel MOS transistor;
Consists of
The NAND decoder is
A first P-channel MOS transistor;
A second P-channel MOS transistor;
A third P-channel MOS transistor;
A first N-channel MOS transistor;
A second N-channel MOS transistor;
A third N-channel MOS transistor;
Consists of
The inverter is
A fourth P-channel MOS transistor;
A fourth N-channel MOS transistor;
Consists of
The gates of the first P-channel MOS transistor and the first N-channel MOS transistor are connected to each other,
The gates of the second P-channel MOS transistor and the second N-channel MOS transistor are connected to each other.
The gates of the third P-channel MOS transistor and the third N-channel MOS transistor are connected to each other.
The drain regions of the first P-channel MOS transistor, the second P-channel MOS transistor, the third P-channel MOS transistor, and the first N-channel MOS transistor are arranged on the substrate side from the silicon pillar, and Connected to the first output terminal (DEC1),
The source region of the second N-channel MOS transistor and the drain region of the third N-channel MOS transistor are disposed on the substrate side from the silicon pillar,
Source regions of the first P-channel MOS transistor, the second P-channel MOS transistor, and the third P-channel MOS transistor are connected to a power supply line,
A source region of the first N-channel MOS transistor is connected to a drain region of the second N-channel MOS transistor;
A source region of the second N-channel MOS transistor is connected to a drain region of the third N-channel MOS transistor;
A source region of the third N-channel MOS transistor is connected to a reference power line;
The gates of the fourth P-channel MOS transistor and the fourth N-channel MOS transistor are connected to each other and connected to the first output terminal (DEC1),
The drain region of the fourth P-channel MOS transistor and the drain region of the fourth N-channel MOS transistor are connected to each other to become a second output terminal (SEL1),
The source region of the fourth P-channel MOS transistor and the source region of the fourth N-channel MOS transistor are connected to a power supply line and a reference power supply line, respectively.
The NAND decoder is
A first address signal line;
A second address signal line;
A third address signal line;
Have
The gates of the first P-channel MOS transistor and the first N-channel MOS transistor connected to each other are connected to the first address signal line,
The gates of the second P-channel MOS transistor and the second N-channel MOS transistor connected to each other are connected to the second address signal line,
The gates of the third P-channel MOS transistor and the third N-channel MOS transistor connected to each other are connected to the third address signal line,
The power supply line, the reference power supply line, the first address signal line, the second address signal, and the third address signal line are arranged to extend in a second direction perpendicular to the first direction. A semiconductor device that is characterized in that:   The eight transistors include one of the fourth N-channel MOS transistor or the fourth P-channel MOS transistor, the other of the fourth N-channel MOS transistor or the fourth P-channel MOS transistor, and the third transistor. P-channel MOS transistor, second P-channel MOS transistor, first P-channel MOS transistor, first N-channel MOS transistor, second N-channel MOS transistor, third N-channel MOS transistor The semiconductor device according to claim 14, wherein the semiconductor device is arranged in a line.   The gates of the first P-channel MOS transistor and the first N-channel MOS transistor, or the gates of the second P-channel MOS transistor and the second N-channel MOS transistor, or the third P-channel MOS transistor At least one of the transistor and the gate of the third N-channel MOS transistor extends in the second direction via a wiring of a first metal wiring layer extending in the first direction at least. 16. The semiconductor device according to claim 14, wherein the semiconductor device is connected to corresponding address signal lines of the first to third address signal lines configured by wiring of the second metal wiring layer formed. apparatus. A semiconductor device that constitutes a NAND-type decoder and an inverter by arranging eight transistors whose sources, drains and gates are arranged hierarchically in a direction perpendicular to the substrate in a first direction on the substrate. There,
Each of the transistors is
Silicon pillars,
An insulator surrounding a side surface of the silicon pillar;
A gate surrounding the insulator;
A source region disposed above or below the silicon pillar;
A drain region disposed above or below the silicon pillar, the drain region disposed opposite to the source region with respect to the silicon pillar;
The eight transistors are:
A first P-channel MOS transistor;
A second P-channel MOS transistor;
A third P-channel MOS transistor;
A fourth P-channel MOS transistor;
A first N-channel MOS transistor;
A second N-channel MOS transistor;
A third N-channel MOS transistor;
A fourth N-channel MOS transistor;
Consists of
The decoder is at least
A first P-channel MOS transistor;
A second P-channel MOS transistor;
A third P-channel MOS transistor;
A first N-channel MOS transistor;
A second N-channel MOS transistor;
A third N-channel MOS transistor;
Consists of
The inverter is
A fourth P-channel MOS transistor;
A fourth N-channel MOS transistor;
Consists of
The gates of the first P-channel MOS transistor and the first N-channel MOS transistor are connected to each other,
The gates of the second P-channel MOS transistor and the second N-channel MOS transistor are connected to each other.
The gates of the third P-channel MOS transistor and the third N-channel MOS transistor are connected to each other.
The drain regions of the first P-channel MOS transistor, the second P-channel MOS transistor, the third P-channel MOS transistor, and the first N-channel MOS transistor are disposed on the substrate side from the silicon pillar, and are mutually connected. Connected to the first output terminal (DEC1),
The source region of the second N-channel MOS transistor and the drain region of the third N-channel MOS transistor are disposed on the substrate side from the silicon pillar,
Source regions of the first P-channel MOS transistor, the second P-channel MOS transistor, and the third P-channel MOS transistor are connected to a power supply line,
A source region of the first N-channel MOS transistor is connected to a drain region of the second N-channel MOS transistor;
A source region of the second N-channel MOS transistor is connected to a drain region of the third N-channel MOS transistor;
A source region of the third N-channel MOS transistor is connected to a reference power line;
The gates of the fourth P-channel MOS transistor and the fourth N-channel MOS transistor are connected to each other and connected to the first output terminal (DEC1),
The drain region of the fourth P-channel MOS transistor and the drain region of the fourth N-channel MOS transistor are connected to each other to become a second output terminal (SEL1),
The source region of the fourth P-channel MOS transistor and the source region of the fourth N-channel MOS transistor are connected to a power supply line and a reference power supply line, respectively.
The semiconductor device includes:
A first a address signal lines;
A second b address signal lines;
A third c address signal lines;
a × b × c NAND decoders and inverters;
Have
In each of the a × b × c NAND decoders and inverters,
The gates of the first P-channel MOS transistor and the first N-channel MOS transistor connected to each other are connected to one of the first a address signal lines, and the second P-channel MOS transistor connected to each other. The gates of the P-channel MOS transistor and the second N-channel MOS transistor are connected to any one of the second b address signal lines, and the third P-channel MOS transistor connected to each other and the gate A gate of the third N-channel MOS transistor is connected to any one of the third c address signal lines, the power supply line, the reference power supply line, the first a address signal lines, 2 b address signal lines and the third c address signal lines are arranged to extend in a second direction perpendicular to the first direction. Semiconductor device.   The eight transistors include one of the fourth N-channel MOS transistor or the fourth P-channel MOS transistor, the other of the fourth N-channel MOS transistor or the fourth P-channel MOS transistor, and the third transistor. P-channel MOS transistor, second P-channel MOS transistor, first P-channel MOS transistor, first N-channel MOS transistor, second N-channel MOS transistor, third N-channel MOS transistor The semiconductor device according to claim 17, wherein the semiconductor devices are arranged in a line in order.   The gates of the first P-channel MOS transistor and the first N-channel MOS transistor, or the gates of the second P-channel MOS transistor and the second N-channel MOS transistor, or the third P-channel MOS transistor At least one of the transistor and the gate of the third N-channel MOS transistor extends in the second direction via a wiring of a first metal wiring layer extending in the first direction at least. 19. The semiconductor device according to claim 17, wherein the semiconductor device is connected to an address signal line corresponding to the first to third address signal lines configured by the wiring of the second metal wiring layer formed. apparatus. A semiconductor device that constitutes a NAND-type decoder and an inverter by arranging eight transistors whose sources, drains and gates are arranged hierarchically in a direction perpendicular to the substrate in a first direction on the substrate. There,
Each of the transistors is
Silicon pillars,
An insulator surrounding a side surface of the silicon pillar;
A gate surrounding the insulator;
A source region disposed above or below the silicon pillar;
A drain region disposed above or below the silicon pillar, the drain region disposed opposite to the source region with respect to the silicon pillar;
The eight transistors are:
A first P-channel MOS transistor;
A second P-channel MOS transistor;
A third P-channel MOS transistor;
A fourth P-channel MOS transistor;
A first N-channel MOS transistor;
A second N-channel MOS transistor;
A third N-channel MOS transistor;
A fourth N-channel MOS transistor;
Consists of
The NAND decoder is
A first P-channel MOS transistor;
A second P-channel MOS transistor;
A third P-channel MOS transistor;
A first N-channel MOS transistor;
A second N-channel MOS transistor;
A third N-channel MOS transistor;
Consists of
The inverter is
A fourth P-channel MOS transistor;
A fourth N-channel MOS transistor;
Consists of
The gates of the first P-channel MOS transistor and the first N-channel MOS transistor are connected to each other,
The gates of the second P-channel MOS transistor and the second N-channel MOS transistor are connected to each other.
The gates of the third P-channel MOS transistor and the third N-channel MOS transistor are connected to each other.
Source regions of the first P-channel MOS transistor, the second P-channel MOS transistor, the third P-channel MOS transistor, and the first N-channel MOS transistor are disposed on the substrate side from the silicon pillar. ,
The drain region of the second N-channel MOS transistor and the source region of the third N-channel MOS transistor are disposed on the substrate side from the silicon pillar,
The drain regions of the first P-channel MOS transistor, the second P-channel MOS transistor, the third P-channel MOS transistor, and the first N-channel MOS transistor are connected to each other and connected to a first output terminal ( DEC1)
Source regions of the first P-channel MOS transistor, the second P-channel MOS transistor, and the third P-channel MOS transistor are connected to a power supply line,
A source region of the first N-channel MOS transistor is connected to a drain region of the second N-channel MOS transistor;
A source region of the second N-channel MOS transistor is connected to a drain region of the third N-channel MOS transistor;
A source region of the third N-channel MOS transistor is connected to a reference power supply;
The gates of the fourth P-channel MOS transistor and the fourth N-channel MOS transistor are connected to each other and connected to the first output terminal (DEC1),
The drain region of the fourth P-channel MOS transistor and the drain region of the fourth N-channel MOS transistor are connected to each other to become a second output terminal (SEL1),
The source region of the fourth P-channel MOS transistor and the source region of the fourth N-channel MOS transistor are connected to a power supply line and a reference power supply line, respectively.
The NAND decoder is
A first address signal line;
A second address signal line;
A third address signal line;
Have
The gates of the first P-channel MOS transistor and the first N-channel MOS transistor connected to each other are connected to the first address signal line,
The gates of the second P-channel MOS transistor and the second N-channel MOS transistor connected to each other are connected to the second address signal line,
The gates of the third P-channel MOS transistor and the third N-channel MOS transistor connected to each other are connected to the third address signal line,
The power supply line, the reference power supply line, the first address signal line, the second address signal line, and the third address signal line extend in a second direction perpendicular to the first direction. A semiconductor device which is arranged.   The eight transistors include one of the fourth N-channel MOS transistor or the fourth P-channel MOS transistor, the other of the fourth N-channel MOS transistor or the fourth P-channel MOS transistor, and the third transistor. A P-channel MOS transistor, the second P-channel MOS transistor, the first P-channel MOS transistor, the first N-channel MOS transistor, the second N-channel MOS transistor, and the third N-channel MOS transistor. 21. The semiconductor device according to claim 20, wherein the semiconductor devices are arranged in a line in order. Source regions of the fourth P-channel MOS transistor and the fourth N-channel MOS transistor are disposed on the substrate side from the silicon pillar,
The eight transistors include the fourth N-channel MOS transistor, the fourth P-channel MOS transistor, the third P-channel MOS transistor, the second P-channel MOS transistor, and the first P-channel MOS transistor. The first N-channel MOS transistor, the second N-channel MOS transistor, and the third N-channel MOS transistor are arranged in a line in the order of the first N-channel MOS transistor, the second N-channel MOS transistor, and the third N-channel MOS transistor. The semiconductor device described.   The gates of the first P-channel MOS transistor and the first N-channel MOS transistor, or the gates of the second P-channel MOS transistor and the second N-channel MOS transistor, or the third P-channel MOS transistor At least one of the transistor and the gate of the third N-channel MOS transistor extends in the second direction via a wiring of a first metal wiring layer extending in the first direction at least. 23. The device according to claim 20, wherein the first signal signal line is connected to an address signal line corresponding to the first to third address signal lines configured by wiring of the second metal wiring layer formed. The semiconductor device according to item. A semiconductor device that constitutes a NAND-type decoder and an inverter by arranging eight transistors whose sources, drains and gates are arranged hierarchically in a direction perpendicular to the substrate in a first direction on the substrate. There,
Each of the transistors is
Silicon pillars,
An insulator surrounding a side surface of the silicon pillar;
A gate surrounding the insulator;
A source region disposed above or below the silicon pillar;
A drain region disposed above or below the silicon pillar, the drain region disposed opposite to the source region with respect to the silicon pillar;
The eight transistors are:
A first P-channel MOS transistor;
A second P-channel MOS transistor;
A third P-channel MOS transistor;
A fourth P-channel MOS transistor;
A first N-channel MOS transistor;
A second N-channel MOS transistor;
A third N-channel MOS transistor;
A fourth N-channel MOS transistor;
Consists of
The NAND decoder is
A first P-channel MOS transistor;
A second P-channel MOS transistor;
A third P-channel MOS transistor;
A first N-channel MOS transistor;
A second N-channel MOS transistor;
A third N-channel MOS transistor;
Consists of
The inverter is
A fourth P-channel MOS transistor;
A fourth N-channel MOS transistor;
Consists of
The gates of the first P-channel MOS transistor and the first N-channel MOS transistor are connected to each other,
The gates of the second P-channel MOS transistor and the second N-channel MOS transistor are connected to each other.
The gates of the third P-channel MOS transistor and the third N-channel MOS transistor are connected to each other.
Source regions of the first P-channel MOS transistor, the second P-channel MOS transistor, the third P-channel MOS transistor, and the first N-channel MOS transistor are disposed on the substrate side from the silicon pillar. ,
The drain region of the second N-channel MOS transistor and the source region of the third N-channel MOS transistor are disposed on the substrate side from the silicon pillar,
The drain regions of the first P-channel MOS transistor, the second P-channel MOS transistor, the third P-channel MOS transistor, and the first N-channel MOS transistor are connected to each other and connected to a first output terminal ( DEC1)
Source regions of the first P-channel MOS transistor, the second P-channel MOS transistor, and the third P-channel MOS transistor are connected to a power supply line,
A source region of the first N-channel MOS transistor is connected to a drain region of the second N-channel MOS transistor;
A source region of the second N-channel MOS transistor is connected to a drain region of the third N-channel MOS transistor;
A source region of the third N-channel MOS transistor is connected to a reference power supply;
The gates of the fourth P-channel MOS transistor and the fourth N-channel MOS transistor are connected to each other and connected to the first output terminal (DEC1),
The drain region of the fourth P-channel MOS transistor and the drain region of the fourth N-channel MOS transistor are connected to each other to become a second output terminal (SEL1),
The source region of the fourth P-channel MOS transistor and the source region of the fourth N-channel MOS transistor are connected to a power supply line and a reference power supply line, respectively.
The semiconductor device includes:
A first a address signal lines;
A second b address signal lines;
A third c address signal lines;
a × b × c NAND decoders and inverters;
Have
In each of the a × b × c NAND decoders and inverters,
The gates of the first P-channel MOS transistor and the first N-channel MOS transistor connected to each other are connected to one of the first a address signal lines, and the second P-channel MOS transistor connected to each other. The gates of the P-channel MOS transistor and the second N-channel MOS transistor are connected to any one of the second b address signal lines, and the third P-channel MOS transistor connected to each other and the gate A gate of the third N-channel MOS transistor is connected to any one of the third c address signal lines, the power supply line, the reference power supply line, the first a address signal lines, 2 b address signal lines and the third c address signal lines are arranged to extend in a second direction perpendicular to the first direction. Semiconductor device. The eight transistors include one of the fourth N-channel MOS transistor or the fourth P-channel MOS transistor, the other of the fourth N-channel MOS transistor or the fourth P-channel MOS transistor, and the third transistor. A P-channel MOS transistor, the second P-channel MOS transistor, the first P-channel MOS transistor, the first N-channel MOS transistor, the second N-channel MOS transistor, and the third N-channel MOS transistor. The semiconductor device according to claim 24 , wherein the semiconductor devices are arranged in a line in order. Source regions of the fourth P-channel MOS transistor and the fourth N-channel MOS transistor are disposed on the substrate side from the silicon pillar,
The eight transistors include the fourth N-channel MOS transistor, the fourth P-channel MOS transistor, the third P-channel MOS transistor, the second P-channel MOS transistor, and the first P-channel MOS transistor. said first N-channel MOS transistor, said second N-channel MOS transistor, the order of the third N-channel MOS transistor, according to 請 Motomeko 25 you being disposed in a row Semiconductor device.   The first P-channel MOS transistor, the second P-channel MOS transistor, the third P-channel MOS transistor, and the fourth P-channel MOS transistor constituting the a × b × c NAND decoders and inverters 27. The semiconductor device according to claim 26, wherein the source regions are connected in common.   The gates of the first P-channel MOS transistor and the first N-channel MOS transistor, or the gates of the second P-channel MOS transistor and the second N-channel MOS transistor, or the third P-channel MOS transistor At least one of the transistor and the gate of the third N-channel MOS transistor extends in the second direction via a wiring of a first metal wiring layer extending in the first direction at least. 23. The device according to claim 20, wherein the first signal signal line is connected to an address signal line corresponding to the first to third address signal lines configured by wiring of the second metal wiring layer formed. The semiconductor device according to item.

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