WO2015071998A1

WO2015071998A1 - Semiconductor device

Info

Publication number: WO2015071998A1
Application number: PCT/JP2013/080823
Authority: WO
Inventors: 舛岡　富士雄; 正通浅野
Original assignee: ユニサンティスエレクトロニクスシンガポールプライベートリミテッド; 舛岡　富士雄; 正通浅野
Priority date: 2013-11-14
Filing date: 2013-11-14
Publication date: 2015-05-21

Abstract

The purpose of the present invention is, using Surrounding Gate Transistors (SGT) which are vertical transistors, to provide a semiconductor device which configures a decoder circuit for memory selection and which occupies a small area. In a decoder circuit which is of a NOR-type configured using a plurality of MOS transistors disposed in a rows and b columns, the MOS transistors configuring the decoder circuit are formed upon a planar silicon layer formed upon a substrate, with drains, gates, and sources being disposed vertically. Said gates surround silicon columns, and said planar silicon layer comprises a first active area having a first conductivity type and a second active area having a second conductivity type, with the active areas being connected to each other through a silicide layer formed upon the planar silicon layer surface. Thus, a semiconductor device which configures a decoder circuit of a small area is provided.

Description

Semiconductor device

The present invention relates to a semiconductor device.

In recent years, semiconductor integrated circuits have been scaled up, and in the state-of-the-art MPU (Micro-processing Unit), semiconductor chips with as many as 1G transistors have been developed. In so-called planar type transistors, as shown in Non-Patent Document 1, it is necessary to completely separate the N-well region for forming the PMOS and the P-type silicon substrate (or P-well region) for forming the NMOS, In addition, the N-well region and the P-type silicon substrate each need a body terminal for applying a potential, which is a factor of increasing the area.

As a means for solving this problem, a Surrounding Gate Transistor (SGT) having a structure in which a source, a gate, and a drain are arranged in a vertical direction with respect to a substrate and the gate surrounds an island-shaped semiconductor layer has been proposed. A CMOS inverter, a NAND circuit, or an SRAM cell using the above is disclosed. For example, see Patent Document 1, Patent Document 2, Patent Document 3, and Patent Document 4.

Japanese Patent No. 5130596 Japanese Patent No. 5031809 Japanese Patent No. 4756221 International Publication No. 2009/096465

FIG. 18, FIG. 19a, FIG. 19b, FIG. 19c, FIG. 19d, and FIG. 20 show circuit diagrams and layout diagrams of static memory cells (hereinafter referred to as SRAM cells) using conventional SGTs.
Details are described in Patent Document 4 and International Publication No. 2009/096465, which will be briefly described below.

FIG. 18 is a circuit diagram of an SRAM cell. Qp1 and Qp2 are P-channel MOS transistors (hereinafter referred to as PMOS transistors) Qn1, Qn2, Qn3 and Qn4 are N-channel MOS transistors (hereinafter referred to as NMOS transistors), and BL is a bit. A line, BLB is an inverted bit line, WL is a word line (row selection line), Vcc is a power supply, and Vss is a reference power supply.
FIG. 19a shows a plan view of a layout in which the SRAM cell of FIG. 19b is a cross-sectional view in the direction of cut line AA ′ in FIG. 19a, FIG. 19c is a cross-sectional view in the direction of cut line BB ′ in FIG. 19a, and FIG. 19d is a cut line in FIG. A cross-sectional view in the direction CC ′ is shown.
19a, the NMOS transistor Qn2, the PMOS transistor Qp2 and the NMOS transistor Qn4 of the SRAM cell of FIG. 18 are in the first row (upper row in the figure), and the NMOS transistor Qn3, the PMOS transistor Qp1 and the NMOS transistor Qn1 are in the second row (see FIG. 19a). Are arranged in order from the left side of the figure.

Planar silicon layers 2pa, 2pb, 2na, 2nb, 2nc, and 2nd are formed on an insulating film such as a buried oxide film layer (BOX) 1 formed on the substrate, and 2pa and 2pb are p + by impurity implantation or the like, respectively. The diffusion layers, 2na, 2nb, 2nc, and 2nd are each composed of an n + diffusion layer. 3 is a silicide layer formed on the surface of the planar silicon layer (2pa, 2pb, 2na, 2nb, 2nc, 2nd), which connects the planar silicon layers 2nc, 2pb, 2nd, and 2nb, 2pa, 2na is connected.
4n1, 4n2 are n-type silicon pillars, 4p1, 4p2, 4p3, 4p4 are p-type silicon pillars, 5 is a gate insulating film surrounding the silicon pillars 4n1, 4n2, 4p1, 4p2, 4p3, 4p4, 6 is a gate electrode, 6a,

Reference numerals

6b, 6c, and 6d denote gate wirings. P + diffusion layers 7p1, 7p2 are formed on the uppermost portions of the silicon pillars 4n1, 4n2, respectively by impurity implantation, and n + diffusion layers 7n1, 7n2, 7n3 are formed on the uppermost portions of the silicon pillars 4p1, 4p2, 4p3, 4p4, respectively. 7n4 are formed by impurity implantation or the like. 8 is a silicon nitride film for protecting the gate insulating film 5, and 9p1, 9p2, 9n1, 9n2, 9n3, and 9n4 are silicides connected to p + diffusion layers 7p1, 7p2, n + diffusion layers 7n1, 7n2, 7n3, and 7n4, respectively. Layers 10p1, 10p2, 10n1, 10n2, 10n3, 10n4 include silicide layers 9p1, 9p2, 9n1, 9n2, 9n3, 9n4 and

wirings

13c, 13g, 13a, 13f, 13e, 13h of the first metal wiring layer. 11a is a contact for connecting the gate wiring 6a and the wiring 13b of the first metal wiring layer, 11b is a contact for connecting the gate wiring 6b and the wiring 13d of the first metal wiring layer, and 11c is a gate wiring 6c. And a contact 11d for connecting the wiring 13i of the first metal wiring layer and a gate arrangement 11d. 6d and a contact for connecting the wires 13j of the first metal wiring layer.
Further, 12a is a contact connecting the silicide 3 connecting the lower diffusion layers 2nb, 2pa and 2na and the wiring 13d of the first metal wiring layer, and 12b is a silicide 3 connecting the lower diffusion layers 2nd, 2pb and 2nc. This is a contact for connecting the wiring 13b of the first metal wiring layer.

The silicon pillar 4n1, the lower diffusion layer 2pa, the upper diffusion layer 7p1, the gate insulating film 5, and the gate electrode 6 constitute the PMOS transistor Qp1, and the silicon pillar 4n2, the lower diffusion layer 2pb, the upper diffusion layer 7p2, the gate insulating film 5, The gate electrode 6 constitutes the PMOS transistor Qp2, and the silicon pillar 4p1, the lower diffusion layer 2na, the upper diffusion layer 7n1, the gate insulating film 5, and the gate electrode 6 constitute the NMOS transistor Qn1, and the silicon pillar 4p2 and the lower diffusion layer 2nc, the upper diffusion layer 7n2, the gate insulating film 5 and the gate electrode 6 constitute an NMOS transistor Qn2, and the silicon pillar 4p3, the lower diffusion layer 2nb, the upper diffusion layer 7n3, the gate insulating film 5 and the gate electrode 6 constitute an NMOS transistor. Qn3, silicon pillar 4p4, lower diffusion layer 2nd, Part diffusion layer 7N4, the gate insulating film 5, the gate electrode 6 constitute a NMOS transistor Qn4.

The gate wiring 6a is connected to the gate electrode 6 of the PMOS transistor Qp1 and the NMOS transistor Qn1, the gate wiring 6b is connected to the gate electrode 6 of the PMOS transistor Qp2 and the gate electrode 6 of the NMOS transistor Qn2, and the NMOS transistor Qnn3 A gate line 6c is connected to the gate electrode 6, and a gate line 6d is connected to the gate electrode 6 of the NMOS transistor Qn4.

The lower diffusion layers 2pa, 2na, and 2nb become common drains of the PMOS transistors Qp1, Qn1, and Qn3 through the silicide 3, are connected to the wiring 13d of the first metal wiring layer through the contact 12a, and are further connected through the contact 11b. To the gate electrode 6b. Similarly, the lower diffusion layers 2pb, 2nc, and 2nd become common drains of the PMOS transistors Qp2, Qn2, and Qn4 through the silicide 3, and are connected to the wiring 13b of the first metal wiring layer through the contact 12b. 11a is connected to the gate electrode 6a.
The upper diffusion layers 7p1 and 7p2 which are the sources of the PMOS transistors Qp1 and Qp2 are connected to the

wirings

13c and 13g of the first metal wiring layer through the silicide layers 9p1 and 9p2 and the contacts 10p1 and 10p2, respectively. It is connected to the wiring 15a of the second metal wiring layer via the contacts 14p1 and 14p2, and the power supply Vcc is supplied to the wiring 15a of the second metal wiring layer.
Upper diffusion layers 7n1 and 7n2 which are sources of NMOS transistors Qn1 and Qn2 are connected to wirings 13a and 13f of the first metal wiring layer via silicide layers 9n1 and 9n2 and contacts 10n1 and 10n2, respectively. The reference power supply Vss is supplied to the

wirings

13a and 13f in the wiring layer.

The upper diffusion layer 7n3 which is the source of the NMOS transistor Qn3 is connected to the wiring 13e of the first metal wiring layer via the silicide layer 9n3 and the contact 10n3, and further to the wiring 15b of the second metal wiring layer via the contact 14n3. And the wiring 15b of the second metal wiring layer becomes the bit line BL. The upper diffusion layer 7n4 which is the source of the NMOS transistor Qn4 is connected to the wiring 13h of the first metal wiring layer via the silicide layer 9n4 and the contact 10n4, and further to the second metal wiring layer via the contact 14n4. The wiring 15c of the second metal wiring layer connected to the wiring 15c becomes the inverted bit line BLB. The gate electrodes 6 of the NMOS transistors Qn3 and Qn4 are connected to

gate wirings

6c and 6d, respectively. As shown in FIG. 19d, the gate wiring 6d is connected to the third metal wiring 17 via the contact 11d, the first metal wiring layer wiring 13j, the contact 14b, the second metal wiring layer wiring 15e, and the contact 16b. Then, the third metal wiring 17 becomes a word line (row selection signal) WL. Similarly, the gate wiring 6c is connected to the third metal wiring 17 through the contact 11c, the wiring 13i of the first metal wiring layer, the contact 14a, the wiring 15d of the second metal wiring layer, and the contact 16a.
Thus, as shown in FIG. 19a, the SRAM cell of FIG. 18 can be provided with the PMOS transistors Qp1 and Qp2 and the NMOS transistors Qn1, Qn2, Qn3, and Qn4 having the minimum dimensions of 2 rows and 3 columns.
The block SRAM surrounded by the thin line frame is a unit cell unit, and the height direction is the dimension Ly1.

FIG. 20 shows an SRAM cell array in which SRAM cells are arranged in a matrix. For convenience, four SRAM cells of M (0,0) M (1,0), M (0,1), and M (1,1) are arranged. As is apparent from FIG. 20, this SRAM cell can be arranged without gaps with 2 rows and 3 columns as a minimum unit, and an SRAM cell array can be provided with a minimum area.

In an SRAM using SGT, a PMOS transistor and an NMOS transistor are completely separated from each other in structure. Well isolation is not necessary unlike a planar transistor, and a silicon pillar is a floating body. The body terminal for supplying the potential to the well is not necessary, and the layout (arrangement) can be very compact.

As described above, the greatest feature of the SGT is that, in terms of structural principle, the lower layer wiring by the silicide layer existing on the substrate side under the silicon pillar and the upper wiring by contact connection at the upper part of the silicon pillar can be used. The present invention makes use of the characteristics of this SGT to arrange the SGTs constituting the row selection decoder in accordance with the SRAM cells arranged in two rows in a row and b columns, thereby arranging them compactly and minimizing the area. An object is to provide a low-cost semiconductor device.

(1) According to the present invention, a source, a drain, and a gate are provided with a plurality of MOS transistors arranged hierarchically in a direction perpendicular to the substrate, and at least a × b MOS transistors are provided on the substrate. A semiconductor device that constitutes a decoder circuit by arranging in rows and columns,
Each of the plurality of MOS transistors includes:
Silicon pillars,
An insulator surrounding a side surface of the silicon pillar;
A gate surrounding the insulator;
A source region disposed above or below the silicon pillar;
A drain region disposed above or below the silicon pillar, the drain region disposed opposite to the source region with respect to the silicon pillar;
The decoder circuit is at least
1st to n-th n P-channel MOS transistors and 1st to n-th n-channel MOS transistors,
The first to n-th P-channel MOS transistors and the first to n-th N-channel MOS transistors are k-th (k = 1 to n) P-channel MOS transistors and k-th N-channel MOS transistors. N gates of transistors are connected to each other to form n transistor pairs;
The drain regions of the first to n-th N-channel MOS transistors and the first P-channel MOS transistors are disposed on the substrate side from the silicon pillar, and the first to n-th N-channel MOS transistors The drain regions of the first P-channel MOS transistors are connected to each other via a silicide region;
Of the first to nth P-channel MOS transistors, the source of the s (s = 1 to n−1) th P-channel MOS transistor and the drain of the s + 1th P-channel MOS transistor are connected to each other. And
The sources of the first to nth N-channel MOS transistors are each connected to a reference power supply line, and the sources of the nth P-channel MOS transistors are connected to a power supply line,
One input signal line for each of at least one set of input signal lines is connected to the gates of the MOS transistors of each of the n pairs of transistors,
At least one set of input signal lines of the power supply line, the reference power supply line, and the input signal line extends in the same direction, and a semiconductor device is provided.

(2) In a preferred aspect of the present invention, the first to nth N-channel MOS transistors are arranged in 1 row and n column,
The first to nth P-channel MOS transistors are arranged in one row and n column,
At least one set of input signal lines of the power supply line, the reference power supply line, and the input signal line extends in a direction perpendicular to the row direction.

(3) In another aspect, the sources of the first to nth N-channel MOS transistors are connected to the wiring of the first metal wiring layer,
The source of the nth P-channel MOS transistor is connected to the wiring of the first metal wiring layer,
The power line is constituted by a second metal wiring layer that is higher than the first metal wiring layer,
The reference power line is constituted by the second metal wiring layer,
The source of the first to n-th N-channel MOS transistors is connected to the reference power supply line via the wiring of the first metal wiring layer to which the sources of the first to n-th N-channel MOS transistors are connected. Connected to the wiring of the second metal wiring layer constituting,
The source of the nth P-channel MOS transistor is a second metal wiring that constitutes the power supply line via a wiring of a first metal wiring layer to which the source of the nth P-channel MOS transistor is connected. Connected to the layer wiring.

(4) Further, in another aspect, at least one set of input signal lines of the input signal lines is configured by a second metal wiring layer, and the gate of the MOS transistor of each of the n sets of transistor pairs is: The wiring of the first metal wiring layer extending in the row direction is connected to the wiring of the second metal wiring layer constituting at least one set of input signal lines of the input signal lines.

(5) In another aspect, the decoder circuit further includes a first inverter and a second inverter,
The first inverter includes at least the (n + 1) th P-channel MOS transistor and the (n + 1) th N-channel MOS transistor,
The second inverter includes at least the n + 2 P-channel MOS transistor and the n + 2 N-channel MOS transistor,
The (n + 1) th P-channel MOS transistor and the (n + 1) th N-channel MOS transistor, and the (n + 2) th P-channel MOS transistor and the (n + 2) th N-channel MOS transistor are arranged in the direction perpendicular to the row direction. ,
The (n + 1) th P-channel MOS transistor and the (n + 2) th P-channel MOS transistor, and the (n + 1) th N-channel MOS transistor and the (n + 2) th N-channel MOS transistor are arranged along the row direction, respectively.
The drain regions of the first to nth N-channel MOS transistors and the first P-channel MOS transistors are connected to the input of the first inverter,
The output wiring of the first inverter is connected to the input wiring of the second inverter, and the output of the second inverter becomes the output of the decoder circuit.

(6) In another aspect, the first to nth N-channel MOS transistors are arranged in n rows and 1 column,
The first to nth P-channel MOS transistors are arranged in n rows and 1 column,
At least one set of input signal lines of the power supply line, the reference power supply line, and the input signal line extends in a direction perpendicular to the row direction.

(7) In another aspect, the sources of the first to nth N-channel MOS transistors are connected to the wiring of the first metal wiring layer,
The source of the nth P-channel MOS transistor is connected to the wiring of the first metal wiring layer,
The power line is constituted by a second metal wiring layer that is higher than the first metal wiring layer,
The reference power line is constituted by the second metal wiring layer,
The source of the first to n-th N-channel MOS transistors is connected to the reference power supply line via the wiring of the first metal wiring layer to which the sources of the first to n-th N-channel MOS transistors are connected. Connected to the wiring of the second metal wiring layer constituting,
The source of the nth P-channel MOS transistor is a second metal wiring that constitutes the power supply line via a wiring of a first metal wiring layer to which the source of the nth P-channel MOS transistor is connected. Connected to the layer wiring.

(8) Furthermore, in another aspect, at least one set of input signal lines of the input signal lines is configured by a second metal wiring layer, and the gates of the MOS transistors of each of the n sets of transistor pairs are: The wiring of the first metal wiring layer extending in the row direction is connected to the wiring of the second metal wiring layer constituting at least one set of input signal lines of the input signal lines.

(9) In another aspect, the decoder circuit further includes a first inverter and a second inverter,
The first inverter includes at least the (n + 1) th P-channel MOS transistor and the (n + 1) th N-channel MOS transistor,
The second inverter includes at least the n + 2 P-channel MOS transistor and the n + 2 N-channel MOS transistor,
The (n + 1) th P-channel MOS transistor and the (n + 1) th N-channel MOS transistor, and the (n + 2) th P-channel MOS transistor and the (n + 2) th N-channel MOS transistor are arranged along the row direction, respectively.
The (n + 1) th P-channel MOS transistor and the (n + 2) th P-channel MOS transistor, and the (n + 1) th N-channel MOS transistor and the (n + 2) th N-channel MOS transistor are arranged in a direction perpendicular to the row direction. ,
The drain regions of the first to n-th N-channel MOS transistors and the first P-channel MOS transistors are connected to the input gate of the first inverter,
The output wiring of the first inverter is connected to the input gate of the second inverter, and the output of the second inverter becomes the output of the decoder circuit.

(10) According to the invention, the source, drain, and gate include a plurality of MOS transistors arranged hierarchically in a direction perpendicular to the substrate, and at least a × b MOS transistors are arranged on the substrate. A semiconductor device that constitutes a decoder circuit by arranging in a rows and b columns,
Each of the plurality of MOS transistors includes:
Silicon pillars,
An insulator surrounding a side surface of the silicon pillar;
A gate surrounding the insulator;
A source region disposed above or below the silicon pillar;
A drain region disposed above or below the silicon pillar, the drain region disposed opposite to the source region with respect to the silicon pillar;
The decoder circuit is at least
1st to n-th n P-channel MOS transistors and 1st to n-th n-channel MOS transistors,
The first to n-th P-channel MOS transistors and the first to n-th N-channel MOS transistors are k-th (k = 1 to n) P-channel MOS transistors and k-th N-channel MOS transistors. Are connected to each other to form n transistor pairs,
Source regions of the first to n-th N-channel MOS transistors and the first P-channel MOS transistors are disposed on the substrate side from the silicon pillar, and the first to n-th N-channel MOS transistors The drain regions of the first P-channel MOS transistors are connected to each other through a contact;
Of the first to nth P-channel MOS transistors, the source of the s (s = 1 to n−1) th P-channel MOS transistor and the drain of the s + 1th P-channel MOS transistor are connected to each other. And
Sources of the first to nth N-channel MOS transistors are respectively connected to a reference power supply line,
A source of the n-th P-channel MOS transistor is connected to a power line;
One input signal line for each of at least one set of input signal lines is connected to the gates of the MOS transistors of each of the n pairs of transistors,
At least one set of input signal lines of the power supply line, the reference power supply line, and the input signal line extends in the same direction, and a semiconductor device is provided.

(11) In another preferred aspect of the present invention, the first to nth P-channel MOS transistors are arranged in 1 row and n column,
The first to nth N-channel MOS transistors are arranged in 1 row and n column,
At least one set of input signal lines of the power supply line, the reference power supply line, and the input signal line extends in a direction perpendicular to the row direction.

(12) In another aspect, a source of the first to nth N-channel MOS transistors is connected to a wiring of a first metal wiring layer extending in a direction parallel to the row direction,
The source of the nth P-channel MOS transistor is connected to the wiring of the first metal wiring layer,
The power line is constituted by a second metal wiring layer that is higher than the first metal wiring layer,
The reference power line is constituted by the second metal wiring layer,
The source of the first to n-th N-channel MOS transistors is connected to the reference power supply line via the wiring of the first metal wiring layer to which the sources of the first to n-th N-channel MOS transistors are connected. Connected to the wiring of the second metal wiring layer constituting,
The source of the nth P-channel MOS transistor is a second metal wiring that constitutes the power supply line via a wiring of a first metal wiring layer to which the source of the nth P-channel MOS transistor is connected. Connected to the layer wiring.

(13) In another aspect, at least one set of input signal lines of the input signal lines is configured by a second metal wiring layer, and the gates of the MOS transistors of each of the n sets of transistor pairs are: The wiring of the first metal wiring layer extending in the row direction is connected to the wiring of the second metal wiring layer constituting at least one set of input signal lines of the input signal lines.

(14) In another aspect, a plurality of the decoder circuits are arranged in a column direction,
Source regions of adjacent N-channel MOS transistors of adjacent decoder circuits to which the reference power supply line is connected are commonly connected via a silicide region and / or adjacent to which the power supply line is connected. The source regions of adjacent P-channel MOS transistors of the decoder circuit are commonly connected via a silicide region.

(15) In another aspect, the decoder circuit comprises a first inverter and a second inverter,
The first inverter includes at least the (n + 1) th P-channel MOS transistor and the (n + 1) th N-channel MOS transistor,
The second inverter includes at least the n + 2 P-channel MOS transistor and the n + 2 N-channel MOS transistor,
The (n + 1) th P-channel MOS transistor and the (n + 1) th N-channel MOS transistor, and the (n + 2) th P-channel MOS transistor and the (n + 2) th N-channel MOS transistor are arranged in the direction perpendicular to the row direction. ,
The (n + 1) th P-channel MOS transistor and the (n + 2) th P-channel MOS transistor, and the (n + 1) th N-channel MOS transistor and the (n + 2) th N-channel MOS transistor are arranged along the row direction, respectively.
The drain regions of the first to nth N-channel MOS transistors and the first P-channel MOS transistor are connected to the input gate of the first inverter,
The output wiring of the first inverter is connected to the input gate of the second inverter, and the output of the second inverter becomes the output of the decoder circuit.

(16) In another aspect, the first inverter includes at least the (n + 1) th P-channel MOS transistor and the (n + 1) th N-channel MOS transistor.
The second inverter includes at least the n + 2 P-channel MOS transistor and the n + 2 N-channel MOS transistor,
The source regions of the first to nth N-channel MOS transistors and the n + 1th N-channel MOS transistor and the source regions of the n + 2 N-channel MOS transistors are connected in common via a silicide region. Connected to the wiring of one metal wiring layer,
The source region of the n-th P-channel MOS transistor, the n + 1-th P-channel MOS transistor, and the source region of the n + 2-th P-channel MOS transistor are connected in common via a silicide region to form a first metal. Connected to the wiring in the wiring layer,
The power line is constituted by a second metal wiring layer that is higher than the first metal wiring layer,
The reference power line is constituted by the second metal wiring layer,
The sources of the first to nth N-channel MOS transistors, the (n + 1) th N-channel MOS transistor, and the (n + 2) th N-channel MOS transistor are the first to n-th N-channel MOS transistors and the source Wiring of the second metal wiring layer constituting the reference power supply line via the wiring of the first metal wiring layer to which the sources of the (n + 1) th N-channel MOS transistor and the (n + 2) th N-channel MOS transistor are connected Connected to
The sources of the nth P channel MOS transistor, the (n + 1) th P channel MOS transistor, and the (n + 2) th P channel MOS transistor are the nth P channel MOS transistor and the (n + 1) th P channel MOS transistor. The MOS transistor and the n + 2 P-channel MOS transistor are connected to the wiring of the second metal wiring layer constituting the power supply line through the wiring of the first metal wiring layer to which the source of the MOS transistor is connected.

(17) In another aspect, the first to nth P-channel MOS transistors are arranged in n rows and 1 column,
The first to nth N-channel MOS transistors are arranged in n rows and 1 column,
At least one set of input signal lines of the power supply line, the reference power supply line, and the input signal line extends in a direction perpendicular to the row direction.

(18) In another aspect, the sources of the first to nth N-channel MOS transistors are connected to the wiring of the first metal wiring layer,
The source of the nth P-channel MOS transistor is connected to the wiring of the first metal wiring layer,
The power line is constituted by a second metal wiring layer that is higher than the first metal wiring layer,
The reference power line is constituted by the second metal wiring layer,
The source of the first to n-th N-channel MOS transistors is connected to the reference power supply line via the wiring of the first metal wiring layer to which the sources of the first to n-th N-channel MOS transistors are connected. Connected to the wiring of the second metal wiring layer constituting,
The source of the nth P-channel MOS transistor is a second metal wiring that constitutes the power supply line via a wiring of a first metal wiring layer to which the source of the nth P-channel MOS transistor is connected. Connected to the layer wiring.

(19) In another aspect, at least one set of input signal lines of the input signal lines is configured by a second metal wiring layer, and the gates of the MOS transistors in each of the n sets of transistor pairs are: The wiring of the first metal wiring layer extending in the row direction is connected to the wiring of the second metal wiring layer constituting at least one set of input signal lines of the input signal lines.

(20) In another aspect, the decoder circuit further includes a first inverter and a second inverter,
The first inverter includes at least the (n + 1) th P-channel MOS transistor and the (n + 1) th N-channel MOS transistor,
The second inverter includes at least the n + 2 P-channel MOS transistor and the n + 2 N-channel MOS transistor,
The (n + 1) th P-channel MOS transistor and the (n + 1) th N-channel MOS transistor, and the (n + 2) th P-channel MOS transistor and the (n + 2) th N-channel MOS transistor are arranged along the row direction, respectively.
The (n + 1) th P-channel MOS transistor and the (n + 2) th P-channel MOS transistor, and the (n + 1) th N-channel MOS transistor and the (n + 2) th N-channel MOS transistor are arranged in a direction perpendicular to the row direction. ,
The drain regions of the first to n-th N-channel MOS transistors and the first P-channel MOS transistors are connected to the input gate of the first inverter,
The output wiring of the first inverter is connected to the input gate of the second inverter, and the output of the second inverter becomes the output of the decoder circuit.

(21) In another aspect, the first inverter includes at least an (n + 1) th P-channel MOS transistor and an (n + 1) th N-channel MOS transistor.
The second inverter includes at least an n + 2 P-channel MOS transistor and an n + 2 N-channel MOS transistor,
Source regions of the (n + 1) th n-channel MOS transistor and the (n + 2) th n-channel MOS transistor are commonly connected via a silicide region and connected to a reference power supply, or the (n + 1) th n-channel MOS transistor And the source region of the n + 2 P-channel MOS transistor are commonly connected via a silicide region and connected to a power supply line.

(22) According to the present invention, in a semiconductor device constituting a static memory by arranging, on a substrate, a plurality of MOS transistors whose sources, drains and gates are arranged hierarchically in a direction perpendicular to the substrate. There,
A plurality of static memory cells in which at least six MOS transistors are arranged on an insulating film formed on a substrate are arranged in a matrix,
A plurality of row address circuits for designating one row line of the memory cells;
A plurality of row decoders for selecting one row of the static memory cell by signals from the plurality of row address circuits;
6 MOS transistors constituting the static memory cell;
Each of the plurality of MOS transistors constituting the row decoder is
Silicon pillars,
An insulator surrounding a side surface of the silicon pillar;
A gate surrounding the insulator;
A source region disposed above or below the silicon pillar;
A drain region disposed above or below the silicon pillar, the drain region disposed opposite to the source region with respect to the silicon pillar;
The six MOS transistors constituting the static memory cell are arranged in two rows and three columns,
The row decoder circuit includes at least
N P-channel MOS transistors arranged in one row and n columns, n N-channel MOS transistors arranged in one row and n columns, a first inverter, and a second inverter,
The n P-channel MOS transistors and the n N-channel MOS transistors are the k-th column (k = 1 to n) of the n P-channel MOS transistors arranged in the first row and the n-th column. ) And the gates of the k-th N-channel MOS transistors of the n N-channel MOS transistors arranged in the first row and the n-th column are connected to each other. Form the
The drain regions of the n N-channel MOS transistors and the first column of the P-channel MOS transistors are arranged on the substrate side from the silicon pillar, and the n N-channel MOS transistors and the first column of the first column are disposed. The drain regions of the P-channel MOS transistors of the eyes are connected to each other via a silicide region,
The source of the P-channel MOS transistor in the s-th column (s = 1 to n−1) and the drain of the P-channel MOS transistor in the s + 1-th column are connected to each other,
The sources of the n N-channel MOS transistors are respectively connected to a reference power supply line extending in the direction perpendicular to the row direction, and the source of the P-channel MOS transistor in the nth column is perpendicular to the row direction. Connected to the power line extending in the direction,
The input signals input to the gates of the MOS transistors of the n transistor pairs are respectively supplied by wirings extending in the direction perpendicular to the row direction,
The drains of the n N-channel MOS transistors and the first column of P-channel MOS transistors are connected to the input gate of the first inverter, and the output wiring of the first inverter is the second inverter. A semiconductor device is provided in which the output wiring of the second inverter is connected to a row selection line of the static memory cell.

(23) In another aspect, the source of the n N-channel MOS transistors is connected to the wiring of the first metal wiring layer,
The source of the n-th column P-channel MOS transistor is connected to the wiring of the first metal wiring layer,
The power line is constituted by a second metal wiring layer that is higher than the first metal wiring layer,
The reference power line is constituted by the second metal wiring layer,
The source of the n N-channel MOS transistors is a second metal that constitutes the reference power supply line via the wiring of the first metal wiring layer to which the sources of the n N-channel MOS transistors are connected. Connected to the wiring in the wiring layer,
The source of the n-th column P-channel MOS transistor constitutes the power supply line via the wiring of the first metal wiring layer to which the source of the n-th column P-channel MOS transistor is connected. Connected to the wiring of the metal wiring layer of 2,
At least one set of the input signal lines is constituted by a second metal wiring layer, and the gate of the MOS transistor of each of the n sets of transistor pairs is a first metal extending in the row direction. The wiring of the second metal wiring layer constituting at least one set of input signal lines of the input signal lines is connected via the wiring of the wiring layer.

(24) Further, according to the present invention, a semiconductor that constitutes a static memory by arranging, on a substrate, a plurality of MOS transistors in which sources, drains, and gates are arranged hierarchically in a direction perpendicular to the substrate. A device,
A plurality of static memory cells in which at least six MOS transistors are arranged on an insulating film formed on a substrate are arranged in a matrix,
A plurality of row address circuits for designating one row line of the memory cells;
A plurality of row decoders for selecting one row of the static memory cell by signals from the plurality of row address circuits;
6 MOS transistors constituting the static memory cell;
Each of the plurality of MOS transistors constituting the row decoder is
Silicon pillars,
An insulator surrounding a side surface of the silicon pillar;
A gate surrounding the insulator;
A source region disposed above or below the silicon pillar;
A drain region disposed above or below the silicon pillar, the drain region disposed opposite to the source region with respect to the silicon pillar;
The six MOS transistors constituting the static memory cell are arranged in two rows and three columns,
The row decoder circuit includes at least
N P-channel MOS transistors arranged in one row and n columns, n N-channel MOS transistors arranged in one row and n columns, a first inverter, and a second inverter,
The n P-channel MOS transistors and the n N-channel MOS transistors are the k-th column (k = 1 to n) of the n P-channel MOS transistors arranged in the first row and the nth column. The gates of the N-channel MOS transistors in the k-th column of the P-channel MOS transistors and the n N-channel MOS transistors arranged in the first row and the n-th column are connected to each other. Forming,
The source regions of the n N-channel MOS transistors and the first column of the P-channel MOS transistors are arranged on the substrate side from the silicon pillar, and the n N-channel MOS transistors and the first column of the first column are disposed. The drain regions of the P-channel MOS transistors of the eyes are connected to each other through contacts,
The source of the P-channel MOS transistor in the s-th column (s = 1 to n−1) and the drain of the P-channel MOS transistor in the s + 1-th column are connected to each other,
The sources of the n N-channel MOS transistors are respectively connected to a reference power supply line extending in the direction perpendicular to the row direction, and the source of the P-channel MOS transistor in the nth column is perpendicular to the row direction. Connected to the power line extending in the direction,
Input signals input to the gates of the MOS transistors of each of the n pairs of transistors are respectively supplied by wirings extending in the direction perpendicular to the row direction,
The drains of the n N-channel MOS transistors and the first column of P-channel MOS transistors are connected to the input gate of the first inverter, and the output wiring of the first inverter is the second inverter. A semiconductor device is provided in which the output wiring of the second inverter is connected to a row selection line of the static memory cell.

(25) In another aspect, the source of the n N-channel MOS transistors is connected to a wiring of a first metal wiring layer extending in a direction parallel to the row direction,
The source of the n-th column P-channel MOS transistor is connected to the wiring of the first metal wiring layer,
The power line is constituted by a second metal wiring layer that is higher than the wiring layer of the first metal wiring layer,
The reference power line is constituted by the second metal wiring layer,
The source of the n N-channel MOS transistors is a second metal that constitutes the reference power supply line via the wiring of the first metal wiring layer to which the sources of the n N-channel MOS transistors are connected. Connected to the wiring in the wiring layer,
The source of the n-th column P-channel MOS transistor constitutes the power supply line via the wiring of the first metal wiring layer to which the source of the n-th column P-channel MOS transistor is connected. Connected to the wiring of the metal wiring layer of 2,
At least one set of the input signal lines is constituted by a second metal wiring layer, and the gate of the MOS transistor of each of the n sets of transistor pairs is a first metal extending in the row direction. The wiring of the second metal wiring layer constituting at least one set of input signal lines of the input signal lines is connected via the wiring of the wiring layer.

1 is a circuit diagram of a semiconductor memory device according to an embodiment of the present invention. It is a selection operation | movement figure of the decoder circuit of this invention. It is an equivalent circuit diagram of the NOR type decoder of the present invention. 1 is a plan view of a NOR decoder according to a first embodiment of the present invention. FIG. 1 is a cross-sectional view of a NOR decoder according to a first embodiment of the present invention. 1 is a cross-sectional view of a NOR decoder according to a first embodiment of the present invention. 1 is a cross-sectional view of a NOR decoder according to a first embodiment of the present invention. 1 is a cross-sectional view of a NOR decoder according to a first embodiment of the present invention. 1 is a cross-sectional view of a NOR decoder according to a first embodiment of the present invention. 1 is a cross-sectional view of a NOR decoder according to a first embodiment of the present invention. 1 is a cross-sectional view of a NOR decoder according to a first embodiment of the present invention. 1 is a cross-sectional view of a NOR decoder according to a first embodiment of the present invention. FIG. 6 is an equivalent circuit diagram showing a row selection decoder according to a second embodiment of the present invention. It is a top view of the row selection decoder of 2nd Example of this invention. It is sectional drawing of the row selection decoder of 2nd Example of this invention. It is sectional drawing of the row selection decoder of 2nd Example of this invention. It is sectional drawing of the row selection decoder of 2nd Example of this invention. It is sectional drawing of the row selection decoder of 2nd Example of this invention. It is sectional drawing of the row selection decoder of 2nd Example of this invention. It is sectional drawing of the row selection decoder of 2nd Example of this invention. It is sectional drawing of the row selection decoder of 2nd Example of this invention. It is sectional drawing of the row selection decoder of 2nd Example of this invention. It is a top view of the row selection decoder containing the memory cell of the 3rd Example of this invention. It is a top view of the NOR type decoder of the 4th example of the present invention. It is sectional drawing of the NOR type decoder of the 4th Example of this invention. It is sectional drawing of the NOR type decoder of the 4th Example of this invention. It is sectional drawing of the NOR type decoder of the 4th Example of this invention. It is sectional drawing of the NOR type decoder of the 4th Example of this invention. It is sectional drawing of the NOR type decoder of the 4th Example of this invention. It is sectional drawing of the NOR type decoder of the 4th Example of this invention. It is sectional drawing of the NOR type decoder of the 4th Example of this invention. It is sectional drawing of the NOR type decoder of the 4th Example of this invention. It is sectional drawing of the NOR type decoder of the 4th Example of this invention. It is a top view of the row selection decoder of the 5th Example of this invention. It is sectional drawing of the row selection decoder of the 5th Example of this invention. It is sectional drawing of the row selection decoder of the 5th Example of this invention. It is sectional drawing of the row selection decoder of the 5th Example of this invention. It is sectional drawing of the row selection decoder of the 5th Example of this invention. It is sectional drawing of the row selection decoder of the 5th Example of this invention. It is sectional drawing of the row selection decoder of the 5th Example of this invention. It is sectional drawing of the row selection decoder of the 5th Example of this invention. It is sectional drawing of the row selection decoder of the 5th Example of this invention. It is sectional drawing of the row selection decoder of the 5th Example of this invention. It is a circuit diagram of the semiconductor memory device of another Example of this invention. It is a selection operation | movement figure of the decoder circuit of another Example of this invention. It is an equivalent circuit diagram of the NOR type decoder of the present invention. It is a top view of the NOR type decoder of the 6th example of the present invention. It is sectional drawing of the NOR type decoder of the 6th Example of this invention. It is sectional drawing of the NOR type decoder of the 6th Example of this invention. It is sectional drawing of the NOR type decoder of the 6th Example of this invention. It is sectional drawing of the NOR type decoder of the 6th Example of this invention. It is a top view of the NOR type decoder of 7th Example of this invention. It is sectional drawing of the NOR type decoder of the 7th Example of this invention. It is sectional drawing of the NOR type decoder of the 7th Example of this invention. It is sectional drawing of the NOR type decoder of the 7th Example of this invention. It is sectional drawing of the NOR type decoder of the 7th Example of this invention. It is sectional drawing of the NOR type decoder of the 7th Example of this invention. It is sectional drawing of the NOR type decoder of the 7th Example of this invention. It is a top view of the row selection decoder of the 8th Example of this invention. It is a top view of the NOR type | mold decoder of the 9th Example of this invention. It is sectional drawing of the NOR type decoder of the 9th Example of this invention. It is sectional drawing of the NOR type decoder of the 9th Example of this invention. It is sectional drawing of the NOR type decoder of the 9th Example of this invention. It is sectional drawing of the NOR type decoder of the 9th Example of this invention. It is sectional drawing of the NOR type decoder of the 9th Example of this invention. It is sectional drawing of the NOR type decoder of the 9th Example of this invention. It is sectional drawing of the NOR type decoder of the 9th Example of this invention. It is a top view of the NOR type decoder of the 10th Example of this invention. It is sectional drawing of the NOR type decoder of the 10th Example of this invention. It is sectional drawing of the NOR type decoder of the 10th Example of this invention. It is sectional drawing of the NOR type decoder of the 109th Example of this invention. It is the equivalent circuit of the SRAM cell which shows a prior art example. It is a top view of SRAM which shows a prior art example. It is sectional drawing of SRAM which shows a prior art example. It is sectional drawing of SRAM which shows a prior art example. It is sectional drawing of SRAM which shows a prior art example. It is a matrix array of conventional SRAM cells.

Example 1
FIG. 1 shows a semiconductor memory device including a decoder circuit for a memory applied to the present invention. An SRAM cell is adopted as an example of the memory cell.
Reference numeral 100 denotes a memory array in which the SRAM cells shown in FIG. 18 are arranged in a matrix. In the figure, a memory array of 256 rows and 16 columns, that is, 4096 bits is constructed.
These SRAM cells are arranged in the horizontal direction by commonly connecting word lines WLm (m = 0 to 255) in the row direction, and bit lines BLn (n = 0 to 15), inverted bit lines in the column direction. BLnB are connected in common and arranged in the vertical direction.
Reference numeral 200 denotes a row selection decoder. The row selection decoder 200 receives the NOR decoder 201 and the outputs of the first inverter 202 and the first inverter 202 that receive the output DECOUTk (k = 0 to 255) as inputs, and receives the row selection signal WLk as an output. It is comprised by the inverter 203 which outputs.
The NOR decoder 201 receives address selection signals XA0 to XA7, XB0 to 3, and XC0 to 7, which will be described later, and receives one of the row selection signals WLk (k = 0 to 255) according to the input address signal. select.
A predecoder 300 receives address signals and outputs address selection signals XA0 to XA0, XB0 to 3, and XC0 to 7 for selecting a row selection decoder. Here, 300A which receives the address signals A0 to A2 and outputs the address selection signals XA0 to X7, 300B which receives the address signals A3 to A4 and outputs the address selection signals XB0 to 3, and the address signals A5 to A7 which receive the address It is composed of 300C that outputs selection signals XC0 to XC7.
For example, the row selection decoder 200 including the NOR type decoder 201 receives the address selection signals XA0, XB0, and XC0, selects WL0, receives the address selection signals XA1, XB0, and XC0, selects WL1, and so on. In response to the address selection signals XA7, XB3, and XC7, WL255 is selected.

Reference numeral 400 denotes a column selection gate, and reference numeral 500 denotes a column selection decoder that selects the column selection gate 400. The column selection decoder 500 receives the column address signals A8 to A11 and outputs a column selection signal CLn (n = 0 to 15). The column selection signal CLn is input to the column selection gate, and the column selection gate transistor CGn ( n = 0-15) and connected to the gate of CGnB. Column select gate transistors CGn and CGnB have sources connected to bit line BLn and inverted bit line BLnB of the SRAM cell, respectively, and drains commonly connected to data line DL and inverted data line DLB.

Reference numeral 600 is a sense amplifier that receives and amplifies and outputs a minute read signal read from the memory cell to the data line via the bit line and the inverted bit line. This is an output circuit that creates a read signal DOUT to be read.
Reference numeral 800 denotes a writing circuit that receives the input data DIN and creates a signal for writing data to the SRAM cell.
As shown in FIG. 1, an SRAM cell arranged in a minimum unit of two row pitches receives an address signal, and uses one of row selection lines WLk (k = 0 to 255) via a row selection decoder. Since the selection is made, the row selection decoder also needs to be arranged in a minimum unit of two rows.

FIG. 2 shows a selection operation table of the row selection decoder. When the address selection signal indicated by a circle is input to the NOR decoder 201, the output DECOUT of the corresponding NOR decoder 201 is selected. For example, when the address selection signals XA2, XB1, and XC0 are input, the output DECOUT10 of the corresponding NOR type decoder 201 is selected. That is, as the address selection signal for selecting the row selection decoder, it is necessary to supply a total of 20 address selection signals to the row selection decoder 200, XA is 8, XB is 4, XC is 8.

FIG. 3 shows a NOR type decoder circuit 201 of the present invention.
Tn1, Tn2, and Tn3 are NMOS transistors configured by SGT, and Tp1, Tp2, and Tp3 are PMOS transistors that are also configured by SGT. The sources of the NMOS transistors Tn1, Tn2, and Tn3 are connected to the reference power supply Vss, and the drains are commonly connected to the node N1. The node N1 becomes the output DECOUTk. The drain of the PMOS transistor Tp1 is connected to the node N1, the source is connected to the drain of the PMOS transistor Tp2 via the node N2, and the source of the PMOS transistor Tp2 is connected to the drain of the PMOS transistor Tp3 via the node N3. The source of Tp3 is connected to the power supply Vcc. An input signal XAh (h = 0 to 7) is input to the gates of the NMOS transistor Tn1 and the PMOS transistor Tp1, and an input signal XBi (i = 0 to 3) is input to the gates of the NMOS transistor Tn2 and the PMOS transistor Tp2. The input signal XCj (j = 0 to 7) is input to the gates of the NMOS transistor Tn3 and the PMOS transistor Tp3.

4a, 4b, 4c, 4d, 4e, 4f, 4g, 4h and 4i show a first embodiment. 4A is a plan view of the layout (arrangement) of the 3-input NOR decoder 201 of the present invention, FIG. 4B is a cross-sectional view along the cut line AA ′ in FIG. 4A, and FIG. 4C is the cut line in FIG. FIG. 4d is a cross-sectional view along the cut line CC ′ in FIG. 4a, FIG. 4e is a cross-sectional view along the cut line DD ′ in FIG. 4a, and FIG. 4f. 4a is a cross-sectional view along the cut line EE ′ in FIG. 4a, FIG. 4g is a cross-sectional view along the cut line FF ′ in FIG. 4a, and FIG. 4h is a cross-sectional view along the cut line GG ′ in FIG. FIG. 4i shows a cross-sectional view along the cut line HH ′ in FIG. 4a.
4a, the NMOS transistors Tn1, Tn2 and Tn3 of the NOR decoder of FIG. 3 are in the first row (upper row in the figure), and the PMOS transistors Tp1, Tp2 and Tp3 are in the second row (lower row in the figure). They are arranged in order from the right side of the figure.
4a, FIG. 4b, FIG. 4c, FIG. 4d, FIG. 4e, FIG. 4f, FIG. 4g, FIG. 4h, and FIG. It is indicated by the equivalent symbol on the base.

Planar silicon layers 102n, 102pa, and 102pb are formed on an insulating film such as a buried oxide film layer (BOX) 101 formed on the substrate. It is composed of an n + diffusion layer, a p + diffusion layer, and a p + diffusion layer. 103 is a silicide layer formed on the surface of the planar silicon layers (102n, 102pa, 102pb), and connects the planar silicon layers 102n, 102pa. 104p1, 104p2, and 104p3 are p-type silicon pillars, 104n1, 104n2, and 104n3 are n-type silicon pillars, 105 is a gate insulating film that surrounds the silicon pillars 104p1, 104p2, 104p3, 104n1, 104n2, and 104n3, 106 is a gate electrode, 106a, 106b, 106c, and 106d are gate wirings, respectively. N + diffusion layers 107n1, 107n2, and 107n3 are respectively formed on the uppermost portions of the silicon pillars 104p1, 104p2, and 104p3 by impurity implantation or the like, and p + diffusion layers 107p1 and 107p2 are formed on the uppermost portions of the silicon pillars 104n1, 104n2, and 104n3, respectively. 107p3 are formed by impurity implantation or the like. 108 is a silicon nitride film for protecting the gate insulating film 105, 109n1, 109n2, 109n3, 109p1, 109p2, and 109p3 are silicides connected to n + diffusion layers 107n1, 107n2, 107n3, and p + diffusion layers 107p1, 107p2, and 107p3, respectively. 110n1, 110n2, 110n3, 110p1, 110p2, and 110p3 include silicide layers 109n1, 109n2, 109n3, 109p1, 109p2, and 109p3 and

wirings

113a, 113a, 113a, 113d, 113d, and 113c of the first metal wiring layer. Contacts for connection, 111a is a contact for connecting the gate wiring 106a and the wiring 113e of the first metal wiring layer, and 111b is a wiring 1 of the gate wiring 106c and the first metal wiring layer. Contacts for connecting the 3f, 111c denotes a contact for connecting the wires 113g of the gate wiring 106d and the first metal wiring layer.
Reference numeral 112a denotes a contact for connecting the silicide 103 connecting the lower diffusion layer 102n and the lower diffusion layer 102pa and the wiring 113b of the first metal wiring layer.

The silicon pillar 104p1, the lower diffusion layer 102n, the upper diffusion layer 107n1, the gate insulating film 105, and the gate electrode 106 constitute the NMOS transistor Tn1, and the silicon pillar 104p2, the lower diffusion layer 102n, the upper diffusion layer 107n2, the gate insulating film 105, The gate electrode 106 constitutes the NMOS transistor Tn2, and the silicon pillar 104p3, the lower diffusion layer 102n, the upper diffusion layer 107n3, the gate insulating film 105, and the gate electrode 106 constitute the NMOS transistor Tn3, and the silicon pillar 104n1 and the lower diffusion layer 102pa, upper diffusion layer 107p1, gate insulating film 105, and gate electrode 106 constitute a PMOS transistor Tp1, and silicon pillar 104n2, lower diffusion layer 102pb, upper diffusion layer 107p2, gate insulating film 105, gate electrode The electrode 106 constitutes a PMOS transistor Tp2, the silicon pillar 104N3, lower diffusion layer 102Pb, the upper diffusion layer 107P3, gate insulating film 105, the gate electrode 106, constituting the PMOS transistor Tp3.

A gate wiring 106a is connected to the gate electrodes 106 of the NMOS transistor Tn1 and the PMOS transistor Tp1. A gate line 106b is connected to the gate electrodes 106 of the NMOS transistor Tn2 and the PMOS transistor Tp2, and a gate line 106c is connected to the gate electrode 106 of the PMOS transistor Tp2. A gate wiring 106d is connected to the gate electrodes 106 of the NMOS transistor Tn3 and the PMOS transistor Tp3.

The lower diffusion layers 102n and 102pa serve as common drains of the NMOS transistors Tn1, Tn2, Tn3 and the PMOS transistor Tp1 through the silicide 103, and are connected to the wiring 113b of the first metal wiring layer through the contact 112a to become the output DECOUT1. . The upper diffusion layer 107n1 which is the source of the NMOS transistor Tn1 is connected to the wiring 113a of the first metal wiring layer via the silicide 109n1 and the contact 110n1, and the wiring 113a of the first metal wiring layer is further connected to the wiring 114a via the contact 114n1. The reference power supply Vss is supplied to 115c connected to the wiring 115c of the second metal wiring layer. Here, the wiring 115c of the second metal wiring layer extends in a direction perpendicular to the row direction. The upper diffusion layer 107n2 which is the source of the NMOS transistor Tn2 is connected to the wiring 113a of the first metal wiring layer extending in the row direction via the silicide 109n2 and the contact 110n2. The upper diffusion layer 107n3 which is the source of the NMOS transistor Tn3 is connected to the wiring 113a of the first metal wiring layer through the silicide 109n3 and the contact 110n3. The upper diffusion layer 107p1, which is the source of the PMOS transistor Tp1, is connected to the wiring 113d of the first metal wiring layer through the silicide 109p1 and the contact 110p1. The upper diffusion layer 107p2 which is the drain of the PMOS transistor Tp2 is connected to the wiring 113d of the first metal wiring layer through the silicide 109p2 and the contact 110p2. Here, the source of the PMOS transistor Tp1 and the drain of the PMOS transistor Tp2 are connected via the wiring 113d of the first metal wiring layer. The source of the PMOS transistor Tp2 is connected to the drain of the PMOS transistor Tp3 through the lower diffusion layer 102pb and the silicide region 103, and the source of the PMOS transistor Tp3 is connected to the wiring 113c of the first metal wiring layer through the contact 110p3. The first metal wiring layer wiring 113c is further connected to the second metal wiring layer wiring 115g via the contact 114p3, and the power Vcc is supplied to 115g. Here, the wiring 115g of the second metal wiring layer extends in a direction perpendicular to the row direction.

The gate wiring 106a to which any of the address selection signals XA0 to XA7 supplied by the wiring of the second metal wiring layer is input is connected to the wiring 113e of the first metal wiring layer via the contact 111a. The wiring 113e of the first metal wiring layer extends in a parallel direction (right side in the drawing) along the row. The wiring of the second metal wiring layer that supplies the address selection signals XA0 to XA7 extends in the direction perpendicular to the row direction, and the wiring of the first metal wiring layer that extends in parallel to the row direction. The contact 114a is arranged at any one of the intersections of the wirings of the second metal wiring layer that supplies the address selection signals XA0 to XA7 extending in the direction perpendicular to the row direction to the address 113e, and the address selection signal XAh The wiring of the second metal wiring layer that supplies (h = 0 to 7) is connected to the gate wiring 106a. In the figure, a contact 114a is provided at the intersection of the wiring 115a of the second metal wiring layer that supplies the address selection signal XA1 and the wiring 113e of the first metal wiring layer. That is, the address selection signal XA1 is input to the gates of the NMOS transistor Tn1 and the PMOS transistor Tp1 of the NOR decoder.
In this figure, the wiring of the second metal wiring layer that supplies the address selection signals XA2 to XA7 is omitted, but it has the same arrangement as the wiring of the second metal wiring layer that supplies the address selection signals XA0 and XA1. Further, it is arranged on the right side in a form perpendicular to the row direction.
Note that a contact 114z is drawn by a broken line at the intersection of the address selection signal XA0 (wiring 115b of the second metal wiring layer) and the wiring 113e of the first metal wiring layer. There is no contact, and if it is desired to input the address selection signal XA0 (the wiring 115b of the second metal wiring layer), it shows the location of the fictitious contact where a contact is provided here. Yes. Hereinafter, the same is true for the other portions.

The gate wiring 106c to which any of the address selection signals XB0 to XB3 supplied by the wiring of the second metal wiring layer is input is connected to the wiring 113f of the first metal wiring layer through the contact 111b. The wiring 113f of the first metal wiring layer extends in a parallel direction (left side in the drawing) along the row. The wiring of the second metal wiring layer that supplies the address selection signals XB0 to XB3 extends in the direction perpendicular to the row direction, and is at one of the intersections with the wiring 113f of the first metal wiring layer. The contact 114b is arranged to connect the wiring of the second metal wiring layer that supplies the address selection signal XBi (i = 0 to 3) to the gate wiring 106c. In the figure, a contact 114b is provided at the intersection of the wiring 115d of the second metal wiring layer that supplies the address selection signal XB0 and the wiring 113f of the first metal wiring layer. That is, the address selection signal XB0 is input to the gates of the NMOS transistor Tn2 and the PMOS transistor Tp2 of the NOR decoder.
Note that the second metal wiring layer 115e for supplying the address selection signal XB1, the second metal wiring layer 115f for supplying the address selection signal XB2, and the second metal wiring layer for supplying the address selection signal XB3. A contact 114z is drawn by a broken line at the intersection of the wiring 115h and the wiring 113f of the first metal wiring layer. However, as described above, there is no contact here, and the location of the fictitious contact is shown. Show.

The gate wiring 106d to which any one of the address selection signals XC0 to XC7 supplied by the wiring of the second metal wiring layer is input is connected to the wiring 113g of the first metal wiring layer through the contact 111c. The wiring 113g of the first metal wiring layer extends in a parallel direction (left side in the drawing) along the row. The wiring of the second metal wiring layer that supplies the address selection signals XC0 to XC7 extends in a direction perpendicular to the row direction, and is at one of the intersections with the wiring 113g of the first metal wiring layer. A contact 114c is arranged to connect the wiring of the second metal wiring layer that supplies the address selection signal XCj (i = 0 to 7) to the gate wiring 106d. In the figure, a contact 114c is provided at the intersection of the wiring 115i of the second metal wiring layer that supplies the address selection signal XC0 and the wiring 113g of the first metal wiring layer. That is, the address selection signal XC0 is input to the gates of the NMOS transistor Tn3 and the PMOS transistor Tp3 of this NOR decoder.
Note that a contact 114z is drawn by a broken line at the intersection of the wiring 115j of the second metal wiring layer that supplies the address selection signal XC1 and the wiring 113g of the first metal wiring layer, as described above. Here, no contact exists, and the location of a fictitious contact is shown.
Further, the wiring of the second metal wiring layer that supplies the address selection signals XC2 to XC7 is omitted for the sake of illustration, but is the same as the wiring of the second metal wiring layer that supplies the address selection signals XC0 and XC1. Furthermore, it is arranged on the left side in a direction perpendicular to the row direction.
According to this embodiment, address selection signals XA1, XB0, and XC0 are input to this NOR type decoder, and the output is DECOUT1 according to FIG.
The NOR decoder BL201A is a region surrounded by a frame in the figure, and the vertical dimension is Ly1 which is the same as the SRAM cell of FIG. 19a.

According to this embodiment, the power supply wiring, the reference power supply wiring, and the address selection signal line are the wirings of the second metal wiring layer, and the SGTMOS transistors constituting the NOR decoder are arranged in 2 rows and 3 columns. Connection between the input gate of the NOR decoder and the wiring of the second metal wiring layer through the wiring of the first metal wiring layer that extends in the vertical direction and is arranged in parallel along the row direction As a result, it is possible to supply an arbitrary address selection signal to the input of the NOR decoder, and the same arrangement as that of a small SRAM having a small area that can be arranged with the minimum wiring pitch of the second metal wiring layer. A NOR type decoder can be realized with a pitch of.

(Example 2)
FIG. 5 shows an equivalent circuit of the row selection decoder 200-k (k = 0 to 255). A NOR type decoder circuit 201k, a first inverter 202k, and a second inverter 203k are included. The NOR decoder 201k is the same as that shown in FIG. 3, and the first inverter 202k includes a PMOS transistor Tp11 and an NMOS transistor Tn11. The drains of the PMOS transistor Tp11 and the NMOS transistor Tn11 are commonly connected by a node N11. The source of the PMOS transistor Tp11 is connected to the power supply Vcc, and the source of the NMOS transistor Tn11 is connected to the reference power supply Vss. Further, the gates of the PMOS transistor Tp11 and the NMOS transistor Tn11 are connected in common, and the output DECOUTk of the NOR decoder is input. The second inverter 203k includes a PMOS transistor Tp12 and an NMOS transistor Tn12. The drains of the PMOS transistor Tp12 and the NMOS transistor Tn12 are commonly connected by the node N12, and the output is WLk that is the output of the row selection decoder 200-k. The source of the PMOS transistor Tp12 is connected to the power supply Vcc, and the source of the NMOS transistor Tn12 is connected to the reference power supply Vss. The gates of the PMOS transistor Tp12 and the NMOS transistor Tn12 are connected in common and connected to the node N11 that is the output of the first inverter 202k.

FIGS. 6a, 6b, 6c, 6d, 6e, 6f, 6g, 6h and 6i show a second embodiment. 6a is a plan view of the layout (arrangement) of the row selection decoder 200-k in FIG. 5, FIG. 6b is a cross-sectional view along the cut line AA ′ in FIG. 6a, and FIG. 6c is a cut line in FIG. FIG. 6d is a cross-sectional view along the cut line CC ′ in FIG. 6a, FIG. 6e is a cross-sectional view along the cut line DD ′ in FIG. 6a, and FIG. 6f. Fig. 6a is a cross-sectional view along the cut line EE 'in Fig. 6a, Fig. 6g is a cross-sectional view along the cut line FF' in Fig. 6a, and Fig. 6h is a cut line GG 'in Fig. 6a. FIG. 6i shows a cross-sectional view along the cut line HH ′ in FIG. 6a.

Inverters

202 and 203 are arranged on the right side of the NOR decoder in FIG. 4, and three sets of main row selection decoders BL200A-7, BL200A-8, and BL200A-9 are arranged at a pitch Ly1 on the upper and lower sides.

In the row selection decoder BL200A-7 in the figure, the sources of the NMOS transistor Tn11 and NMOS transistor Tn12 constituting the first and second inverters are respectively the lower diffusion layer 102nb and are commonly connected by the silicide layer 103, and contact 112b ( The wiring 113h of the first metal wiring layer is connected to the wiring 113h of the first metal wiring layer via the contact 114d. The wiring 113h of the first metal wiring layer is connected to the wiring 115m of the second metal wiring layer via the contact 114d. , 115m is supplied with a reference power source Vss. Further, lower diffusion layers 102nb of the first and second inverters constituting adjacent row selection decoders are commonly connected. In other words, the lower diffusion layers that are the sources of the four transistors of the NMOS transistors Tn11 and Tn12 of the adjacent inverters are connected in common, thereby reducing the area. Here, the wiring 115m of the second metal wiring layer to which the reference power is supplied extends in the direction perpendicular to the row direction.
The sources of the PMOS transistor Tp11 and the PMOS transistor Tp12 constituting the first and second inverters are respectively a lower diffusion layer 102pc and are commonly connected by the silicide layer 103, and are connected via the contact 112c (three in the figure) via the first contact 112c. The wiring 113j of the first metal wiring layer is connected to the wiring 115l of the second metal wiring layer via the contact 114e, and the power supply Vcc is supplied to 115l. . Further, the lower diffusion layers 102pc of the first and second inverters constituting the adjacent row selection decoders are commonly connected. That is, the lower diffusion layers that are the sources of the four transistors of the PMOS transistors Tp11 and Tp12 of the adjacent inverter are connected in common, and the reduction of the area is achieved. Here, the wiring 115l of the second metal wiring layer to which power is supplied extends in the direction perpendicular to the row direction.

The upper diffusion layer 107p11 serving as the drain of the PMOS transistor Tp11 is connected to the wiring 113i of the first metal wiring layer via the silicide layer 109p11 and the contact 110p11, and the wiring 113i of the first metal wiring layer is connected to the first inverter. Output N11. The upper diffusion layer 107n11 serving as the drain of the NMOS transistor Tn11 is connected to the wiring 113i of the first metal wiring layer through the silicide layer 109n11 and the contact 110n11. A gate wiring 106f is connected in common to the gate electrode 106 of the PMOS transistor Tp11 and the gate electrode 106 of the NMOS transistor Tn11, and a gate wiring 106e is connected to the gate electrode of the NMOS transistor Tn11. The output wiring 113b of the NOR decoder BL201A-7 which is the embodiment of FIG. 4, that is, DECOUT7 is input to the gate wiring 106e.
The upper diffusion layer 107p12 serving as the drain of the PMOS transistor Tp12 is connected to the wiring 113k of the first metal wiring layer through the silicide layer 109p12 and the contact 110p12, and 113k serves as the output WL7 of the row selection decoder BL200A-7. The upper diffusion layer 107n12 serving as the drain of the NMOS transistor Tn12 is connected to the wiring 113k of the first metal wiring layer through the silicide layer 109n12 and the contact 110n12. A gate wiring 106g is commonly connected to the gate electrode 106 of the PMOS transistor Tp12 and the gate electrode 106 of the NMOS transistor Tn12, and the wiring 113i of the first metal wiring layer, which is the output wiring of the first inverter, is connected to 106g. Connected.

In FIG. 6a, a row selection decoder BL200A-7 to which address selection signals XA7, XB0, and XC0 are input, a row decoder BL200A-8 to which address selection signals XA0, XB1, and XC0 are input, and address selection signals XA1, XB1, and XC0 are provided. The input row decoder BL200A-9 is adjacently arranged at a pitch (interval) Ly1, and the second metal that supplies the power supply Vcc is commonly used for BL200A-7, BL200A-8, and BL200A-9. Wiring layers 115g and 115l and second metal wiring layers 115c and 115m for supplying the reference power supply Vss are arranged, and second metals for supplying address selection signals XA0 to 7, XB0 to 3, and XC0 to 7 are arranged. All the wirings in the wiring layer are arranged at the minimum pitch of the wirings in the second metal wiring layer, and the first metal wiring is arranged. A layer of wirings 113e, 113f, via the 113 g, any address selection signals, respectively are connected to the input gate of the NOR type decoder.

According to this embodiment, the row selection decoder is composed of a NOR decoder and two inverters and has the same pitch as that of the SRAM and the minimum pitch of the second metal wiring layer, thereby minimizing the area. Can be provided.

Example 3
FIG. 7 shows an embodiment in which the row selection decoder of the present invention is connected to an SRAM cell in which MOS transistors are arranged in 2 rows and 3 columns.
A row selection decoder BL200, a region BLC (Block Connection) for connecting the row selection decoder and the SRAM cell, and an SRAM cell array are arranged.
In the region BLC, the wiring 113k of the first metal wiring layer, which is the output of the row selection decoder, is connected to the wiring 115n of the second metal wiring layer through the contact 114k, and further the third metal wiring through the contact 116a. 17 is connected. The third metal wiring 17 serves as a word line of the SRAM cell, and an arbitrary SRAM cell designated by the address signal can be selected by this row selection decoder. In the embodiment, as the SRAM cell shown in FIG. 19, M (7,0), M (8,0), M (9,0) are arranged in the column direction, and at the same pitch, the row selection decoder BL200A. -7, BL200A-8, and BL200A-9 are arranged adjacent to each other to constitute a row selection decoder for selecting an SRAM cell.

According to this embodiment, it is possible to provide a row selection decoder that is optimal for SRAM cells arranged in 2 rows and 3 columns.

Example 4
8a, 8b, 8c, 8d, 8e, 8f, 8g, 8h, 8i and 8j show a fourth embodiment. 8a is a plan view of the layout (arrangement) of the NOR decoder of the present invention, FIG. 8b is a cross-sectional view taken along the cut line AA ′ in FIG. 8a, and FIG. 8c is a cut line BB in FIG. 8d is a cross-sectional view along the cut line CC ′ in FIG. 8a, FIG. 8e is a cross-sectional view along the cut line DD ′ in FIG. 8a, and FIG. 8a is a cross-sectional view taken along the cut line EE ′, FIG. 8g is a cross-sectional view taken along the cut line FF ′ in FIG. 8a, and FIG. 8h is a cross-sectional view taken along the cut line GG ′ in FIG. FIG. 8i is a cross-sectional view taken along the cut line HH ′ in FIG. 8a, and FIG. 8j is a cross-sectional view taken along the cut line II ′ in FIG. 8a.
In this embodiment, the difference from FIG. 4a (embodiment 1) is that the NMOS transistors Tn1, Tn2, Tn3, the PMOS transistors Tp1, Tp2, and Tp3 have their sources and drains arranged upside down, and the NMOS transistors Tn1, Tn2 , Tn3 and the drains of the PMOS transistor Tp1 are connected in common through contacts.
In FIG. 8a, NMOS transistors Tn1, Tn2 and Tn3 of the NOR decoder of FIG. 3 are in the first row (upper row in the figure), and PMOS transistors Tp1, Tp2 and Tp3 are in the second row (lower row in the figure). They are arranged in order from the left side of the figure.
8a, 8b, 8c, 8d, 8e, 8f, 8g, 8h, 8i, and 8j, FIGS. 4a, 4b, 4c, 4d, 4e, and 4f. 4G, FIG. 4H and FIG. 4I are indicated by equivalent symbols in the 100s.

Planar silicon layers 102n, 102pa, and 102pb are formed on an insulating film such as a buried oxide film layer (BOX) 101 formed on the substrate. It is composed of an n + diffusion layer, a p + diffusion layer, and a p + diffusion layer. Reference numeral 103 denotes a silicide layer formed on the surface of the planar silicon layer (102n, 102pa, 102pb). 104p1, 104p2, and 104p3 are p-type silicon pillars, 104n1, 104n2, and 104n3 are n-type silicon pillars, 105 is a gate insulating film that surrounds the silicon pillars 104p1, 104p2, 104p3, 104n1, 104n2, and 104n3, 106 is a gate electrode, 106a, 106b, 106c, and 106d are gate wirings, respectively. N + diffusion layers 107n1, 107n2, and 107n3 are respectively formed on the uppermost portions of the silicon pillars 104p1, 104p2, and 104p3 by impurity implantation or the like, and p + diffusion layers 107p1 and 107p2 are formed on the uppermost portions of the silicon pillars 104n1, 104n2, and 104n3, respectively. 107p3 are formed by impurity implantation or the like. 108 is a silicon nitride film for protecting the gate insulating film 105, 109n1, 109n2, 109n3, 109p1, 109p2, and 109p3 are silicides connected to n + diffusion layers 107n1, 107n2, 107n3, and p + diffusion layers 107p1, 107p2, and 107p3, respectively. 110n1, 110n2, 110n3, 110p1, 110p2, and 110p3 include silicide layers 109n1, 109n2, 109n3, 109p1, 109p2, and 109p3 and

wirings

113b, 113b, 113b, 113b, 113d, and 113d of the first metal wiring layer. Contacts for connection, 111a is a contact for connecting the gate wiring 106a and the wiring 113g of the first metal wiring layer, and 111b is a wiring 1 of the gate wiring 106c and the first metal wiring layer. Contacts for connecting the 3f, 111c denotes a contact for connecting the wires 113e of the gate wiring 106d and the first metal wiring layer.
112a (five arrangements in the figure) is a contact for connecting the silicide layer 103 and the wiring 113a of the first metal wiring layer, which covers and connects the

lower diffusion layer

102n, and 112b is a connection which covers the lower diffusion layer 102pb. This contact connects the silicide layer 103 to be connected to the wiring 113c of the first metal wiring layer.

The silicon pillar 104p1, the lower diffusion layer 102n, the upper diffusion layer 107n1, the gate insulating film 105, and the gate electrode 106 constitute the NMOS transistor Tn1, and the silicon pillar 104p2, the lower diffusion layer 102n, the upper diffusion layer 107n2, the gate insulating film 105, The gate electrode 106 constitutes the NMOS transistor Tn2, and the silicon pillar 104p3, the lower diffusion layer 102n, the upper diffusion layer 107n3, the gate insulating film 105, and the gate electrode 106 constitute the NMOS transistor Tn3, and the silicon pillar 104n1 and the lower diffusion layer 102 pa, upper diffusion layer 107 p 1, gate insulating film 105, and gate electrode 106 constitute a PMOS transistor Tp 1, and silicon pillar 104 n 2, lower diffusion layer 102 pa, upper diffusion layer 107 p 2, gate insulating film 105, gate electrode 106 The gate electrode 106, constitutes a PMOS transistor Tp2, the silicon pillar 104N3, lower diffusion layer 102Pb, the upper diffusion layer 107P3, gate insulating film 105, the gate electrode 106, constituting the PMOS transistor Tp3.

The gate wiring 106d is connected to the gate electrodes 106 of the NMOS transistor Tn1 and the PMOS transistor Tp1, the gate wiring 106b is connected to the gate electrodes 106 of the NMOS transistor Tn2 and the PMOS transistor Tp2, and the gate electrode of the PMOS transistor Tp2. A gate line 106c is connected to 106, and a gate line 106a is connected to the gate electrodes 106 of the NMOS transistor Tn3 and the PMOS transistor Tp3.

The sources of the NMOS transistors Tn1, Tn2, and Tn3 are the lower diffusion layer 102n, which is connected to the wiring 113a of the first metal wiring layer through the silicide 103 and the contacts 112a (five in the figure), and the first metal wiring The layer wiring 113a is connected to the second metal wiring layer wiring 115d through a contact 114d, and a reference power source Vss is supplied to 115d. Here, the wiring 115d of the second metal wiring layer extends in a direction perpendicular to the row direction. Note that the wiring 113a of the first metal wiring layer extends in the row direction and supplies the power source Vss to the lower diffusion layer and the silicide 103, and the resistance of the silicide layer is almost negligible. The upper diffusion layer 107n1 which is the drain of the NMOS transistor Tn1 is connected to the wiring 113b of the first metal wiring layer via the silicide 109n1 and the contact 110n1, and the wiring 113b of the first metal wiring layer becomes the output DECOUT1. The upper diffusion layer 107n2 which is the drain of the NMOS transistor Tn2 is connected to the wiring 113b of the first metal wiring layer through the silicide 109n2 and the contact 110n2. The upper diffusion layer 107n3, which is the drain of the NMOS transistor Tn3, is connected to the wiring 113b of the first metal wiring layer via the silicide 109n3 and the contact 110n3. The upper diffusion layer 107p1 which is the drain of the PMOS transistor Tp1 is connected to the wiring 113b of the first metal wiring layer through the silicide 109p1 and the contact 110p1. Here, as described above, the drains of the NMOS transistors Tn1, Tn2, Tn3 and the PMOS transistor Tp1 are commonly connected to the wiring 113b of the first metal wiring layer through the contacts. The lower diffusion layer 102pa serving as the source of the PMOS transistor Tp1 is connected to the drain of the PMOS transistor Tp2 through the silicide layer 103. The upper diffusion layer 107p2 that is the source of the PMOS transistor Tp2 is connected to the wiring 113d of the first metal wiring layer through the silicide 109p2 and the contact 110p2. The upper diffusion layer 107p3, which is the drain of the PMOS transistor Tp3, is connected to the wiring 113d of the first metal wiring layer through the silicide 109p3 and the contact 110p3. Here, the source of the PMOS transistor Tp2 and the drain of the PMOS transistor Tp3 are connected via the wiring 113d of the first metal wiring layer. The source of the PMOS transistor Tp3 is connected to the wiring 113c of the first metal wiring layer through the lower diffusion layer 102pb, the silicide region 103, and the contact 112b, and the wiring 113c of the first metal wiring layer is further connected through the contact 114e. Are connected to the wiring 115c of the second metal wiring layer, and the power source Vcc is supplied to 115c. Here, the wiring 115c of the second metal wiring layer extends in a direction perpendicular to the row direction.

The gate wiring 106d to which any of the address selection signals XA0 to XA7 supplied by the wiring of the second metal wiring layer is input is connected to the wiring 113e of the first metal wiring layer through the contact 111c. The wiring 113e of the first metal wiring layer extends in a parallel direction (left side in the drawing) along the row. The wiring of the second metal wiring layer that supplies the address selection signals XA0 to XA7 extends in the direction perpendicular to the row direction, and the wiring of the first metal wiring layer that extends in parallel to the row direction. The contact 114c is arranged at any one of the intersections of the wirings of the second metal wiring layer for supplying the address selection signals XA0 to XA7 extending in the direction perpendicular to the row direction with the address 113e, and the address selection signal XAh The wiring of the second metal wiring layer that supplies (h = 0 to 7) is connected to the gate wiring 106d. In the figure, a contact 114c is provided at the intersection of the wiring 115j of the second metal wiring layer that supplies the address selection signal XA1 and the wiring 113e of the first metal wiring layer. That is, the address selection signal XA1 is input to the gates of the NMOS transistor Tn1 and the PMOS transistor Tp1 of the NOR decoder.
In this figure, the wiring of the second metal wiring layer that supplies the address selection signals XA2 to XA7 is omitted, but it has the same arrangement as the wiring of the second metal wiring layer that supplies the address selection signals XA0 and XA1. Further, it is arranged on the left side in a form perpendicular to the row direction.
Note that a contact 114z is drawn by a broken line at the intersection of the wiring 115i of the second metal wiring layer that supplies the address selection signal XA0 and the wiring 113e of the first metal wiring layer. There is no contact here, and if it is desired to input the wiring 115i of the second metal wiring layer that supplies the address selection signal XA0, the location of the fictitious contact in which a contact is provided here is set. Show. Hereinafter, the same is true for the other portions.

The gate wiring 106c to which any of the address selection signals XB0 to XB3 supplied by the wiring of the second metal wiring layer is input is connected to the wiring 113f of the first metal wiring layer through the contact 111b. The wiring 113f of the first metal wiring layer extends in a parallel direction (left side in the drawing) along the row. The wiring of the second metal wiring layer that supplies the address selection signals XB0 to XB3 extends in the direction perpendicular to the row direction, and is at one of the intersections with the wiring 113f of the first metal wiring layer. The contact 114b is arranged to connect the wiring of the second metal wiring layer that supplies the address selection signal XBi (i = 0 to 3) to the gate wiring 106c. In the figure, a contact 114b is provided at the intersection of the wiring 115e of the second metal wiring layer that supplies the address selection signal XB0 and the wiring 113f of the first metal wiring layer. That is, the selection address signal XB0 is input to the gates of the NMOS transistor Tn2 and the PMOS transistor Tp2 of this NOR decoder.
The second metal wiring layer 115f for supplying the address selection signal XB1, the second metal wiring layer 115g for supplying the address selection signal XB2, and the second metal wiring layer for supplying the address selection signal XB3. A contact 114z is drawn by a broken line at the intersection of the wiring 115h and the wiring 113f of the first metal wiring layer. However, as described above, there is no contact here, and the location of the fictitious contact is shown. Show.

The gate wiring 106a to which any of the address selection signals XC0 to XC7 supplied by the wiring of the second metal wiring layer is input is connected to the wiring 113g of the first metal wiring layer through the contact 111a. The wiring 113g of the first metal wiring layer extends in a parallel direction (right side in the drawing) along the row. The wiring of the second metal wiring layer that supplies the address selection signals XC0 to XC7 extends in a direction perpendicular to the row direction, and is at one of the intersections with the wiring 113g of the first metal wiring layer. The contact 114a is arranged to connect the wiring of the second metal wiring layer that supplies the address selection signal XCj (i = 0 to 7) to the gate wiring 106a. In the figure, a contact 114a is provided at the intersection of the wiring 115b of the second metal wiring layer that supplies the address selection signal XC0 and the wiring 113g of the first metal wiring layer. That is, the address selection signal XC0 is input to the gates of the NMOS transistor Tn3 and the PMOS transistor Tp3 of this NOR decoder.
Note that a contact 114z is drawn by a broken line at the intersection of the wiring 115a of the second metal wiring layer that supplies the address selection signal XC1 and the wiring 113g of the first metal wiring layer, as described above. Here, no contact exists, and the location of a fictitious contact is shown.
Note that the second metal wiring layer for supplying the address selection signals XC2 to XC7 is omitted for the convenience of the drawing, but, as with the second metal wiring layer for supplying the address selection signals XC0 and XC1, further to the right side. Are arranged in a direction perpendicular to the row direction.
According to this figure, address selection signals XA1, XB0, and XC0 are input to this NOR type decoder, and the output is DECOUT1 according to FIG.

The NOR type decoder BL201B is a region surrounded by a frame in the figure, and the vertical dimension is Ly2, which is smaller than the SRAM cell dimension Ly1 in FIG. The reason why Example 4 (FIG. 8) is smaller than the pitch (dimension) of Example 1 (FIG. 4) is that Example 1 is a dead space (area is taken) of the p + diffusion layer and the n + diffusion layer. Whereas there are two gaps in the pitch, there are only 1.5 places in the fourth embodiment, which can be reduced accordingly.

According to this embodiment, the power supply wiring, the reference power supply wiring, and the address selection signal line are the wirings of the second metal wiring layer, and the SGTMOS transistors constituting the NOR decoder are arranged in 2 rows and 3 columns. Connection between the input gate of the NOR decoder and the wiring of the second metal wiring layer through the wiring of the first metal wiring layer that extends in the vertical direction and is arranged in parallel along the row direction As a result, it becomes possible to supply an arbitrary address selection signal to the input of the NOR type decoder, which can be arranged at the minimum pitch of the wiring of the second metal wiring layer, and is smaller than a small SRAM having a small area. A row selection decoder can be realized with a small pitch.

(Example 5)
9a, 9b, 9c, 9d, 9e, 9f, 9g, 9h, 9i and 9j show a fifth embodiment. 9a is a plan view of the layout (arrangement) of the row selection decoder of the present invention, FIG. 9b is a sectional view taken along the cut line AA ′ in FIG. 9a, and FIG. 9c is a cut line BB in FIG. 9a. 9d is a cross-sectional view along the cut line CC ′ in FIG. 9a, FIG. 9e is a cross-sectional view along the cut line DD ′ in FIG. 9a, and FIG. 9a is a cross-sectional view taken along the cut line EE ′, FIG. 9g is a cross-sectional view taken along the cut line FF ′ in FIG. 9a, and FIG. 9h is a cross-sectional view taken along the cut line GG ′ in FIG. FIG. 9i is a cross-sectional view taken along the cut line HH ′ in FIG. 9a, and FIG. 9j is a cross-sectional view taken along the cut line II ′ in FIG. 9a.
The equivalent circuit diagram of this embodiment is obtained by integrating the NOR decoder 201k, the first inverter 202k, and the second inverter 203k in accordance with FIG. 5 to realize a smaller area.
In this embodiment, the difference from FIG. 8a (Embodiment 4) is for supplying power to the PMOS transistor Tp11 and NMOS transistor Tn11 constituting the first inverter and the PMOS transistor Tp12 and NMOS transistor Tn12 constituting the second inverter. By sharing the lower diffusion layer and the lower diffusion layer for supplying the reference power with the NOR decoder of FIG. 8, the useless area is reduced and the area is further reduced.
In FIG. 9a, the configuration on the left side of the wiring 115b of the second metal wiring layer constituting the NOR type decoder is the same as that of FIG. 8 except that the signals supplied to the

wirings

115b, 115c, 115d of the second metal wiring layer are different. Is the same. The

first inverters

202k and 203k are continuously arranged on the right side of the wiring 115a of the second metal wiring layer, sharing the lower diffusion layer.
9a, 9b, 9c, 9d, 9e, 9f, 9g, 9h, 9i, and 9j, FIGS. 8a, 8b, 8c, 8d, 8e, and 8f. 8G, FIG. 8H, FIG. 8I, and FIG. 8J are indicated by equivalent symbols in the 100s.
Although not shown, in the present embodiment, the allocation of the address signal for distributing the address signal to each decoder is changed from the distribution in FIG. That is, in FIG. 1, the address signals A0 to A2 are assigned to the predecoder 300A, A3 to A4 are assigned to 300B, and A5 to A7 are assigned to 300C. However, in this embodiment, the address signal is sent to 300A due to the arrangement of the address selection signal lines. A3 to A5 are assigned to A0 to A2 and 300B, and A6 to A7 are assigned to 300C.
As a result, the number of address selection signal lines is 8 for XAh (h = 0 to 7), 8 for XBi (i = 0 to 7), and 4 for XCj (j = 0 to 3).

Planar silicon layers 102n, 102pa, and 102pb are formed on an insulating film such as a buried oxide film layer (BOX) 101 formed on the substrate. It is composed of an n + diffusion layer, a p + diffusion layer, and a p + diffusion layer. Reference numeral 103 denotes a silicide layer formed on the surface of the planar silicon layer (102n, 102pa, 102pb). 104p1, 104p2, 104p3, 104p11, 104p12 are p-type silicon pillars, 104n1, 104n2, 104n3, 104n11, 104n12 are n-type silicon pillars, 105 are silicon pillars 104p1, 104p2, 104p3, 104p11, 104p12, 104n1, 104n2, 104n3, Gate insulating films surrounding 104n11 and 104n12, 106 is a gate electrode, 106a, 106b, 106c, 106d, 106e, 106f and 106g are gate wirings, respectively. At the top of the silicon pillars 104p1, 104p2, 104p3, 104p11, 104p12, n + diffusion layers 107n1, 107n2, 107n3, 107n11, 107n12 are formed by impurity implantation or the like, and the silicon pillars 104n1, 104n2, 104n3, 104n11, 104n12 On the top, p + diffusion layers 107p1, 107p2, 107p3, 107p11, and 107p12 are formed by impurity implantation or the like, respectively. 108 is a silicon nitride film for protecting the gate insulating film 105, 109n1, 109n2, 109n3, 109n11, 109n12, 109p1, 109p2, 109p3, 109p11, 109p12 are n + diffusion layers 107n1, 107n2, 107n3, 107n11, 107n12, p +, respectively. Silicide layers connected to the diffusion layers 107p1, 107p2, 107p3, 107p11, 107p12, 110n1, 110n2, 110n3, 110n11, 110n12, 110p1, 110p2, 110p3, 110p11, 110p12 are silicide layers 109n1, 109n2, 109n3, 109n11, 109n12 , 109p1, 109p2, 109p3, 109p11, 109p12 and the wiring 113 of the first

metal wiring layer

113b, 113b, 113h, 113i, 113b, 113d, 113d, 113h, and 113i, 111a is a contact that connects the gate wiring 106a and the wiring 113g of the first metal wiring layer, and 111b is a gate wiring 106c. A contact connecting the wiring 113f of the first metal wiring layer, 111c is a contact connecting the gate wiring 106d and the wiring 113e of the first metal wiring layer, and 111d is a wiring connecting the gate wiring 106f and the wiring 113b of the first metal wiring layer. A contact 111e is a contact for connecting the gate wiring 106g and the wiring 113h of the first metal wiring layer.
112a (nine in the figure) is a contact for connecting the silicide layer 103 connected to cover the lower diffusion layer 102n and the wiring 113a of the first metal wiring layer, and 112b (five in the figure) is a lower part. This is a contact for connecting the silicide layer 103 connected to cover the diffusion layer 102pb and the wiring 113c of the first metal wiring layer.

The silicon pillar 104p1, the lower diffusion layer 102n, the upper diffusion layer 107n1, the gate insulating film 105, and the gate electrode 106 constitute the NMOS transistor Tn1, and the silicon pillar 104p2, the lower diffusion layer 102n, the upper diffusion layer 107n2, the gate insulating film 105, The gate electrode 106 constitutes the NMOS transistor Tn2, and the silicon pillar 104p3, the lower diffusion layer 102n, the upper diffusion layer 107n3, the gate insulating film 105, and the gate electrode 106 constitute the NMOS transistor Tn3, and the silicon pillar 104p11, the lower diffusion layer. 102n, the upper diffusion layer 107n11, the gate insulating film 105, and the gate electrode 106 constitute an NMOS transistor Tn11. The silicon pillar 104p12, the lower diffusion layer 102n, the upper diffusion layer 107n12, and the gate insulating film 10 The gate electrode 106 constitutes the NMOS transistor Tn12, and the silicon pillar 104n1, the lower diffusion layer 102pa, the upper diffusion layer 107p1, the gate insulating film 105, and the gate electrode 106 constitute the PMOS transistor Tp1, and the silicon pillar 104n2 and the lower diffusion. The layer 102pa, the upper diffusion layer 107p2, the gate insulating film 105, and the gate electrode 106 constitute the PMOS transistor Tp2, and the silicon pillar 104n3, the lower diffusion layer 102pb, the upper diffusion layer 107p3, the gate insulating film 105, and the gate electrode 106 constitute the PMOS. The transistor Tp3 is configured, and the silicon pillar 104n11, the lower diffusion layer 102pb, the upper diffusion layer 107p11, the gate insulating film 105, and the gate electrode 106 constitute the PMOS transistor Tp11, and the silicon pillar 04N12, lower diffusion layer 102Pb, the upper diffusion layer 107P12, a gate insulating film 105, the gate electrode 106, constituting the PMOS transistor Tp12.

A gate wiring 106d is connected to the gate electrodes 106 of the NMOS transistor Tn1 and the PMOS transistor Tp1. A gate line 106b is connected to the gate electrodes 106 of the NMOS transistor Tn2 and the PMOS transistor Tp2, and a gate line 106c is connected to the gate electrode 106 of the PMOS transistor Tp2. A gate wiring 106a is connected to the gate electrodes 106 of the NMOS transistor Tn3 and the PMOS transistor Tp3. A gate wiring 106e is connected to the gate electrode 106 of the NMOS transistor Tn11 and the PMOS transistor Tp11, and a gate wiring 106f is connected to the gate electrode 106 of the NMOS transistor Tn11. A gate wiring 106g is connected to the gate electrodes 106 of the NMOS transistor Tn12 and the PMOS transistor Tp12.

The sources of the NMOS transistors Tn1, Tn2, Tn3, Tn11, and Tn12 are all shared to form the lower diffusion layer 102n, and the wiring 113a of the first metal wiring layer is formed through the silicide 103 and the contacts 112a (nine in the drawing). The wiring 113a of the first metal wiring layer is connected to the wiring 115k of the second metal wiring layer via the contact 114d, and the reference power source Vss is supplied to 115k. Here, the wiring 115k of the second metal wiring layer extends in a direction perpendicular to the row direction. Note that the wiring 113a of the first metal wiring layer extends along the row direction and supplies the reference power source Vss to the silicide layer 103 and the lower diffusion layer 102n, and the resistance of the silicide layer is almost negligible. The sources of the PMOS transistors Tp3, Tp11, and Tp12 are all shared to form the lower diffusion layer 102pb, and are connected to the wiring 113c of the first metal wiring layer through the silicide 103 and the contacts 112b (five in the drawing). Then, the wiring 113c of the first metal wiring layer is connected to the wiring 115l of the second metal wiring layer through the contact 114e, and the power source Vcc is supplied to 115l. Here, the wiring 115l of the second metal wiring layer extends in a direction perpendicular to the row direction. Note that the wiring 113c of the first metal wiring layer extends along the row direction and supplies the power Vcc to the silicide layer 103 and the lower diffusion layer 102pb, and the resistance of the silicide layer can be almost ignored.

The upper diffusion layer 107n1 which is the drain of the NMOS transistor Tn1 is connected to the wiring 113b of the first metal wiring layer via the silicide 109n1 and the contact 110n1, and the wiring 113b of the first metal wiring layer is connected to the output DECOUT1 (not shown). Become. The upper diffusion layer 107n2 which is the drain of the NMOS transistor Tn2 is connected to the wiring 113b of the first metal wiring layer through the silicide 109n2 and the contact 110n2. The upper diffusion layer 107n3, which is the drain of the NMOS transistor Tn3, is connected to the wiring 113b of the first metal wiring layer via the silicide 109n3 and the contact 110n3. The upper diffusion layer 107p1 which is the drain of the PMOS transistor Tp1 is connected to the wiring 113b of the first metal wiring layer through the silicide 109p1 and the contact 110p1. Here, as described above, the drains of the NMOS transistors Tn1, Tn2, Tn3 and the PMOS transistor Tp1 are commonly connected to the wiring 113b of the first metal wiring layer through the contacts. The lower diffusion layer 102pa serving as the source of the PMOS transistor Tp1 is connected to the drain of the PMOS transistor Tp2 through the silicide layer 103. The upper diffusion layer 107p2 that is the source of the PMOS transistor Tp2 is connected to the wiring 113d of the first metal wiring layer through the silicide 109p2 and the contact 110p2. The upper diffusion layer 107p3, which is the drain of the PMOS transistor Tp3, is connected to the wiring 113d of the first metal wiring layer through the silicide 109p3 and the contact 110p3. Here, the source of the PMOS transistor Tp2 and the drain of the PMOS transistor Tp3 are connected via the wiring 113d of the first metal wiring layer. Further, as described above, the source of the PMOS transistor Tp3 is the lower diffusion layer 102pb.

The upper diffusion layer 107n11 and the upper diffusion layer 107p11 which are the drains of the NMOS transistor Tn11 and the PMOS transistor Tp11 constituting the first inverter are respectively connected to the first metal wiring via the silicide 109n11 and the contact 110n11 or the silicide layer 109p11 and the contact 110p11. It is commonly connected to the wiring 113h of the layer, and 113h becomes an output of the first inverter. Further, the wiring 113b of the first metal wiring layer, which is the output of the NOR decoder, is connected to the gate wiring 106f commonly connected to the gate electrodes of the NMOS transistor Tn11 and the PMOS transistor Tp11 via the gate wiring 106e. .
The upper diffusion layer 107n12 and the upper diffusion layer 107p12 which are the drains of the NMOS transistor Tn12 and the PMOS transistor Tp12 constituting the second inverter are respectively connected to the first metal wiring through the silicide 109n12 and the contact 110n12 or the silicide layer 109p12 and the contact 110p12. Commonly connected to the

layer wiring

113i, 113i becomes the output WL1 of this row selection decoder. Further, the wiring 113h of the first metal wiring layer, which is the output of the first inverter, is connected to the gate wiring 106g commonly connected to the gate electrodes of the NMOS transistor Tn12 and the PMOS transistor Tp12.

The gate wiring 106d to which any of the address selection signals XA0 to XA7 supplied by the wiring of the second metal wiring layer is input is connected to the wiring 113e of the first metal wiring layer through the contact 111c. The wiring 113e of the first metal wiring layer extends in a parallel direction (left side in the drawing) along the row. The wiring of the second metal wiring layer that supplies the address selection signals XA0 to XA7 extends in the direction perpendicular to the row direction, and the wiring of the first metal wiring layer that extends in parallel to the row direction. The contact 114c is arranged at any one of the intersections of the wirings of the second metal wiring layer for supplying the address selection signals XA0 to XA7 extending in the direction perpendicular to the row direction with the address 113e, and the address selection signal XAh The wiring of the second metal wiring layer that supplies (h = 0 to 7) is connected to the gate wiring 106d. In the figure, a contact 114c is provided at the intersection of the wiring 115j of the second metal wiring layer that supplies the address selection signal XA1 and the wiring 113e of the first metal wiring layer. That is, the address selection signal XA1 is input to the gates of the NMOS transistor Tn1 and the PMOS transistor Tp1 of this row selection decoder.
In this figure, the wiring of the second metal wiring layer that supplies the address selection signals XA2 to XA7 is omitted, but it has the same arrangement as the wiring of the second metal wiring layer that supplies the address selection signals XA0 and XA1. Further, it is arranged on the left side in a form perpendicular to the row direction.
Note that a contact 114z is drawn by a broken line at the intersection of the wiring 115i of the second metal wiring layer that supplies the address selection signal XA0 and the wiring 113e of the first metal wiring layer. There is no contact here, and if it is desired to input the wiring 115i of the second metal wiring layer that supplies the address selection signal XA0, the location of the fictitious contact in which a contact is provided here is set. Show. Hereinafter, the same is true for the other portions.

The gate wiring 106c to which any of the address selection signals XB0 to XB7 supplied by the wiring of the second metal wiring layer is input is connected to the wiring 113f of the first metal wiring layer through the contact 111b. The wiring 113f of the first metal wiring layer extends in a parallel direction (left side in the drawing) along the row. The wiring of the second metal wiring layer that supplies the address selection signals XB0 to XB7 extends in a direction perpendicular to the row direction, and is at one of the intersections with the wiring 113e of the first metal wiring layer. The contact 114b is arranged to connect the wiring of the second metal wiring layer that supplies the address selection signal XBi (i = 0 to 7) to the gate wiring 106c. In the figure, a contact 114b is provided at the intersection of the wiring 115e of the second metal wiring layer that supplies the address selection signal XB0 and the wiring 113f of the first metal wiring layer. That is, the address selection signal XB0 is input to the gates of the NMOS transistor Tn2 and the PMOS transistor Tp2 of this row selection decoder.
In this figure, the wiring of the second metal wiring layer that supplies the address selection signals XB4 to XB7 is omitted, but the arrangement is the same as the wiring of the second metal wiring layer that supplies the address selection signals XB0 to XB3. Further, it is arranged on the left side in a form perpendicular to the row direction.
The address selection signal XB1 (second metal wiring layer wiring 115f), the address selection signal XB2 (second metal wiring layer wiring 115g), and the address selection signal XB3 (second metal wiring layer wiring 115h) A contact 114z is drawn by a broken line at the intersection with the wiring 113f of the first metal wiring layer. However, as described above, there is no contact here, and an imaginary contact location is shown. .

The gate wiring 106a to which any one of the address selection signals XC0 to XC3 supplied by the wiring of the second metal wiring layer is input is connected to the wiring 113g of the first metal wiring layer through the contact 111a. The wiring 113g of the first metal wiring layer extends in a parallel direction (right side in the drawing) along the row. The address selection signals XC0 to XC3 extend in a direction perpendicular to the row direction, and a contact 114a is arranged at any one of intersections with the wiring 113g of the first metal wiring layer, so that the address selection signal XCj (I = 0 to 3) is connected to the gate wiring 106a. In the figure, a contact 114a is provided at the intersection of the wiring 115d of the second metal wiring layer of the address selection signal XC0 and the wiring 113g of the first metal wiring layer. That is, the address selection signal XC0 is input to the gates of the NMOS transistor Tn3 and the PMOS transistor Tp3 of this row selection decoder.
The address selection signals XC1 (second metal wiring layer wiring 115c), XC2 (second metal wiring layer wiring 115b), XC3 (second metal wiring layer wiring 115a) and the first metal wiring layer Although the contact 114z is drawn with a broken line at each intersection with the wiring 113g, as described above, there is no contact here, and an imaginary contact is shown.
In this embodiment, address selection signals XA1, XB0, and XC0 are input and WL1 is selected as the row selection signal.
The row selection decoder BL200B is an area surrounded by a frame in the figure, and the vertical dimension is Ly2 which is the same as that in FIG.

According to this embodiment, the NOR type decoder and the first and second inverters are integrated and the SGTMOS transistors constituting them are arranged in 2 rows and 5 columns in the direction perpendicular to the row direction. The input gate of the NOR decoder is arranged via the wiring of the second metal wiring layer and the wiring of the second metal wiring layer, and the wiring of the first metal wiring layer arranged in parallel along the row direction. By connecting the second metal wiring layer to the wiring of the second metal wiring layer, it becomes possible to supply an arbitrary address selection signal to the input of the NOR type decoder, and it is arranged at the minimum wiring pitch of the second metal wiring layer. And a selection decoder with reduced area is provided.
Further, the silicide layer 103 covering the lower diffusion layer 102n serving as the source region of the NMOS transistors Tn1, Tn2, Tn3, Tn11, and Tn12 is a similar row selection decoder in an inverted arrangement adjacent to the upper side of the row selection decoder BL200B in FIG. 9a. Since it is connected in common to the silicide region covering the source region of the NMOS transistor (not shown) and connected to the reference power supply line, it is possible to reduce a region for wasteful reference power supply and to reduce the area.
Further, the silicide layer 103 covering the lower diffusion layer 102pb serving as the source regions of the PMOS transistors Tp3, Tp11, and Tp12 is a PMOS transistor of a similar row selection decoder arranged in an inverted manner adjacent to the lower side of the row selection decoder BL200B in FIG. 9a. Since it is connected to the power source line in common with the silicide region covering the source region, it is possible to reduce a region for wasteful power supply and further reduce the area.

(Example 6)
FIG. 10 shows still another semiconductor memory device including SRAM cells. The difference from FIG. 1 is that the row selection decoder is constituted by a 4-input NOR type decoder. The difference from FIG. 1 is a row selection decoder 210 and a predecoder 310 that generates an address selection signal.
The row address signal assignment is the same as A0 to A7, and the number of word lines is 256. Therefore, four types of

predecoders

310A, 310B, 310C, and 310D are provided in correspondence with 4-input NOR. 310A receives address signals A0 to A1 and outputs address selection signals XA0 to XA3. 310B receives address signals A2 to A3 and outputs address selection signals XB0 to XB3. 310C receives address signals A4 to A5 and outputs address selection signals XC0 to XC3. 310D receives address signals A6 to A7 and outputs address selection signals XD0 to XD3. The 4-input NOR type decoder 211 receives one signal for each of the groups of address selection signals A0 to XA3, XB0 to XB3, XC0 to XC3, and XD0 to XD3. For example, XA1, XB0, XC0, and XD0 are connected to the NOR decoder 211 that outputs DECOUT1. The number of address selection signals in FIG. 1 is 8 for the XA group, 4 for the XB group, and 8 for the XC group, and a total of 20 wires are required. In the embodiment of FIG. The address selection signals of the XA group are 4, the XB group is 4, the XC group is 4, and the XD group is 4, which can be realized with a total of 16 wires.

FIG. 11 shows a selection operation table of the row selection decoder similar to FIG. When a circled address selection signal is input to the NOR decoder 211, the corresponding output DECOUTk is selected.

FIG. 12 shows a NOR decoder 211-k of the present invention.
Tn1, Tn2, Tn3, and Tn4 are NMOS transistors configured by SGT, and Tp1, Tp2, Tp3, and Tp4 are PMOS transistors that are also configured by SGT. The sources of the NMOS transistors Tn1, Tn2, Tn3, and Tn4 are connected to the reference power supply Vss, and the drains are commonly connected to the node N1. The node N1 becomes the output DECOUTk. The drain of the PMOS transistor Tp1 is connected to the node N1, the source is connected to the drain of the PMOS transistor Tp2 via the node N2, and the source of the PMOS transistor Tp2 is connected to the drain of the PMOS transistor Tp3 via the node N3. The source of Tp3 is connected to the drain of the PMOS transistor Tp4 via the node N4, and the source of the PMOS transistor Tp4 is connected to the power supply Vcc. An input signal XAg (g = 0 to 3) is input to the gates of the NMOS transistor Tn1 and the PMOS transistor Tp1, and an input signal XBh (h = 0 to 3) is input to the gates of the NMOS transistor Tn2 and the PMOS transistor Tp2. The input signal XCi (i = 0 to 3) is input to the gates of the NMOS transistor Tn3 and the PMOS transistor Tp3, and the input signal XDj (j = 0 to 3) is connected to the gates of the NMOS transistor Tn4 and the PMOS transistor Tp4. Is done.

A sixth embodiment is shown in FIGS. 13a, 13b, 13c, 13d and 13e. 13a is a plan view of the layout (arrangement) of the NOR decoder according to the present invention, FIG. 13b is a sectional view taken along the cut line AA ′ in FIG. 13a, and FIG. 13c is a cut line BB in FIG. 13d is a cross-sectional view along the cut line CC ′ in FIG. 13a, and FIG. 13e is a cross-sectional view along the cut line DD ′ in FIG. 13a.
An NMOS transistor Tn4 and a PMOS transistor Tp4 are additionally arranged on the right side of the plan view of the layout (arrangement) of the 3-input NOR type decoder in FIG. 8a. The structure and arrangement of the NMOS transistors Tn1, Tn2, Tn3 and the PMOS transistors Tp1, Tp2, Tp3 are the same as those in FIG. In FIG. 13, since the NMOS transistor Tn4 and the PMOS transistor Tp4 are arranged on the right side, the arrangement location of the address selection signal by the wiring of the second metal wiring layer and the connection method are partially different.
In FIGS. 13a, 13b, 13c, 13d, and 13e, the same structure as in FIGS. 8a, 8b, 8c, 8d, 8e, 8f, 8g, 8h, and 8i is shown. Are indicated by equivalent symbols in the 100s.

Planar silicon layers 102n, 102pa, and 102pb are formed on an insulating film such as a buried oxide film layer (BOX) 101 formed on the substrate. It is composed of an n + diffusion layer, a p + diffusion layer, and a p + diffusion layer. Reference numeral 103 denotes a silicide layer formed on the surface of the planar silicon layer (102n, 102pa, 102pb). 104p1, 104p2, 104p3, 104p4 are p-type silicon pillars, 104n1, 104n2, 104n3, 104n4 are n-type silicon pillars, 105 is a silicon pillar 104p1, 104p2, 104p3, 104p4, 104n1, 104n2, 104n3, 104n4. , 106 are gate electrodes, and 106a, 106b, 106c, 106d, 106e, and 106f are gate wirings, respectively. N + diffusion layers 107n1, 107n2, 107n3, and 107n4 are formed by impurity implantation or the like on the uppermost portions of the silicon pillars 104p1, 104p2, 104p3, and 104p4, respectively. The p + diffusion layers 107p1, 107p2, 107p3, and 107p4 are formed by impurity implantation or the like. 108 is a silicon nitride film for protecting the gate insulating film 105, 109n1, 109n2, 109n3, 109n4, 109p1, 109p2, 109p3, 109p4 are n + diffusion layers 107n1, 107n2, 107n3, 107n4, p + diffusion layers 107p1, 107p2, The silicide layers connected to 107p3 and 107p4, 110n1, 110n2, 110n3, 110n4, 110p1, 110p2, 110p3, and 110p4 are silicide layers 109n1, 109n2, 109n3, 109n4, 109p1, 109p2, 109p3, and 109p4 and the first metal

wiring Layer wirings

113b, 113b, 113b, 113b, 113b, 113d, 113d, 113c are respectively connected to contacts, and 111c is a gate wiring 106. 111b is a contact connecting the gate wiring 106c and the first

metal wiring layer

113f, 111a is a contact connecting the gate wiring 106e and the first metal wiring layer 113g. 111d is a contact for connecting the gate wiring 106f and the wiring 113h of the first metal wiring layer.
Reference numeral 112a (seven in the figure) denotes a contact for connecting the silicide layer 103 connected to cover the lower diffusion layer 102n and the wiring 113a of the first metal wiring layer.

The silicon pillar 104p1, the lower diffusion layer 102n, the upper diffusion layer 107n1, the gate insulating film 105, and the gate electrode 106 constitute the NMOS transistor Tn1, and the silicon pillar 104p2, the lower diffusion layer 102n, the upper diffusion layer 107n2, the gate insulating film 105, The gate electrode 106 constitutes the NMOS transistor Tn2, and the silicon pillar 104p3, the lower diffusion layer 102n, the upper diffusion layer 107n3, the gate insulating film 105, and the gate electrode 106 constitute the NMOS transistor Tn3, and the silicon pillar 104p4, the lower diffusion layer. 102n, the upper diffusion layer 107n4, the gate insulating film 105, and the gate electrode 106 constitute the NMOS transistor Tn4. The silicon pillar 104n1, the lower diffusion layer 102pa, the upper diffusion layer 107p1, the gate insulating film 105, the gate electrode The electrode 106 constitutes the PMOS transistor Tp1, and the silicon pillar 104n2, the lower diffusion layer 102pa, the upper diffusion layer 107p2, the gate insulating film 105, and the gate electrode 106 constitute the PMOS transistor Tp2, and the silicon pillar 104n3 and the lower diffusion layer 102pb. The upper diffusion layer 107p3, the gate insulating film 105, and the gate electrode 106 constitute a PMOS transistor Tp3. The silicon pillar 104n4, the lower diffusion layer 102pb, the upper diffusion layer 107p4, the gate insulating film 105, and the gate electrode 106 constitute the PMOS transistor Tp4. Configure.

A gate wiring 106d is connected to the gate electrodes 106 of the NMOS transistor Tn1 and the PMOS transistor Tp1. A gate line 106b is connected to the gate electrodes 106 of the NMOS transistor Tn2 and the PMOS transistor Tp2, and a gate line 106c is connected to the gate electrode 106 of the PMOS transistor Tp2. A gate wiring 106a is connected to the gate electrode 106 of the NMOS transistor Tn3 and the PMOS transistor Tp3, and a gate wiring 106e is connected to the gate electrode 106 of the PMOS transistor Tp3. A gate wiring 106f is connected to the gate electrodes 106 of the NMOS transistor Tn4 and the PMOS transistor Tp4.

The sources of the NMOS transistors Tn1, Tn2, Tn3, and Tn4 are the lower diffusion layer 102n, and are connected to the wiring 113a of the first metal wiring layer through the silicide 103 and the contacts 112a (seven in the drawing), The wiring 113a of the metal wiring layer is connected to the wiring 115d of the second metal wiring layer through the contact 114e, and the reference power source Vss is supplied to 115d. Here, the wiring 115d of the second metal wiring layer extends in a direction perpendicular to the row direction. Note that the wiring 113a of the first metal wiring layer extends in the row direction and supplies the reference power source Vss to the lower diffusion layer and the silicide 103, and the resistance of the silicide layer is almost negligible. The upper diffusion layer 107n1 which is the drain of the NMOS transistor Tn1 is connected to the wiring 113b of the first metal wiring layer via the silicide 109n1 and the contact 110n1, and the wiring 113b of the first metal wiring layer becomes the output DECOUT4. The upper diffusion layer 107n2 which is the drain of the NMOS transistor Tn2 is connected to the wiring 113b of the first metal wiring layer through the silicide 109n2 and the contact 110n2. The upper diffusion layer 107n3 which is the drain of the NMOS transistor Tn3 is connected to the wiring 113b of the first metal wiring layer through the silicide 109n3 and the contact 110n3. The upper diffusion layer 107n4 which is the drain of the NMOS transistor Tn4 is connected to the wiring 113b of the first metal wiring layer through the silicide 109n4 and the contact 110n4. The upper diffusion layer 107p1 which is the drain of the PMOS transistor Tp1 is connected to the wiring 113b of the first metal wiring layer through the silicide 109p1 and the contact 110p1. Here, as described above, the drains of the NMOS transistors Tn1, Tn2, Tn3, Tn4 and the PMOS transistor Tp1 are commonly connected to the wiring 113b of the first metal wiring layer through the contacts. The lower diffusion layer 102pa serving as the source of the PMOS transistor Tp1 is connected to the drain of the PMOS transistor Tp2 through the silicide layer 103. The upper diffusion layer 107p2 that is the source of the PMOS transistor Tp2 is connected to the wiring 113d of the first metal wiring layer through the silicide 109p2 and the contact 110p2. The upper diffusion layer 107p3, which is the drain of the PMOS transistor Tp3, is connected to the wiring 113d of the first metal wiring layer through the silicide 109p3 and the contact 110p3. Here, the source of the PMOS transistor Tp2 and the drain of the PMOS transistor Tp3 are connected via the wiring 113d of the first metal wiring layer. The source of the PMOS transistor Tp3 is connected to the drain of the PMOS transistor Tp4 via the lower diffusion layer 102pb and the silicide region 103, and the source of the PMOS transistor Tp4 is the first metal via the upper diffusion layer 107p4, the silicide 109p4 and the contact 110p4. Connected to the wiring 113c of the wiring layer, the wiring 113c of the first metal wiring layer is further connected to the wiring 115a of the second metal wiring layer via the contact 114p4, and the power supply Vcc is supplied to 115a. Here, the wiring 115a of the second metal wiring layer extends in a direction perpendicular to the row direction.

The gate wiring 106d to which any one of the address selection signals XA0 to XA3 supplied by the wiring of the second metal wiring layer is connected is connected to the wiring 113e of the first metal wiring layer through the contact 111c. The wiring 113e of the first metal wiring layer extends in a parallel direction (left side in the drawing) along the row. The wiring of the second metal wiring layer that supplies the address selection signals XA0 to XA3 extends in the direction perpendicular to the row direction, and the wiring of the first metal wiring layer that extends in parallel to the row direction. A contact 114c is arranged at any one of the intersections of the wirings of the second metal wiring layer that supplies the selection address signals XA0 to XA3 extending in the direction perpendicular to the row direction to the address 113e, and the address selection signal XAh The wiring of the second metal wiring layer that supplies (h = 0 to 3) is connected to the gate wiring 106d. In the figure, a contact 114c is provided at the intersection of the wiring 115i of the second metal wiring layer that supplies the address selection signal XA0 and the wiring 113e of the first metal wiring layer. That is, the address selection signal XA0 is input to the gates of the NMOS transistor Tn1 and the PMOS transistor Tp1 of this NOR decoder.
In this figure, the wiring of the second metal wiring layer that supplies the address selection signals XA2 to XA3 is omitted, but it has the same arrangement as the wiring of the second metal wiring layer that supplies the address selection signals XA0 and XA1. Further, it is arranged on the left side in a form perpendicular to the row direction.
Note that a contact 114z is drawn by a broken line at the intersection of the wiring 115j of the second metal wiring layer that supplies the address selection signal XA1 and the wiring 113e of the first metal wiring layer. There is no contact here, and if it is desired to input the wiring 115j of the second metal wiring layer that supplies the address selection signal XA1, the location of the fictitious contact in which a contact is provided here is provided. Show.

The gate wiring 106c to which any of the address selection signals XB0 to XB3 supplied by the wiring of the second metal wiring layer is input is connected to the wiring 113f of the first metal wiring layer through the contact 111b. The wiring 113f of the first metal wiring layer extends in a parallel direction (left side in the drawing) along the row. The wiring of the second metal wiring layer that supplies the address selection signals XB0 to XB3 extends in the direction perpendicular to the row direction, and is at one of the intersections with the wiring 113f of the first metal wiring layer. The contact 114b is arranged to connect the wiring of the second metal wiring layer that supplies the address selection signal XBi (i = 0 to 3) to the gate wiring 106c. In the figure, a contact 114b is provided at the intersection of the wiring 115f of the second metal wiring layer that supplies the address selection signal XB1 and the wiring 113f of the first metal wiring layer. That is, the address selection signal XB1 is input to the gates of the NMOS transistor Tn2 and the PMOS transistor Tp2 of the NOR decoder.
Note that the intersection of the wiring 115g of the second metal wiring layer that supplies the address selection signal XB2 and the wiring 115h of the second metal wiring layer that supplies the address selection signal XB3 and the wiring 113f of the first metal wiring layer Although the contact 114z is drawn by a broken line, as described above, there is no contact here, and an imaginary contact location is shown.

The gate wiring 106e to which any of the address selection signals XC0 to XC3 supplied by the wiring of the second metal wiring layer is input is connected to the wiring 113g of the first metal wiring layer via the contact 111a. The wiring 113g of the first metal wiring layer extends in a parallel direction (right side in the drawing) along the row. The wiring of the second metal wiring layer that supplies the address selection signals XC0 to XC3 extends in the direction perpendicular to the row direction, and is at one of the intersections with the wiring 113g of the first metal wiring layer. A contact 114a is arranged to connect the wiring of the second metal wiring layer that supplies the address selection signal XCj (i = 0 to 3) to the gate wiring 106e. In the figure, a contact 114a is provided at the intersection of the wiring 115c of the second metal wiring layer that supplies the address selection signal XC0 and the wiring 113g of the first metal wiring layer. That is, the address selection signal XC0 is input to the gates of the NMOS transistor Tn3 and the PMOS transistor Tp3 of this NOR decoder.
Wiring 115b of the second metal wiring layer that supplies the address selection signal XC1, wiring 115p of the second metal wiring layer that supplies the address selection signal XC2, and wiring 115q of the second metal wiring layer that supplies the address selection signal XC3 The contact 114z is drawn by a broken line at the intersection of the first metal wiring layer and the wiring 113g of the first metal wiring layer. However, as described above, there is no contact here, and the location of the fictitious contact is shown. Yes.

The gate wiring 106f to which any of the address selection signals XD0 to XD3 supplied by the wiring of the second metal wiring layer is input is connected to the wiring 113h of the first metal wiring layer through the contact 111d. The wiring 113h of the first metal wiring layer extends in a parallel direction (right side in the drawing) along the row. The wiring of the second metal wiring layer that supplies the address selection signals XD0 to XD3 extends in the direction perpendicular to the row direction, and the wiring of the first metal wiring layer that extends in parallel to the row direction. A contact 114d is arranged at any one of the intersections of the wirings of the second metal wiring layer for supplying the address selection signals XD0 to XD3 extending in the direction perpendicular to the row direction with respect to 113h, and the address selection signal XDj The wiring of the second metal wiring layer that supplies (j = 0 to 3) is connected to the gate wiring 106f. In the figure, a contact 114d is provided at the intersection of the wiring 115r of the second metal wiring layer that supplies the address selection signal XD0 and the wiring 113h of the first metal wiring layer. That is, the address selection signal XD0 is input to the gates of the NMOS transistor Tn4 and the PMOS transistor Tp4 of this NOR decoder.
In this figure, the wiring of the second metal wiring layer that supplies the address selection signals XD2 to XD3 is omitted, but it has the same arrangement as the wiring of the second metal wiring layer that supplies the address selection signals XD0 and XD1. Further, it is arranged on the right side in a form perpendicular to the row direction.
Note that a contact 114z is drawn by a broken line at the intersection of the wiring 115s of the second metal wiring layer that supplies the address selection signal XD1 and the wiring 113h of the first metal wiring layer. There is no contact here, and if it is desired to input the wiring 115s of the second metal wiring layer that supplies the address selection signal XD1, the location of the fictitious contact in which a contact is provided here is provided. Show.
According to this figure, address selection signals XA0, XB1, XC0 and XD0 are input to this NOR type decoder, and the output is DECOUT4 according to FIG.
The NOR type decoder BL211B is a region surrounded by a frame in the figure, and the vertical dimension is Ly2.

According to this embodiment, the power supply wiring, the reference power supply wiring, and the address selection signal line are the wirings of the second metal wiring layer, and the SGTMOS transistors constituting the NOR decoder are arranged in 2 rows and 4 columns. Connection between the input gate of the NOR decoder and the wiring of the second metal wiring layer through the wiring of the first metal wiring layer that extends in the vertical direction and is arranged in parallel along the row direction As a result, it is possible to supply an arbitrary address selection signal to the input of the NOR decoder, and a NOR decoder with a reduced area that can be arranged at the minimum pitch of the wiring of the second metal wiring layer is provided. realizable.
Further, the silicide layer 103 covering the lower diffusion layer 102n serving as the source region of the NMOS transistors Tn1, Tn2, Tn3, and Tn4 is the NMOS of the same NOR type decoder arranged in an inverted manner adjacent to the upper side of the NOR type decoder BL211B in FIG. 13a. Since it is connected in common to the silicide region covering the source region of the transistor and connected to the reference power supply line, a region for supplying unnecessary reference power can be reduced and the area can be reduced.

(Example 7)
14a, 14b, 14c, 14d, 14e, 14f and 14g show a seventh embodiment. This embodiment is a NOR type decoder realizing the equivalent circuit shown in FIG. 12. FIG. 14A is a plan view of the layout (arrangement) of the 4-input NOR type decoder of the present invention, and FIG. 14B is a cut line A in FIG. 14c is a cross-sectional view along the cut line BB ′ in FIG. 14a, FIG. 14d is a cross-sectional view along the cut line CC ′ in FIG. 14a, and FIG. 14a is a cross-sectional view along the cut line DD ′ in FIG. 14a, FIG. 14f is a cross-sectional view along the cut line EE ′ in FIG. 14a, and FIG. 14g is along the cut line FF ′ in FIG. FIG.

This embodiment differs greatly from the other embodiments in this embodiment, in which NMOS transistors Tn1, Tn2, Tn3, and Tn4 constituting the NOR decoder 211k are arranged in one row (right side in the vertical direction in the figure). That is, the PMOS transistors Tp1, Tp2, Tp3, and Tp4 are arranged in one column (left side in the vertical direction in the figure).
The definition of the row and the column is the same when rotated by 90 degrees, but here is an embodiment that constitutes a row selection decoder according to the memory cells arranged in a matrix, where the horizontal direction is the row, the vertical direction Is defined as a column.
That is, in the embodiment, the NMOS transistor Tn1 and the PMOS transistor Tp1 are arranged from the right side in the first row from the top, the NMOS transistor Tn2 and the PMOS transistor Tp2 are arranged in the second row, and the NMOS transistor Tn3 and the PMOS transistor are arranged in the third row. Tp3 is arranged, and NMOS transistor Tn4 and PMOS transistor Tp4 are arranged in the fourth row.
Further, in the present embodiment, as in the fourth embodiment (FIG. 8), the directions of the source and drain of the NMOS transistors Tn1, Tn2, Tn3, Tn4, and the PMOS transistors Tp1, Tp2, Tp3, Tp4 are arranged upside down. The drains of the NMOS transistors Tn1, Tn2, Tn3, Tn4, and the PMOS transistor Tp1 are connected in common through contacts.
14a, FIG. 14b, FIG. 14c, FIG. 14d, FIG. 14e, FIG. 14f, and FIG. 14g, portions having the same structure as FIG.

Planar silicon layers 202n, 202pa, 202pb are formed on an insulating film such as a buried oxide film layer (BOX) 201 formed on the substrate, and these planar silicon layers 202n, 202pa, 202pb are formed by impurity implantation or the like, respectively. It is composed of an n + diffusion layer, a p + diffusion layer, and a p + diffusion layer. Reference numeral 203 denotes a silicide layer formed on the surface of the planar silicon layer (202n, 202pa, 202pb). 204p1, 204p2, 204p3, and 204p4 are p-type silicon pillars, 204n1, 204n2, 204n3, and 204n4 are n-type silicon pillars, 205 is a silicon pillar 204p1, 204p2, 204p3, 204p4, 204n1, 204n2, 204n3, and 204n4. , 206 are gate electrodes, and 206a, 206b, 206c, 206d, 206e, 206f, 206g and 206h are gate wirings, respectively. N + diffusion layers 207n1, 207n2, 207n3, and 207n4 are formed on the uppermost portions of the silicon pillars 204p1, 204p2, 204p3, and 204p4 by impurity implantation, respectively, and the uppermost portions of the silicon pillars 204n1, 204n2, 204n3, and 204n4 are respectively formed on the uppermost portions. P + diffusion layers 207p1, 207p2, 207p3, and 207p4 are formed by impurity implantation or the like. 208 is a silicon nitride film for protecting the gate insulating film 205, 209n1, 209n2, 209n3, 209n4, 209p1, 209p2, 209p3, 209p4 are n + diffusion layers 207n1, 207n2, 207n3, 207n4, p + diffusion layers 207p1, 207p2, respectively. Silicide layers 210n1, 210n2, 210n3, 210n4, 210p1, 210p2, 210p3, 210p4 connected to 207p3, 207p4 are silicide layers 209n1, 209n2, 209n3, 209n4, 209p1, 209p2, 209p3, 209p4 and the first metal

wiring Layer wirings

213b, 213b, 213b, 213b, 213b, 213d, 213d, and 213c are respectively connected to contacts, 211a is a gate wiring 206 And a contact connecting the wiring 213e of the first metal wiring layer, 211b a contact connecting the gate wiring 206d and the wiring 213h of the first metal wiring layer, and 211c a wiring 213f of the gate wiring 206c and the first metal wiring layer. , 211d is a contact connecting the gate wiring 206e and the first

metal wiring layer

213g, and 211e is a contact connecting the gate wiring 206g and the first metal wiring layer 213i.
Reference numeral 212a (two in the figure) is a contact for connecting the silicide layer 203 connected to cover the lower diffusion layer 202n and the wiring 213a of the first metal wiring layer (two places in the figure in the vertical direction). is there.

The silicon pillar 204p1, the lower diffusion layer 202n, the upper diffusion layer 207n1, the gate insulating film 205, and the gate electrode 206 constitute the NMOS transistor Tn1, and the silicon pillar 204p2, the lower diffusion layer 202n, the upper diffusion layer 207n2, the gate insulating film 205, The gate electrode 206 constitutes the NMOS transistor Tn2, and the silicon pillar 204p3, the lower diffusion layer 202n, the upper diffusion layer 207n3, the gate insulating film 205, and the gate electrode 206 constitute the NMOS transistor Tn3, and the silicon pillar 204p4, the lower diffusion layer. 202n, the upper diffusion layer 207n4, the gate insulating film 205, and the gate electrode 206 constitute an NMOS transistor Tn4. The silicon pillar 204n1, the lower diffusion layer 202pa, the upper diffusion layer 207p1, the gate insulating film 205, the gate electrode The electrode 206 constitutes the PMOS transistor Tp1, and the silicon pillar 204n2, the lower diffusion layer 202pa, the upper diffusion layer 207p2, the gate insulating film 205, and the gate electrode 206 constitute the PMOS transistor Tp2, and the silicon pillar 204n3 and the lower diffusion layer 202pb. The upper diffusion layer 207p3, the gate insulating film 205, and the gate electrode 206 constitute a PMOS transistor Tp3, and the silicon pillar 204n4, the lower diffusion layer 202pb, the upper diffusion layer 207p4, the gate insulating film 205, and the gate electrode 206 constitute the PMOS transistor Tp4. Configure.

Further, the gate wiring 206b is connected to the gate electrode 206 of the NMOS transistor Tn1 and the PMOS transistor Tp1, and the gate wiring 206a is connected to the gate electrode 206 of the PMOS transistor Tp1. A gate wiring 206d is connected to the gate electrodes 206 of the NMOS transistor Tn2 and the PMOS transistor Tp2, and a gate wiring 206c is connected to the gate electrode 206 of the PMOS transistor Tp2. A gate wiring 206f is connected to the gate electrode 206 of the NMOS transistor Tn3 and the PMOS transistor Tp3, and a gate wiring 206e is connected to the gate electrode 206 of the PMOS transistor Tp3. A gate wiring 206h is connected to the gate electrode 206 of the NMOS transistor Tn4 and the PMOS transistor Tp4, and a gate wiring 206g is connected to the gate electrode 206 of the PMOS transistor Tp4.

The sources of the NMOS transistors Tn1, Tn2, Tn3, and Tn4 serve as the lower diffusion layer 202n, and are connected to the wiring 213a of the first metal wiring layer through the silicide 203 and the contacts 212a (two upper and lower in the figure), The wiring 213a of the first metal wiring layer is connected to the wiring 215a of the second metal wiring layer through the contact 214e, and the reference power source Vss is supplied to 215a. Here, the wiring 215a of the second metal wiring layer extends in a direction perpendicular to the row direction. The upper diffusion layer 207n1 which is the drain of the NMOS transistor Tn1 is connected to the wiring 213b of the first metal wiring layer via the silicide 209n1 and the contact 210n1, and the wiring 213b of the first metal wiring layer becomes the output DECOUT0. The upper diffusion layer 207n2 which is the drain of the NMOS transistor Tn2 is connected to the wiring 213b of the first metal wiring layer through the silicide 209n2 and the contact 210n2. The upper diffusion layer 207n3 which is the drain of the NMOS transistor Tn3 is connected to the wiring 213b of the first metal wiring layer through the silicide 209n3 and the contact 210n3. Further, the upper diffusion layer 207n4 which is the drain of the NMOS transistor Tn4 is connected to the wiring 213b of the first metal wiring layer through the silicide 209n4 and the contact 210n4. The upper diffusion layer 207p1 which is the drain of the PMOS transistor Tp1 is connected to the wiring 213b of the first metal wiring layer through the silicide 209p1 and the contact 210p1. Here, as described above, the drains of the NMOS transistors Tn1, Tn2, Tn3, Tn4 and the PMOS transistor Tp1 are commonly connected to the wiring 213b of the first metal wiring layer through the contacts. The lower diffusion layer 202pa serving as the source of the PMOS transistor Tp1 is connected to the drain of the PMOS transistor Tp2 through the silicide layer 203. The upper diffusion layer 207p2 that is the source of the PMOS transistor Tp2 is connected to the wiring 213d of the first metal wiring layer through the silicide 209p2 and the contact 210p2. The upper diffusion layer 207p3, which is the drain of the PMOS transistor Tp3, is connected to the wiring 213d of the first metal wiring layer through the silicide 209p3 and the contact 210p3. Here, the source of the PMOS transistor Tp2 and the drain of the PMOS transistor Tp3 are connected via the wiring 213d of the first metal wiring layer. The source of the PMOS transistor Tp3 is connected to the drain of the PMOS transistor Tp4 through the lower diffusion layer 202pb and the silicide region 203. The upper diffusion layer 207p4 serving as the source of the PMOS transistor Tp4 is connected to the wiring 213c of the first metal wiring layer via the silicide 209p4 and the contact 210p4, and 213c is further connected to the second metal wiring layer via the contact 214p4. The power supply Vcc is supplied to the wiring 215c. Here, the wiring 215c of the second metal wiring layer extends in a direction perpendicular to the row direction.

The gate wiring 206a to which any of the address selection signals XA0 to XA3 supplied by the wiring of the second metal wiring layer is input is connected to the wiring 213e of the first metal wiring layer via the contact 211a. The wiring 213e of the first metal wiring layer extends in a parallel direction (left side in the drawing) along the row. The wiring of the second metal wiring layer that supplies the address selection signals XA0 to XA3 extends in the direction perpendicular to the row direction, and the wiring of the first metal wiring layer that extends in parallel to the row direction. A contact 214a is arranged at one intersection of the wirings of the second metal wiring layer for supplying the address selection signals XA0 to XA3 extending in the direction perpendicular to the row direction with respect to 213e, and the address selection signal XAh The wiring of the second metal wiring layer that supplies (h = 0 to 3) is connected to the gate wiring 206a. In the figure, a contact 214a is provided at the intersection of the wiring 215d of the second metal wiring layer that supplies the address selection signal XA0 and the wiring 213e of the first metal wiring layer. That is, the address selection signal XA0 is input to the gates of the NMOS transistor Tn1 and the PMOS transistor Tp1 of this NOR decoder.
In this figure, the address selection signals XA2 to XA3 are omitted, but are arranged in the same manner as XA0 and XA1, and further on the left side in a form perpendicular to the row direction.
Note that a contact 214z is drawn by a broken line at the intersection of the wiring 215e of the second metal wiring layer that supplies the address selection signal XA1 and the wiring 213e of the first metal wiring layer. There is no contact here, and if it is desired to input the wiring 115e of the second metal wiring layer that supplies the selection address signal XA1, the location of the fictitious contact, that is, the contact is provided at this location, is provided. Show.

The gate wiring 206d to which the address selection signal XB0 supplied by the second metal wiring layer is selectively input is connected to the first metal wiring layer wiring 213h via the contact 211b, and the address selection signal XB1˜ The gate wiring 206c to which one of the second metal wiring layers supplying XB3 is input is connected to the wiring 213f of the first metal wiring layer through the contact 211c. The wiring 213f of the first metal wiring layer extends in a parallel direction (left side in the drawing) along the row. The second metal wiring layer that supplies the address selection signals XB0 to XB3 extends in a direction perpendicular to the row direction, and the wiring 213f of the first metal wiring layer or the wiring 213h of the first metal wiring layer A contact 214b is disposed at any one of the intersections, and a second metal wiring layer for supplying an address selection signal XBi (i = 0 to 3) is connected to the

gate wiring

206d or 206c. In the figure, a contact 214b is provided at the intersection of the wiring 215b of the second metal wiring layer that supplies the address selection signal XB0 and the wiring 213h of the first metal wiring layer. That is, the address selection signal XB0 is input to the gates of the NMOS transistor Tn2 and the PMOS transistor Tp2 of the NOR decoder.
A contact 214z is drawn by a broken line at the intersection of the wiring 215f of the second metal wiring layer that supplies the address selection signal XB1 and the wiring 213f of the first metal wiring layer. There is no contact, and the location of the fictitious contact is shown.
Note that the second metal wiring layer that supplies the address selection signals XB2 to XB3 is omitted for the sake of illustration, but it is the same as the second metal wiring layer address selection signal that supplies the address selection signals XB0 and XB1. Further, it is arranged on the left side in a direction perpendicular to the row direction.

The gate wiring 206e to which any of the address selection signals XC0 to XC3 supplied by the wiring of the second metal wiring layer is input is connected to the wiring 213g of the first metal wiring layer through the contact 211d. The wiring 213g of the first metal wiring layer extends in a parallel direction (left side in the drawing) along the row. The wiring of the second metal wiring layer that supplies the address selection signals XC0 to XC3 extends in the direction perpendicular to the row direction, and is at one of the intersections with the wiring 213g of the first metal wiring layer. A contact 214c is arranged to connect the wiring of the second metal wiring layer that supplies the address selection signal XCj (i = 0 to 3) to the gate wiring 206e. In the figure, a contact 214c is provided at the intersection of the wiring 215g of the second metal wiring layer that supplies the address selection signal XC0 and the wiring 213g of the first metal wiring layer. That is, the address selection signal XC0 is input to the gates of the NMOS transistor Tn3 and the PMOS transistor Tp3 of this NOR decoder.
Note that a contact 214z is drawn with a broken line at the intersection of the wiring 215h of the second metal wiring layer that supplies the address selection signal XC1 and the wiring 213g of the first metal wiring layer. Here, no contact exists, and the location of a fictitious contact is shown.
Note that the wiring of the second metal wiring layer that supplies the address selection signals XC2 to XC3 is omitted for the sake of illustration, but is the same as the wiring of the second metal wiring layer that supplies the address selection signals XC0 and XC1. Furthermore, it is arranged on the left side in a direction perpendicular to the row direction.

The gate wiring 206g to which any one of the address selection signals XD0 to XD3 supplied by the wiring of the second metal wiring layer is input is connected to the wiring 213i of the first metal wiring layer through the contact 211e. The wiring 213i of the first metal wiring layer extends in a parallel direction (left side in the drawing) along the row. The wiring of the second metal wiring layer that supplies the address selection signals XD0 to XD3 extends in the direction perpendicular to the row direction, and is at one of the intersections with the wiring 213i of the first metal wiring layer. A contact 214d is arranged to connect the wiring of the second metal wiring layer that supplies the address selection signal XDj (i = 0 to 3) to the gate wiring 206g. In the figure, a contact 214d is provided at the intersection of the wiring 215i of the second metal wiring layer that supplies the address selection signal XD0 and the wiring 213i of the first metal wiring layer. That is, the address selection signal XD0 is input to the gates of the NMOS transistor Tn4 and the PMOS transistor Tp4 of this NOR decoder.
Note that a contact 214z is drawn with a broken line at the intersection of the wiring 215j of the second metal wiring layer that supplies the address selection signal XD1 and the wiring 213i of the first metal wiring layer. Here, no contact exists, and the location of an imaginary contact is shown.
Note that the wiring of the second metal wiring layer that supplies the address selection signals XD2 to XD3 is omitted for the sake of illustration, but the wiring address selection of the second metal wiring layer that supplies the address selection signals XD0 and XD1 is omitted. Similar to the signal, it is arranged on the left side in the direction perpendicular to the row direction.
According to this embodiment, address selection signals XA0, XB0, XC0, and XD0 are input to this NOR type decoder, and the output is DECOUT0 according to FIG.
Further, the NOR decoder BL211C is an area surrounded by a frame in the figure, and the vertical dimension Ly3 is 2.0 diffusion intervals which are dead spaces with respect to four vertical rows.

According to this embodiment, the power supply wiring, the reference power supply wiring, and the address selection signal line are the wiring of the second metal wiring layer, and the SGTMOS transistors constituting the NOR decoder are arranged in 4 rows and 2 columns. Connection between the input gate of the NOR decoder and the wiring of the second metal wiring layer through the wiring of the first metal wiring layer that extends in the vertical direction and is arranged in parallel along the row direction Thus, it becomes possible to supply an arbitrary address selection signal to the input of the NOR decoder, and the NOR decoder having a reduced area can be arranged at the minimum pitch of the wiring of the second metal wiring layer. realizable. Further, by arranging 8 MOS transistors in 4 rows and 2 columns and reducing the number of diffusion intervals, the lateral direction can be reduced, and the area is further reduced.

(Example 8)
FIG. 15 shows an eighth embodiment. A row selection decoder in which a NOR type decoder 211k according to the seventh embodiment is combined and integrated with a first inverter 212 and a second inverter 213 is shown. On the right side of the NOR decoder BL211C of the seventh embodiment (FIG. 14), the NMOS transistor Tn11 and PMOS transistor Tp11 constituting the first inverter, and the PMOS transistor Tp12 and NMOS transistor Tn12 constituting the second inverter are in order from the top. Placed in.
The lower diffusion layer 202nb, which is the source of the NMOS transistor Tn11, is commonly connected to the lower diffusion layer, which is the source of the NMOS transistor (Tn12) of the second inverter adjacent to the upper side (not shown), via the silicide layer 203. The lower diffusion layer 202nc that is the source of Tn12 is commonly connected to the lower diffusion layer that is the source of the NMOS transistor (Tn11) of the first inverter adjacent to the lower side (not shown) via the silicide layer 203. Further, the lower diffusion layer 202 pc which is the source of the PMOS transistors Tp 11 and Tp 12 is also commonly connected through the silicide layer 203.

The upper diffusion layer 207n11 and the upper diffusion layer 207p11 which are the drains of the NMOS transistor Tn11 and the PMOS transistor Tp11 constituting the first inverter are respectively connected to the first metal wiring via the silicide 209n11 and the contact 210n11 or the silicide layer 209p11 and the contact 210p11. The wiring 213j of the first metal wiring layer is commonly connected to the wiring 213j of the layer, and becomes the output of the first inverter. Further, the wiring 213b of the first metal wiring layer, which is the output of the NOR decoder, is connected to the gate wiring 206i commonly connected to the gate electrodes of the NMOS transistor Tn11 and the PMOS transistor Tp11 via the gate wiring 206j. .
The upper diffusion layer 207n12 and the upper diffusion layer 207p12 which are the drains of the NMOS transistor Tn12 and the PMOS transistor Tp12 constituting the second inverter are respectively connected to the first metal wiring via the silicide 209n12, the contact 210n12 or the silicide layer 209p12 and the contact 210p12. The wiring 213k of the first metal wiring layer is commonly connected to the wiring 213k of the layer, and becomes the output WL1 of the row selection decoder. Further, the wiring 113j of the first metal wiring layer, which is the output of the first inverter, is connected to the gate wiring 206k commonly connected to the gate electrodes of the NMOS transistor Tn12 and the PMOS transistor Tp12 via the gate wiring 206l. The

Lower diffusion layer 202nb is connected to wiring 213a of the first metal wiring layer via silicide layer 203 and contact 212b, and further connected to wiring 215a of the second metal wiring layer via contact 214f. Here, the wiring 213a of the first metal wiring layer and the wiring 215a of the second metal wiring layer widely share the wiring of the NOR decoder (BL211C) of FIG.
Lower diffusion layer 202nc is connected to wiring 213a of the first metal wiring layer via silicide layer 203 and contact 212c, and further connected to wiring 215a of the second metal wiring layer via contact 214g. Similarly, the wiring 213a of the first metal wiring layer and the wiring 215a of the second metal wiring layer are shared with the NOR decoder (BL211C) of FIG.
The lower diffusion layer 202pc is connected to the wiring 213l of the first metal wiring layer via the silicide 203 and the contact 212d, and further connected to the wiring 215k of the second metal wiring layer via the contact 214h. The power supply Vcc is supplied to the wiring 215k of the metal wiring layer.
According to the present embodiment, the row selection decoder BL210C is an area surrounded by a frame in the figure, and the vertical dimension can be realized with the minimum Ly3.

According to the present embodiment, a NOR type decoder arranged in 4 rows and 2 columns, and a first inverter and a second inverter arranged in a vertical column are integrally arranged so that there is no useless area. A row selection decoder with a reduced area can be provided. Furthermore, the sources of the NMOS transistors and PMOS transistors of the first inverter and the second inverter share the lower diffusion layer and are arranged in a row, so that the inverter can be arranged with a minimum area.
In the present embodiment, only the row selection decoder is arranged. However, as in the third embodiment (FIG. 7), the memory cell is reduced in size by connecting the SRAM cells in which the MOS transistors are arranged in two rows and three columns. The apparatus can be easily configured.

Example 9
FIGS. 16a, 16b, 16c, 16d, 16e, 16f, 16g, and 16h show a ninth embodiment. This embodiment is a NOR type decoder realizing the equivalent circuit shown in FIG. 12, FIG. 16a is a plan view of the layout (arrangement) of the NOR type decoder of the present invention, and FIG. 16b is a cut line AA in FIG. 16c is a cross-sectional view along the cut line BB ′ in FIG. 16a, FIG. 16d is a cross-sectional view along the cut line CC ′ in FIG. 16a, and FIG. 16a is a cross-sectional view along the cut line DD ′ in FIG. 16a, FIG. 16f is a cross-sectional view along the cut line EE ′ in FIG. 16a, and FIG. 16g is a cross-sectional view along the cut line FF ′ in FIG. FIGS. 16h show a cross-sectional view along the cut line GG ′ in FIG. 16a.

In the present embodiment, similarly to the eighth embodiment (FIG. 14), NMOS transistors Tn1, Tn2, Tn3 and Tn4 constituting a NOR decoder are arranged in one column (right side in the vertical direction in the figure), and similarly, PMOS transistors Tp1, Tp2, Tp3, and Tp4 are arranged in one row (left side in the vertical direction in the figure).
That is, in the embodiment, the NMOS transistor Tn4 and the PMOS transistor Tp4 are arranged in the first row from the right side, the NMOS transistor Tn3 and the PMOS transistor Tp3 are arranged in the second row, and the NMOS transistor Tn2 and the PMOS transistor are arranged in the third row. Tp2 is arranged, and NMOS transistor Tn1 and PMOS transistor Tp1 are arranged in the fourth row.
Further, the direction of the source and drain of the transistor of this embodiment is arranged in the same manner as in the first embodiment. 16a, FIG. 16b, FIG. 16c, FIG. 16d, FIG. 16e, FIG. 16f, FIG. 16g, and FIG. 16h, parts having the same structure as FIG. .

Planar silicon layers 202n, 202pa, 202pb, 202pc are formed on an insulating film such as a buried oxide film layer (BOX) 201 formed on the substrate, and the planar silicon layers 202n, 202pa, 202pb, 202pc are impurity-implanted. The n + diffusion layer, the p + diffusion layer, the p + diffusion layer, and the p + diffusion layer are respectively formed. A silicide layer 203 is formed on the surface of the planar silicon layer (202n, 202pa, 202pb, 202pc), and connects the planar silicon layers 202n and 202pa. Further, 203 is arranged to cover the p + diffusion layers 202pb and 202pc, respectively. 204p1, 204p2, 204p3, and 204p4 are p-type silicon pillars, 204n1, 204n2, 204n3, and 204n4 are n-type silicon pillars, 205 is a silicon pillar 204p1, 204p2, 204p3, 204p4, 204n1, 204n2, 204n3, and 204n4. , 206 are gate electrodes, and 206a, 206b, 206c, 206d, 206e, 206f, 206g and 206h are gate wirings, respectively. N + diffusion layers 207n1, 207n2, 207n3, and 207n4 are formed on the uppermost portions of the silicon pillars 204p1, 204p2, 204p3, and 204p4 by impurity implantation, respectively, and the uppermost portions of the silicon pillars 204n1, 204n2, 204n3, and 204n4 are respectively formed on the uppermost portions. P + diffusion layers 207p1, 207p2, 207p3, and 207p4 are formed by impurity implantation or the like. 208 is a silicon nitride film for protecting the gate insulating film 205, 209n1, 209n2, 209n3, 209n4, 209p1, 209p2, 209p3, 209p4 are n + diffusion layers 207n1, 207n2, 207n3, 207n4, p + diffusion layers 207p1, 207p2, respectively. Silicide layers 210n1, 210n2, 210n3, 210n4, 210p1, 210p2, 210p3, 210p4 connected to 207p3, 207p4 are silicide layers 209n1, 209n2, 209n3, 209n4, 209p1, 209p2, 209p3, 209p4 and the first metal

wiring Layer wirings

213k, 213a, 213a, 213a, 213d, 213d, 213j, and 213j, respectively, contacts 211a, gate wiring 206 And a contact connecting the wiring 213e of the first metal wiring layer, 211b a contact connecting the gate wiring 206c and the wiring 213f of the first metal wiring layer, and 211c a wiring 213h of the gate wiring 206d and the first metal wiring layer , 211d is a contact connecting the gate wiring 206e and the first

metal wiring layer

213g, and 211e is a contact connecting the gate wiring 206g and the first metal wiring layer 213i.
212a is a contact for connecting the silicide 203 connecting the lower diffusion layer 202n and the lower diffusion layer 202pa and the wiring 213b of the first metal wiring layer. Reference numeral 212b denotes a contact for connecting the silicide layer 203 covering the lower diffusion layer 202pc and the wiring 213c of the first metal wiring layer.

The silicon pillar 204p1, the lower diffusion layer 202n, the upper diffusion layer 207n1, the gate insulating film 205, and the gate electrode 206 constitute the NMOS transistor Tn1, and the silicon pillar 204p2, the lower diffusion layer 202n, the upper diffusion layer 207n2, the gate insulating film 205, The gate electrode 206 constitutes the NMOS transistor Tn2, and the silicon pillar 204p3, the lower diffusion layer 202n, the upper diffusion layer 207n3, the gate insulating film 205, and the gate electrode 206 constitute the NMOS transistor Tn3, and the silicon pillar 204p4, the lower diffusion layer. 202n, the upper diffusion layer 207n4, the gate insulating film 205, and the gate electrode 206 constitute an NMOS transistor Tn4. The silicon pillar 204n1, the lower diffusion layer 202pa, the upper diffusion layer 207p1, the gate insulating film 205, the gate The pole 206 constitutes the PMOS transistor Tp1, and the silicon pillar 204n2, the lower diffusion layer 202pb, the upper diffusion layer 207p2, the gate insulating film 205, and the gate electrode 206 constitute the PMOS transistor Tp2, and the silicon pillar 204n3 and the lower diffusion layer 202pb. The upper diffusion layer 207p3, the gate insulating film 205, and the gate electrode 206 constitute a PMOS transistor Tp3, and the silicon pillar 204n4, the lower diffusion layer 202nc, the upper diffusion layer 207p4, the gate insulating film 205, and the gate electrode 206 constitute the PMOS transistor Tp4. Configure.

Further, the gate wiring 206b is connected to the gate electrode 206 of the NMOS transistor Tn1 and the PMOS transistor Tp1, and the gate wiring 206a is connected to the gate electrode of the PMOS transistor Tp1. A gate wiring 206d is connected to the gate electrodes 206 of the NMOS transistor Tn2 and the PMOS transistor Tp2, and a gate wiring 206c is connected to the gate electrode 206 of the PMOS transistor Tp2. A gate wiring 206f is connected to the gate electrode 206 of the NMOS transistor Tn3 and the PMOS transistor Tp3, and a gate wiring 206e is connected to the gate electrode 206 of the PMOS transistor Tp3. The gate wiring 206h is connected to the gate electrode 206 of the NMOS transistor Tn4 and the PMOS transistor Tp4, and the gate wiring 206g is connected to the gate electrode 206 of the PMOS transistor Tp4.

The lower diffusion layers 202n and 202pa serve as a common drain of the NMOS transistors Tn1, Tn2, Tn3, Tn4 and the PMOS transistor Tp1 through the silicide layer 203, and are connected to the wiring 213b of the first metal wiring layer through the contact 212a. DECOUT0. The upper diffusion layer 207n1 which is the source of the NMOS transistor Tn1 is connected to the wiring 213k of the first metal wiring layer via the silicide 209n1 and the contact 210n1, and the wiring 213k of the first metal wiring layer is further connected to the wiring 214c1 via the contact 214n1. The reference power supply Vss is supplied to the wiring 215a of the second metal wiring layer. The upper diffusion layer 207n2 which is the source of the NMOS transistor Tn2 is connected to the wiring 213a of the first metal wiring layer extending along the column direction (vertical direction) via the silicide 209n2 and the contact 210n2, The metal wiring layer wiring 213a is further connected to the second metal wiring layer wiring 215a through a contact 214n2. The upper diffusion layer 207n3 that is the source of the NMOS transistor Tn3 is connected to the wiring 213a of the first metal wiring layer via the silicide 209n3 and the contact 210n3, and the wiring 213a of the first metal wiring layer is further connected to the wiring 214c via the contact 214n3. It is connected to the wiring 215a of the second metal wiring layer.
The upper diffusion layer 207n4 which is the source of the NMOS transistor Tn4 is connected to the wiring 213a of the first metal wiring layer via the silicide 209n4 and the contact 210n4, and the wiring 213a of the first metal wiring layer is further connected to the wiring 214c via the contact 214n4. It is connected to the wiring 215a of the second metal wiring layer.
The upper diffusion layer 207p1 which is the source of the PMOS transistor Tp1 is connected to the wiring 213d of the first metal wiring layer via the silicide 209p1 and the contact 210p1. The upper diffusion layer 207p2 which is the drain of the PMOS transistor Tp2 is connected to the wiring 213d of the first metal wiring layer through the silicide 209p2 and the contact 210p2. Here, the source of the PMOS transistor Tp1 and the drain of the PMOS transistor Tp2 are connected via the wiring 213d of the first metal wiring layer. The source of the PMOS transistor Tp2 is connected to the drain of the PMOS transistor Tp3 through the lower diffusion layer 202pb and the silicide region 203, and the source of the PMOS transistor Tp3 is connected to the wiring 214j of the first metal wiring layer through the contact 210p3. Connected. The upper diffusion layer 207p4 which is the drain of the PMOS transistor Tp4 is connected to the wiring 213j of the first metal wiring layer through the silicide 209p4 and the contact 210p4. Here, the source of the PMOS transistor Tp3 and the drain of the PMOS transistor Tp4 are connected via the wiring 213j of the first metal wiring layer. The lower diffusion layer 202pc which is the source of the PMOS transistor Tp4 is connected to the wiring 213c of the first metal wiring layer via the silicide region 203 and the

contact

212b, and 213c is further connected to the second metal via the contact 214e. The power supply Vcc is supplied to the wiring 215c connected to the wiring 215c of the wiring layer.
Here, the wiring 215c of the second metal wiring layer extends in a direction perpendicular to the row direction.

The gate wiring 206a to which any of the address selection signals XA0 to XA3 supplied by the wiring of the second metal wiring layer is input is connected to the wiring 213e of the first metal wiring layer via the contact 211a. The wiring 213e of the first metal wiring layer extends in a parallel direction (left side in the drawing) along the row. The wiring of the second metal wiring layer that supplies the address selection signals XA0 to XA3 extends in the direction perpendicular to the row direction, and the wiring of the first metal wiring layer that extends in parallel to the row direction. A contact 214a is arranged at one intersection of the wirings of the second metal wiring layer for supplying the address selection signals XA0 to XA3 extending in the direction perpendicular to the row direction with respect to 213e, and the address selection signal XAh The wiring of the second metal wiring layer that supplies (h = 0 to 3) is connected to the gate wiring 206a. In the figure, a contact 214a is provided at the intersection of the wiring 215d of the second metal wiring layer that supplies the address selection signal XA0 and the wiring 213e of the first metal wiring layer. That is, the address selection signal XA0 is input to the gates of the NMOS transistor Tn1 and the PMOS transistor Tp1 of this NOR decoder.
In this figure, the wiring of the second metal wiring layer for supplying the address selection signals XA2 to XA3 is omitted, but it is arranged in the same manner as XA0 and XA1, and further on the left side in a form perpendicular to the row direction. Be placed.
Note that a contact 214z is drawn by a broken line at the intersection of the wiring 215e of the second metal wiring layer that supplies the address selection signal XA1 and the wiring 213e of the first metal wiring layer. There is no contact here, and if it is desired to input the wiring 115e of the second metal wiring layer that supplies the address selection signal XA1, the location of the fictitious contact in which a contact is provided here is provided. Show. Hereinafter, the same is true for the other portions.

The gate wiring 206d to which the address selection signal XB0 supplied by the wiring of the second metal wiring layer is selectively input (input only to the selected decoder) is connected to the first metal wiring layer via the contact 211c. The gate wiring 206c connected to the wiring 213h and to which any one of the address selection signals XB1 to XB3 is input is connected to the wiring 213f of the first metal wiring layer through the contact 211b. The wiring 213f of the first metal wiring layer extends in a parallel direction (left side in the drawing) along the row. The wiring of the second metal wiring layer that supplies the address selection signals XB0 to XB3 extends in the direction perpendicular to the row direction, and the wiring 213h of the first metal wiring layer or the wiring of the first metal wiring layer A contact 214b is arranged at any one of the intersections of 213f, and the wiring of the second metal wiring layer that supplies the address selection signal XBi (i = 0 to 3) is connected to the

gate wiring

206d or 206c. In the figure, a contact 214b is provided at the intersection of the wiring 215b of the second metal wiring layer that supplies the address selection signal XB0 and the wiring 213h of the first metal wiring layer. That is, the address selection signal XB0 is input to the gates of the NMOS transistor Tn2 and the PMOS transistor Tp2 of the NOR decoder.
Note that a contact 214z is drawn by a broken line at the intersection of the wiring 215f of the second metal wiring layer that supplies the address selection signal XB1 and the wiring 213f of the first metal wiring layer, as described above. Here, no contact exists, and the location of a fictitious contact is shown.

The gate wiring 206e to which any of the address selection signals XC0 to XC3 supplied by the wiring of the second metal wiring layer is input is connected to the wiring 213g of the first metal wiring layer through the contact 211d. The wiring 213g of the first metal wiring layer extends in a parallel direction (left side in the drawing) along the row. The wiring of the second metal wiring layer that supplies the address selection signals XC0 to XC3 extends in the direction perpendicular to the row direction, and is at one of the intersections with the wiring 213g of the first metal wiring layer. A contact 214c is arranged to connect the wiring of the second metal wiring layer that supplies the address selection signal XCj (i = 0 to 3) to the gate wiring 206e. In the figure, a contact 214c is provided at the intersection of the wiring 215g of the second metal wiring layer that supplies the address selection signal XC0 and the wiring 213g of the first metal wiring layer. That is, the address selection signal XC0 is input to the gates of the NMOS transistor Tn3 and the PMOS transistor Tp3 of this NOR decoder.
Note that a contact 214z is drawn by a broken line at the intersection of the wiring 215h of the second metal wiring layer that supplies the address selection signal XC1 and the wiring 213g of the first metal wiring layer. Here, no contact exists, and the location of an imaginary contact is shown.
Note that the wiring of the second metal wiring layer that supplies the selection address signals XC2 to XC3 is omitted for the sake of illustration, but is the same as the wiring of the second metal wiring layer that supplies the address selection signals XC0 and XC1. Furthermore, it is arranged on the left side in a direction perpendicular to the row direction.

The gate wiring 206g to which any one of the address selection signals XD0 to XD3 supplied by the wiring of the second metal wiring layer is input is connected to the wiring 213i of the first metal wiring layer through the contact 211e. The wiring 213i of the first metal wiring layer extends in a parallel direction (left side in the drawing) along the row. The wiring of the second metal wiring layer that supplies the address selection signals XD0 to XD3 extends in the direction perpendicular to the row direction, and is at one of the intersections with the wiring 213i of the first metal wiring layer. A contact 214d is arranged to connect the wiring of the second metal wiring layer that supplies the address selection signal XDj (j = 0 to 3) to the gate wiring 206g. In the figure, a contact 214d is provided at the intersection of the wiring 215i of the second metal wiring layer that supplies the address selection signal XD0 and the wiring 213i of the first metal wiring layer. That is, the address selection signal XD0 is input to the gates of the NMOS transistor Tn4 and the PMOS transistor Tp4 of this NOR decoder.
Note that a contact 214z is drawn with a broken line at the intersection of the wiring 215j of the second metal wiring layer that supplies the address selection signal XD1 and the wiring 213i of the first metal wiring layer. Here, no contact exists, and the location of an imaginary contact is shown.
Note that the wiring of the second metal wiring layer that supplies the address selection signals XD2 to XD3 is omitted for the sake of illustration, but is the same as the wiring of the second metal wiring layer that supplies the address selection signals XD0 and XD1. Furthermore, it is arranged on the left side in a direction perpendicular to the row direction.
According to the present embodiment, address selection signals XA0, XB0, XC0, and XD0 are input to the row selection decoder, and the output is WL0 according to FIG.
Further, the NOR decoder BL211D is an area surrounded by a frame in the figure, and the vertical dimension Ly4 is 2.5 diffusion intervals.

According to this embodiment, the power supply wiring, the reference power supply wiring, and the address selection signal line are the wiring of the second metal wiring layer, and the SGTMOS transistors constituting the NOR decoder are arranged in 4 rows and 2 columns. Connection between the input gate of the NOR decoder and the wiring of the second metal wiring layer through the wiring of the first metal wiring layer that extends in the vertical direction and is arranged in parallel along the row direction Thus, it becomes possible to supply an arbitrary address selection signal to the input of the NOR decoder, and the NOR decoder having a reduced area can be arranged at the minimum pitch of the wiring of the second metal wiring layer. realizable. Furthermore, by arranging 8 MOS transistors in 4 rows and 2 columns, the horizontal direction can be reduced, and the area is further reduced.
In this embodiment, only the NOR type decoder is arranged. However, as in the eighth embodiment (FIG. 15), the first inverter and the second inverter are arranged in one column to reduce the area. A decoder can be easily configured.

(Example 10)
In the above embodiments, the arrangement has been described using an example of a process in which planar silicon is arranged on an insulating film such as a buried oxide film layer (BOX) formed on a substrate. However, a bulk CMOS process is used. Is the same. As an example, FIGS. 17a, 17b, 17c, and 17d show a tenth embodiment in which the embodiment of FIG. 4 is arranged in a bulk CMOS process.
17a is a plan view of the layout (arrangement) of the 3-input NOR decoder according to the present invention, FIG. 17b is a cross-sectional view along the cut line AA ′ in FIG. 17a, and FIG. 17c is a cut line B in FIG. FIG. 17d shows a cross-sectional view along the cut line CC ′ in FIG. 17a.
In FIGS. 17a, 17b, 17c, and 17d, portions having the same structure as those in FIGS. 4a, 4b, 4d, 4f, and 4i are denoted by the same reference numerals in the 100s.
Referring to Japanese Patent No. 4756221 of Patent Document 3, there is no difference between the BOX process of FIG. 4 and the bulk CMOS process of FIG. 17 in the plan view of FIG. 17a. There are differences in the cross-sectional views of FIGS. 17b, 17c, and 17d. In FIG. 17b, reference numeral 150 denotes a p-type silicon substrate. Reference numeral 160 denotes an insulator for element isolation (isolation). Reference numeral 170 denotes an n− region which serves as a leakage preventing separation layer. Except for this p-type silicon substrate 150, the element isolation insulator 160, and the leak prevention isolation layer 170, the process and structure above the lower diffusion layer are exactly the same. Can be realized by a process.

As described above, the first to tenth embodiments have been described. In this embodiment, a typical configuration is described, and the type of NOR decoder, the combination with an inverter, and the like can be freely selected. For example, the row selection decoder of FIG. 9 may be replaced with the row selection decoder of FIG. 7, or the first and second inverters of FIG. 15 are adopted as the NOR type decoder of FIG. It may be configured.
In this embodiment, in order to minimize the area of the decoder, the number of transistors constituting the decoder is minimized. Modifications such as arranging a plurality of transistors in parallel for the purpose of increasing the operation speed of the NOR decoder or increasing the drive capability (current amount) of the inverter are included as design matters in the present invention. Further, providing a reset transistor for resetting the decoder or adding a standby (current cut) function is included in the design matters. On the other hand, in a design where the operation speed is not important, there is no problem in operation even if the first inverter and the second inverter are omitted and the output of the NOR decoder is directly used as the row selection signal. The configuration is included in the design matters.
In the description of this embodiment, for convenience, the silicon column of the PMOS transistor is defined as n-type silicon and the NMOS silicon column is defined as a p-type silicon layer. However, it is difficult to control the concentration by impurity implantation in a miniaturized process. Therefore, both the PMOS transistor and the NMOS transistor use a so-called neutral semiconductor that does not inject impurities into the silicon pillar, and the channel control, that is, the threshold values of the PMOS and NMOS are specific to the metal gate material. In some cases, the difference in work function (Work Function) is used.
In this embodiment, the lower diffusion layer or the upper diffusion layer is covered with the silicide layer. However, silicide is used to reduce the resistance, and other low-resistance materials may be used. A generic term for metal compounds is defined as silicide.
The essence of the present invention is to reduce the area by commonly connecting the drains of the transistors connected to the output terminal via the lower diffusion layer, which is a feature of the SGT, in accordance with the pitch of the memory cells. Alternatively, the area of the transistor connected to the output terminal is reduced by commonly connecting the drains of the transistors via the upper diffusion layer and the contact, and further, the power supply line, the reference power supply line, and the plurality of address selection lines input to the decoder By devising the wiring method, a decoder having a reduced area including the wiring region is provided. When this arrangement method is followed, the wiring method of the gate wiring, the wiring position, and the wiring method of the metal wiring The wiring positions and the like other than those shown in the drawings of this embodiment belong to the technical scope of the present invention.

Tp1, Tp2, Tp3, Tp4, Tp11, Tp12: P channel MOS transistors Tn1, Tn2, Tn3, Tn4, Tn11, Tn12: N channel MOS transistors 101, 201: buried oxide film layers 102pa, 102pb, 102pc, 102n, 202pa, 202pb, 202pc, 202n, 202nb, 202nc: planar silicon layer 103, 203: silicide layer 104p1, 104p2, 104p3, 104p4, 104p11, 104p12, 204p1, 204p2, 204p3, 204p4, 204p11, 204p12: p-type silicon pillar 104n1, 104n2, 104n3, 104n4, 104n11, 104n12, 204n1, 204n2, 204n3, 204n4, 204n11, 204n1 : N-type silicon pillars 105 and 205: gate insulating films 106 and 206: gate electrodes 106a, 106b, 106c, 106d, 106e, 106f, 106g, 106h, 206a, 206b, 206c, 206d, 206e, 206f, 206g, 206h: Gate lines 107p1, 107p2, 107p3, 107p4, 107p11, 107p12, 207p1, 207p2, 207p3, 207p4, 207p11, 207p12: p + diffusion layers 107n1, 107n2, 107n3, 107n4, 107n11, 107n12, 207n1, 207n2, 207n3, 207n4, 20711 207n12: n + diffusion layer 108, 208: silicon nitride films 109p1, 109p2, 109p3, 109p4, 109p11, 109p 2, 109n1, 109n2, 109n3, 109n4, 109n11, 109n12, 209p1, 209p2, 209p3, 209p4, 209p11, 209p12, 209n1, 209n2, 209n3, 209n4, 209n11, 209n12: Silicide layers 110p1, 110p11p, 110p3 110p12, 110n1, 110n2, 110n3, 110n4, 110n11, 110n12, 210p1, 210p2, 210p3, 210p4, 210p11, 210p12, 210n1, 210n2, 210n3, 210n4, 210n11, 210n12: Contacts 111a, 111b, 111c, 111d, 111e, 111f 111g, 211a, 211b, 211c, 211d 211e, 211f, 211g: Contacts 112a, 112b, 212a, 212b, 212c: Contacts 113a, 113b, 113c, 113d, 113e, 113f, 113g, 113h, 113i, 113j, 113k, 213a, 213b, 213c, 213d, 213e 213f, 213g, 213h, 213i, 213j, 213k, 213l: wirings 114a, 114b, 114c, 114d, 114e, 214a, 214b, 214c, 214d, 214e, 214f, 214g of the first metal wiring layer: contacts 115a, 115b, 115c, 115d, 115e, 115f, 115g, 115h, 115i, 115j, 115k, 115l, 115m, 115n, 115p, 115q, 115r, 115s, 15a, 215b, 215c, 215d, 215e, 215f, 215g, 215h, 215i, 215j, 215k: second metal wiring layer wiring 150 silicon substrate 160: element isolation insulator 170: leakage preventing separation layer

Claims

A decoder comprising a plurality of MOS transistors whose sources, drains and gates are arranged hierarchically in a direction perpendicular to the substrate, wherein at least a × b MOS transistors are arranged in a rows and b columns on the substrate A semiconductor device constituting a circuit,
Each of the plurality of MOS transistors includes:
Silicon pillars,
An insulator surrounding a side surface of the silicon pillar;
A gate surrounding the insulator;
A source region disposed above or below the silicon pillar;
A drain region disposed above or below the silicon pillar, the drain region disposed opposite to the source region with respect to the silicon pillar;
The decoder circuit is at least
1st to n-th n P-channel MOS transistors and 1st to n-th n-channel MOS transistors,
The first to n-th P-channel MOS transistors and the first to n-th N-channel MOS transistors are k-th (k = 1 to n) P-channel MOS transistors and k-th N-channel MOS transistors. N gates of transistors are connected to each other to form n transistor pairs;
The drain regions of the first to n-th N-channel MOS transistors and the first P-channel MOS transistors are disposed on the substrate side from the silicon pillar, and the first to n-th N-channel MOS transistors The drain regions of the first P-channel MOS transistors are connected to each other via a silicide region;
Of the first to nth P-channel MOS transistors, the source of the s (s = 1 to n−1) th P-channel MOS transistor and the drain of the s + 1th P-channel MOS transistor are connected to each other. And
The sources of the first to nth N-channel MOS transistors are each connected to a reference power supply line, and the sources of the nth P-channel MOS transistors are connected to a power supply line,
One input signal line for each of at least one set of input signal lines is connected to the gates of the MOS transistors of each of the n pairs of transistors,
At least one set of input signal lines of the power supply line, the reference power supply line, and the input signal line extends in the same direction.
The first to nth N-channel MOS transistors are arranged in 1 row and n column,
The first to nth P-channel MOS transistors are arranged in one row and n column,
2. The semiconductor device according to claim 1, wherein at least one set of input signal lines of the power supply line, the reference power supply line, and the input signal line extends in a direction perpendicular to the row direction.
The sources of the first to nth N-channel MOS transistors are connected to the wiring of the first metal wiring layer,
The source of the nth P-channel MOS transistor is connected to the wiring of the first metal wiring layer,
The power line is constituted by a second metal wiring layer that is higher than the first metal wiring layer,
The reference power line is constituted by the second metal wiring layer,
The source of the first to n-th N-channel MOS transistors is connected to the reference power supply line via the wiring of the first metal wiring layer to which the sources of the first to n-th N-channel MOS transistors are connected. Connected to the wiring of the second metal wiring layer constituting,
The source of the n-th P-channel MOS transistor is a second metal wiring that constitutes the power supply line via the wiring of the first metal wiring layer to which the source of the n-th P-channel MOS transistor is connected. The semiconductor device according to claim 2, wherein the semiconductor device is connected to a wiring of a layer.
At least one set of the input signal lines is constituted by a second metal wiring layer, and the gate of the MOS transistor of each of the n sets of transistor pairs is a first metal extending in the row direction. The wiring of the second metal wiring layer constituting at least one set of the input signal lines of the input signal lines is connected to the wiring of the second metal wiring layer through the wiring of the wiring layer. Semiconductor device.
The decoder circuit further includes a first inverter and a second inverter,
The first inverter includes at least the (n + 1) th P-channel MOS transistor and the (n + 1) th N-channel MOS transistor,
The second inverter includes at least the n + 2 P-channel MOS transistor and the n + 2 N-channel MOS transistor,
The (n + 1) th P-channel MOS transistor and the (n + 1) th N-channel MOS transistor, and the (n + 2) th P-channel MOS transistor and the (n + 2) th N-channel MOS transistor are arranged in the direction perpendicular to the row direction. ,
The (n + 1) th P-channel MOS transistor and the (n + 2) th P-channel MOS transistor, and the (n + 1) th N-channel MOS transistor and the (n + 2) th N-channel MOS transistor are arranged along the row direction, respectively.
The drain regions of the first to nth N-channel MOS transistors and the first P-channel MOS transistors are connected to the input of the first inverter,
The output wiring of the first inverter is connected to the input wiring of the second inverter, and the output of the second inverter becomes the output of the decoder circuit. 2. The semiconductor device according to claim 1.
The first to nth N-channel MOS transistors are arranged in n rows and 1 column,
The first to nth P-channel MOS transistors are arranged in n rows and 1 column,
2. The semiconductor device according to claim 1, wherein at least one set of input signal lines of the power supply line, the reference power supply line, and the input signal line extends in a direction perpendicular to the row direction.
The sources of the first to nth N-channel MOS transistors are connected to the wiring of the first metal wiring layer,
The source of the nth P-channel MOS transistor is connected to the wiring of the first metal wiring layer,
The power line is constituted by a second metal wiring layer that is higher than the first metal wiring layer,
The reference power line is constituted by the second metal wiring layer,
The source of the first to n-th N-channel MOS transistors is connected to the reference power supply line via the wiring of the first metal wiring layer to which the sources of the first to n-th N-channel MOS transistors are connected. Connected to the wiring of the second metal wiring layer constituting,
The source of the n-th P-channel MOS transistor is a second metal wiring that constitutes the power supply line via the wiring of the first metal wiring layer to which the source of the n-th P-channel MOS transistor is connected. The semiconductor device according to claim 6, wherein the semiconductor device is connected to a wiring of a layer.
At least one set of the input signal lines is constituted by a second metal wiring layer, and the gate of the MOS transistor of each of the n sets of transistor pairs is a first metal extending in the row direction. 8. The wiring of a second metal wiring layer constituting at least one set of input signal lines of the input signal lines is connected to wirings of a second metal wiring layer through wirings of a wiring layer. Semiconductor device.
The decoder circuit further includes a first inverter and a second inverter,
The first inverter includes at least the (n + 1) th P-channel MOS transistor and the (n + 1) th N-channel MOS transistor,
The second inverter includes at least the n + 2 P-channel MOS transistor and the n + 2 N-channel MOS transistor,
The (n + 1) th P-channel MOS transistor and the (n + 1) th N-channel MOS transistor, and the (n + 2) th P-channel MOS transistor and the (n + 2) th N-channel MOS transistor are arranged along the row direction, respectively.
The (n + 1) th P-channel MOS transistor and the (n + 2) th P-channel MOS transistor, and the (n + 1) th N-channel MOS transistor and the (n + 2) th N-channel MOS transistor are arranged in a direction perpendicular to the row direction. ,
The drain regions of the first to n-th N-channel MOS transistors and the first P-channel MOS transistors are connected to the input gate of the first inverter,
The output wiring of the first inverter is connected to the input gate of the second inverter, and the output of the second inverter becomes the output of the decoder circuit. The semiconductor device according to any one of the above.
A decoder comprising a plurality of MOS transistors whose sources, drains and gates are arranged hierarchically in a direction perpendicular to the substrate, wherein at least a × b MOS transistors are arranged in a rows and b columns on the substrate A semiconductor device constituting a circuit,
Each of the plurality of MOS transistors includes:
Silicon pillars,
An insulator surrounding a side surface of the silicon pillar;
A gate surrounding the insulator;
A source region disposed above or below the silicon pillar;
A drain region disposed above or below the silicon pillar, the drain region disposed opposite to the source region with respect to the silicon pillar;
The decoder circuit is at least
1st to n-th n P-channel MOS transistors and 1st to n-th n-channel MOS transistors,
The first to n-th P-channel MOS transistors and the first to n-th N-channel MOS transistors are k-th (k = 1 to n) P-channel MOS transistors and k-th N-channel MOS transistors. Are connected to each other to form n transistor pairs,
Source regions of the first to n-th N-channel MOS transistors and the first P-channel MOS transistors are disposed on the substrate side from the silicon pillar, and the first to n-th N-channel MOS transistors The drain regions of the first P-channel MOS transistors are connected to each other through a contact;
Of the first to nth P-channel MOS transistors, the source of the s (s = 1 to n−1) th P-channel MOS transistor and the drain of the s + 1th P-channel MOS transistor are connected to each other. And
Sources of the first to nth N-channel MOS transistors are respectively connected to a reference power supply line,
A source of the n-th P-channel MOS transistor is connected to a power line;
One input signal line for each of at least one set of input signal lines is connected to the gates of the MOS transistors of each of the n pairs of transistors,
At least one set of input signal lines of the power supply line, the reference power supply line, and the input signal line extends in the same direction.
The first to nth P-channel MOS transistors are arranged in one row and n column,
The first to nth N-channel MOS transistors are arranged in 1 row and n column,
11. The semiconductor device according to claim 10, wherein at least one set of input signal lines of the power supply line, the reference power supply line, and the input signal line extends in a direction perpendicular to the row direction.
Sources of the first to n-th N-channel MOS transistors are connected to wirings of a first metal wiring layer extending in a direction parallel to the row direction,
The source of the nth P-channel MOS transistor is connected to the wiring of the first metal wiring layer,
The power line is constituted by a second metal wiring layer that is higher than the first metal wiring layer,
The reference power line is constituted by the second metal wiring layer,
The source of the first to n-th N-channel MOS transistors is connected to the reference power supply line via the wiring of the first metal wiring layer to which the sources of the first to n-th N-channel MOS transistors are connected. Connected to the wiring of the second metal wiring layer constituting,
The source of the n-th P-channel MOS transistor is a second metal wiring that constitutes the power supply line via the wiring of the first metal wiring layer to which the source of the n-th P-channel MOS transistor is connected. The semiconductor device according to claim 11, wherein the semiconductor device is connected to a wiring of a layer.
At least one set of the input signal lines is constituted by a second metal wiring layer, and the gate of the MOS transistor of each of the n sets of transistor pairs is a first metal extending in the row direction. 13. The wiring of a second metal wiring layer constituting at least one set of input signal lines of the input signal lines is connected to wiring of a second metal wiring layer through wiring of a wiring layer. Semiconductor device.
A plurality of the decoder circuits are arranged in the column direction,
Source regions of adjacent N-channel MOS transistors of adjacent decoder circuits to which the reference power supply line is connected are commonly connected via a silicide region and / or adjacent to which the power supply line is connected. 14. The semiconductor device according to claim 11, wherein source regions of adjacent P-channel MOS transistors of the decoder circuit are commonly connected via a silicide region.
The decoder circuit includes a first inverter and a second inverter,
The first inverter includes at least the (n + 1) th P-channel MOS transistor and the (n + 1) th N-channel MOS transistor,
The second inverter includes at least the n + 2 P-channel MOS transistor and the n + 2 N-channel MOS transistor,
The (n + 1) th P-channel MOS transistor and the (n + 1) th N-channel MOS transistor, and the (n + 2) th P-channel MOS transistor and the (n + 2) th N-channel MOS transistor are arranged in the direction perpendicular to the row direction. ,
The (n + 1) th P-channel MOS transistor and the (n + 2) th P-channel MOS transistor, and the (n + 1) th N-channel MOS transistor and the (n + 2) th N-channel MOS transistor are arranged along the row direction, respectively.
The drain regions of the first to nth N-channel MOS transistors and the first P-channel MOS transistor are connected to the input gate of the first inverter,
15. The output wiring of the first inverter is connected to the input gate of the second inverter, and the output of the second inverter becomes the output of the decoder circuit. The semiconductor device according to any one of the above.
The first inverter includes at least the (n + 1) th P-channel MOS transistor and the (n + 1) th N-channel MOS transistor,
The second inverter includes at least the n + 2 P-channel MOS transistor and the n + 2 N-channel MOS transistor,
The source regions of the first to nth N-channel MOS transistors and the n + 1th N-channel MOS transistor and the source regions of the n + 2 N-channel MOS transistors are connected in common via a silicide region. Connected to the wiring of one metal wiring layer,
The source region of the n-th P-channel MOS transistor, the n + 1-th P-channel MOS transistor, and the source region of the n + 2-th P-channel MOS transistor are connected in common via a silicide region to form a first metal. Connected to the wiring in the wiring layer,
The power line is constituted by a second metal wiring layer that is higher than the first metal wiring layer,
The reference power line is constituted by the second metal wiring layer,
The sources of the first to nth N-channel MOS transistors, the (n + 1) th N-channel MOS transistor, and the (n + 2) th N-channel MOS transistor are the first to n-th N-channel MOS transistors and the source Wiring of the second metal wiring layer constituting the reference power supply line via the wiring of the first metal wiring layer to which the sources of the (n + 1) th N-channel MOS transistor and the (n + 2) th N-channel MOS transistor are connected Connected to
The sources of the nth P channel MOS transistor, the (n + 1) th P channel MOS transistor, and the (n + 2) th P channel MOS transistor are the nth P channel MOS transistor and the (n + 1) th P channel MOS transistor. It is connected to the wiring of the second metal wiring layer constituting the power supply line through the wiring of the first metal wiring layer to which the source of the MOS transistor and the n + 2 P-channel MOS transistor is connected. The semiconductor device according to any one of claims 11 to 15, wherein:
The first to nth P-channel MOS transistors are arranged in n rows and 1 column,
The first to nth N-channel MOS transistors are arranged in n rows and 1 column,
11. The semiconductor device according to claim 10, wherein at least one set of input signal lines of the power supply line, the reference power supply line, and the input signal line extends in a direction perpendicular to the row direction.
The sources of the first to nth N-channel MOS transistors are connected to the wiring of the first metal wiring layer,
The source of the nth P-channel MOS transistor is connected to the wiring of the first metal wiring layer,
The power line is constituted by a second metal wiring layer that is higher than the first metal wiring layer,
The reference power line is constituted by the second metal wiring layer,
The source of the first to n-th N-channel MOS transistors is connected to the reference power supply line via the wiring of the first metal wiring layer to which the sources of the first to n-th N-channel MOS transistors are connected. Connected to the wiring of the second metal wiring layer constituting,
The source of the nth P-channel MOS transistor is a second metal wiring that constitutes the power supply line via a wiring of a first metal wiring layer to which the source of the nth P-channel MOS transistor is connected. The semiconductor device according to claim 17, wherein the semiconductor device is connected to a wiring of a layer.
At least one set of the input signal lines is constituted by a second metal wiring layer, and the gate of the MOS transistor of each of the n sets of transistor pairs is a first metal extending in the row direction. 19. The wiring of a second metal wiring layer constituting at least one set of input signal lines of the input signal lines is connected to wiring of a second metal wiring layer through wiring of a wiring layer. Semiconductor device.
The decoder circuit further includes a first inverter and a second inverter,
The first inverter includes at least the (n + 1) th P-channel MOS transistor and the (n + 1) th N-channel MOS transistor,
The second inverter includes at least the n + 2 P-channel MOS transistor and the n + 2 N-channel MOS transistor,
The (n + 1) th P-channel MOS transistor and the (n + 1) th N-channel MOS transistor, and the (n + 2) th P-channel MOS transistor and the (n + 2) th N-channel MOS transistor are arranged along the row direction, respectively.
The (n + 1) th P-channel MOS transistor and the (n + 2) th P-channel MOS transistor, and the (n + 1) th N-channel MOS transistor and the (n + 2) th N-channel MOS transistor are arranged in a direction perpendicular to the row direction. ,
The drain regions of the first to n-th N-channel MOS transistors and the first P-channel MOS transistors are connected to the input gate of the first inverter,
The output wiring of the first inverter is connected to the input gate of the second inverter, and the output of the second inverter becomes the output of the decoder circuit. The semiconductor device according to any one of the above.
The first inverter includes at least an (n + 1) th P-channel MOS transistor and an (n + 1) th N-channel MOS transistor.
The second inverter includes at least an n + 2 P-channel MOS transistor and an n + 2 N-channel MOS transistor,
Source regions of the (n + 1) th n-channel MOS transistor and the (n + 2) th n-channel MOS transistor are commonly connected via a silicide region and connected to a reference power supply, or the (n + 1) th n-channel MOS transistor 21. The semiconductor according to claim 17, wherein a source region of said n + 2 P-channel MOS transistor is connected in common through a silicide region and connected to a power supply line. apparatus.
A semiconductor device that constitutes a static memory by arranging a plurality of MOS transistors in which sources, drains, and gates are arranged hierarchically in a direction perpendicular to the substrate, on the substrate,
A plurality of static memory cells in which at least six MOS transistors are arranged on an insulating film formed on a substrate are arranged in a matrix,
A plurality of row address circuits for designating one row line of the memory cells;
A plurality of row decoders for selecting one row of the static memory cell by signals from the plurality of row address circuits;
6 MOS transistors constituting the static memory cell;
Each of the plurality of MOS transistors constituting the row decoder is
Silicon pillars,
An insulator surrounding a side surface of the silicon pillar;
A gate surrounding the insulator;
A source region disposed above or below the silicon pillar;
A drain region disposed above or below the silicon pillar, the drain region disposed opposite to the source region with respect to the silicon pillar;
The six MOS transistors constituting the static memory cell are arranged in two rows and three columns,
The row decoder circuit includes at least
N P-channel MOS transistors arranged in one row and n columns, n N-channel MOS transistors arranged in one row and n columns, a first inverter, and a second inverter,
The n P-channel MOS transistors and the n N-channel MOS transistors are the k-th column (k = 1 to n) of the n P-channel MOS transistors arranged in the first row and the n-th column. ) And the gates of the k-th N-channel MOS transistors of the n N-channel MOS transistors arranged in the first row and the n-th column are connected to each other. Form the
The drain regions of the n N-channel MOS transistors and the first column of the P-channel MOS transistors are arranged on the substrate side from the silicon pillar, and the n N-channel MOS transistors and the first column of the first column are disposed. The drain regions of the P-channel MOS transistors of the eyes are connected to each other via a silicide region,
The source of the P-channel MOS transistor in the s-th column (s = 1 to n−1) and the drain of the P-channel MOS transistor in the s + 1-th column are connected to each other,
The sources of the n N-channel MOS transistors are respectively connected to a reference power supply line extending in the direction perpendicular to the row direction, and the source of the P-channel MOS transistor in the nth column is perpendicular to the row direction. Connected to the power line extending in the direction,
The input signals input to the gates of the MOS transistors of the n transistor pairs are respectively supplied by wirings extending in the direction perpendicular to the row direction,
The drains of the n N-channel MOS transistors and the first column of P-channel MOS transistors are connected to the input gate of the first inverter, and the output wiring of the first inverter is the second inverter. A semiconductor device, wherein the output wiring of the second inverter is connected to a row selection line of the static memory cell.
The sources of the n N-channel MOS transistors are connected to the wiring of the first metal wiring layer,
The source of the n-th column P-channel MOS transistor is connected to the wiring of the first metal wiring layer,
The power line is constituted by a second metal wiring layer that is higher than the first metal wiring layer,
The reference power line is constituted by the second metal wiring layer,
The source of the n N-channel MOS transistors is a second metal that constitutes the reference power supply line via the wiring of the first metal wiring layer to which the sources of the n N-channel MOS transistors are connected. Connected to the wiring in the wiring layer,
The source of the n-th column P-channel MOS transistor constitutes the power supply line via the wiring of the first metal wiring layer to which the source of the n-th column P-channel MOS transistor is connected. Connected to the wiring of the metal wiring layer of 2,
At least one set of the input signal lines is constituted by a second metal wiring layer, and the gate of the MOS transistor of each of the n sets of transistor pairs is a first metal extending in the row direction. 23. The semiconductor device according to claim 22, wherein the semiconductor device is connected to a wiring of a second metal wiring layer constituting at least one set of the input signal lines of the input signal lines via a wiring of a wiring layer.
A semiconductor device that constitutes a static memory by arranging a plurality of MOS transistors in which sources, drains, and gates are arranged hierarchically in a direction perpendicular to the substrate, on the substrate,
A plurality of static memory cells in which at least six MOS transistors are arranged on an insulating film formed on a substrate are arranged in a matrix,
A plurality of row address circuits for designating one row line of the memory cells;
A plurality of row decoders for selecting one row of the static memory cell by signals from the plurality of row address circuits;
6 MOS transistors constituting the static memory cell;
Each of the plurality of MOS transistors constituting the row decoder is
Silicon pillars,
An insulator surrounding a side surface of the silicon pillar;
A gate surrounding the insulator;
A source region disposed above or below the silicon pillar;
A drain region disposed above or below the silicon pillar, the drain region disposed opposite to the source region with respect to the silicon pillar;
The six MOS transistors constituting the static memory cell are arranged in two rows and three columns,
The row decoder circuit includes at least
N P-channel MOS transistors arranged in one row and n columns, n N-channel MOS transistors arranged in one row and n columns, a first inverter, and a second inverter,
The n P-channel MOS transistors and the n N-channel MOS transistors are the k-th column (k = 1 to n) of the n P-channel MOS transistors arranged in the first row and the nth column. The gates of the N-channel MOS transistors in the k-th column of the P-channel MOS transistors and the n N-channel MOS transistors arranged in the first row and the n-th column are connected to each other. Forming,
The source regions of the n N-channel MOS transistors and the first column of the P-channel MOS transistors are arranged on the substrate side from the silicon pillar, and the n N-channel MOS transistors and the first column of the first column are disposed. The drain regions of the P-channel MOS transistors of the eyes are connected to each other through contacts,
The source of the P-channel MOS transistor in the s-th column (s = 1 to n−1) and the drain of the P-channel MOS transistor in the s + 1-th column are connected to each other,
The sources of the n N-channel MOS transistors are respectively connected to a reference power supply line extending in the direction perpendicular to the row direction, and the source of the P-channel MOS transistor in the nth column is perpendicular to the row direction. Connected to the power line extending in the direction,
Input signals input to the gates of the MOS transistors of each of the n pairs of transistors are respectively supplied by wirings extending in the direction perpendicular to the row direction,
The drains of the n N-channel MOS transistors and the first column of P-channel MOS transistors are connected to the input gate of the first inverter, and the output wiring of the first inverter is the second inverter. A semiconductor device, wherein the output wiring of the second inverter is connected to a row selection line of the static memory cell.
Sources of the n N-channel MOS transistors are connected to wiring of a first metal wiring layer extending in a direction parallel to the row direction,
The source of the n-th column P-channel MOS transistor is connected to the wiring of the first metal wiring layer,
The power line is constituted by a second metal wiring layer that is higher than the wiring layer of the first metal wiring layer,
The reference power line is constituted by the second metal wiring layer,
The source of the n N-channel MOS transistors is a second metal that constitutes the reference power supply line via the wiring of the first metal wiring layer to which the sources of the n N-channel MOS transistors are connected. Connected to the wiring in the wiring layer,
The source of the n-th column P-channel MOS transistor constitutes the power supply line via the wiring of the first metal wiring layer to which the source of the n-th column P-channel MOS transistor is connected. Connected to the wiring of the metal wiring layer of 2,
At least one set of the input signal lines is constituted by a second metal wiring layer, and the gate of the MOS transistor of each of the n sets of transistor pairs is a first metal extending in the row direction. 25. The semiconductor device according to claim 24, wherein the semiconductor device is connected to a wiring of a second metal wiring layer constituting at least one set of input signal lines of the input signal lines via a wiring of a wiring layer.