JP6070848B2 - Information processing apparatus, data transfer apparatus, data transfer method, and control apparatus - Google Patents

Description

  The present invention relates to an information processing device, a data transfer device, a data transfer method, and a control device.

  In communication between devices in an information processing system (information processing device) using a computer such as a server or a personal computer (PC), data is transferred from a plurality of transmission source devices to one transmission destination device. There is. Here, as the device, an integrated circuit such as a large scale integration (LSI), for example, a processor or memory such as a central processing unit (CPU), an input / output (I / O) device, a memory controller, an I / O controller, or the like Is mentioned. Hereinafter, the apparatus is also referred to as an LSI. In such an information processing system, a data transfer device such as a crossbar, which is an example of a mechanism for selecting and arbitrating data to be transferred, may be used to connect a plurality of devices to each other.

The data transfer device selects a source from which data is transferred when data is input from a plurality of sources, and first-in first-out (first in first out) data not selected by the control circuit. FIFO) can be provided for storing queues.
As a related technique, a network transfer apparatus capable of different redundant configurations is known (see, for example, Patent Document 1). For example, when a failure occurs in the crossbar switch connected to the packet transmission destination, the network transfer apparatus can stop packet transmission from the packet transmission source to the sub crossbar switch. When there is no packet in the crossbar switch and sub-crossbar switch, this network transfer device can switch the connection between the output buffer and the port in the sub-crossbar switch and connect the sub-crossbar switch to the standby crossbar switch. it can.

  As another related technique, a crossbar having one or more input queues for each transfer destination (output port) is known (see, for example, Patent Document 2). This crossbar can include, for example, an input queue group in which input queues are arranged in multiple stages for each input port, and input queues are arranged for each output port of the data transfer destination.

JP 2004-260368 A JP 2006-39677 A International Publication No. 2010/103610 Pamphlet

In the data transfer to the counter LSI facing (connected) to the output port, the data transfer device transfers data to the counter LSI (transfer destination) due to a failure or congestion in the transfer path to the counter LSI or the counter LSI. Transfer may fail.
If there are a plurality of transfer paths from the data transmission source to the transmission destination, and the data reaches the transmission destination even if the data transfer device transfers data to any of the two or more opposing LSIs, the data transfer device It is also conceivable to transfer data via another output port as a detour.

  However, in the above-described data transfer apparatus having an input queue (buffer) for each transfer destination (output port), it may be difficult to transfer data via another output port as a detour. The reason is that the data transfer apparatus described above can transfer data stored in the input queue to an output port corresponding to another counter LSI because the input queue and output port are associated with one counter LSI. This is because it may be difficult.

As described above, in a data transfer apparatus having an input queue (storage unit) for each transfer destination, even when there are a plurality of transfer paths from the data transmission source to the transmission destination, data transfer becomes difficult due to a failure or congestion. There is a problem that it may become.
Up to this point, the device has been described as an LSI (integrated circuit) such as a processor, memory, and various controllers. However, the above-described problem is not limited to communication between these LSIs (integrated circuits). The problem described above is that the device is, for example, a computer such as a system board having a CPU and a memory, an I / O board, a network interface, and the like, and the data transfer device is a device that transfers data between these devices. It can occur as well.

In one aspect, an object of the present invention is to reliably transfer data even if a failure or congestion of the data transfer destination occurs.
In addition, the present invention is not limited to the above-described object, and other effects of the present invention can be achieved by the functions and effects derived from the respective configurations shown in the embodiments for carrying out the invention which will be described later. It can be positioned as one of

Present information processing apparatus, a source device that transmits data, a destination device for receiving the data transmitted from the transmission source device, 1 a or more data transfer device, Ru provided with a. The one or more data transfer devices are interposed between the transmission source device and the transmission destination device, and the data is transmitted from the transmission source device to the transmission destination via any one of a plurality of different transfer paths. Transfer to device. The data transfer device includes a plurality of storage units, a switching unit, a control unit, a reception storage unit, and a suppression unit. The plurality of storage units store input transfer data for each transfer destination including the transmission destination device or another data transfer device connected to the own data transfer device . The switching unit, the transfer data stored in said plurality of storage portions, and outputs selectively switches to one of said plurality of transfer destination. The control unit, from said switching unit depending on the state of the data transfer to one destination through one of the transfer path, the transfer destination of the one stored in the storage unit corresponding to the one destination An alternative output process is performed to control the switching unit so that the transfer data is output to other transfer destinations included in the plurality of different transfer paths. The reception storage unit collectively stores transfer data stored in the plurality of storage units. The suppression unit suppresses storage of the transfer data stored in the reception storage unit in the plurality of storage units according to a state of data transfer to the plurality of transfer destinations.

  According to an embodiment, data can be reliably transferred even if a failure or congestion of the data transfer destination occurs.

It is a figure showing an example of an information processing system concerning one embodiment. It is a figure which shows the structural example of the information processing system shown in FIG. It is a figure which shows the structure of the crossbar as contrast of the crossbar which concerns on one Embodiment. It is a figure which shows the structure of the crossbar as contrast of the crossbar which concerns on one Embodiment. It is a figure which shows the detailed structural example of the information processing system shown in FIG. It is a figure which shows an example of the data structure of the routing table which the crossbar shown in FIG. 5 hold | maintains. It is a figure which shows an example of the data structure of the management information which the management part shown in FIG. 5 hold | maintains. It is a figure which shows the hardware structural example of the management part shown in FIG. FIG. 6 is a flowchart for explaining an operation example of a retransmission process at a reception port of the crossbar shown in FIG. 5. FIG. 6 is a flowchart for explaining an operation example of retransmission processing at an input port of the crossbar shown in FIG. 5. 6 is a flowchart for explaining an operation example of routing table update processing in the management unit shown in FIG. 5. It is a figure which shows the Example of a structure of the reception port shown in FIG. It is a figure which shows the Example of a structure of the input port shown in FIG. It is a figure explaining an example of the control method of the input queue in the input port shown in FIG. It is a figure which shows an example of the timing chart in the input port shown in FIG. It is a figure which shows the Example of a structure of the output port shown in FIG. It is a figure which shows the data structure of the routing table which concerns on the 1st modification of one Embodiment. It is a figure which shows the data structure of the routing table which concerns on the 2nd modification of one Embodiment. It is a figure which shows the structure of the resending state machine which concerns on the 3rd modification of one Embodiment.

Hereinafter, embodiments will be described with reference to the drawings.
[1] One Embodiment [1-1] Configuration Example of Information Processing System First, a configuration example of an information processing system 1 as an example of an embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a diagram illustrating an example of an information processing system 1 according to an embodiment, and FIG. 2 is a diagram illustrating a configuration example of the information processing system 1 illustrated in FIG.

As illustrated in FIG. 1, the information processing system 1 includes a crossbar unit 20, a plurality of (six in the example illustrated in FIG. 1) devices 3, and a management unit 4.
The device 3 has at least one function of a transmission source device that transmits data and a transmission destination device that receives data transmitted from the transmission source device. In the example illustrated in FIG. 2, the devices 3D to 3F have the function of the transmission source device, and the devices 3A to 3C have the function of the transmission destination device.

The devices 3D to 3F serving as the transmission source devices can transmit the data to be transmitted by dividing the data into frames or packets (hereinafter collectively referred to simply as frames). At this time, the devices 3D to 3F can add information (destination information) for specifying the transmission destination devices (3A to 3C) to each frame to be transmitted.
The devices 3A to 3C as the transmission destination devices can receive frames from the transmission source devices 3D to 3F via the crossbar unit 20, and can acquire data transmitted by the transmission source devices 3D to 3F from the received frames.

  The device 3 includes an integrated circuit such as an LSI, for example, a processor such as a CPU, a memory, an I / O device, a memory controller, an I / O controller, and the like. Further, as the device 3, for example, various devices such as a system board having a CPU and a memory, an I / O board having an I / O controller, a card slot, a storage device, etc., or a server, a PC, a storage device, etc. And other computers.

  The crossbar unit 20 is interposed between the plurality of devices 3 and transfers the data transmitted from the data transmission source devices 3D to 3F to the transmission destination devices 3A to 3C. The crossbar unit 20 can include one or more crossbars 2 (crossbar group). Hereinafter, the crossbar unit 20 will be described as including nine crossbars 2A to 2I (shown simply by reference numeral 2 in the following description when the crossbars 2A to 2I are not distinguished) as illustrated in FIG.

The plurality of crossbars 2 are interposed between the transmission source devices 3D to 3F and the transmission destination devices 3A to 3C, and each of them is connected to one or more other crossbars 2 so as to communicate with each other. The plurality of crossbars 2 transfer data (frames) from the transmission source devices 3D to 3F to the transmission destination devices 3A to 3C via any one of a plurality of different transfer paths.
Hereinafter, the transfer route includes a route through one or more crossbars 2 and one or more data paths (transfer routes) between the transmission source devices 3D to 3F and the transmission destination devices 3A to 3C. Examples of the transfer path include various buses including a system bus, cables such as Local Area Network (LAN), Fiber Channel, and InfiniBand, or a wireless communication path. In addition, the plurality of different transfer paths include a plurality of paths in which at least one of the crossbar 2 and the data path that pass through is different from each other. Further, hereinafter, as the transfer destination, there is an opposing LSI facing the output port of the crossbar 2, that is, an opposing LSI including the transmission destination devices 3A to 3C or the crossbar 2 connected to the output port via the data path (transfer path). included.

The management unit 4 is connected to each of the plurality of crossbars 2 so as to be communicable with each other, and manages a routing table provided by each crossbar 2. Details of the management unit 4 will be described later.
[1-2] Crossbar Comparison The crossbars 200A and 200B as the crossbar 2 comparison will be described with reference to FIGS. FIG. 3 and FIG. 4 are diagrams each showing a configuration of the crossbars 200A and 200B as a cross-proportional of the crossbar 2 according to the embodiment. The crossbars 200A and 200B can be applied to the information processing system 1 instead of the crossbar 2 shown in FIG. Hereinafter, description will be made by taking the three-input three-output crossbars 200A and 200B (corresponding to the crossbars A to C and G to I shown in FIG. 2) as an example.

As illustrated in FIG. 3, the crossbar 200 </ b> A includes a plurality of reception ports 500, input ports 600 </ b> A, output ports 800, and connection units 900 (three each in the example of FIG. 3) and one routing unit 700. I have it.
In FIG. 3, for simplification of the drawing, one configuration example of each of the reception port 500, the input port 600A, the output port 800, and the connection unit 900 is illustrated, but the other reception ports 500, input ports 600A, The same applies to the output port 800 and the connection unit 900.

  The reception port 500 includes a holding unit 510 such as a memory or a register. Examples of the memory include volatile memory such as Random Access Memory (RAM). The holding unit 510 holds a routing table 520 in which destination information and information for specifying the output port 800 such as the number of the output port 800 are associated with each other. The reception port 500 searches the routing table 520, specifies the output port 800 that outputs the frame from the destination information included in the input frame, and outputs the frame and the information of the specified output port 800 to the input port 600A. To do. Note that the routing table 520 may be registered and updated by the management unit 4.

The input port 600A has an input queue 610A used in common for all destinations (transfer destinations), and stores data input from the reception port 500 in the input queue 610A. The input queue 610A may have a FIFO data structure.
The routing unit 700 connects between the input queue 610A in each input port 600A and each output queue 810 in each output port 800, and outputs a frame input from the input queue 610A to the routing unit 700 as a corresponding output. Output to the queue 810.

  The output port 800 includes a plurality (three in the example of FIG. 3) of output queues 810 and selectors 820 corresponding to a plurality of transmission sources. The output queue 810 can have a FIFO data structure similar to the input queue 610A. The output port 800 selects the top frame of the input queue 610A and stores it in the output queue 810 via the routing unit 700. If the head frame of the input queue 610A is not selected by the output port 800, neither the head frame nor the subsequent frame is output to the transfer destination output port 800.

The connection unit 900 is connected to a transfer destination counter LSI by wiring, a cable, a socket, or the like, and transfers a frame output from the output port 800.
As illustrated in FIG. 4, the crossbar 200B includes an input port 600B different from the input port 600A of the crossbar 200A shown in FIG.
The input port 600B has an input queue 610B for each destination (transfer destination), and distributes and stores frames input from the reception port 500 to the input queue 610B for each transfer destination based on the information of the output port 800. Each input queue 610B can have a FIFO data structure in the same manner as the input queue 610A. Since the configuration other than the input port 600B is the same as that of the crossbar 200A, detailed description thereof is omitted.

  With the configuration described above, the crossbar 200B has the same number of transfer destinations as the beginning of the input queue 610B, so that the frame selection at the output port 800 can be performed in parallel. Therefore, in the crossbar 200B, since the first frame is not selected, a subsequent frame addressed to the other output port 800 is not waited. Therefore, an improvement in throughput can be expected as compared with the crossbar 200A shown in FIG.

  In the example shown in FIGS. 3 and 4, the output port 800 includes a plurality of output queues 810, but these output queues 810 may be omitted. Further, the crossbars 200A and 200B improve the latency when the entries of the input queues 610A and 610B in the input ports 600A and 600B and / or the output queue 810 in the output port 800 are empty. May be bypassed.

  By the way, the crossbars 200A and 200B have a retry function for holding the data output to the opposite LSI (transfer destination) in the output queue 810 of the output port 800, and when an error occurs in the data transfer, the data transfer is retried. Can also be performed. Possible causes of errors include continuous failures (fixed failures) such as disconnection of wiring between LSIs and failure of devices that relay data, temporary failures due to neutron hits to LSIs, electromagnetic waves, heat, etc. (Intermittent failure).

Even if an error due to an intermittent failure occurs in the data transfer, the crossbars 200A and 200B may be able to avoid the error by retrying the data transfer by the retry function and succeeding in the data transfer after the natural recovery from the intermittent failure.
On the other hand, if an error due to a fixed failure occurs in data transfer, the crossbars 200A and 200B can return data to the opposing LSI without any error or loss if the fixed failure is not addressed even if retrying the data transfer between the LSIs. It may be difficult to transfer. The same applies when data transfer is busy or congestion occurs due to congestion between LSIs. That is, it is difficult for the crossbars 200A and 200B to switch the data from the input queue 610A or 610B corresponding to the opposite LSI that is congested in data transfer to the output port 800 corresponding to another available opposite LSI.

  For the crossbar 200A, when a fixed failure and congestion occur, an error may be avoided by providing the following functions. For example, the crossbar 200A may not release the frame from the input queue 610A only by transmitting the frame from the input queue 610A to the output port 800. As an example, the crossbar 200A may release the frame from the input queue 610A when the counter LSI of the output port 800 has confirmed that the frame has been correctly received. Note that the opposing LSI can notify the crossbar 200A whether or not the LSI has correctly received the frame by, for example, returning a reception confirmation signal (Acknowledge signal) when one frame is correctly received. .

  If a failure occurs in the connection between a certain output port 800 and the opposing LSI and the crossbar 200A cannot transmit a frame correctly, the crossbar 200A temporarily stops data transfer to the path where the failure has occurred. Can do. Then, the management unit 4 dynamically updates the routing table 520 without stopping the entire information processing system 1, and the output port 800 may transfer the frame stored in the input queue 610A to the detour. As a result, the crossbar 200A can transfer the frame to the destination without losing the frame.

  However, as described above, the crossbar 200A shown in FIG. 3 has a lower throughput than the crossbar 200B shown in FIG. Therefore, it is desirable that the crossbar 200B also dynamically updates the routing table 520 to transfer the frame to the detour as in the crossbar 200A. However, in the crossbar 200B, since the input queue 610B of the input port 600B is divided for each transfer destination, it is difficult to transfer a frame already stored in each input queue 610B to the detour.

  Therefore, the information processing system 1 as an example of the embodiment can dynamically change the transfer path in the throughput-enhanced crossbar 2 having an input queue for each transfer destination like the crossbar 200B illustrated in FIG. To do. That is, as will be described in detail below, the information processing system 1 as an example of an embodiment includes a crossbar 2 and transfers data when there are a plurality of transfer paths from the data transmission source to the transmission destination. Even if the previous failure or congestion occurs, data can be transferred reliably.

[1-3] Transfer Route Changing Method in Information Processing System Returning to the description of FIG. 2, the transfer route changing method in the information processing system 1 will be described. For convenience, as shown in FIG. 2, the crossbars 2A to 2I may be referred to as crossbars A to I, and the devices 3A to 3F may be referred to as devices A to F.
As shown in FIG. 2, the information processing system 1 can connect the LSIs so that there are a plurality of transfer paths that pass through the LSIs for data transfer. For example, each of the plurality of devices 3 is connected to one different crossbar 2, and each of the plurality of crossbars 2 is connected to two to four other crossbars 2. In addition, it is preferable that the LSIs (between the device 3 and the crossbar 2 and between the two crossbars 2) are electrically connected so as to be capable of bidirectional communication. That is, it is preferable that the input port of one LSI and the output port of the other LSI are electrically connected, and the output port of one LSI and the input port of the other LSI are electrically connected.

The information processing system 1 (crossbar 2) stops data transfer between the corresponding LSIs and performs data transfer via different transfer paths in any of the following cases (a) to (c) (data transfer) Continue).
(A) The error is not resolved even if the crossbar 2 retries data transfer between LSIs a predetermined number of times.

(B) When the crossbar 2 outputs a frame but does not receive a frame reception completion notification from the transmission destination LSI and times out.
(C) The output port of the crossbar 2 is congested compared to the output port of the detour.
For example, in the information processing system 1 shown in FIG. 2, the routing table of each crossbar 2 is set by the management unit 4 so that the transfer paths from the transmission source devices 3D to 3F to the transmission destination devices 3A to 3C are the following transfer routes. Assume that it is set.

Device D-Crossbar G-Crossbar D-Crossbar A-Device A (shortest path)
When the wiring between the crossbar G and the crossbar D fails, the information processing system 1 cannot transfer data to the device A via the shortest path. Therefore, the information processing system 1 (management unit 4) changes the transfer route so that the number of crossbars 2 (the number of hops) that pass through becomes one of the following, which is the second smallest after the shortest route, thereby transferring the data to the device A Can be transferred. Note that the number of crossbars 2 that pass through increases and the data arrival time to the device A takes longer, but the information processing system 1 may select transfer paths other than the following two.

Device D-Crossbar G-Crossbar H-Crossbar E-Crossbar D-Crossbar A-Device A
Device D-Crossbar G-Crossbar H-Crossbar E-Crossbar B-Crossbar A-Device A
The information processing system 1 only needs to be able to switch the frame addressed to the device A input to the crossbar G from the transfer to the crossbar D to the transfer to the crossbar H in order to change the transfer path described above. The frame addressed to the device A input to the crossbar H is transferred to the crossbar E according to the setting of the crossbar H routing table. The frame addressed to the device A input to the crossbar E is transferred to either the crossbar D or the crossbar B according to the setting of the crossbar E routing table. Thus, each crossbar 2 routes a frame addressed to the device A (destination device) so as to go to the device A. That is, the information processing system 1 (management unit 4) does not need to change the routing table other than the crossbar G even if the wiring between the crossbar G and the crossbar D fails.

  The crossbar 2 (information processing system 1), which is described in detail below as an example of the embodiment, is applied to at least the crossbar G, for example, so that even if the wiring between the crossbar G and the crossbar D breaks down, the device D to the device The data transfer path to A can be changed. 2 can all have the same configuration, the crossbar 2 may be applied to any crossbars A to I. By applying the crossbar 2 to all of the crossbars A to I, it is possible to change the communication transfer path between the devices 3 even if any crossbar 2 fails.

[1-4] Configuration Example of Crossbar Hereinafter, a configuration example of the information processing system 1 (particularly the crossbar 2) as an example of an embodiment will be described with reference to FIGS. 5 and 6. FIG. 5 is a diagram showing a detailed configuration example of the information processing system 1 shown in FIG. 2, and FIG. 6 is a diagram showing an example of the data structure of the routing table 53 in the crossbar 2 shown in FIG. In addition, illustration of the apparatus 3 is abbreviate | omitted in FIG.

  The crossbar 2 is an example of a data transfer apparatus that transfers an input frame (transfer data) to a transfer destination counter LSI. Examples of the data transfer device include an integrated circuit, for example, an electronic circuit having a function as the crossbar 2, such as an LSI, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). Note that when the device 3 is a device such as the CPU, memory, I / O device, or various controllers described above, an L1 crossbar switch may be used as the crossbar 2. In the following description, as before, the device 3 facing or connected to the output port of the crossbar 2, the other crossbar 2, etc. are collectively referred to as an LSI or a counter LSI. The crossbar 2 may be one integrated circuit or a combination of a plurality of integrated circuits. The crossbar 2 may be incorporated in an integrated circuit such as a processor such as a CPU, a memory, an I / O device, and various controllers, and the mounting location is not particularly limited. The device 3 may be a device such as a system board or an I / O board. In this case, an L2 crossbar switch may be used as the crossbar 2.

Hereinafter, the crossbar 2 having three inputs and three outputs (crossbars A to C and G to I shown in FIG. 2) will be described as an example, but the crossbar 2 having four inputs and four outputs (crossbars D to F shown in FIG. 2). Can be configured similarly.
As illustrated in FIG. 5, the crossbar 2 includes a plurality of reception ports 5, input ports 6, output ports 8, and connection units 9 (three in the example of FIG. 5), and one routing unit 7. I have it. When the configuration according to the embodiment is applied to the 4-input 4-output crossbar 2, four reception ports 5, input ports 6, output ports 8, and connection portions 9 may be provided. Hereinafter, for convenience, as shown in FIG. 5, the input port 6 is specified by any one of the input ports A to C, the input queue 61 is specified by any one of the input queues A to C, and the output port 8 is specified by the output port A. May be specified and described in any one of -C. Further, in FIG. 5, for the sake of simplification, one configuration example of each of the reception port 5, the input port 6, the output port 8 (output port A), and the connection unit 9 is illustrated. The same applies to the input port 6, the output port 8 (output ports B and C), and the connection unit 9.

  The output port 8 includes a plurality of (three in the example of FIG. 5) output queues 81 corresponding to a plurality of transmission sources and a selector 82. Unless otherwise stated, the basic functions of the output port 8 (output queue 81 and selector 82) are the same as those of the output port 800 (output queue 810 and selector 820) shown in FIG. The plurality of output ports 8 are an example of a plurality of output units provided for each of the transfer destinations 2 and 3 and outputting a frame to the transfer destination of the frame.

Further, the output queue 81 can have a retry function. The output queue 81 can have a FIFO data structure. Examples of the output queue 81 include a circuit capable of high-speed read / write operations such as a high-speed volatile memory such as a static RAM (SRAM) and a logic circuit such as a flip-flop and a latch.
The output port 8 is used when the error is not resolved even if data transfer between LSIs is retried a certain number of times, or when a frame is transmitted but a time-out occurs without an Acknowledge signal being sent from the opposite LSI. It can be determined that a failure has occurred in the wiring. The output port 8 can determine that data transfer between LSIs is congested when the frame transmission frequency exceeds a specified value or is higher than the other output port 8.

  When an error is detected in the data transfer from the output port 8 to the opposite LSI, the output port 8 attempts to retransmit (retry) a plurality of frames in the hope that the error that has occurred is due to an intermittent failure. If an error is detected even after retransmitting more than the specified number of times, the output port 8 can be determined to be a fixed failure for the time being, and the own output port 8 can be blocked. Note that the output port 8 can block the own output port 8 even when the occurrence of congestion is detected. When the output port 8 closes the own output port 8, the output port block signal (output) indicating that the own port (output port 8) is closed to all the input ports 6, the reception port 5, and the management unit 4 (Suppression signal) is output. That is, the output port 8 (output queue 81) outputs an output suppression signal according to the state of data transfer to the corresponding transfer destination.

  Note that the output port 8 may determine whether or not to reuse the own output port 8, and may include information on the presence or absence of reuse in the output port block signal. For example, the output port 8 may determine that there is no reuse when it is determined that the error is due to a fixed failure, and may determine that there is reuse when it detects congestion. Even if the error is due to a fixed failure, if there is a possibility that the error will be resolved by dynamic replacement of the failure location, it may be determined that there is reuse. The determination of whether or not the output port 8 is reused is not limited to these, and may be performed based on various conditions. For example, the output port 8 may determine whether or not the own output port 8 is reused based on the content of the detected error, the congestion status, the operation rule of the information processing system 1, and the like.

Note that the output port 8 may perform a synchronous reset while the output port 8 is closed. Further, when the output port 8 receives the output port blockage release signal from the input port 6, the output port 8 can release the synchronous reset so that the output port 8 can be reused, and can prepare for reuse.
The connection unit 9 is connected to a transfer destination counter LSI by wiring, a cable, a socket, or the like, and transfers a frame output from the output port 8.

The reception port 5 includes a reception queue 51, a holding unit 52, and a frame transmission determination circuit 54. Unless otherwise mentioned, the basic function of the reception port 5 is the same as that of the reception port 500 shown in FIG.
The reception queue 51 stores the frames stored in the plurality of input queues 61 in a lump and is an example of a reception storage unit. The reception queue 51 can have a FIFO data structure in the same manner as the output queue 81. As the reception queue 51, a circuit capable of performing a high-speed read / write operation, like the output queue 81, can be cited.

The holding unit 52 holds a routing table 53 in which destination information and information for specifying the output port 8 such as the number of the output port 8 are associated with each other. Examples of the holding unit 52 include a storage device such as a memory or a register. As the memory, for example, a volatile memory such as a RAM can be used.
Here, an example of the data structure of the routing table 53 will be described with reference to FIG. As illustrated in FIG. 6, the routing table 53 is set with information of any output port 8 of the crossbar 2 that holds the routing table 53 with the final transmission destination (destination) of data as an input (entry). It is a table to be.

  Specifically, the routing table 53 includes a bit indicating validity (for example, “0”) or invalidity (for example, “1”) of the entry of the routing table 53, destination information of the data transmission destination, and the normal output port 8. Information may be included. Further, the routing table 53 includes a bit indicating validity (for example, “0”) or invalidity (for example, “1”) of one or more detour output ports 8 for an entry having the detour output port 8 and for detouring. The output port 8 information may be included. For example, in the entry of the transmission destination A, the output port A is set to the normal output port 8, the output port B is set to the first candidate detour output port 8, and the output port C is set to the second candidate detour output port 8. Is done.

In the routing table 53, the validity / invalidity of the entry is set to valid when, for example, the transmission destination devices 3A to 3C are communicable, and the transmission destination devices 3A to 3C cannot communicate due to a failure or the like. In this case, it is disabled. The validity / invalidity of the bypass output port 8 indicates whether or not the corresponding bypass output port 8 is valid.
The bypass output port 8 is used when a failure or congestion occurs between the normal output port 8 and the opposing LSI in the order of the first candidate and the second candidate (in order of priority). Whether the bypass output port 8 is set as the first candidate or the second candidate may be determined according to the priority order based on the number of LSIs through which the bypass output port 8 is set, or the bypass output port 8 is used. May be determined in the order in which congestion is unlikely to occur due to the relationship with the output port 8 of another transmission destination.

The routing table 53 is registered and updated by the management unit 4 described later.
As described above, in the routing table 53 illustrated in FIG. 6, the output port 8 corresponding to the detour (transfer destination) is set for each frame (for each transmission destination). That is, the routing table 53 is an example of transfer destination information regarding one or more transfer destinations of a frame. More specifically, it can be said that the routing table 53 illustrated in FIG. 6 is an example of transfer destination information regarding one or more transfer destinations corresponding to the frame transmission destination devices 3A to 3C.

  Returning to the description of FIG. 5, the frame transmission determination circuit 54 sequentially outputs the frames stored in the reception queue 51 to the corresponding input queue 61. When the frame transmission determination circuit 54 receives the output port block signal from the output port 8, the frame transmission determination circuit 54 receives a plurality of input queues 61 of frames stored in the reception queue 51 until it receives a frame transmission restart instruction signal from the retransmission state machine 63. Control to suppress output to. As a result, even when the reception port 5 receives an output port block signal in the middle of outputting the frame to the input queue 61, the reception port 5 stops outputting the frame to the input queue 61 at a frame delimiter that is the minimum unit of data transfer. be able to. Therefore, since the input port 6 can switch the transfer path, which will be described later, at a frame break, it is possible to avoid data loss due to frame damage or the like.

  That is, the frame transmission determination circuit 54 outputs the frames stored in the reception queue 51 to the input queue 61 from the completion of the output of the frame being output from the reception queue 51 until the retransmission processing by the retransmission state machine 63 is completed. It is an example of the reception control part which suppresses an output. The reception port 5 is an example of a suppression unit that suppresses storage of input frames in a plurality of input queues 61.

The input port 6 includes three input queues 61, a selector 62, a retransmission state machine 63, and a bypass output port management circuit 64. Unless otherwise stated, the basic function of the input port 6 (input queue 61) is the same as that of the input port 600B (input queue 610B) shown in FIG.
As with the output queue 81, the input queue 61 can have a FIFO data structure. As the input queue 61, like the output queue 81, a circuit that can perform high-speed read / write operations can be used. The plurality of input queues 61 are an example of a plurality of storage units that store input frames for each transmission destination (crossbar 2 or device 3) including the transmission destination devices D to F or the crossbar 2 connected to the own crossbar 2. is there.

  The selector 62 is provided on the output side of each input queue 61 of the input port 6. The selector 62 is an example of a switching unit that selectively switches and outputs frames stored in the plurality of input queues 61 to any one of a plurality of transfer destinations (output ports 8). An example of the selector 62 is a circuit such as a bus switch. In the example illustrated in FIG. 5, the selector 62 is provided for each output port 8, and each selector is connected to the three input queues 61 and the corresponding output port 8 by wiring. As a result, it is possible to cope with a change in the transfer destination of the frame held in the input queue 61.

  The selection logic of the selector 62 may be such that the output port 8 is selected for each frame. For this purpose, the following logic circuits (i) and (ii) that are not required unless the transfer path is changed are used. Will be used. When these logic circuits are added to the crossbar 2, the logic circuit of the input port 6 becomes complicated, and the amount of the circuit, delay time, occurrence frequency of delay, and the like may increase.

(I) A logic circuit that determines the separation between frames.
(Ii) A logic circuit that performs arbitration such as Least Recently Used (LRU).
Therefore, in one embodiment, for example, the frame transmission determination circuit 54 and the retransmission state machine 63 are added to the crossbar 2 without adding the logic circuits (i) and (ii) described above. The transfer path can be changed with a simple logic circuit.

  The retransmission state machine 63 is a logic circuit that controls the crossbar 2 and the management unit 4 from the reception of the output port block signal from the output port 8 to the transmission of the frame transmission restart instruction signal to the reception port 5. In FIG. 5, one retransmission state machine 63 is illustrated in one input port 6, but it is preferable that a retransmission state machine 63 is provided for each input queue 61.

For example, the retransmission state machine 63 manages the state of the crossbar 2 using a bit value (register value) of a register or the like, and changes the register value in the following cases (I) to (V). The retransmission state machine 63 realizes control of each circuit and the management unit 4 by making each circuit and the management unit 4 in the crossbar 2 refer to the register value or giving an instruction according to the register value.
(I) In the normal operation state of the crossbar 2 (register value “3′b000”), the retransmission state machine 63 receives the output port block signal from the output port 8. At this time, the register value of the retransmission state machine 63 corresponding to the output port (hereinafter also referred to as a blocked port) 8 that has output the output port blocked signal transitions to “3′b001”.

(II) The retransmission state machine 63 receives a signal indicating that frame transmission from the reception port 5 to the input port 6 has been stopped. At this time, the register value of the retransmission state machine 63 corresponding to the blocked port 8 transitions to “3′b010”.
(III) The input port 6 transmits the frame in the input queue 61 addressed to the detour output port (hereinafter also referred to as alternative port) 8 to the corresponding output port 8. When all the frames in the input queue 61 addressed to the alternative port 8 are transmitted and arrival at the opposite LSI is confirmed, the register value of the retransmission state machine 63 corresponding to the blocked port 8 transitions to “3′b011”.

(IV) The input port 6 transmits a frame in the input queue 61 addressed to the blocked port 8 to the alternative port 8 by controlling the selector 62. When all the frames in the input queue 61 addressed to the blocked port 8 are transmitted and arrival at the opposite LSI is confirmed, the register value of the retransmission state machine 63 corresponding to the blocked port 8 transitions to “3′b100”.
(V) The retransmission state machine 63 notifies the management unit 4 that the routing table 53 can be updated. When the blocked port 8 is not reused, the management unit 4 updates the routing table 53 and switches the blocked port 8 to the alternative port 8. On the other hand, when the blocked port 8 is reused, the retransmission state machine 63 transmits a signal for releasing the blocked state to the blocked port 8. Finally, when the retransmission state machine 63 transmits a signal for resuming frame transmission to the reception port 5, the register value of the retransmission state machine 63 corresponding to the blocked port 8 transitions to “3′b000” (normal state).

  In this way, the retransmission state machine 63 transfers a frame to one transfer destination stored in the input queue 61 corresponding to one transfer destination to another (alternate) transfer destination included in a plurality of different transfer paths. It is an example of the control part which performs the alternative output process which controls the selector 62 so that it may output. More specifically, in the alternative output process, the retransmission state machine 63 converts a plurality of frames to one transfer destination stored in the input queue 61 corresponding to one transfer destination to each of the transmission destination devices 3A to 3A. The selector 62 is controlled to output the data to alternative transfer destinations corresponding to 3C. This alternative output process is performed by the retransmission state machine 63 according to the state of data transfer from the selector 62 (output side thereof, for example, one output port 8) to one transfer destination (opposite LSI) via one transfer path. It is done.

  As described above, according to the information processing system 1 (crossbar 2) according to the embodiment, even if a data transfer destination failure or congestion occurs, a transfer path (transfer destination) is provided to the alternative output port 8. Since the data is changed, the data (frame) can be reliably transferred to the transmission destination. Further, according to the information processing system 1, when a fixed failure occurs, the frame can be correctly transferred to the transmission destination. Furthermore, according to the information processing system 1, even when the traffic is congested, the transfer path can be switched to a detour, and even when an intermittent failure occurs, transfer is performed before the intermittent failure is recovered. Since the path can be switched to a detour, data transfer delay can be reduced.

  Further, according to the information processing system 1, the frame transfer destination can be dynamically switched to the alternative port 8 for each input port 6 while the operation of the crossbar 2 is continued. Therefore, it is possible to complete the switching for each input port 6 without waiting for all the frames staying at the other input ports 6 to be transmitted, and it is not necessary to stop the operation of the entire crossbar 2. The influence on other output ports 8 can be minimized.

  In (IV), the frame in the input queue 61 addressed to the blocked port 8 may include a frame that has been output to the blocked port 8 but has not been confirmed to reach the opposing LSI due to a failure or the like. . That is, the retransmission state machine 63 outputs one or more frames stored in the input queue 61 corresponding to the blocked port 8 and including the frames already output to the blocked port 8 to the alternative port 8 corresponding to each frame. Can do.

As described above, according to the information processing system 1, a failure has occurred in the transfer path because the frame including the transfer failure frame stored in the input queue 61 corresponding to the blocked port 8 is output to the alternative port 8. Even in this case, data loss can be avoided.
The bypass output port management circuit 64 is a circuit that holds the information of the bypass output port 8 in the routing table 53 for each frame input from the reception queue 51 to the input queue 61. For example, when the retransmission state machine 63 outputs a frame in the input queue 61 corresponding to the blocked port 8 in the process (IV), the bypass output port management circuit 64 uses the output destination for each frame as a normal one. Conversion from the output port 8 to the bypass output port 8 is possible. The bypass output port management circuit 64 can include a storage device such as a memory or a register. As the memory, for example, a volatile memory such as a RAM may be used. Although one bypass output port management circuit 64 is shown in one input port 6 in FIG. 5, it is preferable that a bypass output port management circuit 64 is provided for each input queue 61.

  In this way, the retransmission state machine 63 cooperates with the detour output port management circuit 64 that has acquired the information of the alternative port 8 from the routing table 53, and transmits the frame stored in the input queue 61 corresponding to the blocked port 8. The data can be output to the alternative port 8. In other words, when the retransmission state machine 63 includes an alternative transfer destination (alternate port 8) in the routing table 53 for a frame stored in the input queue 61 corresponding to one transfer destination in which a failure or the like is detected. It can be said that the alternative output processing is performed.

That is, according to the information processing system 1, the alternative port 8 can be set as an arbitrary output port 8 by setting the routing table 53, and can be transferred to a different alternative port 8 for each frame, that is, a different detour. It becomes possible. Therefore, the degree of freedom of switching to the alternative port 8 is increased, and fault tolerance can be improved.
The routing unit 7 connects each input queue 61 in each input port 6 and each output queue 81 in each output port 8 to correspond to a frame input from the input queue 61 to the routing unit 7. Output to the output queue 81. Examples of the routing unit 7 include a static network in which the input queue 61 and the output queue 81 are connected by a data path (frame transfer path). Note that when the distance between the input queue 61 and the output queue 81 is long, the routing unit 7 may include a flip-flop or the like in each of a plurality of data paths to synchronize the frames.

[1-5] Configuration Example of Management Unit Next, the management unit 4 as an example of an embodiment will be described with reference to FIGS. 7 is a diagram showing an example of the data structure of the management information 42 held by the management unit 4 shown in FIG. 5, and FIG. 8 is a diagram showing a hardware configuration example of the management unit 4 shown in FIG.
The management unit 4 includes a holding unit 41 (see FIG. 5). As shown in FIG. 7, the holding unit 41 holds information of all routing tables 53 (see FIG. 6) of all crossbars 2 in the information processing system 1 as management information 42. Examples of the holding unit 41 include a storage device such as a memory or a register. As the memory, for example, a volatile memory such as a RAM can be used.

  The management unit 4 can register and update the management information 42 and the routing table 53 of the reception port 5. For example, the management unit 4 can update the management information 42 after receiving an output port blocking signal from the output port 8 of each crossbar 2 or before updating the routing table 53. In addition, for example, when the update of the management information 42 is completed, the management unit 4 responds to the routing table update availability notification signal from the retransmission state machine 63 with the same contents as the update made to the management information 42, and the routing table 53 is updated. Then, when updating the routing table 53, the management unit 4 transmits an output port switching completion signal to the retransmission state machine 63. In other words, in response to the update request, the management unit 4 sends a frame output to one transfer destination (for example, a transfer destination connected to the blocked port 8) to an alternative transfer destination (for example, a transfer destination connected to the alternative port 8). The routing table 53 is updated so that it is output to ().

  In the update of the management information 42 or the routing table 53, the management unit 4 sets the bypass output port of the blocked port 8 to invalid for the entry in which the blocked port 8 is set as the bypass output port, It can be prevented from being used as an output port. In addition, the management unit 4 may set the original bypass output port to be invalid by overwriting the bypass output port with the normal output port for the entry in which the blocked port 8 is set as the normal output port. it can. With these settings, the management unit 4 can switch the bypass output port to the normal output port.

  The management unit 4 does not need to update the routing table 53 and the management information 42 when reusing the blocked output port 8. Whether or not to re-use the blocked output port 8 can be determined by the management unit 4 after the management unit 4 can determine whether or not to reuse. For example, the management unit 4 determines whether or not to reuse the management unit 4 by setting a mode in which the management unit 4 fixes or does not reuse, or reuses the output port blocking signal from the output port 8. For example, there are two types of cases of whether or not to do so. The management unit 4 may use two types of output port switching completion signals when the routing table 53 is updated / not updated. Thereby, the management unit 4 can notify the retransmission state machine 63 that the routing table 53 is not updated when it is determined not to reuse the blocked port 8.

As described above, the management unit 4 determines the routing table 53 held in the holding unit 52 of the reception port 5 according to the state of data transfer from the selector 62 (each of the plurality of output ports 8) to a plurality of transfer destinations. It is an example of the update part which updates.
Thus, according to the management unit 4, the routing table 53 can be updated while the operation of the crossbar 2 is continued. Further, it is possible to prevent the frame from being output from the input queue 61 to the blocked port 8 after the routing table 53 is updated.

The operation of the management unit 4 described above may be realized by processing by software such as firmware of the information processing system 1, for example. For example, as illustrated in FIG. 8, the management unit 4 can include a CPU 40a, a memory 40b, a storage unit 40c, an interface unit 40d, an input / output unit 40e, a recording medium 40f, and a reading unit 40g.
The CPU 40a is an example of a processing device (processor) that is connected to the corresponding blocks 40b to 40g in FIG. 8 and performs various controls and operations. The CPU 40a can realize various functions in the management unit 4 by executing programs stored in the memory 40b, the recording media 40f and 40h, or a read only memory (ROM) (not shown). The memory 40b is a storage device that temporarily stores various data and programs. When executing the program, the CPU 40a stores and develops data and programs in the memory 40b. An example of the memory 40b is a volatile memory such as a RAM.

  The storage unit 40c is hardware that stores various data, programs, and the like. Examples of the storage unit 40c include various devices such as a magnetic disk device such as a hard disk drive (HDD), a semiconductor drive device such as a solid state drive (SSD), and a nonvolatile memory such as a flash memory. The interface unit 40d performs connection and communication control with a network and other devices by wire or wireless. The input / output unit 40e may include at least one of an input device such as a mouse and a keyboard and an output device such as a display and a printer. The input / output unit 40e can receive an operation command by an operation of an operator (administrator) or the like of the management unit 4 by an input device and can display (output) an operation result by the management unit 4 on an output device.

  The recording medium 40f is a storage device such as a flash memory or a ROM, and can record various data and programs. The reading unit 40g is a device that reads data and programs recorded on a computer-readable recording medium 40h. At least one of the recording media 40f and 40h may store a management (update) program that realizes all or some of the various functions of the management unit 4 according to the present embodiment. For example, the CPU 40a can execute the program read from the recording medium 40f or the program read from the recording medium 40h via the reading unit 40g in a storage device such as the memory 40b. Accordingly, the computer (including the CPU 40a, the information processing apparatus, and various terminals) as the management unit 4 can realize the function of the management unit 4 according to the present embodiment.

  Examples of the recording medium 40h include optical disks such as flexible disks, compact discs (CDs), digital versatile discs (DVDs), and Blu-ray discs, and flash memories such as universal serial bus (USB) memories. Examples of the CD include CD-ROM, CD-Recordable (CD-R), and CD-Rewritable (CD-RW). Examples of DVD include DVD-ROM, DVD-RAM, DVD-R, DVD-RW, DVD + R, DVD + RW, and the like.

  The blocks 40a to 40g described above are connected to be communicable with each other via a bus. The above-described hardware configuration example of the management unit 4 is an example. For example, the management unit 4 may share at least a part of the hardware shown in FIG. As an example, the management unit 4 may use a CPU and a memory as an example of the device 3 of the information processing system 1 instead of the CPU 40a and the memory 40b. Moreover, increase / decrease or division of hardware in the management unit 4 and the information processing system 1, integration in an arbitrary combination, and the like may be performed as appropriate.

[1-6] Operation Example of Information Processing System Next, an operation example of the information processing system 1 as an example of an embodiment will be described with reference to FIGS. 9 to 11.
FIG. 9 is a flowchart for explaining an operation example of the retransmission processing in the reception port 5 of the crossbar 2 shown in FIG. 5, and FIG. 10 explains an operation example of the retransmission processing in the input port 6 of the crossbar 2 shown in FIG. It is a flowchart. FIG. 11 is a flowchart for explaining an operation example of the update processing of the routing table 53 in the management unit 4 shown in FIG.

[1-6-1] Example of Retransmission Process at Reception Port First, the retransmission process at the reception port 5 will be described with reference to FIG.
When the reception port 5 receives an output port block signal from the output port 8 via the input port 6 (step S1), the frame transmission determination circuit 54 determines whether or not a frame is being output from the reception queue 51 to the input port 6. Determination is made (step S2). If the frame is being output (Yes route in step S2), the frame transmission determination circuit 54 determines whether the frame being output to the input port 6 has been output to the end (step S3). When the frame being output has not been output to the end (No route in step S3), the frame transmission determination circuit 54 waits for a predetermined clock (for example, several clocks; a predetermined time) (step S4), and the process proceeds to step S3. To do.

  On the other hand, if the frame is not being output in step S2 (No route in step S2), or if the frame being output has been output to the end in step S3 (Yes route in step S3), the process proceeds to step S5. . In step S5, the frame transmission determination circuit 54 stops frame transmission to the input port 6, and a frame transmission stop signal indicating that frame transmission to the input port 6 is stopped is transmitted to the input port 6. .

Next, when the frame transmission restart instruction signal indicating that frame reception is resumed from the input port 6 is received by the reception port 5, the frame transmission determination circuit 54 resumes frame transmission from the reception queue 51 to the input port 6. (Step S6), the process ends.
[1-6-2] Operation Example of Retransmission Process at Input Port Next, the retransmission process at the input port 6 will be described with reference to FIG.

  It is assumed that the state managed by the retransmission state machine 63 is a normal state (register value “3′b000”) in which no error or congestion is detected at the output port 8. 10 is executed by the retransmission state machine 63 that controls the input queue 61 corresponding to the blocked port 8 among the plurality of retransmission state machines 63 (corresponding to the blocked port 8). Shall. That is, the retransmission state machine 63 that controls the input queue 61 addressed to the alternative port 8 (corresponding to the alternative port 8) does not have to change the state as shown in FIG.

  When the output port block signal is received from the output port 8 by the input port 6 (step S11), the state of the retransmission state machine 63 corresponding to the block port 8 changes to the input port frame transmission stop transition state (register value “3”). b001 "). Further, the input port 6 receives a signal indicating that frame transmission has been stopped from the reception port 5 (step S12). When the processing in step S12 is completed, the state of the retransmission state machine 63 corresponding to the blocked port 8 transitions to the input queue frame transmission state (register value “3′b010”) addressed to the alternative port.

Next, the frame staying in the input queue 61 addressed to the alternative port 8 of the blocked port 8 is transmitted from the input port 6 to the output port 8 corresponding to the transfer destination of the frame (step S13). The process of step S13 is performed under the control of the selector 62 by the retransmission state machine 63 corresponding to the alternative port 8.
In step S13, the retransmission state machine 63 corresponding to the blocked port 8 can detect that transmission of all the frames staying in the input queue 61 addressed to the alternative port 8 has been completed. Alternatively, the retransmission state machine 63 corresponding to the blocked port 8 may be notified from the retransmission state machine 63 corresponding to the alternative port 8 that transmission of all frames has been completed. When the process of step S13 is completed, the state of the retransmission state machine 63 corresponding to the blocked port 8 transitions to the input queue frame transmission state (register value “3′b011”) addressed to the blocked port. When there are a plurality of retransmission state machines 63 corresponding to the alternative port 8 such as when the alternative port 8 is set for each frame, the transmission to all the alternative ports 8 is completed after the transmission of all frames is completed. The state of the corresponding retransmission state machine 63 transitions.

Next, the selector 62 is controlled by the retransmission state machine 63 corresponding to the blocked port 8, and the frame staying in the input queue 61 addressed to the blocked port 8 is transmitted to the output port 8 corresponding to the detour (transfer destination). (Step S14).
In steps S13 and S14, the retransmission state machine 63 confirms that all the frames to be transmitted have normally reached the opposite LSI from the corresponding output port 8 in order to prevent the loss of frames. It is preferable to release the transmitted frame.

When the process of step S14 is executed, the state of the retransmission state machine 63 corresponding to the blocked port 8 changes to the routing table updatable state (register value “3′b100”).
Then, the retransmission state machine 63 notifies the management unit 4 that the processing up to steps S13 and S14 has been completed by a routing table updateable notification signal (step S15). In the management unit 4, when the blocked port 8 is not reused, the routing table 53 is updated (step S15).

  When the retransmission state machine 63 receives an output port switching completion signal from the management unit 4 (step S16), the retransmission state machine 63 causes the new output port 8 to be a blocked output port 8 scheduled to be reused. It is determined whether or not there is (step S17). When the new output port 8 is scheduled to be reused (Yes route in step S17), the retransmission state machine 63 transmits the output port block release signal to the blocked output port 8 to release the block state (step S18). ), The process proceeds to step S19. In other words, the retransmission state machine 63 releases the blocked state of the output port 8 when the blocked port 8 is reused in the routing table updatable state for reasons such as dynamic replacement of a failed device or elimination of congestion.

  Note that the retransmission state machine 63 can transmit a routing table updatable notification signal in step S15 in order to update the routing table 53 when it is desired to change the transfer path due to failure or congestion of the output port 8. On the other hand, when the blocked port 8 is reused, the retransmission state machine 63 does not need to transmit the routing table update availability notification signal (steps S15 and S16 can be omitted), but the management unit 4 determines whether or not to reuse. When making a determination, the signal may be transmitted.

  In step S19, the retransmission state machine 63 transmits a frame transmission resumption instruction signal to the reception port 5, frame transmission (normal control) from the input queue 61 to the output port 8 is resumed, and the process ends. If the new output port 8 is not scheduled to be reused (No route in step S17), the process proceeds to step S19. When the process of step S19 is completed, the state of the retransmission state machine 63 corresponding to the blocked port 8 transitions to the normal state (register value “3′b000”).

[1-6-3] Operation Example of Routing Table Update Processing in Management Unit Next, the update processing of the routing table 53 in the management unit 4 will be described with reference to FIG.
As a premise, the control of the flowchart illustrated in FIG. 11 is executed when the blocked port 8 is not reused, and the management unit 4 determines to reuse the blocked port 8 based on the output port blocked signal. In case it is not executed.

When the management unit 4 receives an output port block signal from the output port 8, the bit corresponding to the block port 8 in the detour output port in the management information 42 is updated from valid to invalid (step S21).
Next, when the management unit 4 receives a routing table update availability notification signal from the retransmission state machine 63 (step S22), the management unit 4 determines whether or not the routing table 53 can be updated (step S23). . For example, the management unit 4 refers to the management information 42, determines whether or not the bypass output port is set to be valid in the entry in which the blocked port 8 is set as the normal output port, and outputs the bypass output. It can be determined that the port can be updated when the port is set to be valid.

  If it is determined in step S23 that the routing table 53 can be updated (Yes route in step S23), the management information 42 is updated by the management unit 4 (step S24). For example, the management unit 4 assigns the number of the normal output port of the entry in which the blocked port 8 is set as the normal output port in the management information 42 to the nth (n is an integer of 1 or more) candidate (for example, the first Overwrite with the number of the output port for detour. Thereby, the management unit 4 can update the management information 42. When there are a plurality of detour output ports, the management unit 4 can raise (shift) the ranks of the second to n-th candidates, respectively, and change them to the first to (n-1) candidates. . Further, since the nth candidate moves up to the (n−1) th candidate, the management unit 4 can set the detour output port set as the nth candidate to be invalid.

Then, the management information updated in steps S21 and S24 is used by the management unit 4 to update the routing table 53 of the crossbar 2 (step S25). When the update of the routing table 53 is completed, the management unit 4 transmits an output port switching completion signal to the retransmission state machine 63 (step S26), and the process ends.
On the other hand, when it is determined in step S23 that the routing table 53 cannot be updated (No route in step S23), the management unit 4 notifies the crossbar 2 (for example, the retransmission state machine 63) of a fatal error (step S23). S27), the process ends. As an example in which the routing table 53 cannot be updated, for example, the bypass output port is not set or disabled in the entry in which the blocked port 8 is set as the normal output port. Cases. When a fatal error is notified from the management unit 4, the crossbar 2 or the information processing system 1 may stop the operation of the entire system.

[1-7] Embodiment Next, an embodiment of the information processing system 1 (particularly the crossbar 2) will be described with reference to FIGS.
FIG. 12 is a diagram showing an example of the configuration of the reception port 5 shown in FIG. 5, and FIG. 13 is a diagram showing an example of the configuration of the input port 6 shown in FIG. FIG. 14 is a diagram for explaining an example of a control method of the input queue 61 in the input port shown in FIG. 13, and FIG. 15 is a diagram showing an example of a timing chart in the input port 6 shown in FIG. FIG. 16 is a diagram showing an embodiment of the configuration of the output port 8 shown in FIG.

In the following description, one configuration of each of the reception port 5, the input port 6, the output port 8, and the connection unit 9 is illustrated, but the other reception port 5, the input port 6, the output port 8, and the connection unit are illustrated. The same applies to 9.
[1-7-1] Example of Accepting Port First, an example of the accepting port 5 will be described with reference to FIG.

  As shown in FIG. 12, the reception port 5 can include the reception queue 51, the holding unit 52, and the frame transmission determination circuit 54 illustrated in FIG. 5, and can include the credit management circuit 55 and the read control circuit 56. Unless otherwise specified, the basic functions of the reception queue 51, the holding unit 52, and the frame transmission determination circuit 54 are the same as those shown in FIG.

  The credit management circuit 55 is a circuit that determines whether or not there is a vacancy in the input queue 61 of the input port 6, that is, whether or not frames can be transmitted from the reception queue 51 to the input queue 61. In the following description, the credit may be a signal indicating that data stored in a transmission destination queue (for example, the input queue 61) is output and the queue is empty. The credit unit may be set for each frame, may be set to a unit obtained by dividing a frame by several clocks, or a combination thereof.

  For example, the credit management circuit 55 includes a circuit such as a counter. When the credit A1 for input port is received from the input port 6, the credit management circuit 55 adds (or subtracts) the count value of the circuit and reads the frame from the reception queue 51. Is subtracted (or added). If the count value is positive (or the input queue 61 is not Full), the credit management circuit 55 can determine that the frame can be transmitted to the input port 6. Then, the credit management circuit 55 transmits the determination result to the frame transmission determination circuit 54 as the input port credit management information A2.

The frame transmission determination circuit 54 is a circuit having basically the same function as that shown in FIG. 5, and realizes at least a part of the flowchart shown in FIG. The frame transmission determination circuit 54 gives a frame transmission permission A3 to the read control circuit 56 when both of the following conditions (A) and (B) are satisfied.
(A) When the input port credit management information A2 indicates that frame transmission is possible.

(B) None of the output ports 8 of the connection destination is blocked, or when any of the output port blocking signals A4 is received, the frame is being output to the input port 6 and transmission up to the end of the frame is performed. If incomplete.
In (B) above, whether or not the data being output is the end of the frame is determined by frame transmission management information A7 from the reception queue 51 described later.

  The frame transmission determination circuit 54 transmits a frame transmission stop signal A5 to the input port 6 to the input port 6 according to the flowchart shown in FIG. When the input port 6 receives the output port switching completion signal B10 (see FIG. 13) from the management unit 4 and receives the frame transmission restart instruction signal A6 from the input port 6 in response to this reception, the frame transmission determination circuit 54 stops. Restart the frame transmission that was being performed.

The read control circuit 56 receives the frame transmission permission A3 from the frame transmission determination circuit 54 and controls the read operation from the reception queue 51 when the frame is stored in the reception queue 51, and the input port through the data path 6 is output.
The holding unit 52 holds the routing table 53 and is basically a storage device similar to that shown in FIG. The routing table 53 derives a destination output port (normal output port; including a detour output port overwritten on the normal output port) A9 and a first candidate detour output port A10 from the destination ID A8. (See FIG. 6). The transmission destination ID A8 is information included in a frame output from the reception queue 51 (or output together with the frame), and is supplied to the routing table 53 via a data path or other wiring.

[1-7-2] Embodiment of Input Port Next, an embodiment of the input port 6 will be described with reference to FIGS.
As shown in FIG. 13, the input port 6 includes the input queue 61, the selector 62, the retransmission state machine 63, and the detour output port management circuit 64 shown in FIG. 5, and can further include the following circuits. That is, the input port 6 can include the control signal generation circuit 65, the credit generation circuit 66, and the encoder 67, and can include the input queue control unit 60 for each output port 8. For convenience, as shown in FIG. 13, the input queue control unit 60 may be specified by any of the input queue control units A to C. Unless otherwise noted, the basic functions of the input queue 61, selector 62, retransmission state machine 63, and detour output port management circuit 64 are the same as those shown in FIG.

  The control signal generation circuit 65 is a circuit that generates a frame transmission control signal B1 for each transfer destination output port from the frame transmission control information A11, for example, in order to distribute the frame to the input queue control unit 60. For example, the control signal generation circuit 65 acquires the validity of the frame passing through the data path as the frame transmission control information A11. Then, the control signal generation circuit 65 outputs a frame transmission control signal B1 indicating that a frame is input to the input queue control unit 60 to which the frame is input.

  The credit generation circuit 66 is a circuit that transmits the input port credit A1 to the reception port 5 when the frame can be stored in the input queue 61 even if a frame addressed to any output port 8 arrives. That is, the credit generation circuit 66 transmits the input port credit A1 to the reception port 5 when all the input queues 61 are empty. The credit generation circuit 66 includes a circuit such as a counter, for example. The credit generation circuit 66 adds (or subtracts) the count value of the circuit when detecting that a frame is input to the input port 6 based on the frame transmission control information A11, and transmits the count value when transmitting the input port credit A1. Subtract (or add). Further, the credit generation circuit 66, when the count value of the circuit becomes larger (or smaller) than the maximum value (or minimum value) of the number of queue retransmission entries B2 for each transfer destination output port, the input port credit A1. Send.

The input queue control unit 60 is provided for each output port 8 that is a frame transfer destination. Each of the input queue control units 60 includes the input queue 61, the retransmission state machine 63, and the detour output port management circuit 64 described above, and the following circuit 601. ~ 609 can be provided.
The write control circuit 601 performs write control to the input queue 61. For example, when the frame transmission control signal B1 from the control signal generation circuit 65 is input, the write control circuit 601 indicates the next entry to be written in the input queue 61 with the write pointer. Since the write operation is managed as described above, the possibility that the input queue 61 overflows is low.

  The read control circuit 602 performs read control from the input queue 61. The read control circuit 602 indicates the entry to be read next in the input queue 61 with a read pointer. For example, when a frame is stored in the input queue 61 (the value of the queue holding entry number management circuit 604 is positive) and the output port credit management information B8 of the transmission destination output port 8 indicates that frame transmission is possible, the read control circuit 602 The frame can be read. Since the destination output port 8 may be the detour output port 8 in addition to the normal output port 8, the read control circuit 602 may output the output port credit management information corresponding to the output port 8 that actually transmits the frame. B8 is selected to determine whether or not reading is possible.

  When the retransmission read pointer 603 receives the queue frame release signal B4 and the release frame length B5 indicating that the input queue 61 is released from the output port 8 that transmitted the frame, the retransmission read pointer 603 adds the pointer by the release frame length B5. The retransmission read pointer 603 is updated to follow the read pointer in the read control circuit 602. The retransmission read pointer 603 can receive the input port control unit number B6 indicating the number of the input queue control unit 60 together with the queue frame release signal B4. For example, if the input port control unit number B6 matches its own control unit number, the retransmission read pointer 603 determines that the queue frame release signal B4 is a release signal related to the frame transmitted by its own control unit 60, and Updates can be performed. When the retransmission read pointer 603 receives the output port block signal B7, the read control circuit 602 can be updated by overwriting the pointer value on the read pointer of the read control circuit 602.

The queue holding entry number management circuit 604 is a circuit that manages the number of entries held in the input queue 61. The queue holding entry number management circuit 604 includes a circuit such as a counter, for example, and can add the count value of the circuit when written to the input queue 61 and subtract the count value when read from the input queue 61.
The queue retransmission entry number management circuit 605 is a circuit that manages the number of entries that may still be retransmitted in the input queue 61. The queue retransmission entry number management circuit 605 can output the number of entries (queue retransmission entry number B2) to the credit generation circuit 66 and the retransmission state machine 63. The queue retransmission entry number management circuit 605 includes a circuit such as a counter, for example, and can add the count value of the circuit when written to the input queue 61. When the queue retransmission entry number management circuit 605 receives the queue frame release signal B4 and the release frame length B5 from the output port 8 that transmitted the frame, the queue retransmission entry number management circuit 605 can subtract the count value by the release frame length B5.

  For example, when the input port control unit number B6 matches its own control unit number, the queue retransmission entry number management circuit 605 determines that the queue frame release signal B4 is a release signal related to the frame transmitted by its own control unit 60. The count value of the circuit is updated. When the queue retransmission entry number management circuit 605 receives the output port blocking signal B7, the queue holding entry number management circuit 604 can be updated by overwriting the count value of the circuit on the queue holding entry number management circuit 604. .

Here, with reference to FIG. 14, the relationship between the write pointer, the read pointer, and the retransmission read pointer used for controlling the input queue 61 and the queue holding entry number management circuit 604 and the queue retransmission entry number management circuit 605 will be described. To do.
As illustrated in FIG. 14, the input queue 61 in the operating crossbar 2 includes a blank entry, an entry that holds data (part of a frame), and data that has been transmitted from the input queue 61 to the opposite LSI. It may include an entry that is waiting for confirmation that it has arrived normally. A blank entry is indicated by the write pointer of the write control circuit 601, an entry holding data is indicated by the read pointer of the read control circuit 602, and an entry for which data has been transmitted and waiting for arrival confirmation is indicated by the retransmission read pointer 603. Indicated.

Each pointer basically moves from the head of the input queue 61 toward the tail, and returns to the head when it reaches the tail. The read pointer may be returned to the value of the retransmission read pointer 603 when the input queue control unit 60 receives an output port block signal, and in this case, the read pointer is in the reverse direction (from the end to the top). Move.
Since the queue holding entry number management circuit 604 holds the number of entries that hold data in the input queue 61, the count value of the queue holding entry number management circuit 604 indicates 1 in the example shown in FIG. The queue retransmission entry number management circuit 605 holds the total number of entries in the input queue 61 including the number of entries that hold data and the number of entries that have already been sent and are waiting for arrival confirmation. Therefore, in the example illustrated in FIG. 14, the count value of the queue retransmission entry number management circuit 605 indicates 2.

  Returning to the description of FIG. 13, the output port credit management circuit 606 is a circuit that determines whether or not there is a vacancy in the output queue 81 of the output port 8, that is, whether or not transmission of a frame from the input queue 61 is possible. is there. The output port credit management circuit 606 includes, for example, a circuit such as a counter. When the output port credit B3 is received, the count value of the circuit is added (or subtracted), and when read from the input queue 61, the count value is subtracted. (Or addition). If the count value is positive (or the output queue 81 is not full), the output port credit management circuit 606 can determine that the frame can be transmitted to the output port 8. Then, the output port credit management circuit 606 can transmit the determination result to the read control circuit 602 as output port credit management information B8.

  The detour output port management circuit 64 is a circuit that holds information of the detour output port A10 from the routing table 53 every time a frame is written to the input queue 61 when a detour is set for each frame. When the detour output port management circuit 64 receives the queue frame release signal B4 from the output port 8 that transmitted the frame, the detour output port management circuit 64 can release the stored information of the old detour output port A10.

  The retransmission state machine 63 is a circuit having basically the same function as that shown in FIG. 5, and realizes at least a part of the flowchart shown in FIG. As shown in FIG. 13, the retransmission state machine 63 receives the output port block signal B7, the frame transmission stop signal A5 to the input port 6, the output port switching completion signal B10, the queue retransmission entry number B2, and the like. Further, the retransmission state machine 63 outputs the frame transmission resumption instruction signal A6 to the reception port 5, the routing table update enable notification signal B9 to the management unit 4, and the output port blockage release signal B11 to the output port 8, respectively.

  The selection signal generation circuit 607 is a circuit that generates selection signals for selecting the data path addressed to the output port 8, the selector 608, and the selector 609 based on information from the retransmission state machine 63 and the detour output port management circuit 64. is there. Here, the selector 608 selects the queue retransmission entry number B2 from any of the queue retransmission entry number management circuits 605 in the input queue control units A to C, and outputs it to the retransmission state machine 63 to retransmit the number of entries. Is a selector that notifies The selector 609 is a selector that selects the output port credit management information B8 from any of the output port credit management circuits 606 in the input queue control units A to C and outputs the selected output port credit management information B8 to the read control circuit 602.

  If an error or congestion is detected at the output port 8, the retransmission state machine 63 corresponding to the blocked port 8 can refer to the queue retransmission entry number B2 corresponding to the alternative port 8 by the selector 608. As a result, the retransmission state machine 63 corresponding to the blocked port 8 has completed transmission of all the frames staying in the input queue 61 addressed to the alternative port 8 (for example, the value of the queue retransmission entry number B2 becomes “0”). Can be detected.

  The selection signal generation circuit 607 outputs a selection signal for selecting an output port 8 other than the normal output port 8 connected in the normal operation (normal state). For example, the number of lines from the selection signal generation circuit 607 to the selector 62 is one less than the number of output ports 8 connected to the input port 6. As an example, when there are three output ports 8 connected to the input port 6 as shown in FIG. 13, the number of selection signal wires to the selector 62 is two. The selection signal from the selection signal generation circuit 607 is encoded by the encoder 67 and transmitted to the output port 8 as the input port control unit number B12. The input port control unit number B12 transmitted here is transmitted from the output port 8 as the input port control unit number B6, and the input queue control unit 60 determines whether or not to release the input queue 61 of its own control unit 60. Used for judgment.

  In FIG. 13, a white circle on the input side of the selector 62 indicates an intersection with the selection signal. For example, the selector 62 can select an input-side data path corresponding to the asserted selection signal and output the frame to the output-side data path. For example, when there is no asserted selection signal, the selector 62 selects the remaining one input-side data path that is not connected to the selection signal, and outputs the frame to the output-side data path. it can.

[1-7-2-1] Operation Example of Input Port Here, an operation example of the input port 6 shown in FIG. 13 will be described with reference to FIG.
FIG. 15 is an example of a timing chart of each signal in the input queue control unit 60 corresponding to the blocked port 8 and the input queue control unit 60 corresponding to one of the alternative ports 8 in the same input port 6. Indicates. In the following description, it is assumed that the output port credit management circuit 606 adds the count value when receiving the output port credit.

  As shown in FIG. 15, at the timing t0, the state of the retransmission state machine 63 corresponding to a certain output port (later blocked port) 8 is “3′b000”. Here, it is assumed that an error or congestion is detected at the output port 8 and the output port block signal B7 is input to the input port 6. At this time, the state of the retransmission state machine 63 corresponding to the blocked port 8 changes to “3b′001” at the timing t1. Also, the count value “1” of the queue holding entry number management circuit 604 is overwritten with the count value “2” of the queue retransmission entry number management circuit 605. Further, the count value of the output port credit management circuit 606 is reset from “3” to “0” in order to stop transmission to the blocked port 8.

  Next, when the frame transmission stop signal A5 from the reception port 5 to the input port 6 is input to the input port 6, the state of the retransmission state machine 63 corresponding to the blocked port 8 changes to “3b'010” at timing t2. Transition. At this time, output of all the frames in the input queue 61 corresponding to the alternative port 8 is started, and at the timing t3, the counts of the queue holding entry number management circuit 604 and the output port credit management circuit 606 corresponding to the alternative port 8 are counted. The value is subtracted. Further, at timing t4, the count value of the queue retransmission entry number management circuit 605 corresponding to the alternative port 8 is subtracted later than timing t3 to confirm the arrival of the frame at the counter LSI.

  When the count value of the queue retransmission entry number management circuit 605 corresponding to the alternative port 8 becomes “0”, the state of the retransmission state machine 63 corresponding to the blocked port 8 changes to “3b′011” at the timing t5. At this time, output of all the frames in the input queue 61 corresponding to the blocked port 8 is started, and the count value of the queue holding entry number management circuit 604 corresponding to the blocked port 8 is subtracted at timing t6. At this time, since the frame from the input queue 61 corresponding to the blocked port 8 is output to the alternative port 8, the count value of the output port credit management circuit 606 corresponding to the alternative port 8 is also subtracted. Further, at the timing t7, the count value of the queue retransmission entry number management circuit 605 corresponding to the blocked port 8 is subtracted later than the timing t6 in order to confirm the arrival of the frame at the counter LSI.

  When the count value of the queue retransmission entry number management circuit 605 corresponding to the blocked port 8 becomes “0”, the state of the retransmission state machine 63 corresponding to the blocked port 8 changes to “3b′100” at the timing t8. At this time, the retransmission state machine 63 transmits a routing table update availability notification signal B9 to the management unit 4. When the retransmission state machine 63 receives the output port switching completion signal from the management unit 4, the retransmission state machine 63 transmits the frame transmission restart instruction signal A 6 to the reception port 5. Then, the state of the retransmission state machine 63 corresponding to the blocked port 8 transits to “3b'000” at the timing t9 and returns to the normal state.

[1-7-3] Embodiment of Output Port Next, an embodiment of the output port 8 will be described with reference to FIG.
As shown in FIG. 16, the output port 8 includes the output queue 81 and the selector 82 shown in FIG. 5 and can further include the following circuits. That is, the output port 8 includes a queue read request arbitration circuit 83, a frame transmission availability determination circuit 84, a frame arrival confirmation management circuit 85, and an output port blockage determination circuit 86, and an output queue control unit 80 for each input port 6. You can have it. For convenience, as shown in FIG. 16, the output queue control unit 80 may be specified by any one of the output queue control units A to C. Unless otherwise stated, the basic functions of the output queue 81 and the selector 82 are the same as those shown in FIG.

The output queue control unit 80 is provided for each input port 6 serving as a frame transfer source, and each of the output queue control units 80 can include the output queue 81 described above and the following circuits 801 to 805.
The write control circuit 801 performs write control to the output queue 81. For example, when the frame transmission control information C1 relating to the frame passing through the data path is input, the write control circuit 801 indicates the next entry to be written in the output queue 81 with the write pointer. Since the write operation is managed as described above, the possibility that the output queue 81 overflows is low.

  The read control circuit 802 performs read control from the output queue 81. The read control circuit 802 designates an entry to be read next in the output queue 81 with a read pointer. For example, when a frame is stored in the output queue 81 (the value of the queue holding entry number management circuit 803 is positive) and the queue read request acquisition signal C5 is received from the queue read request arbitration circuit 83, the read control circuit 802 Can be read.

The queue holding entry number management circuit 803 is a circuit that manages the number of entries held in the output queue 81. The queue holding entry number management circuit 803 has a circuit such as a counter, for example, and can add the count value of the circuit when written to the output queue 81 and subtract the count value when read from the output queue 81.
The queue read request generation circuit 804 is a circuit that generates a queue read request signal C 2 for transmitting to the queue read request arbitration circuit 83 that the frame can be read from the output queue 81. For example, the queue read request generation circuit 804 receives a queue read request when a frame is stored in the output queue 81 and the selector 82 of the data path to be transmitted to the connection unit 9 with the opposing LSI has not selected anything. Signal C2 can be generated. Note that the queue read request generation circuit 804 can determine that a frame is stored in the output queue 81 when the value of the queue holding entry number management circuit 803 is positive. The queue read request signal C2 may be added with or included the frame length C3.

  The output port credit generation circuit 805 is a circuit that transmits the output port credit B3 to the input port 6 when the output queue 81 becomes empty. The output port credit generation circuit 805 includes, for example, a circuit such as a counter. When a frame is input to the output port 8, the count value of the circuit is added (or subtracted), and the output port credit B3 is transmitted. Can be subtracted (or added).

  The queue read request arbitration circuit 83 receives the queue read request C2 and the frame length C3 from each output queue control unit 80, and arbitrates the request when the frame transmission permission determination circuit 84 outputs the frame transmission permission C4. Then, the queue read request arbitration circuit 83 transmits a queue read request acquisition signal C5 to the control unit 80 that has won the arbitration, and receives an input port selection signal C6 that causes the data path selector 82 to select the control unit 80 that has won the arbitration. It is a circuit to output. The input port selection signal C6 is preferably output so that the selector 82 continues to select the winning control unit 80 while the data of the transmission frame length C3 is output from the control unit 80 that has won the arbitration.

  The frame transmission permission determination circuit 84 determines whether or not the frame transmission to the connection unit 9 is possible, and outputs the frame transmission permission C4 to the queue read request arbitration circuit 83 when it is determined that the frame transmission is possible. It is a circuit to do. The frame transmission availability determination circuit 84 can perform determination and output of frame transmission permission based on, for example, a frame transmission availability determination condition related to a frame transfer destination state such as an opposing LSI. The processing of the frame transmission availability determination circuit 84 can be realized by various methods such as credit management and busy management based on the load status of the opposing LSI. In addition, it is preferable that the frame transmission availability determination circuit 84 can instruct the frame transmission from the output port 8 to be stopped when it is determined to suppress the frame transmission.

  The frame arrival confirmation management circuit 85 is a circuit for confirming whether or not a frame has arrived at the opposing LSI connected to the output port 8. For example, when the queue read request acquisition signal C5 from the queue read request arbitration circuit 83 is valid (for example, “1”), the frame arrival confirmation management circuit 85 uses information C7 and C8 transmitted from the output queue 81 as a frame. It can be stored in the order of transmission. The information C7 and C8 may be information on the input port 6, information about the frame such as the frame length C7 of the read frame and the input port control unit number C8. Further, when the frame arrival confirmation management circuit 85 receives the frame normal arrival confirmation signal C9 from the opposing LSI, it can release the stored information C7 and C8 in order from the oldest. In addition, the frame arrival confirmation management circuit 85 can transmit the queue frame release signal B4, the frame length B5, and the input port control unit number B6 to the input port 6 based on the information C7 and C8.

  The output port blockage determination circuit 86 determines that a failure or congestion has occurred between the output port 8 and the opposing LSI, and blocks the output port 8. Further, when the output port 8 is blocked, the output port blockage determination circuit 86 is a circuit that transmits an output port block signal B7 to the input port 6 and an output port block signal C10 to the management unit 4. The output port blockage determination circuit 86 can perform determination and output of the output port blockage signal B7 based on an output port blockage determination condition relating to the state of the transfer destination of a frame such as an opposing LSI. That is, the output port blockage determination circuit 86 monitors the output status (transfer status) of the frame to the corresponding transfer destination, and outputs the output port blockage signals B7 and C10 when the output status satisfies a predetermined condition. It is. Thus, the output port blockage determination circuit 86 is an example of a notification unit that outputs the output port blockage signals B7 and C10 according to the state of data transfer to a plurality of transfer destinations.

  Each output port 8 determines whether the output status of the frame from the selector 82 (own output port 8) to the transfer destination satisfies the first condition, for example, whether the transmission frequency exceeds the first threshold. Judgment can be made. Each output port 8 determines whether the output status of the frame from the selector 82 (own output port 8) to the transfer destination satisfies the second condition, for example, a second frequency whose transmission frequency is lower than the first threshold value. It can be determined whether or not the threshold value is below.

  The retransmission state machine 63 controls the selector 62 for the frame to the first transfer destination stored in the input queue 61 corresponding to the first transfer destination (output port 8) whose output status satisfies the first condition. And output to the detour. For example, the retransmission state machine 63 converts the frame to the first transfer destination stored in the input queue 61 corresponding to the first transfer destination to the second transfer destination (alternatively, the output status satisfies the second condition) The selector 62 can be controlled to output to the output port 8).

  As described above, according to the information processing system 1, not only the closed port 8 is closed and switched to the alternative port 8, but also the frame transmission frequency for each input port 6 (input queue 61) connected to the output port 8. Is monitored. The retransmission state machine 63 can divert a frame from a specific input port 6 (input queue 61) or all the input ports 6 (input queue 61) to a transfer destination (detour) having a low transmission frequency. , Throughput can be improved.

  The output port blockage determination circuit 86 may synchronously reset the circuit in the output port 8 while the output port 8 is blocked. Further, the output port blockage determination circuit 86 may transmit the output port blockage signal B7 to all the input ports 8 at the same time in the case of a failure, and send the output port blockage signal B7 to a specific input port 8 in the case of congestion. You may send only. Furthermore, when the blocked output port 8 is reused, the output port blockage determination circuit 86 can receive the output port blockage release signal B11 from the input port 8 and cancel the synchronous reset in the output port 8.

[2] Modification [2-1] First Modification The crossbar 2 according to the embodiment includes a normal output port and a bypass output port for each frame (for each frame transmission destination) as shown in FIG. Although described as holding the routing table 53 to be set, the present invention is not limited to this. For example, instead of the routing table 53, the crossbar 2 may hold a routing table 53 ′ in which a normal output port and a detour output port are set for each output port 8 as shown in FIG. Unless otherwise stated, each configuration of the information processing system 1 is the same as that shown in FIG.

  FIG. 17 is a diagram illustrating a data structure of the routing table 53 ′ according to the first modification of the embodiment. As shown in FIG. 17, the routing table 53 ′ omits the destination column as compared with the routing table 53 shown in FIG. 6. Further, the number of entries in the routing table 53 ′ corresponds to the number of output ports 8 (for example, three) provided in the crossbar 2. Thus, in the information processing system 1 according to the first modification, the detour output port 8 is determined for each output port 8 by the routing table 53 ′.

  For example, the detour output port management circuit 64 can hold the information of the detour output port 8 in the routing table 53 ′ with the output port (normal output port) 8 corresponding to itself as an entry. That is, when the retransmission state machine 63 outputs the frame in the input queue 61 corresponding to the blocked port 8 in the process (IV), the detouring output port management circuit 64 sets the output destination of all frames to one. It is possible to convert to the detour output port 8. As an example, when the output port A is the blocked port 8 in the crossbar 2 shown in FIG. 5, the retransmission state machine 63 converts all frames in the input queue 61 to the detour output port B in the process (IV). (First candidate) can be output (see FIG. 17).

Therefore, according to the information processing system 1 according to the first modification, the same effect as that of the embodiment can be obtained, and other output ports 8 that do not correspond to the blocked port 8 and the alternative port 8 operate independently. Therefore, the throughput of the crossbar 2 can be improved.
Further, since the data structure of the routing table 53 ′ is simplified, it is possible to reduce the load applied to the updating process of the routing table 53 ′ by the management unit 4.

The management unit 4 (holding unit 41) may hold the information of all routing tables 53 ′ (see FIG. 17) of all crossbars 2 in the information processing system 1 as management information 42.
[2-2] Second Modification The crossbar 2 according to an embodiment has been described as holding a routing table 53 having valid / invalid columns for each detour output port 8 as shown in FIG. However, the present invention is not limited to this. For example, instead of the routing table 53, the crossbar 2 can select the destination output port 8 from the normal output port 8 and the detour output port 8 by a bit value as shown in FIG. Unless otherwise stated, each configuration of the information processing system 1 is the same as that shown in FIG.

  18 is a diagram illustrating a data structure of the routing table 53 ″ according to the second modification of the embodiment. As illustrated in FIG. 18, the routing table 53 ″ is compared with the routing table 53 illustrated in FIG. Thus, instead of omitting the valid / invalid column of each detour output port 8, a column of output port selection bits is added. For example, in the routing table 53 ″, the bit value of the output port selection bit and the transmission destination output port 8 can be associated as follows.

Output port selection bit value “00”: Normal output port 8
Bit value “01” of output port selection bit: first candidate bypass output port 8
Bit value “10” of output port selection bit: second candidate bypass output port 8
...
Note that the bit width of the output port selection bit may be appropriately increased or decreased according to the number of candidates for the detour output port 8.

  The detour output port management circuit 64 holds the information of the detour output port 8 in the routing table 53 ″ for each frame input from the reception queue 51 to the input queue 61, as in the embodiment. In the routing table 53 ″, since the bit value of the output port selection bit indicates the transmission destination output port 8, the detour output port management circuit 64 detours corresponding to the bit value obtained by adding “1” to the output port selection bit. The information of the output port 8 may be held.

Further, in the update process of the routing table 53 ″, the management unit 4 overwrites the normal output port 8 with the bypass output port 8 and rewrites the valid / invalid of the bypass output port 8 as in the embodiment. It is only necessary to rewrite the bit value of the output port selection bit.
Therefore, according to the information processing system 1 according to the second modification, the same effect as that of the embodiment can be obtained, and the load on the update process of the routing table 53 ″ by the management unit 4 can be reduced. .

  The management unit 4 (holding unit 41) stores information on all routing tables 53 ″ (see FIG. 18) of all crossbars 2 in the information processing system 1 and information on validity / invalidity of all output ports 8 of all crossbars 2. What is necessary is just to hold | maintain as the management information 42. Moreover, the management part 4 may delete about the output port number of the output port 8 which is not reused in the update process of the routing table 53 ".

  In the second modification, the modification of the routing table 53 according to the embodiment has been described. However, the second modification can be applied to the routing table 53 ′ according to the first modification. . That is, the valid / invalid column of each detour output port 8 may be omitted from the routing table 53 ′ shown in FIG. 17 and an output port selection bit column may be added instead. By combining the first modification and the second modification, the same effects as in the first modification can be obtained, and the load applied to the updating process of the routing table 53 ″ by the management unit 4 is changed to the first modification. Can be reduced.

[2-3] Third Modification Although the crossbar 2 according to the embodiment has been described as including the retransmission state machine 63 in each input queue control unit 60 of each input port 6, the present invention is not limited to this. Absent.
FIG. 19 is a diagram illustrating a configuration of a retransmission state machine 63 ′ according to a third modification of the embodiment. For example, the crossbar 2 can be provided with the retransmission state machine 63 ′ shown in FIG. 19 outside the input queue control unit 60, and the input queue control unit 60 and the retransmission state machine 63 ′ can be connected by wiring, You may connect by a pin etc.

As illustrated in FIG. 19, the retransmission state machine 63 ′ according to the third modification includes, for example, a state management unit 631, an alternative output control unit 632, a management unit control unit 633, an output port control unit 634, and a reception port control unit. 635 can be provided.
The state management unit 631 includes a storage device such as a register, and manages the states (I) to (V) described above (see FIG. 10). The state management unit 631 receives the output port block signal B7, the frame transmission stop signal A5 to the input port 6, the output port switching completion signal B10, and the queue retransmission entry number B2 shown in FIG. The register value is changed accordingly.

  The alternative output control unit 632 performs an alternative output process when the register value of the state management unit 631 is “3′b011”. For example, according to the alternative port 8 indicated by the detour output port management circuit 64 A signal D 1 for controlling the selector 62 is transmitted to the selection signal generation circuit 607. In other words, the substitute output control unit 632 substitutes a frame to one transfer destination stored in the input queue 61 corresponding to one transfer destination according to the data transfer state managed by the state management unit 631. The selector 62 is controlled so as to output to the transfer destination.

When the register value of the state management unit 631 is “3′b100”, the management unit control unit 633 transmits the routing table update availability notification signal B9 to the management unit 4.
When the register value of the state management unit 631 is “3′b100” and the routing table 53 is not updated by the management unit 4, the output port control unit 634 sends the output port blockage release signal B11 to the output port 8. Send.

The reception port control unit 635 transmits a frame transmission restart instruction signal A6 to the reception port 5. The reception port control unit 635 transmits the output port blockage release signal B11 when the register value of the state management unit 631 is “3′b100” and the routing table 53 is updated or when the output port control unit 634 transmits the output port blockage release signal B11. If so, the above processing is performed.
As described above, according to the retransmission state machine 63 ′ according to the third embodiment, the function of managing the transfer path change process can be provided outside the crossbar 2, and the control mode ( Logic) can be easily changed. As a result, it is possible to update the retransmission state machine 63 ′ according to changes in the operation mode and configuration of the information processing system 1 at a lower cost than when the entire crossbar 2 is replaced.

  The retransmission state machine 63 ′ is an example of a control device that controls the crossbar 2. A plurality of retransmission state machines 63 ′ in the input port 6 or the crossbar 2 may be integrated in the control device, such as a detour output port management circuit 64 and a selection signal generation circuit 607 in the input queue control unit 60. A plurality of circuits may be included. Further, each function (circuit) block shown in FIG. 19 may be provided in the retransmission state machine 63 shown in FIG. 5 or FIG.

[3] Others While the preferred embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made without departing from the spirit of the present invention. It can be changed and implemented.
For example, the crossbar 2 described above has been described as having three reception ports 5, input ports 6, output ports 8, and connection units 9, but the present invention is not limited to this, and two or four are provided. You may have more than one. The crossbar 2 may have at least one input port 6 and at least as many output ports 8 as the number of transfer destinations. Further, the routing tables 53, 53 ′ and 53 ″ may not be provided for each reception port 5, and the management information 42 provided by the management unit 4 may be provided in the crossbar 2. 62 may be provided outside the input port 6.

The functions of the crossbar 2 (reception port 5, input port 6, routing unit 7, output port 8, and connection unit 9) may be integrated or distributed in any combination.
Furthermore, the processing order of steps S13 and S14 in FIG. 10 is not limited to that described above, and the order may be changed. In this case, the state indicated by the register value of the retransmission state machine 63 may be switched.

Furthermore, although the information processing system 1 illustrated in FIG. 2 has been described as including a plurality of crossbars 2, the present invention is not limited to this. For example, the information processing system 1 may have one crossbar 2. In this case, two or more different transfer paths (for example, a combination of two or more of the same kind or different kinds of buses, cables, wireless communication paths, etc.) may exist between the crossbar 2 and the transmission destination device 3. The crossbar 2 may output a frame to any one of a plurality of transfer destinations to the transmission destination device 3.
[4] Notes
The following supplementary notes are further disclosed with respect to the above embodiment and each modified example.
(Appendix 1)
A transmission source device for transmitting data; and
A transmission destination device that receives the data transmitted from the transmission source device;
A plurality of data transfer devices that are interposed between the transmission source device and the transmission destination device and transfer the data from the transmission source device to the transmission destination device via any one of a plurality of different transfer paths And
The data transfer device
A plurality of storage units that store input transfer data for each transfer destination including the transmission destination device or other data transfer devices connected to the own data transfer device;
A switching unit that selectively switches and outputs the transfer data stored in the plurality of storage units to any of the plurality of transfer destinations;
According to the state of data transfer from the switching unit to one transfer destination via one transfer path, the transfer data to the one transfer destination stored in the storage unit corresponding to the one transfer destination, A control unit that performs an alternative output process for controlling the switching unit so as to output to another transfer destination included in the plurality of different transfer paths.
An information processing apparatus.
(Appendix 2)
The data transfer device
A holding unit that holds transfer destination information regarding one or more transfer destinations of the transfer data;
When the other transfer destination is included in the transfer destination information for the transfer data stored in the storage unit corresponding to the one transfer destination, the control unit performs the alternative output processing based on the transfer destination information. Do
The information processing apparatus according to appendix 1, wherein:
(Appendix 3)
The transfer destination information is information relating to one or more transfer destinations according to a transmission destination device of the transfer data,
In the alternative output process, the control unit is configured to select a plurality of transfer data to the one transfer destination stored in a storage unit corresponding to the one transfer destination according to each transmission destination device of the transfer data. Control the switching unit to output to each other transfer destination
The information processing apparatus according to supplementary note 2, wherein
(Appendix 4)
According to the state of data transfer from the switching unit to the plurality of transfer destinations, further comprising an update unit for updating the transfer destination information held in the holding unit,
The data transfer device
A deterrence unit for deterring storage of the input transfer data in the plurality of storage units;
The control unit, when performing the alternative output processing, transmits an update request for the transfer destination information to the update unit,
In response to an update request from the control unit, the update unit updates the transfer destination information so that transfer data output to the one transfer destination is output to the other transfer destination.
The information processing apparatus according to Supplementary Note 2 or Supplementary Note 3, wherein
(Appendix 5)
The data transfer device
Provided for each transfer destination connected to the own data transfer device, further comprising a plurality of output units for outputting the transfer data to the transfer destination of the transfer data,
In the alternative output process, the control unit stores in a storage unit corresponding to the one output unit in accordance with a state of data transfer from one output unit to the one transfer destination via one transfer path. The switching unit is controlled to output one or more transfer data including the transfer data already output to the one output unit to another output unit corresponding to each transfer data.
The information processing apparatus according to any one of appendices 1 to 4, characterized by:
(Appendix 6)
The data transfer device
A notification unit that outputs an output suppression signal according to a state of data transfer to the plurality of transfer destinations;
An acceptance storage unit that collectively stores transfer data stored in the plurality of storage units;
When the transfer data stored in the reception storage unit is sequentially output to the corresponding storage unit and the output suppression signal is received for the one transfer destination from the notification unit, the output of the transfer data being output from the reception storage unit A reception control unit that performs control to suppress output of the transfer data stored in the reception storage unit to the plurality of storage units until the alternative output process by the control unit is completed
The information processing apparatus according to any one of appendices 1 to 5, characterized in that:
(Appendix 7)
The control unit is a case where the output status of the transfer data from the switching unit to the first transfer destination satisfies the first condition, and the output status of the transfer data from the switch unit to the second transfer destination is When the second condition is satisfied, the switching unit is configured to output transfer data to the first transfer destination stored in the storage unit corresponding to the first transfer destination to the second transfer destination. Control
The information processing apparatus according to any one of appendices 1 to 6, characterized in that:
(Appendix 8)
A transmission source device that transmits data and a transmission destination device that receives the data transmitted from the transmission source device, and the data is transmitted via any one of a plurality of different transfer paths. A data transfer device for transferring from a transmission source device to the transmission destination device,
A plurality of storage units that store input transfer data for each transfer destination including the transmission destination device or other data transfer devices connected to the own data transfer device;
A switching unit that selectively switches and outputs the transfer data stored in the plurality of storage units to any of the plurality of transfer destinations;
According to the state of data transfer from the switching unit to one transfer destination via one transfer path, the transfer data to the one transfer destination stored in the storage unit corresponding to the one transfer destination, A control unit that performs an alternative output process for controlling the switching unit so as to output to another transfer destination included in the plurality of different transfer paths.
A data transfer device.
(Appendix 9)
A holding unit that holds transfer destination information regarding one or more transfer destinations of the transfer data;
When the other transfer destination is included in the transfer destination information for the transfer data stored in the storage unit corresponding to the one transfer destination, the control unit performs the alternative output processing based on the transfer destination information. Do
The data transfer apparatus according to appendix 8, wherein
(Appendix 10)
The transfer destination information is information relating to one or more transfer destinations according to a transmission destination device of the transfer data,
In the alternative output process, the control unit is configured to select a plurality of transfer data to the one transfer destination stored in a storage unit corresponding to the one transfer destination according to each transmission destination device of the transfer data. Control the switching unit to output to each other transfer destination
The data transfer device according to appendix 9, wherein
(Appendix 11)
Provided for each transfer destination connected to the own data transfer device, further comprising a plurality of output units for outputting the transfer data to the transfer destination of the transfer data,
In the alternative output process, the control unit stores in a storage unit corresponding to the one output unit in accordance with a state of data transfer from one output unit to the one transfer destination via one transfer path. The switching unit is controlled to output one or more transfer data including the transfer data already output to the one output unit to another output unit corresponding to each transfer data.
The data transfer device according to any one of appendices 8 to 10, characterized in that:
(Appendix 12)
A notification unit that outputs an output suppression signal according to a state of data transfer to the plurality of transfer destinations;
An acceptance storage unit that collectively stores transfer data stored in the plurality of storage units;
When the transfer data stored in the reception storage unit is sequentially output to the corresponding storage unit and the output suppression signal is received for the one transfer destination from the notification unit, the output of the transfer data being output from the reception storage unit A reception control unit that performs control to suppress output of the transfer data stored in the reception storage unit to the plurality of storage units until the alternative output process by the control unit is completed
The data transfer device according to any one of appendices 8 to 11, characterized in that:
(Appendix 13)
The control unit is a case where the output status of the transfer data from the switching unit to the first transfer destination satisfies the first condition, and the output status of the transfer data from the switch unit to the second transfer destination is When the second condition is satisfied, the switching unit is configured to output transfer data to the first transfer destination stored in the storage unit corresponding to the first transfer destination to the second transfer destination. Control
The data transfer device according to any one of appendices 8 to 12, characterized in that:
(Appendix 14)
A transmission source device that transmits data, a transmission destination device that receives the data transmitted from the transmission source device, and a plurality of different transfer paths interposed between the transmission source device and the transmission destination device. A data transfer method in an information processing system, comprising: one or more data transfer devices that transfer the data from the transmission source device to the transmission destination device via any of them,
The input transfer data corresponds to a transfer destination of the transfer data among a plurality of storage units provided for each transfer destination including the transmission destination device or other data transfer devices connected to the own data transfer device. Store in the storage,
Acquisition of data transfer status to one transfer destination via one transfer path from a switching unit that selectively switches and outputs the transfer data stored in the plurality of storage units to one of the plurality of transfer destinations And
According to the acquired state, the transfer data to the one transfer destination stored in the storage unit corresponding to the one transfer destination is output to other transfer destinations included in the plurality of different transfer paths. Alternate output processing for controlling the switching unit
A data transfer method.
(Appendix 15)
For the transfer data stored in the storage unit corresponding to the one transfer destination, when the transfer destination information related to one or more transfer destinations of the transfer data held in the holding unit includes the other transfer destination, Perform the alternative output processing based on the destination information
15. The data transfer method according to appendix 14, wherein
(Appendix 16)
The transfer destination information is information relating to one or more transfer destinations according to a transmission destination device of the transfer data,
In the alternative output processing, a plurality of transfer data to the one transfer destination stored in a storage unit corresponding to the one transfer destination is transferred to another transfer destination corresponding to each destination device of the transfer data Control the switching unit to output each
The data transfer method according to supplementary note 15, wherein
(Appendix 17)
Suppressing storage of the input transfer data in the plurality of storage units,
When storage of the transfer data in the plurality of storage units is suppressed,
Performing the alternative output process;
The transfer destination information is updated so that transfer data output to the one transfer destination is output to the other transfer destination.
The data transfer method according to Supplementary Note 15 or Supplementary Note 16, wherein
(Appendix 18)
In the alternative output processing, one transfer from one output unit among a plurality of output units provided for each transfer destination connected to the own data transfer device and outputting the transfer data to the transfer destination of the transfer data. One or more including transfer data that has been output to the one output unit and stored in a storage unit corresponding to the one output unit, depending on the state of data transfer to the one transfer destination via the path The switching unit is controlled to output the transfer data to another output unit corresponding to each transfer data.
18. The data transfer method according to any one of appendices 14 to 17, characterized in that:
(Appendix 19)
Sequentially transferring the transfer data stored in the reception storage unit that collectively stores the transfer data stored in the plurality of storage units to the corresponding storage unit;
When the output of the transfer data being output from the reception storage unit is completed when the state of data transfer from the switching unit to the one transfer destination satisfies a predetermined condition, the transfer stored in the reception storage unit Suppress output of the data to the plurality of storage units,
When the alternative output process is completed, output of the transfer data stored in the reception storage unit to the plurality of storage units is resumed.
The data transfer method according to any one of appendices 14 to 18, characterized in that:
(Appendix 20)
The output state of transfer data from the switching unit to the first transfer destination satisfies the first condition, and the output state of transfer data from the switch unit to the second transfer destination satisfies the second condition. If the condition is satisfied, the switching unit is controlled to output the transfer data to the first transfer destination stored in the storage unit corresponding to the first transfer destination to the second transfer destination.
20. The data transfer method according to any one of appendices 14 to 19, wherein
(Appendix 21)
A transmission source device that transmits data and a transmission destination device that receives the data transmitted from the transmission source device, and the data is transmitted via any one of a plurality of different transfer paths. A plurality of storage units that transfer data from a transmission source device to the transmission destination device and store input transfer data for each transfer destination including the transmission destination device or other data transfer devices connected to the own data transfer device. A control device in a data transfer device,
The transfer data stored in the plurality of storage units is selectively switched to one of the plurality of transfer destinations and output from the switching unit to one transfer destination via one transfer path. A state management unit to manage,
Transfer data to the one transfer destination stored in the storage unit corresponding to the one transfer destination is included in the plurality of different transfer paths according to the state of the data transfer managed by the state management unit. An alternative output control unit that controls the switching unit to output to another transfer destination.
A control device.

1 Information processing system (information processing equipment)
2,2A-2I Crossbar (data transfer device)
3, 3A-3F Device 4 Management unit (update unit)
5 reception port (deterrence part)
6 Input port 7 Routing part 8 Output port (output part)
9 Connection 40a CPU
40b Memory 40c Storage unit 40d Interface unit 40e Input / output unit 40f, 40h Recording medium 40g Reading unit 41, 52 Holding unit 42 Management information 51 Reception queue (reception storage unit)
53, 53 ', 53 "routing table (forwarding destination information)
54 Frame transmission judgment circuit (acceptance control unit)
61 Input queue (storage)
62 Selector (switching unit)
63, 63 'retransmission state machine (control unit, control device)
64 Detour output port management circuit 81 Output queue 82 Selector 86 Output port blockage judgment circuit (notification unit)

Claims (8)

A transmission source device for transmitting data; and
A transmission destination device that receives the data transmitted from the transmission source device;
One or more data transfers that are interposed between the transmission source device and the transmission destination device and transfer the data from the transmission source device to the transmission destination device via any one of a plurality of different transfer paths With equipment,
The data transfer device
A plurality of storage units that store input transfer data for each transfer destination including the transmission destination device or other data transfer devices connected to the own data transfer device;
A switching unit that selectively switches and outputs the transfer data stored in the plurality of storage units to any of the plurality of transfer destinations;
According to the state of data transfer from the switching unit to one transfer destination via one transfer path, the transfer data to the one transfer destination stored in the storage unit corresponding to the one transfer destination, A control unit for performing an alternative output process for controlling the switching unit to output to another transfer destination included in the plurality of different transfer paths;
An acceptance storage unit that collectively stores transfer data stored in the plurality of storage units;
And a deterring unit that deters storage of the transfer data stored in the reception storage unit in the plurality of storage units according to a state of data transfer to the plurality of transfer destinations. Processing equipment. The data transfer device
A holding unit that holds transfer destination information regarding one or more transfer destinations of the transfer data;
When the other transfer destination is included in the transfer destination information for the transfer data stored in the storage unit corresponding to the one transfer destination, the control unit performs the alternative output processing based on the transfer destination information. The information processing apparatus according to claim 1, wherein the information processing apparatus performs the processing. The transfer destination information is information relating to one or more transfer destinations according to a transmission destination device of the transfer data,
In the alternative output process, the control unit is configured to select a plurality of transfer data to the one transfer destination stored in a storage unit corresponding to the one transfer destination according to each transmission destination device of the transfer data. The information processing apparatus according to claim 2, wherein the switching unit is controlled to output to each of other transfer destinations. Depending on the state of the data transfer to the plurality of transfer destination from the switching unit, to together further equipped with a update unit for updating the transfer destination information held in the holding portion,
The control unit, when performing the alternative output processing, transmits an update request for the transfer destination information to the update unit,
The update unit updates the transfer destination information so that transfer data output to the one transfer destination is output to the other transfer destination in response to an update request from the control unit. The information processing apparatus according to claim 2 or 3. The data transfer device
A notification unit that outputs an output suppression signal according to a state of data transfer to the plurality of transfer destinations ;
When the transfer data stored in the reception storage unit is sequentially output to the corresponding storage unit and the output suppression signal is received for the one transfer destination from the notification unit, the output of the transfer data being output from the reception storage unit A reception control unit that performs control to suppress output of the transfer data stored in the reception storage unit to the plurality of storage units until the alternative output process by the control unit is completed The information processing apparatus according to any one of claims 1 to 4, wherein the information processing apparatus is characterized. A transmission source device that transmits data and a transmission destination device that receives the data transmitted from the transmission source device, and the data is transmitted via any one of a plurality of different transfer paths. A data transfer device for transferring from a transmission source device to the transmission destination device,
A plurality of storage units that store input transfer data for each transfer destination including the transmission destination device or other data transfer devices connected to the own data transfer device;
A switching unit that selectively switches and outputs the transfer data stored in the plurality of storage units to any of the plurality of transfer destinations;
According to the state of data transfer from the switching unit to one transfer destination via one transfer path, the transfer data to the one transfer destination stored in the storage unit corresponding to the one transfer destination, A control unit for performing an alternative output process for controlling the switching unit to output to another transfer destination included in the plurality of different transfer paths;
An acceptance storage unit that collectively stores transfer data stored in the plurality of storage units;
And a deterring unit that deters storage of the transfer data stored in the reception storage unit in the plurality of storage units according to a state of data transfer to the plurality of transfer destinations. Transfer device. A transmission source device that transmits data, a transmission destination device that receives the data transmitted from the transmission source device, and a plurality of different transfer paths interposed between the transmission source device and the transmission destination device. A data transfer method in an information processing system, comprising: one or more data transfer devices that transfer the data from the transmission source device to the transmission destination device via any of them,
The input transfer data corresponds to a transfer destination of the transfer data among a plurality of storage units provided for each transfer destination including the transmission destination device or other data transfer devices connected to the own data transfer device. Store in the storage,
Acquisition of data transfer status to one transfer destination via one transfer path from a switching unit that selectively switches and outputs the transfer data stored in the plurality of storage units to one of the plurality of transfer destinations And
According to the acquired state, the transfer data to the one transfer destination stored in the storage unit corresponding to the one transfer destination is output to other transfer destinations included in the plurality of different transfer paths. alternative output process for controlling the switching portion rows that are in,
Storing the transfer data stored in the reception storage unit that collectively stores the transfer data stored in the plurality of storage units in the plurality of storage units according to the state of data transfer to the plurality of transfer destinations A data transfer method characterized by suppressing the data. A transmission source device that transmits data and a transmission destination device that receives the data transmitted from the transmission source device, and the data is transmitted via any one of a plurality of different transfer paths. A plurality of storage units that transfer data from a transmission source device to the transmission destination device and store input transfer data for each transfer destination including the transmission destination device or other data transfer devices connected to the own data transfer device. A control device in a data transfer device,
The transfer data stored in the plurality of storage units is selectively switched to one of the plurality of transfer destinations and output from the switching unit to one transfer destination via one transfer path. A state management unit to manage,
Transfer data to the one transfer destination stored in the storage unit corresponding to the one transfer destination is included in the plurality of different transfer paths according to the state of the data transfer managed by the state management unit. An alternative output control unit that controls the switching unit to output to another transfer destination;
Storing the transfer data stored in the reception storage unit that collectively stores the transfer data stored in the plurality of storage units in the plurality of storage units according to the state of data transfer to the plurality of transfer destinations And a reception storage control unit for resuming storage of the transfer data stored in the reception storage unit in the plurality of storage units with respect to a suppression unit that suppresses the transfer .

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