JP6070308B2 - Imaging device - Google Patents

Description

  The present invention relates to an imaging apparatus having a plurality of sensor modules.

  Conventionally, imaging devices having multiple (compound eye) sensor modules measure the distance to an obstacle by calculating the parallax of multiple images, generate a panoramic image by combining multiple images, etc. Has been.

  As such an imaging apparatus, an imaging apparatus using a sensor module having no external synchronization signal input terminal is known in order to reduce the number of signal lines as much as possible. In this case, a synchronization error such as an output video signal becomes a problem between the sensor modules.

  In recent years, the high resolution of sensor modules has been remarkable, and while current consumption has increased, temperature rise cannot be ignored. The temperature rise can be covered by a cooling mechanism outside the sensor module, but there are severe situations in terms of cost. When the temperature rises, the output video signal of each sensor module becomes asynchronous due to an error in the output clock of the PLL circuit in each sensor module, and there is a possibility that the subsequent image processing will be broken. Further, when the sensor module includes a CMOS sensor as an image sensor, sensor characteristics are deteriorated due to an increase in dark current accompanying a temperature rise.

  For example, in Patent Document 1, as an image synchronization technique for a plurality of camera modules having no external synchronization signal input terminal, a vertical synchronization signal output from a plurality of camera modules is output from a camera module determined in advance as a reference. Detects the phase advance amount of the vertical sync signal output from another camera module with respect to the vertical sync signal, and cuts off the clock supply of this other camera module for a time corresponding to the detected phase advance amount Thus, a technique for temporarily stopping the operation is disclosed. However, no consideration is given to the reduction of an asynchronous state or deterioration of sensor characteristics due to a clock error of a PLL circuit in each sensor module due to a temperature rise.

  An object of the present invention is to prevent asynchronism between sensor modules and further prevent deterioration of sensor characteristics in the sensor module by suppressing temperature rise in the sensor module as much as possible in an imaging apparatus having a plurality of sensor modules.

  The present invention provides an imaging device having a plurality of sensor modules, each of which outputs a video signal, a frame synchronization signal, and a line synchronization signal, and a counter that counts a frame synchronization signal of any one of the plurality of sensor modules; The main feature is that it has control means for powering down the plurality of sensor modules each time the counter reaches a predetermined count.

  According to the present invention, since the sensor module is powered down every predetermined frame, it is possible to suppress the temperature rise of the sensor module, and as a result, it is possible to prevent asynchronization between the sensor modules, It is also possible to prevent the deterioration of the characteristics of the image sensor and the like.

1 is an overall configuration diagram according to an embodiment of an imaging apparatus of the present invention. It is a specific block diagram which concerns on 1st Example of an image synchronizer. It is a figure which shows the relationship between a frame synchronizing signal and a power down set reset. It is a figure which shows the relationship between a line synchronizing signal and a power down set reset. It is a specific block diagram which concerns on 2nd Example of an image synchronizer.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the embodiment, the imaging apparatus includes two sensor modules. However, in general, the number of sensor modules may be two or more (a plurality).

  FIG. 1 is an overall configuration diagram of an imaging apparatus according to the present embodiment. In FIG. 1, 11 and 12 are sensor modules (camera modules), 20 is an image synchronization unit, and 30 is an image processing unit. Note that the image processing unit 30 may have a different configuration (such as a personal computer) from the imaging apparatus.

  Each of the sensor module (1) 11 and the sensor module (2) 12 is a lens (for example, a fish-eye lens), and an imaging device such as a CMOS sensor that converts an optical image obtained by the lens into a video signal (image data) of an electrical signal and outputs it. Sensor, PLL circuit that generates clock signal, timing signal generation circuit that generates pixel clock of image sensor, line synchronization signal (horizontal synchronization signal), frame synchronization signal (vertical synchronization signal), etc. based on clock signal doing.

  Each of the sensor module (1) 11 and the sensor module (2) 12 operates independently and outputs a video signal, a frame synchronization signal, and a line synchronization signal. That is, the sensor module (1) 11 sends the video signal 1, the frame synchronization signal 1, and the line synchronization signal 1. The sensor module (2) 12 sends the video signal 2, the frame synchronization signal 2, and the line synchronization signal 2.

  The image synchronization unit 20 receives the video signal, the frame synchronization signal, and the line synchronization signal output from the sensor module (1) 11 and the sensor module (2) 12, and sends these signals to the image processing unit 30 at the same timing. hand over. That is, the image synchronization unit 20 performs a process of synchronizing the video signals output from the sensor module (1) 11 and the sensor module (2) 12, and outputs the synchronized video signals 1 and 2. At the same time, the image synchronization unit 20 outputs a synchronized frame synchronization signal and line synchronization signal.

  The image processing unit 30 receives the video signal 1 and video signal 2 of the sensor module (1) 11 and sensor module (2) 12 synchronized with the image synchronization unit 20, the frame synchronization signal, and the line synchronization signal. Perform the necessary processing. For example, in the distance measurement to an object such as an obstacle, the parallax of the video signal 1 and the video signal 2 of the sensor module (1) 11 and the sensor module (2) 12 is obtained, and the distance to the object is determined by the principle of triangulation. Measure. In the case of an omnidirectional camera or the like, the omnidirectional panoramic image is synthesized by combining the video signal 1 and the video signal 2 of the sensor module (1) 11 and the sensor module (2) 12 based on the overlapping area. Generate.

  Here, in the present embodiment, the image synchronization unit 20 monitors the frame synchronization signal, the line synchronization signal, and the like of the sensor module (1) 11 and the sensor module (2) 12, and the sensor module (1) 11 and Control means for sending a power down signal to the sensor module (2) 12 and powering down the sensor module (1) 11 and the sensor module (2) 12 for a predetermined period is provided. Thereby, the temperature rise of sensor module (1) 11 and sensor module (2) 12 is suppressed.

  Hereinafter, a specific configuration example and operation of the image synchronization unit 20 according to the present embodiment will be described in detail.

  FIG. 2 is a diagram illustrating a specific configuration example of the first embodiment of the image synchronization unit 20. In FIG. 2, a PLL circuit 210 is a circuit that generates a clock for operating the image synchronization unit 20. The line buffer (1) 201 is a buffer memory that temporarily stores the video signal 1 output from the sensor module (1) 11, and the line buffer (2) 202 is the video signal 2 output from the sensor module (2) 12. This is a buffer memory to be temporarily saved. Each of the line buffer (1) 201 and the line buffer (2) 202 has a memory capacity capable of storing video signals for several lines, and can cover a certain amount of line deviation.

  The line buffer write control circuit 220 generates a buffer 1 write address control signal based on the frame synchronization signal 1 and the line synchronization signal 1 from the sensor module (1) 11, and synchronizes with the clock of the PLL circuit 210. (1) The video signal 1 from 11 is sequentially stored in the line buffer (1) 201. The line buffer write control circuit 220 generates a buffer 2 write address control signal based on the frame synchronization signal 2 and the line synchronization signal 2 from the sensor module (2) 12, and is also synchronized with the clock of the PLL circuit 210. The video signal 2 from the sensor module (2) 12 is sequentially stored in the line buffer (2) 202.

  On the other hand, the line buffer read control circuit 230 generates a buffer 1 read address control signal based on the clock from the PLL circuit 210, and the video signal 1 from the line buffer (1) 201 in synchronization with the clock from the PLL circuit 210. Are read sequentially. Similarly, the line buffer read control circuit 230 generates a buffer 2 read address control signal based on the clock from the PLL circuit 210, and sequentially reads the video signal 2 from the line buffer (2) 202.

  Here, the counter (1) 245 counts the line synchronization signal 2 with reference to the line synchronization signal 1, for example. The count value of the counter (1) 245 is output from the line synchronization signal 1 and the line synchronization signal 2, that is, the video signal 1 output from the sensor module (1) 11 and the sensor module (2) 12. The number of line shifts of the video signal 2 is expressed.

  In practice, the line buffer read control circuit 230 receives the video signal 1 and the video signal 2 of the same line from the line buffer (1) 201 and the line buffer (2) 202 based on the count value of the counter (1) 245. A buffer 1 read address control signal and a buffer 2 read address control signal are generated so as to be read. As a result, the synchronized video signal 1 and video signal 2 with no line shift are sequentially read from the line buffer (1) 201 and the line buffer (2) 202.

  The line buffer read control circuit 230 transmits the synchronized video signal 1 and video signal 2 to the image processing unit 30. Further, the line buffer read control circuit 230 generates a frame synchronization signal and a line synchronization signal based on the clock of the PLL circuit 210, and similarly transmits them to the image processing unit 30.

  By the way, when the sensor module (1) 11 and the sensor module (2) 12 are operated for a long time, the temperature rises, and an output video of each sensor module is caused by an error of an output clock of a PLL circuit in each sensor module. The signal is out of sync. Increasing the number of lines in the line buffer (1) 201 and the line buffer (2) 202 can absorb a certain degree of synchronization shift, but increases the cost. Therefore, in this embodiment, the temperature rise of the sensor module (1) 11 and the sensor module (2) 12 is suppressed as follows, and as a result, the synchronization shift of the output video signal of each sensor module is prevented.

  In FIG. 2, a counter (2) 255 is a counter that counts the frame synchronization signal 1 output from the sensor module (1) 11. The counter (2) 255 may be configured to count the frame synchronization signal 2 output from the sensor module (2) 12.

  When the counter (2) 255 reaches a predetermined count number, the frame monitor circuit 250 resets the counter (2) 255 and passes the OR circuit 260 to the sensor module (1) 11 and the sensor module (2) 12. Send a power-down signal. The counter (2) 255 starts counting when the frame synchronization signal 1 is output again from the sensor module (1) 11 after reset. That is, the frame monitor circuit 250 transmits a power-down signal to the sensor module (1) 11 and the sensor module (2) 12 every time the counter (2) 255 reaches a predetermined count (every predetermined frame). To do. That is, the frame monitor circuit 250 functions as a control unit that powers down each sensor module.

  When the sensor module (1) 11 and the sensor module (2) 12 receive the power down signal from the frame monitor circuit 250, the sensor module (1) 11 and the sensor module (2) 12 enter the low power mode (standby state). In the low power mode, the PLL circuit and the image sensor (CMOS sensor, etc.) in the sensor module (1) 11 and the sensor module (2) 12 stop operating, and the sensor module (1) and the sensor module (2) 12 No video signal, frame synchronization signal, or line synchronization signal is transmitted.

  Thereafter, when the power down is released, the sensor module (1) 11 and the sensor module (2) 12 return to the normal power mode. When returning to the normal power mode, the PLL circuit and the imaging sensor in the sensor module (1) 11 and sensor module (2) 12 resume operation, and the sensor module (1) 11 and sensor module (2) 12 start again. A video signal, a frame synchronization signal, and a line synchronization signal are transmitted.

  In the low power mode, the PLL circuit, the image sensor, and the like in the sensor module (1) 11 and the sensor module (2) 12 stop operating, so that current consumption of these sensor modules is reduced and temperature rise is suppressed.

  FIG. 3 shows the relationship between the frame synchronization signal and the power down set / reset. FIG. 3 shows an example in which power-down is performed for one frame period every N frames, but how many frames the power-down is applied and for how long the power-down is performed are, for example, In addition, the temperature rise rate of the sensor module, the frame skip frequency, or the like may be simulated in advance, or the user may determine whether frame skip is acceptable as an application.

  Returning to FIG. 2, on the other hand, the line monitor circuit 240, when the count number of the counter (1) 245 described above becomes equal to or greater than a predetermined value, that is, the line synchronization signal 1 of the sensor module (1) 11 and the sensor module ( 2) When the line shift of the line synchronization signal 2 of 12 becomes an unacceptable number of lines, the counter (1) 245 is reset and the OR circuit 260 is used to detect the sensor module (1) 11 and the sensor module (2) 12. Send a power-down signal. That is, the line monitor circuit 240 functions as a control unit that powers down the sensor module, like the frame monitor circuit 250 described above. When the line synchronization signals 1 and 2 are output from the sensor module (1) 11 and the sensor module (2) 12 after the reset, the counter (1) 245 is reset to the line of the line synchronization signal 2 based on the line synchronization signal 1 again. Start counting deviations.

  When the sensor module (1) 11 and the sensor module (2) 12 receive the power down signal from the line monitor circuit 240, they enter the low power mode. The operations of the sensor module (1) 11 and the sensor module (2) 12 at this time are the same as when the power down signal is received from the previous frame monitor circuit 250. Thereafter, when the power down is released, the sensor module (1) 11 and the sensor module (2) 12 return to the normal power mode.

  FIG. 4 shows the relationship between the line synchronization signal and the power down set / reset. When the line shift between the line synchronization signal 1 and the line synchronization signal 2 becomes an unacceptable number of lines, how long the power down is performed is basically the same as in the case of the previous frame synchronization signal. For example, it may be shorter than the frame synchronization signal.

  According to the present embodiment, since the sensor module (1) 11 and the sensor module (2) 12 temporarily stop operation every predetermined frame, the current consumption of these sensor modules is reduced and the temperature rises. As a result, it is possible to prevent the occurrence of synchronization loss. Further, even when the deviation of the line synchronization signal between the sensor module (1) 11 and the sensor module (2) 12 exceeds the allowable value, the operation is temporarily stopped in the same manner, so that the synchronization deviation is eliminated at an early stage. Is possible.

  Note that when the sensor module (1) 11 and the sensor module (2) 12 stop operating, the video signal, the frame synchronization signal, and the line synchronization signal are not transmitted. However, this is temporary and does not cause any trouble. . By suppressing the temperature rise in the sensor module (1) 11 and the sensor module (2) 12, it is possible to prevent deterioration of characteristics of an image sensor (such as a CMOS sensor).

  FIG. 5 is a diagram illustrating a specific configuration example according to the second embodiment of the image synchronization unit 20. This second embodiment is based on the premise that the sensor module (1) 11 and the sensor module (2) 12 each have a built-in temperature sensor.

  5 is different from FIG. 2 in that a temperature monitor circuit 270 is added. Other configurations are the same as those in FIG. The temperature monitor circuit 270 inputs temperature sensor values (temperature sensor value 1 and temperature sensor value 2) from the sensor module (1) 11 and the sensor module (2) 12, respectively, and one of the temperature sensor values is predetermined. When the threshold value is exceeded, a power down signal is transmitted to the sensor module (1) 11 and the sensor module (2) 12 via the OR circuit 260. That is, the temperature monitor circuit 270 functions as a control unit that powers down each sensor module.

  When the sensor module (1) 11 and the sensor module (2) 12 receive the power down signal from the temperature monitor circuit 270, the sensor module (1) 11 and the sensor module (2) 12 enter the low power mode. The operations in the sensor module (1) 11 and the sensor module (2) 12 at this time are the same as when the power down signal is received from the previous line monitor circuit 240 or frame monitor circuit 250. Thereafter, when the power down is released, the sensor module (1) and the sensor module (2) 12 return to the normal power mode.

  In addition, when the temperature of the sensor module (1) 11 and the sensor module (2) 12 becomes equal to or higher than a predetermined temperature, the duration of the power down is determined by simulating the rate of temperature rise of the sensor module in advance. You can set it.

  According to the present embodiment, more precise temperature management of the sensor module (1) 11 and the sensor module (2) 12 can be realized, and further suppression of temperature rise, prevention of asynchronousness, prevention of deterioration of the imaging sensor, and the like can be realized.

  As mentioned above, although embodiment of this invention was described, this invention is not limited to the above-mentioned embodiment. The present invention can be variously modified and replaced without departing from the scope of the claims.

DESCRIPTION OF SYMBOLS 11, 12 Sensor module 20 Image synchronization part 30 Image processing part 201,202 Line buffer 210 PLL circuit 220 Line buffer write control circuit 230 Line buffer read control circuit 240 Line monitor circuit 245 Counter (1)
250 Frame monitor circuit 255 Counter (2)
270 Temperature monitor circuit

Japanese Patent No. 4529841

Claims (3)

In an imaging device having a plurality of sensor modules, each sending a video signal, a frame synchronization signal, and a line synchronization signal,
A counter that counts a frame synchronization signal of any one of the plurality of sensor modules;
Control means for powering down the plurality of sensor modules each time the counter reaches a predetermined count number;
An imaging device comprising: A counter that counts the number of line shifts of line synchronization signals of the plurality of sensor modules;
The control means powers down the plurality of sensor modules when the counter reaches a predetermined count.
The imaging apparatus according to claim 1. Each of the plurality of sensor modules has a built-in temperature sensor,
When the value of the temperature sensor of any of the plurality of sensor modules exceeds a predetermined threshold, the control means sets the plurality of sensor modules to power down.
The imaging apparatus according to claim 1 or 2, wherein

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