JP6066658B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device in which a plurality of large scale integrated circuits (LSIs) and the like are stacked, and more particularly to a semiconductor device used in an imaging device such as a digital camera.

  In recent years, miniaturization of semiconductor elements such as transistors has progressed, and as a result, the performance of large-scale integrated circuits such as LSIs has been dramatically improved. For example, the transistor gate length is 0.1 μm or less, and the driving clock frequency is on the order of GHz. As described above, the performance and function of an LSI are improved by integrating a large number of semiconductor elements on one chip by using a miniaturization technique.

  However, due to the limitations of miniaturization and the increase in functions to be mounted, when many transistors are integrated on one chip, an increase in the area of one chip becomes significant when considering signal wiring in LSI. End up. Considering this point, it is not always appropriate to integrate a large number of transistors on one chip.

  In order to suppress an increase in the area of one chip, for example, there is a semiconductor device in which a plurality of LSIs (that is, chips) are stacked. That is, a semiconductor device in which a plurality of LSIs are stacked in a three-dimensional direction (three-dimensional) is known. In this type of semiconductor device, LSIs having different functions such as a logic LSI, a memory LSI, and an image sensor LSI are three-dimensionally stacked to improve integration efficiency.

  In such a semiconductor device, communication between stacked LSIs and communication between stacked LSI groups and an external device are performed by micro bumps or through vias (see Patent Document 1).

JP 2010-80802 A

  By the way, in the semiconductor device described in Patent Document 1, the LSIs to be stacked have the same size, and the LSI located between the highest and lowest LSIs is the same as the highest or lowest LSI. If they are different, it is difficult to efficiently stack a plurality of LSIs.

  Furthermore, in the semiconductor device described in Patent Document 1, when the highest-order LSI and the lowest-order LSI communicate with each other, communication is performed using a dedicated through electrode, so that the lowest-order LSI and the lowest-order LSI are used. When a semiconductor element such as a transistor is integrated in an LSI located between the two LSIs, the degree of freedom in layout is reduced due to the through electrodes.

  In addition, for example, taking a digital camera as an example, when a captured image is continuously recorded in a high-speed frame using an imaging device having a large number of pixels, a device (LSI) for the imaging device and recording processing are performed. It is necessary to increase the transmission speed with the device (LSI) that performs the process.

  In order to perform high-speed transmission, it is desirable that the above devices be adjacent to each other, but it may be difficult to make the above devices adjacent due to layout.

  On the other hand, if a three-dimensionally stacked semiconductor device using the above-described through electrode is used, the above devices can be directly connected to perform high-speed transmission. However, when the through electrode is used, the semiconductor device is connected to the through electrode. Must be used as a region for the through electrode.

  As a result, a semiconductor element such as a transistor cannot be mounted on a part of the semiconductor device, and circuit efficiency (that is, mounting efficiency) is lowered.

  Accordingly, an object of the present invention is to easily stack an integrated circuit such as a plurality of LSIs, and the degree of freedom of layout in each integrated circuit is not lowered, and the mounting efficiency is lowered. It is an object of the present invention to provide a semiconductor device that does not occur.

To achieve the object, the semiconductor device according to the present invention is a semiconductor device in which at least three integrated circuits are arranged stacked on the substrate, the first integrated circuit and said first integrated circuit a third integrated circuit and the first integrated circuit and the connection for connecting the positioned above said except second integrated circuits a first integrated circuit located immediately above, the second integrated An insulating spacer provided for laminating the third integrated circuit on the upper side of the circuit, and the connecting portion includes a plurality of lower electrodes for connecting to the electrodes of the first integrated circuit And a plurality of upper electrodes for connecting to the electrodes of the third integrated circuit, and the corresponding electrodes of the upper electrode and the lower electrode are connected to each other by an internal substrate, and the first integrated circuit and the second is connected with the first integrated circuit Wherein the of being arranged so as to overlap with a portion of an integrated circuit.

  According to the present invention, when a plurality of integrated circuits such as LSIs are stacked, they can be easily stacked, and the degree of freedom of layout in each integrated circuit is not lowered, and the mounting efficiency can be improved. it can.

It is a figure which fractures | ruptures and shows the structure about an example of the semiconductor device by the 1st Embodiment of this invention. 2A and 2B are diagrams for explaining a configuration of a connection area illustrated in FIG. 1, in which FIG. 1A is a diagram illustrating an example in which lSIs are connected by wire, and FIG. 2B is a diagram illustrating an example in which LSIs are connected by radio. is there. It is a figure which fractures | ruptures and shows an example about the structure of the semiconductor device by the 2nd Embodiment of this invention. It is a figure which fractures | ruptures and shows another example about the structure of the semiconductor device by the 2nd Embodiment of this invention. It is a figure which fractures | ruptures and shows an example about the structure of the semiconductor device by the 3rd Embodiment of this invention. 6A and 6B are diagrams for explaining the configuration of the LSI shown in FIG. 5, wherein FIG. 5A is a side view showing the configuration of the first LSI, FIG. 5B is a side view showing the configuration of the third LSI, and FIG. It is a side view which shows the structure of a 2nd LSI. FIG. 6 is a perspective view showing arrangement positions of a second electrode, a third electrode, and a fourth electrode provided in the second LSI shown in FIG. 5. It is a figure which fractures | ruptures and shows the structure about an example of the semiconductor device by the 4th Embodiment of this invention.

  Hereinafter, semiconductor devices according to embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a diagram showing a configuration of an example of a semiconductor device according to the first embodiment of the present invention, with the configuration broken.

  The illustrated semiconductor device 100 is packaged by stacking a plurality of integrated circuits such as LSIs. In the illustrated example, a semiconductor device (hereinafter referred to as a stacked LSI) 100 includes three LSIs 103, 106, and 107 stacked, and the LSI 103 is disposed on one surface on an interposer (substrate) 102. A plurality of external terminals 101 are formed on the other surface of the interposer 102.

  The LSI 103 has a plurality of electrodes 104, and the LSI 103 is connected to the LSI 106 by micro bumps 105. An LSI 107 is disposed on the LSI 106 via a spacer 109, and a connection area 108 is defined between the LSI 103 and the LSI 107.

  In the illustrated example, the size (surface area) of the LSI 106 is smaller than the sizes of the LSIs 103 and 107.

  The external terminal 101 is a terminal for connecting the stacked LSI 100 and an external device. Although not shown in FIG. 1, wiring for connecting the LSI 103 and the external terminal 101 is formed in the interposer 102.

  In the illustrated example, the LSI 103 includes a CPU and an image processing unit that performs image processing and a communication unit that performs high-speed communication with an external device on a system board outside the stacked LSI 100. The electrode 104 is used to electrically connect LSIs to each other and to electrically connect LSIs and interposers.

  As shown in the figure, the electrodes 104 of the LSI 103 and the electrodes 104 of the LSI 106 are connected by micro bumps 105, and signals are transmitted and received between these LSIs.

  For example, a memory such as DRAM, SRAM, flash memory, or magnetic memory is mounted on the LSI 106. That is, the LSI 106 is a memory LSI. Further, the LSI 107 is equipped with an image sensor that photoelectrically converts light incident from the outside.

  The connection area (connection portion) 108 is a dedicated area for connecting the electrode 104 of the LSI 103 and the electrode 104 of the LSI 107. The height is equal to the interval between the LSI 103 and the LSI 107. The spacer 109 is used as a member for stacking the LSI 106 and the LSI 107.

  Here, a signal flow in the illustrated stacked LSI 100 will be described.

  Now, when light incident from the outside is received by the LSI 107 positioned on the upper side of the LSI 103, the LSI 1107 photoelectrically converts the light and then transmits it as a digital signal (for example, an image signal) to the LSI 103 via the connection region 108. . The LSI 103 performs image signal processing and encoding processing on the digital signal using the LSI 106 which is a memory LSI, and the processed digital signal is recorded on an external device (such as an SD card connected to the outside of the stacked LSI 100). Send as.

  FIG. 2 is a diagram for explaining the configuration of connection region 108 shown in FIG. FIG. 2A is a diagram showing an example in which lSIs are connected by wire, and FIG. 2B is a diagram showing an example in which LSIs are connected by radio.

  In FIG. 2A, the connection region 108 includes a silicon substrate 200, and a through electrode 201 extending in the vertical direction in the figure is formed on the silicon substrate 200. Electrodes 104 are formed at both ends of the through electrode 201, and micro bumps are disposed on the electrodes 104 (note that the micro bumps 105 are not shown in the connection region 108 in FIG. 1). . In other words, the through electrode 201 electrically connects the LSI 103 and the LSI 107 via the electrode 104 and the micro bump 105.

  As a result, the digital signal obtained as a result of photoelectric conversion in the LSI 107 is converted into the electrode 104 of the LSI 107, the micro bump 105, the connection region electrode 104, the through electrode 201, the electrode 104 of the connection region 108, the micro bump 105, and the LSI 103. It is sent to the LSI 103 via the electrode 104.

  In FIG. 2B, the connection area 108 includes a transmitter (transmission unit) 202 and a receiver (reception unit) 203. An electrode 104 is formed on the transmitter 202, and a micro bump 105 is disposed on the electrode 104. Similarly, an electrode 104 is formed on the receiver 203, and a micro bump 105 is disposed on the electrode 104.

  Although not shown, the transmitter 202 includes a conversion unit for converting a digital signal (image data) into parallel serial data, an amplitude amplification unit, and an antenna unit. The receiver 203 includes an antenna unit, an amplitude amplification unit, and a conversion unit for serial / parallel conversion of image data.

  Image data obtained as a result of photoelectric conversion in the LSI 107 is given to the transmitter 202 via the electrode 104 of the LSI 107, the micro bump 105, and the electrode 104 of the transmitter 202. Then, the transmitter 202 sends image data to the receiver 203 by radio. When receiving the image data, the receiver 203 sends the image data to the LSI 103 via the electrode 104 of the receiver 203, the micro bump 105, and the electrode 104 of the LSI 103.

  As a synchronization method used for transmission / reception, for example, a synchronization signal transmission method in which the LSI 107 generates a synchronization signal and the transmitter 202 transmits the synchronization signal to the receiver 203 is used. Furthermore, the receiver 203 may be provided with a PLL (Phase Locked Loop) circuit and a demodulator so as to be synchronized.

  In the example shown in FIG. 2B, the example in which the micro bump 105, the electrode 104, the transmitter 202, and the receiver 203 are mounted on the connection region 108 has been described. However, the receiver 203 is mounted on the LSI 103 and the transmitter 202 is mounted on the LSI 107. You may make it mount in. At this time, the connection area 108 is included in the LSI 103 and the LSI 107.

  Furthermore, in the first embodiment of the present invention, an example in which an image sensor, a memory, a CPU, and the like are mounted on the LSI 103, the LSI 106, and the LSI 107 has been described. Is not limited to the above functions.

  In addition, in the above-described example, the case where the size of the LSI of the intermediate layer is smaller than the size of the LSI of the lowermost layer and the uppermost layer in the stacked LSI 100 stacked in three layers has been described. Thus, the laminated LSI 100 can be configured. When the stacked LSI 100 has four or more layers, the LSI located immediately above the LSI is directly connected to the reference LSI with the lowermost LSI as the reference LSI. The remaining LSIs are each connected to the reference LSI by connection areas formed in the reference LSI. As a result, in the stacked LSI 100, the lowest-layer LSI is the largest, the LSI located immediately above the lowest-layer LSI is the smallest, and the size of the LSI increases toward the upper layer.

  As described above, in the first embodiment of the present invention, the lowermost LSI 103 which is the reference LSI (predetermined LSI) and the LSI 107 excluding the LSI located immediately above the reference LSI overlap with parts of the LSIs 103 and 107. Since the connection is performed by the connection region (connection portion) arranged in the LSI, not only the stacking is facilitated but also the LSIs can be easily connected without impairing the freedom of layout of the LSIs.

[Second Embodiment]
Subsequently, an example of the semiconductor device according to the second embodiment of the present invention will be described.

  FIG. 3 is a diagram showing an example of the configuration of the semiconductor device according to the second embodiment of the present invention, broken away. In FIG. 3, the same constituent elements as those of the semiconductor device shown in FIG.

  The illustrated semiconductor device (laminated LSI) 300 further includes LSIs 301, 302, and 303. The LSI 301 is disposed on the LSI 106 and the LSI 302 is disposed on the LSI 301. The LSI 103, LSI 106, LSI 301, and LSI 302 are sequentially electrically connected by the electrode 104 and the micro bump 105. A spacer 109 that is an insulator is disposed between the LSI 302 and the LSI 107.

  On the other hand, as described with reference to FIGS. 1 and 2, the first connection region 108 is provided on the LSI 103, and the LSI 303 serving as a relay layer is disposed on the first connection region 108. (That is, the connection area is divided). A second connection area 108 is arranged on the LSI 303. The LSI 103, the first connection region 108, the LSI 303, and the second connection region 108 are electrically connected by the electrode 104, and the LSI 107 is electrically connected to the second connection region 108.

  Each of the LSI 301 and the LSI 302 is a memory on which, for example, a DRAM, SRAM, flash memory, or magnetic memory is mounted, and is used as a memory together with the LSI 106 in image signal processing and encoding processing performed by the LSI 103. The LSI 303 is a relay layer that connects the first and second connection areas 108 and relays signals transmitted through the first and second connection areas 108.

  In the example illustrated in FIG. 3, the three LSIs 106, 301, and 302 are sequentially stacked between the LSI 103 and the LSI 107, and thus the height thereof is increased. For this reason, when trying to connect the LSI 103 and the LSI 107 with one connection area 108, the strength may be insufficient. For this reason, here, the LSI 303 is used as a relay layer, and the LSI 303 is disposed between the first connection region 108 and the second connection region 108 to avoid a decrease in strength.

  Note that the first and second connection areas 108 transmit signals by wire or wirelessly as described with reference to FIG.

  FIG. 4 is a diagram showing another example of the configuration of the semiconductor device according to the second embodiment of the present invention. In FIG. 4, the same components as those of the semiconductor device shown in FIG.

  The illustrated semiconductor device (laminated LSI) 400 includes an LSI 303 ′ instead of the LSIs 301 and 303. The LSI 303 ′ is disposed between the LSIs 106 and 302 and includes first and second connection regions. 108.

  The LSI 303 ′ is electrically connected to the LSI 302 by the electrode 104 and the micro bump 105, and a spacer 109 is disposed between the LSI 303 ′ and the LSI 106. The LSI 303 ′ is electrically connected to the first and second connection regions 108 by the electrode 104.

  In the illustrated example, the LSI 303 ′ is a logic LSI including a CPU, and is connected to the LSI 103 via the first connection area 108. A part of the LSI 303 'is also used as a relay layer.

  The functions of the LSIs shown in the second embodiment of the present invention are not limited to the functions described above.

  As described above, according to the second embodiment of the present invention, when the height of the semiconductor device is increased, the relay layer (LSI) is disposed between the connection regions. Even if it is high, the strength is not insufficient. Since the lowermost LSI, which is the reference LSI, and the remaining LSI except for the LSI located immediately above the reference LSI are connected to other LSIs using the connection area formed in the reference LSI. In addition to facilitating lamination, LSIs can be easily connected without impairing the degree of freedom of LSI layout.

[Third Embodiment]
Next, a semiconductor device according to a third embodiment of the present invention will be described.

  FIG. 5 is a cutaway view showing an example of the configuration of the semiconductor device according to the third embodiment of the present invention.

  The illustrated semiconductor device 500 has a three-dimensional structure in which a plurality of integrated circuits (LSIs) are three-dimensionally arranged and packaged. The semiconductor device 500 includes a substrate 517 and is electrically connected to each component (not shown) mounted on the upper surface thereof. A package substrate 504 having solder balls 504a is stacked on the substrate 517. The package substrate 504 is sequentially provided with a second LSI (second integrated circuit) 502, a third LSI (third integrated circuit) 503, and A first LSI (first integrated circuit) 501 is stacked.

  FIG. 6 is a diagram for explaining the configuration of the LSI shown in FIG. FIG. 6A is a side view showing the configuration of the first LSI, and FIG. 6B is a side view showing the configuration of the third LSI. FIG. 6C is a side view showing the configuration of the second LSI.

  A first LSI 501 illustrated in FIG. 6A includes a semiconductor layer 505 (the semiconductor layer 505 of the first LSI 501 is a first semiconductor layer). The semiconductor layer 505 includes, for example, a transistor. Gate, source, and drain and channel regions are formed. An insulating film (not shown) such as silicon dioxide is formed on the first semiconductor layer 505. On the semiconductor layer 505, a wiring layer 506 having a wiring 507 that electrically connects the transistor and the first electrode 508 mounted on the top of the first LSI 501 is formed (the wiring of the first LSI 501). Layer 506 is a first wiring layer).

  The wiring layer 506 may be formed of two or more multilayer wiring layers. The metal used for wiring in the wiring layer 506 is, for example, Au (gold) or Al (aluminum), but can be variously selected according to conductivity and application.

  Similar to the first LSI 501, the third LSI 503 illustrated in FIG. 6B includes a semiconductor layer 505 and a wiring layer 506. The semiconductor layer 505 and the wiring layer 506 of the third LSI 503 are a third semiconductor layer and a third wiring layer, respectively.

  Further, the third LSI 503 includes a seventh electrode 514 similar to the first electrode 508 provided in the first LSI 501, and also includes a fifth electrode 512 and a sixth electrode 513.

  The fifth electrode 512 is formed on the lower surface of the semiconductor layer 505, and the sixth electrode 513 and the seventh electrode 514 are formed on the upper surface of the wiring layer 506. The fifth electrode 512 and the sixth electrode 513 are electrically connected through a wiring 507 formed in the wiring layer 506 and a through-silicon via 515 formed in the semiconductor layer 505.

  Similar to the first LSI 501, the second LSI 502 illustrated in FIG. 6C includes a semiconductor layer 505 and a wiring layer 506. The semiconductor layer 505 and the wiring layer 506 of the second LSI 502 are a second semiconductor layer and a second wiring layer, respectively. Further, the second LSI 502 includes a second electrode 509, a third electrode 510, and a fourth electrode 511 similar to the first electrode 508 provided in the first LSI 501.

  In the semiconductor device 500 shown in FIG. 5, a second LSI 502 is stacked on a package substrate 504 having solder balls with the semiconductor layer 505 as a lower surface. The second electrode 509 provided in the second LSI 502 is electrically connected to the package substrate 504 by a bonding wire 516 made of Au (gold) or the like.

  A third LSI 503 is stacked on the second LSI 502. When the third LSI 503 is stacked, the sixth electrode 513 and the seventh electrode 514 are positioned on the lower surface side, and the fifth electrode 512 is positioned on the upper surface side. Arrangement is performed such that the third electrode 510 provided in the second LSI 502 and the sixth electrode 513 provided in the third LSI 503 are electrically connected. Further, the arrangement is performed such that the fourth electrode 511 provided in the second LSI 502 and the seventh electrode 514 provided in the third LSI 503 are electrically connected.

  A first LSI 501 is stacked on the third LSI 503. When the first LSI 501 is stacked again, the first electrode 508 is positioned on the lower surface side and the semiconductor layer 505 is positioned on the upper surface side. The first electrode 508 provided in the first LSI 501 and the fifth electrode 512 provided in the third LSI 503 are electrically connected. The first electrode 508 is electrically connected to the third electrode 510 via the fifth electrode 512, the through silicon via 515, the wiring, and the sixth electrode 513 provided in the third LSI 503. The

  FIG. 7 is a perspective view showing the arrangement positions of the second electrode 509, the third electrode 510, and the fourth electrode 511 provided in the second LSI 502.

  In the second LSI 502, the second electrode 509 is disposed in the vicinity of the outer peripheral portion of the second LSI 502. The fourth electrode 511 is disposed near the center portion of the second LSI 502. The third electrode 510 is disposed so as to be positioned between the second electrode 509 and the fourth electrode 511.

  It should be noted that the first LSI 501 and the third LSI 503 and the third LSI 503 and the second LSI 502 may be configured to sandwich an insulating material other than the portion where each electrode is in contact. Furthermore, a material having an adhesive effect for bonding each LSI may be used as the insulating material.

  As described above, in the semiconductor device according to the third embodiment of the present invention, the wiring layer, the electrode, the semiconductor layer, and the like are arranged as described above, so that the integration efficiency can be improved. The transmission speed between LSIs can be improved.

[Fourth Embodiment]
Subsequently, an example of a semiconductor device according to the fourth embodiment of the present invention will be described.

  FIG. 8 is a diagram showing the configuration of an example of a semiconductor device according to the fourth embodiment of the present invention, with the configuration broken. In the semiconductor device shown in FIG. 8, the same components as those in the semiconductor device shown in FIG.

  In the semiconductor device 500 illustrated in FIG. 8, a case portion 519 is attached to a package substrate 504, and the first LSI 501, the second LSI 502, and the third LSI 503 are covered with the case portion 519. An opening is formed in the case portion 519 so as to face the first LSI 501, and a lens 518 is fitted in the opening.

  In the example illustrated in FIG. 8, the first LSI 501 is a CMOS image sensor having an A / D conversion circuit, and the first LSI 501 receives an optical image via a lens 118. Then, the first LSI 501 photoelectrically converts the optical image and outputs an analog signal corresponding to the optical image. The analog signal is converted into a digital signal by an A / D conversion circuit.

  This digital signal is transmitted from the first electrode 508 provided in the first LSI 501 to the fifth electrode 512 provided in the third LSI 503, the through-silicon via 115, the wiring, and the sixth electrode 513. , And input from the third electrode 510 to the second LSI 502. The third LSI 502 through which the digital signal passes is, for example, a memory such as a DRAM. The digital signal is not directly recorded in the memory portion, but is written to the memory portion via the second LSI 502 and is read out through the seventh electrode 514 under the control of the second LSI 502.

  The second LSI 502 is, for example, a signal processing LSI, performs predetermined processing on the input digital signal, and writes the processed digital signal as image data in the third LSI 503 that is a memory. Further, the second LSI 502 also performs read control of image data written in the memory.

  The second LSI 502 performs signal connection with a component mounted on the substrate 117, for example, a recording medium such as an SD card, via the second electrode 509 and the bonding wire 516.

  Thus, in the fourth embodiment of the present invention, if a lens is attached to the semiconductor device 100, an imaging device such as a camera or a video camera can be easily configured.

  As described above, in the semiconductor device according to the embodiment of the present invention, when a plurality of integrated circuits such as LSIs are stacked, not only can they be stacked easily, but also the degree of freedom of layout in each integrated circuit is increased. Circuit efficiency (that is, mounting efficiency) can be improved without being reduced.

  As mentioned above, although preferable embodiment of this invention was described, this invention is not limited to these embodiment, A various deformation | transformation and change are possible within the range of the summary.

102 Interposer 103, 106, 107 LSI
104 Electrode 105 Micro bump 108 Connection area 109 Spacer 200 Silicon substrate 201 Through electrode 202 Transmitter 203 Receiver

Claims (8)

A semiconductor device in which at least three integrated circuits are stacked on a substrate,
And a third integrated circuit and the first integrated circuit with the exception of the second integrated circuit located located above the said first integrated circuit directly on the first integrated circuit and said first integrated circuit a connecting portion for connection,
An insulating spacer provided on the upper side of the second integrated circuit for stacking the third integrated circuit ;
The connecting portion includes a plurality of lower electrodes for connecting to the electrodes of the first integrated circuit and a plurality of upper electrodes for connecting to the electrodes of the third integrated circuit, and the upper electrode and the the corresponding electrodes of the lower electrode is connected by an internal substrate respectively, are arranged so as to overlap a portion of the third integrated circuit connected to the first integrated circuit and the first integrated circuit A semiconductor device. Wherein said second integrated circuit located between said first integrated circuit and the third integrated circuit, characterized in that the area is smaller than the first integrated circuit and the third integrated circuit Item 14. The semiconductor device according to Item 1. 3. The semiconductor device according to claim 1, wherein a height of the connection portion is an interval between the first integrated circuit and the third integrated circuit. The connection unit includes a transmission unit connected to the third integrated circuit,
A receiver connected to the first integrated circuit,
The semiconductor device according to claim 1, wherein the transmission unit and the reception unit are connected wirelessly. 3. The semiconductor device according to claim 1 , wherein the connection unit connects the first integrated circuit and the third integrated circuit by wire. When the interval between the first integrated circuit and the third integrated circuit is larger than a predetermined interval, the connection portion is divided into a plurality of connection regions in the height direction, and the space between the connection regions is The semiconductor device according to claim 1, further comprising a relay layer that relays electrical connection. The semiconductor device according to claim 6, wherein a part of the second integrated circuit is used as the relay layer. The first integrated circuit is the bottommost integrated circuit closest to the substrate, and the third integrated circuit is the topmost integrated circuit farthest from the substrate;
The third integrated circuit is an LSI for performing at least photoelectric conversion;
The first integrated circuit is a logic LSI that processes a signal obtained as a result of the photoelectric conversion,
8. The semiconductor device according to claim 1, wherein the second integrated circuit is a memory LSI.

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