JP6047900B2 - Verification device, verification method, verification program - Google Patents

Description

  The present invention relates to a verification device, a verification method, and a verification program.

  Conventionally, there is a technique for efficiently designing a high-quality printed circuit board. For example, Patent Document 1 discloses an invention such as a circuit board design support apparatus that can examine component placement without performing unnecessary examination of component placement when downsizing a printed circuit board. Yes.

  The circuit-based design support apparatus as described above may be provided with a function for verifying whether the circuit diagram information created by the user by CAD and the design specification are logically consistent. Automatic verification cannot be performed when there is a shortage of information necessary for verification, and the user has to perform a manual review. However, if automatic verification is assumed, it is easy to overlook the part that needs to be reviewed again. Forgetting to verify the logical connection information, or when the user immediately identifies the part that needs to be reviewed. There was a problem that it took time and trouble.

  The present invention has been made in view of the above, and provides a verification device for verifying a circuit diagram, in which a user can easily grasp a portion to be verified in a circuit diagram. There is.

In order to solve the above-described problems and achieve the object, the present invention provides terminal identification information of a component arranged on a printed circuit board, terminal identification information to which the terminal is connected, and signal of the terminal. Created based on design specification information having logical connection information including at least one of the information, identification information of terminals of components arranged on a printed circuit board, identification information of terminals to which the terminals are connected, and the Circuit diagram input means for inputting circuit diagram information including logic connection information including at least one of terminal signal information, the logic connection information included in the design specification information, and the circuit diagram information included in the circuit diagram information Information acquisition means for acquiring logical connection information, logical connection information included in the design specification information acquired by the information acquisition means, and logical connection information included in the circuit diagram information match And design verification means for verifying whether or not Luke, the included in the circuit diagram information on the circuit diagram information is a screen showing the logical connection information, the design verification means of the logical connection information shown in said screen It said logical connection information pre Symbol logical connection information could not validate the match, the logical connection information that could verify the match to generate a screen shows a different display mode than the failed verification of matching by Even so, it is characterized by comprising screen generating means for generating a screen shown in a different display mode under certain conditions .

FIG. 1 is a diagram illustrating a functional configuration of the verification apparatus according to the present embodiment. FIG. 2 is a flowchart from creation of a design specification to verification of a circuit diagram. FIG. 3 is a diagram for explaining symbols of parts used to create a design specification. FIG. 4 is a diagram for explaining connection symbols used for creating a design specification. FIG. 5 is a diagram illustrating an example of a design specification created by the symbol creation unit. FIG. 6 is a diagram illustrating an example of logical connection information. FIG. 7 is a flowchart showing processing for verifying the logical connection information included in the design specification. FIG. 8 is a flowchart showing processing for verifying logical connections included in the connector specification table and the functional block diagram. FIG. 9 is a diagram illustrating an example of the verification result of the design specification. FIG. 10 is a flowchart of a process for verifying the logical connection in the circuit diagram. FIG. 11 is a detailed flowchart of processing for verifying a logical connection in a circuit diagram. FIG. 12 is a flowchart of processing for reading a net list. FIG. 13 is a flowchart of processing for associating with an external interface signal. FIG. 14 is a diagram illustrating the types of errors output by the netlist verification. FIG. 15 is a diagram illustrating an example of a display form of the determination result in the circuit diagram generated by the screen generation unit. FIG. 16 is a diagram illustrating an example of a hardware configuration of the verification apparatus.

  Hereinafter, embodiments of a verification apparatus will be described in detail with reference to the accompanying drawings.

(Functional configuration of the verification apparatus of this embodiment)
FIG. 1 is a diagram illustrating a functional configuration of the verification apparatus according to the present embodiment. In the verification apparatus 1 in FIG. 1, the logical connection of the circuit diagram created based on the design specification of the printed circuit board is finally verified. However, at the stage of creating the design specification, the verification of the design specification is performed independently. It can be carried out. The design specification information included in the design specification includes, for example, information on components arranged on a printed circuit board, information on terminals included in the components, and information on logical connection between terminals. Design specification information refers to electronic information that can be processed by a computer among information included in a design specification. The design specifications include a functional block diagram having information on connections between terminals of components arranged on the printed circuit board, a connector specification table having information on connections to connectors serving as external interfaces of the printed circuit board, and the like.

  The circuit diagram is created by an operator using CAD or the like based on the design specification, and includes logical connection information between the terminals of the components. The logical connection information includes, for example, terminal identification information, terminal identification information as a connection destination of the terminal, and signal information. The signal information is information of a signal input to or output from the terminal, and includes, for example, signal identification information and information on the direction of the signal.

  The verification apparatus 1 includes, for example, a specification creation unit 100, a logical connection information acquisition unit 200, a design specification verification unit 300, a circuit diagram input unit 500, a design verification unit 600, a screen generation unit 700, and a manual verification unit 800. Have.

  In the specification creation unit 100, a design specification for the printed circuit board is created by the operator. The specification creation unit 100 includes a symbol creation unit 110 and a logical connection table input unit 130. The symbol creating unit 110 creates a design specification by selecting and arranging symbols such as parts on the screen for creating a design specification by an operator. In the design specification created by the symbol creation unit 110, the logical connection information between the terminals is associated with the symbol of the component including the terminal, the symbol representing the connection between the terminals, and the like.

  The symbol creation unit 110 includes a component selection unit 111, a connection selection unit 113, and an output unit 115. In the component selection unit 111, a symbol representing a component is selected by an operator on a screen on which a design specification is created. The symbol representing the component includes information on the terminals included in the component.

  In the connection selection unit 113, a symbol representing a connection between terminals is selected by an operator on a screen on which a design specification is created. The symbol representing the selected connection is associated with the symbol representing the terminal of the component, whereby the specification of the logical connection of the terminal is determined. The specification of the logical connection is, for example, information on a terminal connected to the terminal and information on a signal input to the terminal or output from the terminal.

  The output unit 115 outputs information on the specification of the logical connection determined by the symbol representing the connection between the terminals as the logical connection information. The output unit 115 also outputs a design specification expressed by symbols. The design specification output by the output unit 115 is, for example, a functional block diagram.

  The logical connection table input unit 130 receives an input of a logical connection table for the verification device 1. The logical connection table is a table including logical connection information, and has, for example, signal information for each terminal. The logical connection table input unit 130 may further receive a logical connection table including terminal identification information and terminal identification information as a connection destination of the terminal. The logical connection table input unit 130 may also receive a logical connection table including signal information. The signal information includes, for example, signal identification information, signal direction information, and the like. The connector specification table in which the terminal of the connector is associated with the information of the signal input to the terminal is an example of the logical connection table.

  The logical connection table input unit 130 outputs the input logical connection table. This logical connection table is one of the documents constituting the design specification, and is, for example, a connector specification table including specifications of the external interface of the printed circuit board.

  The parties review the design specifications expressed by the symbols output from the output unit 115 and the design specifications based on the logical connection table output from the logical connection table input unit 130. In addition, a circuit diagram is designed by CAD or the like based on the reviewed design specifications.

  The logical connection information acquisition unit 200 acquires logical connection information from the design specification created by the specification creation unit 100. The logical connection information acquisition unit 200 acquires logical connection information included in the design specification created by the symbol creation unit 110. The logical connection information acquisition unit 200 also acquires the logical connection information input by the logical connection table input unit 130.

  The design specification verification unit 300 verifies the logical connection included in the design specification based on the logical connection information acquired by the logical connection information acquisition unit 200. The design specification verification unit 300 is based on a record corresponding to each terminal in the logical connection information, and when the record includes information on the direction of the signal, the direction of the signal input or output for each record is the terminal Verify whether there is a conflict between the two. If there is a contradiction between terminals, it is determined that the specification of the logical connection of the terminal is incorrect.

  Based on the record corresponding to each terminal in the logical connection information, the design specification verification unit 300 verifies the presence / absence of the record of the terminal as the connection destination when the record includes the identification information of the terminal as the connection destination. If there is no record of the terminal to be connected, it is determined that the specification of the logical connection of the terminal is incorrect.

  Based on the record corresponding to each terminal in the logical connection information, the design specification verification unit 300 determines whether there is a record of another terminal including the same signal information when the record includes the signal information of the terminal. Validate. If there is no record of another terminal including the information of the same signal, it is determined that the specification of the logical connection of the terminal is incorrect.

  The verification result by the design specification verification unit 300 is output to a file, for example. The verification result includes the identification information of the terminal or signal in which the logical connection is incorrect in the design specification and the content of the error.

  From the circuit diagram input unit 500, circuit diagram information created by CAD or the like based on the design specifications is input. The circuit diagram information includes logical connection information for each terminal. The circuit diagram input unit 500 outputs circuit diagram information to the design verification unit 600. The circuit diagram input unit 500 may convert the circuit diagram information into a format corresponding to the design verification unit 600.

  The design verification unit 600 compares the logical connection information acquired by the logical connection information acquisition unit 200 with the logical connection information based on the circuit diagram information input from the circuit diagram input unit 500, thereby obtaining circuit diagram information. Verify the logical connection information contained in. In the present embodiment, the logical connection information acquisition unit 200 and the circuit diagram input unit 500 correspond to the information acquisition unit.

  The design verification unit 600 includes an expected value generation unit 610, a comparison unit 620, and a verification storage unit 630. The expected value generation unit 610 generates an expected value in the logical connection for each terminal based on the logical connection information acquired by the logical connection information acquisition unit 200. The expected value is, for example, the truth value of the signal at the connection source terminal obtained based on the connection destination terminal and signal information.

  The comparison unit 620 compares the logical connection information acquired by the logical connection information acquisition unit 200 with the logical connection information based on the circuit diagram information, and verifies the consistency for each terminal. The comparison unit 620 further verifies the logical connection information based on the circuit diagram information using the expected value generated by the expected value generation unit 610.

  The verification storage unit 630 stores the verification history by the comparison unit 620 for each logical connection information. At this time, the verification judgment classification in the verification history includes “match”, “non-match”, “verification impossible”, “warning”, and the like. “Match” is a determination result when the logical connection information matches. The mismatch is a determination result when the logical connection information does not match, the direction of the connector terminal is mismatched, or the terminal in the design specification is not in the circuit diagram information.

  “Unverifiable” is a determination result when there is no information in the specification or when there is information in the specification but cannot be verified. “Warning” is given in the case of an error of high importance among “mismatch”, and is a determination result when the NC terminal of the connector specification is connected on the circuit diagram, for example.

  The screen generation unit 700 generates a screen that displays the verification result of the logical connection information verified by the design verification unit 600. The image forming unit 700 also generates a screen for displaying the logical connection information verification result by the manual verification unit 800 described later. The display mode of these screens will be described later.

  The manual verification unit 800 accepts a manual review by the user for the logical connection information of the circuit information determined as “unverifiable” without being automatically verified by the design verification unit 600. The manual verification unit 800 includes an evaluation unit 810 and an evaluation storage unit 820. The evaluation unit 810 can select and give determination information of “error acceptable” or “mismatch” to the logical connection information in the circuit diagram. “Error tolerance” is a determination result given when it can be considered that there is no problem in design even if it is determined as “mismatch” or “warning”. In this case, the user actually makes a judgment by reviewing the design specification and the circuit diagram. The evaluation storage unit 820 stores the determination information given by the evaluation unit 810 for each logical connection information.

  In FIG. 1, the specification creation unit 100, the logical connection information acquisition unit 200, the design specification verification unit 300, the circuit diagram input unit 500, the design verification unit 600, the screen generation unit 700, and the manual verification unit 800 are verified. Although provided in the device 1, these units may be provided in different devices and connected via a network or the like.

(Flow from creation of design specifications to verification of circuit diagram)
FIG. 2 is a flowchart from creation of a design specification to verification of a circuit diagram in the present embodiment. As shown in FIG. 2, a design specification is created by the specification creation unit 100 (step S1). Progressing to step S2 following step S1, the logical connection information acquisition unit 200 acquires logical connection information from the design specification information included in the design specification created in step S1 (step S2). In step S3 following step S2, the design specification verification unit 300 verifies the logical connection between the terminals of the printed circuit board based on the design specification based on the logical connection information acquired in step S2 (step S3).

  By the processing from step S2 to step S3, the logical connection information in the design specification created in step S1 is verified. As a result of this verification, when an error such as contradiction is detected in the design specification information, the process returns to step S1 and the process is repeated.

  On the other hand, if no contradiction is detected in the verified design specification, the process proceeds to step S4. In step S4, a circuit design based on the design specification created in step S1 is performed by an operator operating CAD or the like, and a circuit diagram is created (step S4).

  After the processes in steps S3 and S4, the process proceeds to step S5, where the design verification unit 600 includes the logical connection information included in the design specification acquired in step S3, and the logical connection information based on the circuit diagram created in step S4. Are compared to verify the logical connection in the designed circuit diagram (step S5).

(Explanation of symbols used to create design specifications)
3 and 4 are diagrams for explaining symbols used for creating a design specification.

  FIG. 3 is a diagram for explaining symbols representing components and terminals included in the components. The symbol in FIG. 3A includes a component outline and a symbol representing a terminal included in the component. FIG. 3B is an example of information associated with a component symbol. In FIG. 3B, the identifier of information associated with the symbol of the part is described in the “column name” column. The “instance name” is component identification information, the “terminal name” is terminal identification information, and the “terminal attribute” is signal information corresponding to each terminal.

  FIG. 4 is a diagram illustrating symbols representing connections between terminals. “Signal line shape” in FIG. 4 is a symbol representing connection between terminals. By associating the end of the “signal line shape” with a symbol representing a terminal, a specification of a signal input to or output from the terminal is created.

(Example of design specifications created by the symbol creation department)
FIG. 5 is a diagram illustrating an example of a design specification created by the symbol creation unit 110. In FIG. 5A, the symbols of the terminals included in the component symbols are connected by a symbol representing connection. The symbol a1 in FIG. 5 includes a terminal “ADD [10:31]” of the component “LSI1”, a terminal “ADD [20: 0]” of the component “MEM1”, and a terminal “ADD [18: 0] of the component“ MEM2 ”. ] ”Is a symbol representing a bus connecting the 5 represents a bus that connects the terminal “DATA [0:15]” of the component “LSI1” and the terminal “D_Q [15: 0]” of the component “MEM1” using a bidirectional signal. Symbol.

  FIG. 5B is a diagram illustrating an example of logical connection information included in the design specification created by the symbol creation unit 110. In FIG. 5B, a set of identification information of a terminal serving as a signal transmission source and identification information of a terminal serving as a signal transmission destination is shown for each row in each logical connection in the CSV format. . The logical connection information b1 in FIG. 5B is information on the logical connection included in the bus represented by the symbol a1 in FIG. The logical connection information b1 is logical connection information when the terminal “ADD12” of the component “LSI1” and the terminal “ADD18” of the component “MEM2” are connected. In the logical connection information b1, “LSI1.ADD12” is identification information of the transmission source terminal, and “MEM2.ADD18” is identification information of the transmission destination terminal.

  The logical connection information b2 in FIG. 5B is information on the logical connection included in the bus represented by the symbol a2 in FIG. The logical connection information b2 is logical connection information when the terminal “D0” of the component “LSI1” and the terminal “DQ15” of the component “MEM1” are connected. In the logical connection information b2, “D0” is signal identification information, “MEM1.DQ15” is terminal identification information, and “GND” is signal information indicating pull-up or pull-down.

(Example of logical connection information)
FIG. 6 is an example of a design specification including logical connection information. In FIG. 6, “CN103” is component identification information. “Pin No.” is the terminal number of the connector, “logic signal name” is the identification information of the signal input to or output from the connector terminal, and “I / O” indicates the direction of the signal. Information. For example, in the logical connection information d, “A5” is terminal identification information, “SBU_CLK” is signal identification information, and “O” is signal direction information.

(Process to verify logical connection information included in design specifications)
FIG. 7 is a flowchart illustrating an example of processing for verifying logical connection information included in a design specification. In FIG. 7, the design specification verification unit 300 verifies the logical connection information included in the connector specification table and the functional block diagram.

  As shown in FIG. 7, logical connection information based on the connector specification table is input to the design specification verification unit 300 (step S101). The connector specification table has, for example, the configuration shown in FIG. Progressing to step S102 following step S101, the design specification verification unit 300 confirms whether or not there is duplication of terminal information and signal information in the connector specification table input in step S101 (step S102).

  Progressing to step S103 following step S102, the design specification verification unit 300 opens the functional block diagram file in the reading mode (step S103). The functional block diagram has, for example, the configuration shown in FIG.

  Following step S103, the process proceeds from step S104 to step S109. The processing from step S104 to step S109 is repeated until the verification of the logical connection information included in the file opened in the reading mode in step S103 is completed.

  In step S105 following step S104, logical connection information for one line in the file of the functional block diagram is read (step S105). The logical connection information for one row is logical connection information corresponding to one terminal.

  Proceeding to step S106 following step S105, if the identification information of the transmission source terminal and the identification information of the transmission destination terminal are acquired in the logical connection information acquired in step S105, the flow proceeds to step S108. When the signal identification information is acquired instead of either the transmission source terminal identification information or the transmission destination terminal identification information, the process proceeds to step S107 (step S106).

  In step S107 following step S106, the presence / absence of logical connection information having the same signal identification information as the acquired signal identification information is confirmed in the connector specification table and the functional block diagram (step S107). Thereby, it is possible to verify the coincidence of the directionality of signals between different logical connection information, or the duplication of signal identification information in the design specification. After the process of step S107, the process returns to step S104 and is repeated.

  On the other hand, in step S108 following step S106, the logical connection in the design specification is verified based on the acquired identification information of the terminal of the transmission destination (step S108). Progressing to step S109 following step S108, the logical connection in the design specification is verified based on the acquired terminal identification information (step S109). By the processing in step S108 and step S109, duplication of signal identification information in the design specification and confirmation of signal directionality can be performed. After step S109, the process returns to step S104 and the process is repeated.

  In step S110 following step S104 to step S109, the file opened in the reading mode in step S103 is closed (step S110).

  Proceeding to step S111 following step S110, in step S107, it is determined that the logical connections connected to the connector terminals are not duplicated among the logical connections determined to have duplicate signal identification information. (Step S111).

  Progressing to step S112 following step S111, the process of step S113 is repeated for each logical connection information corresponding to one terminal in the connector specification table read in step S101 (step S112). In step S113, based on the verification from step S107 to step S109, the identification information of the terminal in which the error is detected is output for each identification information of the signal (step S113).

  Progressing to step S114 following step S112 and step S113, it is determined whether there is a terminal in which an error is detected (step S114). If there is no terminal in which an error has been detected (step S114: No), the process ends. On the other hand, if there is a terminal in which an error is detected (step S114: Yes), the terminal identification information output in step S113 is output to a file (step S115), and the design specification verification is completed.

(Verification of logical connections included in the connector specification table and functional block diagram)
FIG. 8 is a flowchart showing the process of verifying the logical connection in the design specification performed in step S108 and step S109 in FIG. In FIG. 8, the design specification verification unit 300 verifies the logical connection information included in the connector specification table and the functional block diagram. The process of FIG. 8 is executed for each piece of logical connection information.

  In step S201 of FIG. 8, it is determined whether or not the signal included in the logical connection information acquired from the functional block diagram is a logical signal (step S201). If it is a logic signal, the process proceeds to step S202. If it is not a logic signal, the process ends.

  In step S202 following step S201, it is determined whether or not logical connector information including the same signal as the signal included in the logical connection information to be verified is included in the connector specification table (step S202). If it is included in the connector specification table, the process proceeds to step S203. If it is not included in the connector specification table, the process ends.

  In step S203 following step S202, it is determined whether the attribute of the signal included in the logical connection information to be verified is a power source, a ground, or not connected (step S203). If it is either, the process is terminated. In step S204 following step S203, it is determined whether or not the logical connection information to be verified is information on connection to the connector terminal (step S204). If it is information on connection to a connector terminal, the process proceeds to step S205. If it is not information about connection to a connector terminal, the process proceeds to step S213.

  In step S205 following step S204, it is determined whether the signal in the logical connection information to be verified is a one-way signal or a bidirectional signal (step S205). If it is a unidirectional signal, the process proceeds to step S206. If it is a bidirectional signal, the process proceeds to step S210.

  In step S206 following step S205, if the signal in the logical connection information to be verified is an output signal and the signal of the same identification information in the connector specification table is not an input signal, it is determined that there is an error in the design specification. (Step S206). If there is an error, the process proceeds to step S207, and if there is no error, the process proceeds to step S208. In step S207 following step S206, information indicating an error in the signal direction is associated with the logical connection information to be verified (step S207).

  In step S208 following step S206, if the signal in the logical connection information to be verified is an input signal and the signal of the same identification information in the connector specification table is not an output signal, it is determined that there is an error in the design specification. (Step S208). If there is an error, the process proceeds to step S209. If there is no error, the process ends. In step S209 following step S208, information indicating an error in the signal direction is associated with the logical connection information to be verified (step S209). After step S209, the process ends.

  On the other hand, in step S210 following step S205, it is set not to determine an error with respect to duplication of signal identification information in the logical connection information to be verified (step S210). Following step S210, the process proceeds to step S211, and if the signal in the connector specification table having the same identification information as the signal included in the logical connection information to be verified is not a bidirectional signal, the process proceeds to step S212. The process ends (step S211). In step S212 following step S211, information indicating an error in the signal direction is associated with the logical connection information to be verified (step S212).

  In step S213 following step S204, information indicating that the signal identification information is duplicated is associated with the logical connection information to be verified (step S213).

  In step S214 following step S202, when the logical connection information to be verified includes information indicating that the terminal is connected to the terminal of the connector, the process proceeds to step S215. Is finished (step S214). In step S215 following step S214, information indicating that there is no connection destination terminal is associated with the logical connection information to be verified (step S215).

(Example of design specification verification results)
FIG. 9 is a diagram illustrating an example of the verification result of the design specification output from the design specification verification unit 300. FIG. 9A is a summary of verification results in the design specifications. In FIG. 9A, the number of errors detected by verification is shown for each type of error. In FIG. 9A, logical connection information coverage information e represents the proportion of terminals for which logical connections have been established in the verification of the design specification.

  FIG. 9B is a diagram showing details of errors detected by the verification. In FIG. 9B, the presence / absence of an error is associated with each terminal by “determination”, and the content of the error is associated with a terminal having an error by “message” and “pattern when mismatching”. ing. The “mismatch pattern” includes information on a design specification and a circuit diagram in which an error is detected.

(Verification of logical connection in circuit diagram)
FIG. 10 is a flowchart showing an example of processing for verifying logical connection information in a circuit diagram created based on a design specification by comparing it with logical connection information included in the design specification. The process of FIG. 10 is performed by the design verification unit 600. In FIG. 10, library information is read (step S21). The library information includes, for example, truth value information that is an expected value corresponding to each logical connection. Progressing to step S22 following step S21, logical connection information included in the functional block diagram of the design specification is read (step S22). Progressing to step S23 following step S22, the logical connection information included in the connector specification table of the design specification is read (step S23).

  Progressing to step S24 following step S23, the logical connection information included in the circuit diagram created based on the design specification is read (step S24). The circuit diagram is read as a net list, for example. Progressing to step S25 following step S24, the verification conditions are set. The ini file is read (step S25).

  In step S26 following step S25, the logical connection information in the circuit diagram is compared by comparing the logical connection information in the circuit diagram read in step S24 with the logical connection information in the design specifications read in steps S22 and S23. Information is verified (step S26).

(Netlist verification based on logical connection information in design specifications)
FIG. 11 is a flowchart showing a netlist verification process based on the logical connection information of the design specification. In step S301 in FIG. 11, whether there is a contradiction in logical connection information between the functional block diagram of the design specification and the connector specification is verified. This process is the same as the process of FIG. Proceeding to step S302 following step S301, the process ends if the logical connection information of the design specification contains a contradiction in the process of step S301.

  In step S303 following step S302, the library file is read. Progressing to step S304 following step S303, processing for connecting an external interface signal to a terminal is performed based on the connector specification table. Progressing to step S305 following step S304, the net list is read. Progressing to step S306 following step S305,. The ini file is read.

  Note that in steps S303 to S306, for each read file, the presence or absence of contradiction is verified for information such as the correspondence with the connection destination and the signal direction, and a terminal for verifying the logical connection information is set. The Thereby, a list of terminals for verifying the logical connection information is generated.

  Proceeding to step S307 following step S306, if there is any contradiction in information such as correspondence with the connection destination or signal direction in the processing from step S303 to step S306, the processing is terminated. In step S308 subsequent to step S307, whether there is any contradiction is verified between the netlist and the design specification regarding information such as correspondence with the connection destination and signal direction.

  Progressing to step S309 following step S308, the value of the signal to be connected is initialized for the terminal for verifying the logical connection information. Here, the value “x” is input to the target terminal.

  Following step S309, the process proceeds from step S310 to step S314. Here, the process is repeated for each terminal for which the logical connection information is verified based on the list of terminals created in steps S303 to S306. In step S310, information on one terminal among the information on the terminals included in the list is acquired.

  In step S311 following step S310, it is determined whether or not the terminal information acquired from the list in step S310 is already verified terminal information. If the information is already verified terminal information, the process returns to step S310 to repeat the process.

  In step S312 following step S311, based on the terminal information acquired in step S310, it is determined whether the information is bidirectional connection information including a logic circuit. In the case of bidirectional connection information including a logic circuit, the process proceeds to step S313. Otherwise, the process proceeds to step S314.

  In step S313, based on the terminal information acquired in step S310, the logical connection information of the terminal is verified by using the expected value. Here, the bidirectional connection including the logic circuit is verified. In step S314, based on the terminal information acquired in step S310, the logical connection information of the terminal is verified by using the expected value. Here, verification of the logical connection is performed when the bidirectional connection including the logic circuit is not performed. Finally, in step S315, the screen generation unit 700 creates a summary file of logical connection verification results and displays it on the screen.

(Process to read circuit diagram)
FIG. 12 is a flowchart showing details of the process of reading the net list in step S305 of FIG.

  In step S401 to step S408 in FIG. 12, signal information corresponding to each terminal is associated with all input terminals and output terminals included in the read netlist. In step S401, information corresponding to one terminal included in the netlist is acquired. If the information is acquired, the process proceeds to step S402. If the process has been completed for all terminals, the process proceeds to step S409.

  In step S402 following step S401, a counter that counts the number of terminals to be verified is counted up. This counter is initialized prior to processing of all terminals. Progressing to step S403 following step S402, based on the terminal information acquired in step S401, it is determined whether the terminal is a terminal included in the connector. If the terminal is included in the connector, the process proceeds to step S404. If the terminal is not included in the connector, the process proceeds to step S405.

  In step S404 following step S403, processing for associating with an external interface signal is performed. On the other hand, in step S405 following step S403, whether the terminal identification information included in the terminal information acquired in step S401 and the logical connection information of the terminal having the same identification information are included in the functional block diagram. Confirmation is made.

  Following step S405, the process proceeds to step S406, and based on the result confirmed in step S405, if the logical connection information of the terminal having the same identification information is included in the functional block diagram, the process proceeds to step S407. If it is not included in the block diagram, the process proceeds to step S408.

  In step S407 following step S406, the terminal information included in the net list acquired in step S401 is associated with the logical connection information of the terminals having the same identification information included in the functional block diagram.

  On the other hand, in step S408 following step S406, error information indicating that the logical connection information corresponding to the terminal information included in the netlist acquired in step S401 is not included in the functional block diagram is output. Is done.

  Subsequent to the processing from step S401 to step S408, the processing from step S409 to step S411 is performed for all the input terminals included in the netlist. In step S409, information on one input terminal included in the netlist is acquired.

  Progressing to step S410 following step S409, it is determined whether or not the terminal information acquired in step S409 is information on a terminal included in the connector. In the case of terminal information included in the connector, the process proceeds to step S411. In step S411, the terminal information acquired in step S409 is associated with an external interface signal.

(Process of association with external interface signals)
FIG. 13 is a flowchart illustrating an example of processing for associating terminal information included in a read netlist with information of an external interface signal. The process of FIG. 13 is the detail of the process performed by step S404 and step S411 of FIG.

  In step S501 of FIG. 13, information on terminals having the same identification information is retrieved from the connector specification table based on information on terminals of the net list to be connected (hereinafter referred to as “connection terminals”). Following step S501, the process proceeds to step S502. If there is no terminal information having the same identification information in the connector specification table in step S501, the process proceeds to step S503, where the terminal information having the same identification information is If it is in the specification table, the process proceeds to step S504.

  In step S503 following step S502, error information indicating that the logical connection information corresponding to the connection terminal information is not included in the connector specification table is output.

  In step S504 following step S502, if the terminal is an input terminal and is a power supply or ground based on the information of the connection terminal, the process proceeds to step S505. Otherwise, the process proceeds to step S506. move on. In step S505 following step S504, a counter that counts the number of connection terminals is counted up.

  Proceeding to step S506 following step S504 and step S505, the signal direction information in the connection terminal information and the signal direction information in the logical connection information of the terminals having the same identification information included in the connector specification table Are compared. If the signal directions do not match, an error (mismatch) is determined.

  Following step S507, the process proceeds to step S508. If an error is determined in step S507, the process proceeds to step S509. In step S509, error (mismatch) information indicating that the signal directions do not match is output.

  Proceeding to step S510 following step S508 and step S509, the connection terminal identification information and the logical connection information of the terminal having the same identification information are searched in the functional block diagram. If the logical connection information of the terminals having the same identification information is not included in the logical connection information of the functional block diagram, the process proceeds to step S511. In step S511, connection terminal identification information is added to the information in the functional block diagram.

  The processing from step S512 to step S516 following step S510 is performed on the logical connection information of the terminal having the same identification information as the connection terminal in the functional block diagram. In the functional block diagram, when there are a plurality of logical connection information of terminals having the same identification information as the connection terminals, the processing from step S512 to step S516 is repeated for each logical connection information.

  Progressing to step S513 following step S512, the information on the direction of the signal corresponding to the connection terminal is compared with the information on the direction of the signal in the logical connection information of the functional block diagram. If the signal directions match, the process proceeds to step S514. If the signal directions do not match, the process ends. In step S514 following step S513, a record for registering logical connection information for connecting the connection terminal to the terminal in the functional block diagram is created.

  Progressing to step S515 following step S514, the handler for the connection terminal is added to the record created in step S514 and registered. Following step S515, the process proceeds to step S516, and is associated with information indicating whether or not the logical connection information for the connection terminal registered in step S515 is to be verified.

  On the other hand, if a logic signal matching the method is not detected in step S517, the process proceeds to step S518 and an error is output.

(Error output due to netlist verification)
FIG. 14 is a diagram for explaining the types of errors detected when the netlist is verified by the processing of FIGS. 11 to 13. FIG. 14A is a diagram for explaining the types of netlist errors based on the connector specification table. The “error number” in FIG. 14A is identification information representing an error that is output when the signal direction in the connector specification table differs from the signal direction in the netlist. The “error number” in FIG. 14B is identification information that represents an error that is output when the design specification and the netlist have different terminal identification information or signal information.

  FIG. 15 shows an example of a screen after the examination generated by the screen generation unit 700. The screen generation unit 700 generates a verification result display screen after verification by the design verification unit 600 or after verification by the manual verification unit 800. As illustrated in FIG. 15, the screen generation unit 700 displays determination information, which is a result of verification by the design verification unit 600, for each logical connection information in the circuit diagram information. At this time, the display mode varies depending on the determination result, and is easy for the user to visually recognize. For example, the logical connection information determined as “match” by the design verification unit 600 is displayed by the letters “black”. In addition, the logical connection information determined as “unverifiable” by the design verification unit 600 is displayed with the characters “pink”. In addition, the logical connection information that has been “not verified” is displayed in the letters “green” after being checked by the manual verification unit 800. In addition, logical connection information determined as “mismatch” or “warning” by the design verification unit 600 or the manual verification unit 800 is displayed in “red” characters. The logical connection information that the user has determined to be “error acceptable” through the manual verification unit 800 with respect to the logical connection information that has been determined to be “mismatch” by the design verification unit 600 or the manual verification unit 800 is “blue”. Displayed in characters. Therefore, in this embodiment, the determination results for the logical connection information are displayed in different display modes so that they can be easily distinguished from other determination results. In the present embodiment, the display mode is changed by changing the color. However, the display mode may be changed by another method as appropriate, for example, the thickness and size of characters, the difference in fonts, and the like. .

  Next, the hardware configuration of the verification apparatus according to the present embodiment will be described with reference to FIG. FIG. 16 is an explanatory diagram illustrating a hardware configuration of the verification apparatus 1.

  The verification apparatus 1 according to the present embodiment communicates with a control device such as a CPU (Central Processing Unit) 51 and a storage device such as a ROM (Read Only Memory) 52 and a RAM (Random Access Memory) 53 connected to a network. The communication I / F 54, an external storage device such as an HDD (Hard Disk Drive) and a CD (Compact Disc) drive device, a display device such as a display device, and an input device such as a keyboard and a mouse. A bus 61 is provided and has a hardware configuration using a normal computer.

  The verification program executed by the verification apparatus 1 according to the present embodiment is a file in an installable format or an executable format, and is a CD-ROM (Compact Disk Read Only Memory), a flexible disk (FD), a CD-R. (Compact Disk Recordable), recorded on a computer-readable recording medium such as a DVD (Digital Versatile Disk), etc., and provided as a computer program product.

  Further, the verification program executed by the verification apparatus 1 according to the present embodiment may be provided by being stored on a computer connected to a network such as the Internet and downloaded via the network. . The verification program executed by the verification apparatus 1 according to the present embodiment may be provided or distributed via a network such as the Internet.

  Further, the verification program executed in the verification device 1 according to the present embodiment may be configured to be provided by being incorporated in advance in a ROM or the like.

  The verification program executed by the verification apparatus 1 according to the present embodiment has a module configuration including the above-described units. As actual hardware, the CPU 51 (processor) reads the verification program from the storage medium. When executed, the above-described units are loaded onto the main storage device, and the above-described units are generated on the main storage device.

DESCRIPTION OF SYMBOLS 1 Verification apparatus 100 Specification preparation part 110 Symbol preparation part 111 Component selection part 113 Connection selection part 115 Output part 130 Logical connection table input part 200 Logical connection information acquisition part 300 Design specification verification part 500 Circuit diagram input part 600 Design verification part 610 Expected value generation unit 620 Comparison unit 630 Verification storage unit 700 Screen generation unit 800 Manual verification unit

JP 2007-148664 A

Claims (7)

Based on design specification information having logical connection information including at least one of terminal identification information of a component arranged on a printed circuit board, terminal identification information of a connection destination of the terminal, and signal information of the terminal The circuit diagram including the logical connection information including at least one of the terminal identification information of the component created and arranged on the printed circuit board, the terminal identification information of the connection destination of the terminal, and the signal information of the terminal Circuit diagram input means for inputting information;
Information acquisition means for acquiring the logical connection information included in the design specification information and the logical connection information included in the circuit diagram information;
Design verification means for verifying whether or not the logical connection information included in the design specification information acquired by the information acquisition means matches the logical connection information included in the circuit diagram information;
Wherein a screen showing the logical connection information contained on the circuit diagram information to the circuit diagram information, the design verification means according to prior Symbol logical connections could not verify the coincidence of the logical connection information shown in said screen information, and generates the screen shows a different display mode and could verify the match the logical connection information, yet different display at said certain conditions even logical connection information could not validate the match Screen generating means for generating the screen shown in the aspect ;
A verification apparatus comprising: Manual verification means for accepting verification by a user for the logical connection information in the circuit diagram information that could not be verified whether or not they match;
Verification storage means for storing a verification result by the manual verification means in association with the logical connection information in the circuit diagram information;
Further comprising
The screen generation unit displays the verified logical connection information on the circuit diagram information in a display mode different from the unverified logical connection information based on the verification result stored in the verification storage unit. The verification apparatus according to claim 1, wherein a screen is generated. An evaluation unit that gives determination information of error tolerance and mismatch to the verification result by the manual verification unit;
Evaluation storage means for storing the determination information by the evaluation means in association with the logical connection information in the circuit diagram information;
Further comprising
The screen generation means, based on the determination information stored in the verification storage means, the logical connection information in which the error tolerance determination information is stored, and the logical connection information in which the mismatch determination information is stored. The verification apparatus according to claim 2, wherein the screen shown on the circuit diagram information is generated in a different display mode. A specification creating means for creating design specification information having logical connection information between terminals of components arranged on the printed circuit board;
The specification creation means
Component selection means for selecting a symbol of the component;
Connection selection means for selecting a symbol representing a connection between terminals in a symbol of a plurality of parts selected by the part selection means;
The verification apparatus according to claim 1, further comprising: an output unit that outputs a connection relationship between a terminal at a start point and a terminal at an end point of a symbol representing connection between the terminals as logical connection information. The specification creating means includes connection information input means for receiving input of logical connection information associated with a signal input to the terminal or information of a signal output from the terminal for each terminal. The verification device according to claim 1. A logical connection in which the circuit diagram input means of the verification device includes at least one of identification information of terminals of components arranged on the printed circuit board, identification information of terminals to which the terminals are connected, and signal information of the terminals At least one of identification information of terminals of components created on the basis of design specification information having information and arranged on a printed circuit board, identification information of terminals to which the terminals are connected, and signal information of the terminals A circuit diagram input step for inputting circuit diagram information including logical connection information including:
An information acquisition step in which the information acquisition means of the verification device acquires the logical connection information included in the design specification information and the logical connection information included in the circuit diagram information;
The design verification means of the verification device verifies whether the logical connection information included in the design specification information acquired by the information acquisition step matches the logical connection information included in the circuit diagram information. The design verification process;
The screen generation means of the verification device is a screen indicating the logical connection information included in the circuit diagram information on the circuit diagram information, and the matching by the design verification step is included in the logical connection information displayed on the screen the pre-Symbol logical connection information could not be verified, it generates the screen shows a different display mode and could verify the match the logical connection information, a said logical connection information could not validate the match A screen generation step for generating a screen shown in a different display mode under certain conditions ;
A verification method characterized by comprising: On the computer,
Based on design specification information having logical connection information including at least one of terminal identification information of a component arranged on a printed circuit board, terminal identification information of a connection destination of the terminal, and signal information of the terminal The circuit diagram including the logical connection information including at least one of the terminal identification information of the component created and arranged on the printed circuit board, the terminal identification information of the connection destination of the terminal, and the signal information of the terminal A circuit diagram input process for inputting information;
An information acquisition step of acquiring the logical connection information included in the design specification information and the logical connection information included in the circuit diagram information;
A design verification step for verifying whether the logical connection information included in the design specification information acquired by the information acquisition step matches the logical connection information included in the circuit diagram information;
Wherein a screen showing the logical connection information contained on the circuit diagram information to the circuit diagram information, the design verification process by pre-Symbol logical connections could not verify the coincidence of the logical connection information shown in said screen information, and generates the screen shows a different display mode and could verify the match the logical connection information, yet different display at said certain conditions even logical connection information could not validate the match A screen generation step for generating the screen shown in the aspect ;
Verification program to execute.

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