JP6036457B2 - 演算処理装置、情報処理装置及び情報処理装置の制御方法 - Google Patents

演算処理装置、情報処理装置及び情報処理装置の制御方法 Download PDF

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JP6036457B2
JP6036457B2 JP2013062811A JP2013062811A JP6036457B2 JP 6036457 B2 JP6036457 B2 JP 6036457B2 JP 2013062811 A JP2013062811 A JP 2013062811A JP 2013062811 A JP2013062811 A JP 2013062811A JP 6036457 B2 JP6036457 B2 JP 6036457B2
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data
arithmetic processing
cluster
cache
memory
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Japanese (ja)
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JP2014186675A5 (enExample
JP2014186675A (ja
Inventor
隆宏 青柳
隆宏 青柳
吉朗 池田
吉朗 池田
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Fujitsu Ltd
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Fujitsu Ltd
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Priority to JP2013062811A priority Critical patent/JP6036457B2/ja
Priority to US14/195,245 priority patent/US20140289481A1/en
Priority to CN201410086349.1A priority patent/CN104077249A/zh
Publication of JP2014186675A publication Critical patent/JP2014186675A/ja
Publication of JP2014186675A5 publication Critical patent/JP2014186675A5/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0826—Limited pointers directories; State-only directories without pointers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1048—Scalability
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2013062811A 2013-03-25 2013-03-25 演算処理装置、情報処理装置及び情報処理装置の制御方法 Expired - Fee Related JP6036457B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2013062811A JP6036457B2 (ja) 2013-03-25 2013-03-25 演算処理装置、情報処理装置及び情報処理装置の制御方法
US14/195,245 US20140289481A1 (en) 2013-03-25 2014-03-03 Operation processing apparatus, information processing apparatus and method of controlling information processing apparatus
CN201410086349.1A CN104077249A (zh) 2013-03-25 2014-03-10 运算处理设备、信息处理设备及控制信息处理设备的方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013062811A JP6036457B2 (ja) 2013-03-25 2013-03-25 演算処理装置、情報処理装置及び情報処理装置の制御方法

Publications (3)

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JP2014186675A JP2014186675A (ja) 2014-10-02
JP2014186675A5 JP2014186675A5 (enExample) 2016-04-28
JP6036457B2 true JP6036457B2 (ja) 2016-11-30

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JP2013062811A Expired - Fee Related JP6036457B2 (ja) 2013-03-25 2013-03-25 演算処理装置、情報処理装置及び情報処理装置の制御方法

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US (1) US20140289481A1 (enExample)
JP (1) JP6036457B2 (enExample)
CN (1) CN104077249A (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6515779B2 (ja) * 2015-10-19 2019-05-22 富士通株式会社 キャッシュ方法、キャッシュプログラム及び情報処理装置
CN106603674A (zh) * 2016-12-19 2017-04-26 广东欧珀移动通信有限公司 无线播放设备的通信方法、系统及移动终端
US11836523B2 (en) * 2020-10-28 2023-12-05 Red Hat, Inc. Introspection of a containerized application in a runtime environment
CN112732591B (zh) * 2021-01-15 2023-04-07 杭州中科先进技术研究院有限公司 一种缓存深度学习的边缘计算架构

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6996679B2 (en) * 2003-04-28 2006-02-07 International Business Machines Corporation Cache allocation mechanism for saving multiple elected unworthy members via substitute victimization and imputed worthiness of multiple substitute victim members
US7376799B2 (en) * 2005-07-21 2008-05-20 Hewlett-Packard Development Company, L.P. System for reducing the latency of exclusive read requests in a symmetric multi-processing system
US20080133844A1 (en) * 2006-12-01 2008-06-05 Srinivasan Ramani Method and apparatus for extending local caches in a multiprocessor system
JP2009223759A (ja) * 2008-03-18 2009-10-01 Fujitsu Ltd 情報処理装置，メモリ制御方法およびメモリ制御装置
JP5338375B2 (ja) * 2009-02-26 2013-11-13 富士通株式会社 演算処理装置、情報処理装置および演算処理装置の制御方法
US8996812B2 (en) * 2009-06-19 2015-03-31 International Business Machines Corporation Write-back coherency data cache for resolving read/write conflicts
JP2011150653A (ja) * 2010-01-25 2011-08-04 Renesas Electronics Corp マルチプロセッサシステム

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CN104077249A (zh) 2014-10-01
US20140289481A1 (en) 2014-09-25
JP2014186675A (ja) 2014-10-02

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