JP6024449B2 - Ferroelectric memory manufacturing method and ferroelectric memory - Google Patents

Description

  The present invention relates to a method for manufacturing a ferroelectric memory and a ferroelectric memory.

  Flash memories and ferroelectric memories (FeRAM: Ferroelectric Random Access Memory) are known as nonvolatile memories that do not lose data even when the power is turned off. Ferroelectric memories have the advantages of lower power consumption and higher speed operation than flash memories.

  A ferroelectric capacitor used in a ferroelectric memory has a structure in which a ferroelectric film is sandwiched between a lower electrode and an upper electrode. The ferroelectric film is formed of a ferroelectric material having ferroelectric properties (polarization properties) such as PZT (lead zirconate titanate).

  In a ferroelectric memory, a predetermined voltage is applied between an upper electrode and a lower electrode to generate polarization in the ferroelectric film. Even if the application of voltage is stopped in this state, polarization (residual polarization) corresponding to the applied voltage remains in the ferroelectric film.

  The ferroelectric film has two stable polarization states corresponding to the applied voltage. Data is recorded in the ferroelectric memory by making one polarization state correspond to “0” and making the other polarization state correspond to “1”.

JP 2008-294345 A JP 2011-77226 A

  An object of the present invention is to provide a ferroelectric memory having a small leakage current between electrodes of a ferroelectric capacitor and a method for manufacturing the same.

According to one aspect of the disclosed technology, a step of forming a first conductor film above a semiconductor substrate, a step of forming a ferroelectric film on the first conductor film, and the ferroelectric Forming a metal atom supply film made of ruthenium (Ru) or an alloy or compound containing ruthenium on the body film, and performing a heat treatment to form the first conductor film and the strong film from the metal atom supply film. And a step of diffusing ruthenium in the interface with the dielectric film to form a metal dispersion layer in which the ruthenium is dispersed in the interface between the first conductor film and the ferroelectric film. A method for manufacturing a ferroelectric memory is provided.

According to another aspect of the disclosed technology, a semiconductor substrate, a lower electrode formed above the semiconductor substrate, a ferroelectric material is formed on the lower electrode, and ruthenium is formed at an interface with the lower electrode. A capacitor insulating film having a metal dispersion layer in which is dispersed, and an upper electrode formed on the capacitor insulating film, and ruthenium (Ru) or ruthenium is included on the capacitor insulating film side of the upper electrode. There is provided a ferroelectric memory characterized in that a metal atom supply film made of an alloy or a compound is provided.

  According to the method for manufacturing a ferroelectric memory according to the above aspect, a ferroelectric memory having a small leakage current between the electrodes of the ferroelectric capacitor can be obtained.

FIG. 1 is a cross-sectional view (part 1) illustrating the method for manufacturing a ferroelectric memory according to the embodiment. FIG. 2 is a sectional view (No. 2) showing the method for manufacturing the ferroelectric memory according to the embodiment. FIG. 3 is a sectional view (No. 3) showing the method for manufacturing the ferroelectric memory according to the embodiment. FIG. 4 is a sectional view (No. 4) showing the method for manufacturing the ferroelectric memory according to the embodiment. FIG. 5 is a diagram showing the result of examining the distribution state of ruthenium in the depth direction of the capacitive insulating film by SIMS analysis. FIG. 6 is a SIMS profile of strontium. FIG. 7 is a diagram showing the results of examining the relationship between the thickness of the metal atom supply film and the leakage current between the upper electrode and the lower electrode.

  In the ferroelectric memory, data is held by the residual polarization of the ferroelectric film as described above. However, if the leakage current between the upper electrode and the lower electrode is large, the remanent polarization gradually decreases and data is lost.

  In the following embodiments, a method for manufacturing a ferroelectric memory with a small leakage current between electrodes will be described.

(Embodiment)
1 to 4 are sectional views showing a method of manufacturing a ferroelectric memory according to the embodiment in order of steps. Normally, an n-type transistor and a p-type transistor constituting a drive circuit (such as a write circuit and a read circuit) are formed on a semiconductor substrate at the same time as a memory cell, but these are not shown here.

  First, steps required until a structure shown in FIG.

As shown in FIG. 1A, an element isolation layer 11 is formed in a predetermined region of the semiconductor substrate 10. Specifically, a trench is formed in a predetermined region of the semiconductor substrate 10 by photolithography, and an insulating material such as SiO ₂ is embedded in the trench to form the element isolation layer 11. In the present embodiment, a silicon substrate is used as the semiconductor substrate 10.

  Such a method of forming the element isolation layer 11 by the trench embedded with an insulator is called an STI (Shallow Trench Isolation) method. Instead of the element isolation layer 11 by the STI method, the element isolation layer 11 may be formed by a known LOCOS (Local Oxidation of Silicon) method.

  Next, a p-type impurity such as boron (B) is introduced into the n-type transistor formation region of the semiconductor substrate 10 (the memory cell region and the n-type transistor formation region of the driving circuit: the same applies hereinafter) to form the p well 12. To do. Further, an n-type impurity such as phosphorus (P) is introduced into a p-type transistor formation region of the semiconductor substrate 10 (p-type transistor formation region of the drive circuit: the same applies hereinafter) to form an n-well (not shown). .

  Next, the surfaces of the p well 12 and the n well (not shown) are thermally oxidized to form the gate insulating film 13. Thereafter, a polysilicon film is formed on the entire upper surface of the semiconductor substrate 10 by a CVD (Chemical Vapor Deposition) method, and this polysilicon film is patterned by a photolithography method to form the gate electrode 14.

  As shown in FIG. 1A, it is preferable to form a metal silicide (silicide) layer such as cobalt silicide or titanium silicide on the gate electrode 14 as the contact layer 15. Hereinafter, the gate electrode 14 and the contact layer 15 are collectively referred to simply as the gate electrode 14.

  As shown in FIG. 1A, in the memory cell region, two gate electrodes 14 are arranged on one p-well 12 in parallel to each other.

  Next, using the gate electrode 14 as a mask, an n-type impurity such as phosphorus (P) is ion-implanted into the p-well 12 in the n-type transistor formation region to form a low concentration n-type impurity region 16. Similarly, using the gate electrode 14 as a mask, a p-type impurity such as boron (B) is ion-implanted into an n-well (not shown) of the p-type transistor formation region to form a low-concentration p-type impurity region (not shown). ).

Next, sidewalls 17 are formed on both sides of the gate electrode 14. The sidewall 17 is formed by forming an insulating film made of SiO ₂ or SiN on the entire upper surface of the semiconductor substrate 10 by, for example, CVD, and then etching back the insulating film to leave only on both sides of the gate electrode 14. Is done.

  Thereafter, n-type impurities are ion-implanted into the p-well 12 in the n-type transistor formation region using the gate electrode 14 and the sidewall 17 as a mask to form a high concentration n-type impurity region 18. Similarly, a p-type impurity is ion-implanted into an n-well (not shown) using the gate electrode and sidewall of the p-type transistor formation region as a mask to form a high concentration p-type impurity region (not shown).

  In this manner, a transistor having a source / drain with a DDD (Double Doped Drain) structure is formed in each transistor formation region.

Next, as shown in FIG. 1B, for example, a SiON film having a thickness of 200 nm is formed as a cover insulating film 19 on the entire upper surface of the semiconductor substrate 10 by the CVD method. For example, a SiO ₂ film having a thickness of 300 nm is formed as one interlayer insulating film 20. Thereafter, the surface of the first interlayer insulating film 20 is polished and planarized by a CMP (Chemical Mechanical Polishing) method.

Next, as shown in FIG. 1C, an adhesion layer 21 is formed on the entire upper surface of the semiconductor substrate 10 by sputtering. In this embodiment, a film made of alumina (Al ₂ O ₃ ) is formed to a thickness of about 20 nm to form the adhesion layer 21. The adhesion layer 21 has a function of improving adhesion between the first interlayer insulating film 20 and a first conductor film 22 described later, and hydrogen and moisture contained in the first interlayer insulating film 20 are upward. And the function of preventing diffusion. Note that the adhesion layer 21 may be formed of a material other than alumina.

  Next, the first conductor film 22 is formed on the adhesion layer 21. In the present embodiment, platinum (Pt) is deposited to a thickness of about 150 nm on the adhesion layer 21 by sputtering to form the first conductor film 22.

  Next, a ferroelectric film 23 is formed on the first conductor film 22. In the present embodiment, PZT added with calcium (Ca), strontium (Sr), and lanthanum (La) is deposited on the first conductive film 22 by sputtering to a thickness of about 90 nm, and the ferroelectric film is formed. The body membrane 23 is used.

  The ferroelectric film 23 formed by sputtering is amorphous and has poor ferroelectric properties. Therefore, annealing is performed in an oxygen atmosphere, and the ferroelectric film 23 is crystallized.

  In addition to the sputtering method, the ferroelectric film 23 may be formed by MO (Metal Organic) CVD method, sol-gel method, or the like. Further, the ferroelectric film 23 may be formed of another ferroelectric material.

  Next, an amorphous strontium ruthenate (hereinafter referred to as “SRO”) is formed to a thickness of 1 nm to 3 nm on the ferroelectric film 23 by, for example, DC sputtering, and the metal atom supply film 24 is formed. Form. Further, iridium oxide (IrOx) is formed to a thickness of 200 nm to 300 nm on the metal atom supply film 24 by sputtering to form the second conductor film 25.

  In this embodiment, the metal atom supply film 24 is formed of SRO. However, the metal atom supply film 24 may be formed of ruthenium (Ru) or an alloy or compound containing ruthenium.

  Thereafter, annealing is performed at a processing temperature of 700 ° C. to 750 ° C. in an oxygen atmosphere, and a part of the SRO of the metal atom supply film 24 is crystallized.

  At this time, a part of ruthenium in the metal atom supply film 24 diffuses into the ferroelectric film 23. However, ruthenium hardly remains in the ferroelectric film 23 and is trapped at the interface between the ferroelectric film 23 and the first conductor film 22, and as shown in FIG. A metal dispersion layer 26 is formed at the interface between the first conductive film 22 and the first conductive film 22.

  In FIG. 2A, the metal dispersion layer 26 is schematically shown. However, the thickness of the metal dispersion layer 26 is actually extremely thin and the boundary with the ferroelectric film 23 is unclear. It is difficult to observe the metal dispersion layer 26 with a (transmission type) electron microscope.

  In this embodiment, annealing for diffusing ruthenium is performed after the second conductor film 25 is formed. However, annealing is performed after the metal atom supply film 24 is formed, and then the second conductor film 25 is formed. May be formed.

  Next, as shown in FIG. 2B, the second conductor film 25, the metal atom supply film 24, the ferroelectric film 23, and the metal dispersion layer 26 are patterned using a photolithography method and an etching method. Then, an upper electrode and a capacitor insulating film are formed.

  Hereinafter, the patterned second conductor film 25 and the metal atom supply film 24 are collectively referred to as an upper electrode 25a, and the patterned ferroelectric film 23 and the metal dispersion layer 26 are collectively referred to as a capacitive insulating film 23a. After forming the upper electrode 25a and the capacitor insulating film 23a in this way, the photoresist film used for forming the upper electrode 25a and the capacitor insulating film 23a is removed.

  Next, the first conductor film 22 and the adhesion layer 21 are patterned again using a photolithography method and an etching method to form a lower electrode. Hereinafter, the patterned first conductor film 22 is referred to as a lower electrode 22a.

  In this manner, a ferroelectric capacitor having a structure in which the lower electrode 22a, the capacitive insulating film 23a, and the upper electrode 25a are stacked is obtained.

  Next, recovery annealing is performed in order to recover the damage of the capacitive insulating film 23a in the patterning process described above. Specifically, heat treatment is performed in an oxygen atmosphere at a temperature of, for example, 550 ° C. to 650 ° C. for about 60 minutes.

  Next, as shown in FIG. 2C, alumina is deposited on the entire upper surface of the semiconductor substrate 10 to a thickness of 50 nm, for example, by sputtering to form a protective film 27 that covers the ferroelectric capacitor. The protective film 27 is formed to prevent the entry of hydrogen and moisture into the ferroelectric capacitor and to protect the capacitive insulating film 24 formed of a ferroelectric material that is easily reduced by hydrogen and moisture.

  After forming the protective film 27, a second interlayer insulating film 28 is further formed on the protective film 27. In the present embodiment, a silicon oxide film is deposited to a thickness of about 1500 nm by the CVD method to form the second interlayer insulating film 28. After forming the second interlayer insulating film 28, the upper surface of the second interlayer insulating film 28 is polished and planarized by CMP.

  Next, as shown in FIG. 3A, a contact hole 28a reaching the impurity region 18 from the upper surface of the second interlayer insulating film 28 is formed by using a photolithography method and a dry etching method.

  Next, as shown in FIG. 3B, a barrier metal 29 is formed on the entire upper surface of the semiconductor substrate 10, and the wall surface of the contact hole 28 a is covered with the barrier metal 29. In the present embodiment, a film in which a Ti film and a TiN film are stacked is used as the barrier metal 29.

  Thereafter, a tungsten film is formed on the entire upper surface of the semiconductor substrate 10 by CVD or the like, and tungsten is embedded in the contact holes 22a. Next, the tungsten film and the barrier metal 29 are polished by CMP until the second interlayer insulating film 28 is exposed. A conductive plug 30 is formed by tungsten and the barrier metal 29 remaining in the contact hole 28a after the CMP polishing.

  Next, as shown in FIG. 4A, the contact hole 28b reaching the upper electrode 25a from the upper surface of the second interlayer insulating film 28 and the lower electrode 22a are formed by using a photolithography method and a dry etching method. A reaching contact hole 28c is formed.

  Next, as shown in FIG. 4B, a Ti film and a TiN film are sequentially formed as a barrier metal film 31 on the entire upper surface of the semiconductor substrate 10 by sputtering or the like.

  Next, aluminum is deposited on the entire upper surface of the semiconductor substrate 10 by CVD or the like to form an aluminum film 32, and aluminum is embedded in the contact holes 28b and 28c. Further, a Ti film and a TiN film are formed as a barrier metal 33 on the aluminum film 32.

  Thereafter, the barrier metal 33, the aluminum film 32, and the barrier metal 31 are patterned by using a photolithography method and an etching method to form a wiring having a desired pattern. In this way, a semiconductor device provided with a ferroelectric memory is completed.

  In this embodiment, as described above, the metal atom supply film 24 made of SRO is formed on the ferroelectric film 23, and ruthenium is diffused from the metal atom supply film 24 into the ferroelectric film 23, so that the ferroelectric film A metal dispersion layer 26 is formed at the interface between the body film 23 and the first conductor film 22.

  FIG. 5 is a diagram showing a result of examining the distribution state (SIMS profile) of ruthenium in the depth direction of the capacitive insulating film 23a by SIMS (Secondary Ion Mass Spectrometry) analysis. In FIG. 5, the horizontal axis indicates the time from the start of SIMS and can be converted to depth. The vertical axis represents the intensity (number of detections) of ruthenium. Furthermore, the thickness of the metal atom supply film 24 formed on the ferroelectric film 23 is 1 nm.

  As can be seen from the ruthenium SIMS profile of FIG. 5, the maximum peak of ruthenium is at the position of the metal atom supply film 24, but there is also a large peak at the interface between the ferroelectric film 23 and the first conductor film 22. To do.

  On the other hand, since there is no large ruthenium peak in the ferroelectric film 23, the ruthenium hardly remains in the ferroelectric film 23 and is trapped at the interface between the ferroelectric film 23 and the first conductor film 22. I understand that

  From these facts, it can be seen that the metal dispersion layer 26 is formed of ruthenium trapped at the interface between the ferroelectric film 23 and the first conductor film 22.

  FIG. 6 is a SIMS profile of strontium. Since strontium is originally added to the ferroelectric film 23, a large amount of strontium exists in the ferroelectric film 23 even in the sample in which the metal atom supply film 24 is not formed.

  In the sample on which the metal atom supply film 24 is formed, a strontium peak exists at the position of the metal atom supply film 24, but a strontium peak is present at the interface between the ferroelectric film 23 and the first conductor film 22. not exist. Therefore, it can be seen that strontium in the metal atom supply film 24 is hardly diffused at the interface between the ferroelectric film 23 and the first conductor film 22.

FIG. 7 is a diagram showing the results of examining the relationship between the horizontal axis with the thickness of the metal atom supply film 24 and the vertical axis with the leakage current between the upper electrode 25a and the lower electrode 22a. . As can be seen from FIG. 7, when there was no metal atom supply film 24 (when the thickness of the metal atom supply film 24 was 0 nm), there was a leakage current of about 9 × 10 ⁻⁹ A. However, when the metal atom supply film 24 having a thickness of 1 nm to 3 nm is formed on the ferroelectric film 23, the leakage current between the upper electrode 25a and the lower electrode 22a is about 3 × 10 ⁻⁹ A. Reduced to:

  The reason why the leakage current decreases when the metal atom supply film 24 is formed on the ferroelectric film 23 is not clear, but the metal dispersion layer 26 formed at the interface between the ferroelectric film 23 and the lower electrode 22a leaks. This is considered to act as a current barrier layer.

  The following additional notes are disclosed with respect to the above embodiments.

(Appendix 1) Forming a first conductor film above a semiconductor substrate;
Forming a ferroelectric film on the first conductive film;
Forming a metal atom supply film on the ferroelectric film;
A heat treatment is performed to diffuse metal atoms from the metal atom supply film to the interface between the first conductor film and the ferroelectric film, so that the first conductor film and the ferroelectric film Forming a metal dispersion layer in which the metal atoms are dispersed at an interface. A method for manufacturing a ferroelectric memory, comprising:

  (Supplementary note 2) The method of manufacturing a ferroelectric memory according to supplementary note 1, wherein the metal atom is ruthenium.

  (Supplementary note 3) The method for manufacturing a ferroelectric memory according to supplementary note 1 or 2, wherein the metal atom supply film is formed of strontium ruthenate.

  (Supplementary note 4) The method for manufacturing a ferroelectric memory according to any one of supplementary notes 1 to 3, wherein the thickness of the metal atom supply film is 3 nm or less.

(Additional remark 5) It has the process of forming a 2nd conductor film on the metal atom supply film between the process of forming the metal atom supply film, and the process of forming the metal dispersion layer,
After the step of forming the metal dispersion layer, the second conductor film and the metal atom supply film are patterned to form an upper electrode, and the ferroelectric film and the metal dispersion layer are patterned to capacitively insulate. 5. The method of manufacturing a ferroelectric memory according to claim 1, further comprising a step of forming a film and patterning the first conductive film to form a lower electrode.

  (Supplementary note 6) The method for manufacturing a ferroelectric memory according to any one of supplementary notes 1 to 5, wherein a temperature during the heat treatment is 700 ° C to 750 ° C.

(Appendix 7) a semiconductor substrate;
A lower electrode formed above the semiconductor substrate;
A capacitive insulating film formed on the lower electrode by a ferroelectric material and having a metal dispersion layer in which metal atoms are dispersed at the interface with the lower electrode;
An upper electrode formed on the capacitive insulating film,
A ferroelectric memory, wherein a metal atom supply film containing metal atoms of the same type as metal atoms dispersed in the metal dispersion layer is provided on the capacitor insulating film side of the upper electrode.

  (Supplementary note 8) The ferroelectric memory according to supplementary note 7, wherein the metal atom is ruthenium.

  (Supplementary note 9) The ferroelectric memory according to supplementary note 7 or 8, wherein the metal atom supply film is made of strontium ruthenate.

  (Supplementary note 10) The ferroelectric memory according to any one of supplementary notes 7 to 9, wherein the thickness of the metal atom supply film is 3 nm or less.

  DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, 11 ... Element isolation layer, 12 ... Well, 13 ... Gate insulating film, 14 ... Gate electrode, 15 ... Contact layer, 17 ... Side wall, 19 ... Cover insulating film, 20 ... 1st interlayer insulating film 21 ... Adhesion layer, 22 ... Metal atom supply film, 22a ... Lower electrode, 23 ... Ferroelectric film, 23a ... Capacitance insulating film, 24 ... Metal atom supply film, 25 ... Second conductor film, 25a ... Upper part Electrode, 26 ... Metal dispersion layer, 27 ... Protective film, 28 ... Second interlayer insulating film, 28a, 28b, 28c ... Contact hole, 29, 31, 33 ... Barrier metal, 30 ... Conductive plug, 32 ... Aluminum film .

Claims (4)

Forming a first conductor film above the semiconductor substrate;
Forming a ferroelectric film on the first conductive film;
Forming a metal atom supply film made of ruthenium (Ru) or an alloy or compound containing ruthenium on the ferroelectric film;
An interface between the first conductor film and the ferroelectric film is formed by diffusing ruthenium from the metal atom supply film to the interface between the first conductor film and the ferroelectric film by performing a heat treatment. Forming a metal dispersion layer in which the ruthenium is dispersed in a method for manufacturing a ferroelectric memory. 2. The method of manufacturing a ferroelectric memory according to claim 1, wherein the metal atom supply film is formed of strontium ruthenate. A step of forming a second conductor film on the metal atom supply film between the step of forming the metal atom supply film and the step of forming the metal dispersion layer;
After the step of forming the metal dispersion layer, the second conductor film and the metal atom supply film are patterned to form an upper electrode, and the ferroelectric film and the metal dispersion layer are patterned to capacitively insulate. 3. The method of manufacturing a ferroelectric memory according to claim 1, further comprising a step of forming a film and patterning the first conductive film to form a lower electrode. A semiconductor substrate;
A lower electrode formed above the semiconductor substrate;
A capacitive insulating film formed on the lower electrode by a ferroelectric material and having a metal dispersion layer in which ruthenium is dispersed at the interface with the lower electrode;
An upper electrode formed on the capacitive insulating film,
A ferroelectric memory, wherein a metal atom supply film made of ruthenium (Ru) or an alloy or compound containing ruthenium is provided on the capacitor insulating film side of the upper electrode.

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