JP6020043B2 - Compound semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a compound semiconductor device and a manufacturing method thereof.

  Nitride semiconductors have been studied for application to high breakdown voltage and high output semiconductor devices utilizing characteristics such as high saturation electron velocity and wide band gap. For example, the band gap of GaN that is a nitride semiconductor is 3.4 eV, which is larger than the band gap of Si (1.1 eV) and the band gap of GaAs (1.4 eV), and has a high breakdown electric field strength. Therefore, GaN is extremely promising as a material for a semiconductor device for a power supply that obtains high voltage operation and high output.

  As semiconductor devices using nitride semiconductors, many reports have been made on field effect transistors and Schottky Barrier Diodes (SBDs). SBD has the advantages of higher response speed and lower loss than pn diodes, and SBD using GaN (GaN · SBD) is expected as a next-generation low power consumption device.

JP 2004-31896 A JP 2011-49461 A

O. Ambacher et al., JOURNAL OF PHYSICS: CONDENSED MATTER 14 (2002) 3399-3434

  As a method for further reducing the loss in the SBD, it is possible to reduce the ON voltage of the SBD. In order to lower the on-voltage, it is essential to lower the Schottky barrier height at the interface between the metal (electrode) and the semiconductor. However, if the Schottky barrier height is low, the depletion layer formed at the time of reverse bias becomes thinner. Therefore, a sufficient off breakdown voltage cannot be obtained. Therefore, it is difficult to achieve both a low ON voltage and a high OFF breakdown voltage.

  As a technique for achieving both a low on-voltage and a high off-breakdown voltage, a technique for forming an anode electrode from two different metals has been devised (see Patent Document 1). However, this technique requires at least two times each of a film forming step of an electrode metal and a patterning step associated therewith in the manufacturing process. Therefore, there is a problem that the cleanliness at the interface between the metal and the semiconductor cannot be sufficiently maintained, resulting in deterioration of Schottky characteristics and reduction in device yield.

  The present invention has been made in view of the above problems, and without causing deterioration of Schottky characteristics and device yield reduction, it is possible to reliably achieve both low on-voltage and high off-voltage with a simple configuration, An object of the present invention is to provide a highly reliable compound semiconductor device that improves device characteristics and a method for manufacturing the compound semiconductor device.

One embodiment of a compound semiconductor device, and the electron transit layer of GaN, formed over the electron transit layer, and the compound semiconductor multilayer structure including an electron supply layer of InAlN having a first region and a second region And the electrode formed on the electron supply layer, wherein the first region has a lower In composition ratio than the second region, and the electrode includes the first region and the first region at an end thereof. 1 Schottky junction is formed, and the second region and the second Schottky junction are formed at a portion other than the end portion, and the electrode includes the first Schottky junction portion and the first Schottky junction. The two Schottky junction portions are made of the same material .

One aspect of the production method of a compound semiconductor device, and the electron transit layer GaN, a compound semiconductor multilayer structure including an electron supply layer of InAlN having a first region and a second region above said electron transit layer And forming an electrode on the electron supply layer, wherein the first region has an In composition ratio lower than that of the second region, and the electrode has the first portion at the end thereof. A first Schottky junction is formed with the first region, and the second Schottky junction is formed with the second region at a portion other than the end portion, and the electrode has the first Schottky junction And the portion of the second Schottky junction are made of the same material .

  According to the above aspects, the reliability of improving the device characteristics by ensuring both a low on-voltage and a high off-breakdown voltage with a simple configuration without causing deterioration of the Schottky characteristics and a decrease in device yield. A high compound semiconductor device is realized.

It is a schematic sectional drawing which shows the manufacturing method of InAlN / GaN * SBD by 1st Embodiment to process order. FIG. 2 is a schematic cross-sectional view illustrating the manufacturing method of the InAlN / GaN · SBD according to the first embodiment in the order of steps, following FIG. 1. FIG. 3 is a schematic cross-sectional view subsequent to FIG. 2, illustrating the method of manufacturing InAlN / GaN · SBD according to the first embodiment in the order of steps. It is a schematic diagram which shows the conduction band in a 1st Schottky junction and a 2nd Schottky junction. It is a schematic sectional drawing for demonstrating the effect of the 1st Schottky junction in InAlN / GaN * SBD by 1st Embodiment. It is a schematic sectional drawing which shows the manufacturing method of InAlN / GaN * SBD by 2nd Embodiment to process order. FIG. 7 is a schematic cross-sectional view subsequent to FIG. 6 showing the InAlN / GaN · SBD manufacturing method according to the second embodiment in the order of steps. FIG. 8 is a schematic cross-sectional view subsequent to FIG. 7, illustrating a method of manufacturing InAlN / GaN · SBD according to the second embodiment in the order of steps. It is a connection diagram which shows the PFC circuit by 3rd Embodiment. It is a connection diagram which shows schematic structure of the power supply device by 4th Embodiment.

(First embodiment)
In the present embodiment, a configuration and manufacturing method of an SBD (InAlN / GaN · SBD) having a heterointerface between InAlN and GaN is disclosed as a compound semiconductor device.
1 to 3 are schematic cross-sectional views showing a method of manufacturing InAlN / GaN · SBD according to the first embodiment in the order of steps.

First, as shown in FIG. 1A, a compound semiconductor multilayer structure 2 is formed on, for example, a Si substrate 1 as a growth substrate. As the growth substrate, a semi-insulating SiC substrate, sapphire substrate, GaAs substrate, GaN substrate or the like may be used instead of the Si substrate. Further, the conductivity of the substrate may be semi-insulating or conductive.
The compound semiconductor multilayer structure 2 includes an initial layer 2a, a buffer layer 2b, an electron transit layer 2c, a spacer layer 2d, and an InAlN layer 2A.

Specifically, the following compound semiconductors are grown on the Si substrate 1 by, for example, metal organic vapor phase epitaxy (MOVPE). Instead of the MOVPE method, a molecular beam epitaxy (MBE) method or the like may be used.
On the Si substrate 1, AlN is grown to a thickness of, for example, about 200 nm, and then AlGaN is grown. This AlGaN may be, for example Al composition rate changing multilayer structure _{(Al x Ga 1-x N} : 0.2 <x <0.8) and, to a total thickness of about 500 nm. Subsequently, i (Intensive Undoped) -GaN is grown to a thickness of about 1 μm, AlN to a thickness of about 2 nm, and InAlN to a thickness of about 20 nm, for example. Thus, the AlN initial layer 2a, the AlGaN buffer layer 2b, the i-GaN electron transit layer 2c, the AlN spacer layer 2d, and the InAlN layer 2A are formed.

As growth conditions for AlN, a mixed gas of trimethylaluminum (TMAl) gas and ammonia (NH ₃ ) gas is used as a source gas. As a growth condition for GaN, a mixed gas of trimethylgallium (TMGa) gas and NH ₃ gas is used as a source gas. As growth conditions for AlGaN, a mixed gas of TMAl gas, TMGa gas, and NH ₃ gas is used as a source gas. As growth conditions for InAlN, a mixed gas of trimethylindium (TMIn) gas, TMAl gas, and NH ₃ gas is used as a source gas. The presence / absence and flow rate of TMAl gas that is an Al source, TMGa gas that is a Ga source, and TMIn gas that is an In source are appropriately set according to the compound semiconductor to be grown. The flow rate of ammonia gas, which is a common raw material, is about 100 ccm to 10 LM.

For AlN, GaN, and AlGaN, the growth pressure is about 50 Torr to 300 Torr, and the growth temperature is about 1000 ° C. to 1200 ° C.
For InAlN, the growth pressure is about 50 Torr to 200 Torr, and the growth temperature is about 650 ° C. to 800 ° C.

Subsequently, an element isolation structure is formed.
Specifically, for example, argon (Ar) is implanted into the element isolation region of the compound semiconductor multilayer structure 2. Thereby, an element isolation structure is formed in the compound semiconductor multilayer structure 2 and the surface layer portion of the Si substrate 1. With this element isolation structure, an active region is defined on the compound semiconductor multilayer structure 2.
The element isolation may be performed by using, for example, an STI (Shallow Trench Isolation) method instead of the above-described implantation method. At this time, for example, a chlorine-based etching gas is used for the dry etching of the compound semiconductor multilayer structure 2.

Subsequently, as shown in FIG. 1B, an insulating film 10 for forming a mask is formed.
Specifically, an insulator such as silicon nitride (SiN) is deposited on the compound semiconductor multilayer structure 2 to a thickness of about 100 nm by a plasma CVD method or the like. Thus, the mask forming insulating film 10 is formed.
Here, instead of forming the insulating film 10, SiN may be continuously grown following the InAlN layer 2 </ b> A by MOVPE, for example, using SiH ₄ as a source gas. When SiN is continuously grown by the MOVPE method, the thickness is set to about 10 nm, for example. As the insulator, silicon oxide (SiO ₂ ) can be used instead of SiN.

Subsequently, as shown in FIG. 1C, a mask 10a is formed.
Specifically, the deposited insulating film 10 is processed by lithography and wet etching using a hydrofluoric acid-based solution, and the insulating film 10 is left at a position where the anode electrode is to be formed on the compound semiconductor multilayer structure 2. Thus, the mask 10a made of SiN is formed on the compound semiconductor multilayer structure 2. The mask 10a functions as an InN desorption prevention layer in the following heat treatment process.

Subsequently, as shown in FIG. 2A, the InAlN layer 2A of the compound semiconductor multilayer structure 2 is heat-treated.
Specifically, the Si substrate 1 is placed in the chamber of the MOCVD apparatus, and the InAlN layer 2A is heat-treated with the mask 10a formed. The heat treatment condition is that hydrogen (H ₂ ) or ammonia (NH ₃ ), here H ₂ is introduced into the chamber to form an H ₂ atmosphere, and a temperature in the range of about 700 ° C. to 1000 ° C., here about 800 ° C. And By this heat treatment, in the region where the mask 10a is not present, InN in the region of the InAlN layer 2A is thermally desorbed, and the In composition ratio decreases. In InAlN layer 2A, the first region 2e ₁ a reduced area of the In composition ratio. In the region where the mask 10a exists, thermal desorption of InN in the region of the InAlN layer 2A is suppressed, and the In composition ratio during InAlN growth is maintained. A region in which the In composition ratio is maintained (a region in which the composition of InAlN does not change) is defined as a second region 2e ₂ . Thus, the second region 2e _2, constitute a second region 2e low at ₂ on both sides of the 2 In composition ratio than the region 2e ₂ of the first region 2e ₁ Metropolitan electron supply layer 2e from.

In the present embodiment, in the electron supply layer 2e, the In composition ratio x (In _x Al _1-x N) of the first region 2e ₁ is 0 (0%) or more and 0.17 (17%) or less, for example, 0 .10. Here, when x = 0, the first region 2e ₁ is AlN. Here, the first region 2e ₁ is formed such that its In composition ratio is slightly lower on the surface than on the surface other than the surface (part in the depth direction). The In composition ratio y (In _y Al _1-y N) of the second region 2e ₂ is 0.17 (17%) or more and 0.4 or less, for example, 0.3 (30%).

If the temperature in the heat treatment is lower than about 700 ° C., the thermal desorption amount of InN satisfies the expected amount for the In composition ratio x of the first region 2e ₁ to be within the above range. There will be no. If the temperature is higher than about 1000 ° C., thermal desorption occurs even in the region under the mask 10a. By setting the temperature within the range of about 700 ° C. to about 1000 ° C., the thermal desorption amount of InN is determined as the In composition ratio of the _first region 2e ₁ in a state where thermal desorption of the region under the mask 10a is suppressed. x can be an expected amount within the above range.

Subsequently, as shown in FIG. 2B, a cathode electrode 3 which is an ohmic electrode is formed.
First, a resist mask for forming the cathode electrode is formed. A resist is applied on the compound semiconductor multilayer structure 2 to form an opening exposing the electrode formation region of the electron supply layer 2e. Thus, a resist mask having the opening is formed.

Using this resist mask, for example, Ti / Al is deposited as an electrode material on the resist mask including the inside of the opening, for example, by vapor deposition. The thickness of Ti is about 10 nm, and the thickness of Al is about 300 nm. The resist mask and Ti / Al deposited thereon are removed by a lift-off method. Thereafter, the Si substrate 1 is heat-treated (Rapid Thermal Anneal: RTA) at a temperature of about 400 ° C. to 1000 ° C., for example, about 700 ° C., for example, in a nitrogen atmosphere with the mask 10a formed. Thereby, the remaining Ti / Al makes ohmic contact with the electron supply layer 2e (the first region 2e ₁ thereof). By performing the heat treatment with the mask 10a formed, thermal desorption of InN in the _first region 2e ₁ due to the heat treatment is suppressed. If an ohmic contact with the Ti / Al electron supply layer 2e is obtained, heat treatment may be unnecessary. Thus, the cathode electrode 3 is formed on the electron supply layer 2e (the first region 2e ₁ thereof).
Thereafter, the mask 10a is removed by wet etching using a hydrofluoric acid-based solution.

Subsequently, as shown in FIG. 2C, a passivation film 4 is formed.
Specifically, an insulator such as SiN is deposited on the entire surface of the compound semiconductor multilayer structure 2 by a plasma CVD method or a sputtering method to a thickness of about 30 nm to 500 nm, for example, about 500 nm. Thereby, the passivation film 4 is formed. As an insulator for the passivation film, SiO ₂ , AlN, Al ₂ O ₃ or the like may be deposited instead of SiN.

Subsequently, as shown in FIG. 3A, an electrode recess 4 a is formed in the passivation film 4.
Specifically, a resist is applied to the surface of the passivation film 4. The resist is processed by lithography, and an opening that exposes the surface of the passivation film 4 corresponding to the region where the anode electrode is to be formed is formed in the resist. Thus, a resist mask having the opening is formed.

Using this resist mask, the electrode formation scheduled region of the passivation film 4 is removed by dry etching until the surface of the electron supply layer 2e is exposed. As described above, the electrode recess 4a is formed in the passivation film 4 to expose the electrode formation scheduled region on the surface of the electron supply layer 2e. Electrode recesses 4a, of the surface of the electron supply layer 2e, it exposed a second region 2e ₂ of the surface, a portion of the first region 2e ₁ of the surface on both sides of the second region 2e _2. For dry etching, for example, a fluorine-based etching gas is used. In this dry etching, etching damage to the electron supply layer 2e is required to be as small as possible. However, dry etching using a fluorine-based gas has little etching damage to the electron supply layer 2e. The electrode recess may be formed by wet etching using a fluorine-based solution instead of dry etching.
Thereafter, the resist mask is removed by an ashing process using oxygen plasma or a wet process using a chemical solution.

Subsequently, as shown in FIG. 3B, an anode electrode 5 which is a Schottky electrode is formed.
Specifically, a resist mask for forming the anode electrode is formed. A resist is applied on the compound semiconductor multilayer structure 2 to form an opening exposing the electrode recess 4a. Thus, a resist mask having the opening is formed.

Using this resist mask, for example, Ni / Au is deposited as an electrode material on the resist mask including the inside of the opening exposing the electrode recess 4a, for example, by vapor deposition. As the electrode material, Pt or the like may be used instead of Ni / Au. The thickness of Ni is about 50 nm, and the thickness of Au is about 300 nm. The resist mask and Ni / Au deposited thereon are removed by a lift-off method. Thus, the anode electrode 5 having a shape that fills the electrode recess 4a and rides on the passivation film 4 (a cross section along the longitudinal direction is a so-called overhang shape) is formed. The anode electrode 5 is in Schottky junction with the compound semiconductor multilayer structure 2 (electron supply layer 2e) in the electrode recess 4a. In the present embodiment, the anode electrode 5, the bottom surface of the electrode recesses 4a, both ends first region 2e ₁ surface and a first Schottky junction with portion SK1 is formed, the second region at the central portion The surface of 2e ₂ and the second Schottky junction SK2 are formed.

  Thereafter, the InAlN / GaN SBD according to the present embodiment is formed through various processes such as formation of each wiring connected to the cathode electrode 3 and the anode electrode 5.

  In the InAlN / GaN · SBD according to the present embodiment, when a forward bias voltage is applied, first, current is passed through the second Schottky junction on the inner side having a low Schottky barrier height. Therefore, the rising voltage in the forward direction becomes faster. On the other hand, when a reverse bias voltage is applied, a depletion layer spreads from the outer first Schottky junction having a high Schottky barrier height to the compound semiconductor multilayer structure immediately below, and is pinched off. In the InAlN / GaN SBD according to the present embodiment, it is possible to reliably achieve both a low on-voltage and a high off-voltage with a simple configuration without causing deterioration of Schottky characteristics and a reduction in device yield.

In InAlN / GaN * SBD by this embodiment, a schematic diagram is shown about the conduction band in the 1st Schottky junction and the 2nd Schottky junction.
FIG. 4 is a schematic diagram showing a conduction band in the first Schottky junction and the second Schottky junction, where (a) is a second Schottky junction having an In composition ratio of 30%, and (b). Indicates first Schottky junctions with an In composition ratio of 10%.

In the InAlN / GaN · SBD according to the present embodiment, when the In composition ratio in the second region 2e ₂ of the electron supply layer 2e is 30% or more and 40% or less, particularly about 30%, the effect of reducing the on-voltage is high. . As shown in FIG. 4A, at the interface between GaN and InAlN, when the In composition is about 30%, the polarities of the piezo polarization and the natural polarization are reversed, and the absolute values of the charges due to the respective polarizations are the same. Theoretically, no charge is generated at the interface. Under the condition that no charge is generated at the interface between GaN and InAlN, the band is not lifted or lifted by the charge. Furthermore, when the In composition ratio is 30%, ΔEc (conduction band energy difference) between GaN and InAlN can be lowered (about 0.2 eV). Therefore, the barrier when electrons in the GaN conduction band flow to the anode electrode side in the second Schottky junction at the time of forward bias can be kept small. For this reason, a forward current easily flows, which is effective in reducing the on-voltage.

On the other hand, in the first region 2e ₁ of the electron supply layer 2e, the low In composition ratio leads to an improvement in reverse breakdown voltage and a reduction in on-resistance, and the In composition ratio ranges from 0% to 17%. Hereinafter, it is particularly preferably less than 17%. From the viewpoint of the off breakdown voltage, as shown in FIG. 4B, the lower the In composition ratio, the wider the band gap of InAlN and the larger ΔEc with GaN, so the Schottky barrier height is higher and the reverse direction is increased. Off breakdown voltage increases.
Further, as shown in FIG. 5, when the In composition ratio of the first region 2e ₁ is less than 17%, the current path in the compound semiconductor multilayer structure 2 is the interface between GaN and InAlN (in the example shown, GaN and It becomes a two-dimensional electron gas (2DEG) generated at the interface with AlN under InAlN. At this time, by applying a reverse electric field, 2DEG is blocked by the depletion layer extending from the first Schottky junction SK1, and is pinched off. As a result, the reverse breakdown voltage in the reverse direction becomes extremely high.
Also from the viewpoint of on-resistance, the In composition ratio of the first region 2e ₁ is preferably low. The lower the In composition ratio, the stronger the piezoelectric charge is generated with GaN, leading to an increase in 2DEG and a decrease in sheet resistance, resulting in a decrease in on-resistance.

  As described above, according to the present embodiment, a low on-voltage and a high off-withstand voltage can be reliably achieved with a simple configuration without degrading the Schottky characteristics and reducing the yield of the device, and the device characteristics can be improved. Improved and highly reliable InAlN / GaN SBD is realized.

(Second Embodiment)
In the present embodiment, as in the first embodiment, the configuration and manufacturing method of InAlN / GaN · SBD are disclosed. However, the present embodiment is different from the first embodiment in that the aspect of the first region of the electron supply layer is different. To do. In addition, about the same thing as the structural member of 1st Embodiment, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted.
6 to 8 are schematic cross-sectional views showing a method of manufacturing InAlN / GaN · SBD according to the second embodiment in the order of steps.

First, the same process as that in FIG. 1A of the first embodiment is performed to form the compound semiconductor stack 2. The state at this time is shown in FIG. The InAlN layer 2A of the compound semiconductor stack 2 has an InN composition ratio of 30% to 40%, for example, 30%.
Subsequently, as in the first embodiment, an element isolation structure is formed.

Subsequently, as shown in FIG. 6B, an insulating film 20 for forming a mask is formed.
Specifically, an insulator such as silicon oxide (SiO ₂ ) is deposited on the compound semiconductor multilayer structure 2 by a plasma CVD method or the like to a thickness of about 200 nm. Thus, the mask forming insulating film 20 is formed.

Subsequently, as shown in FIG. 6C, a mask 20a is formed.
Specifically, the deposited insulating film 20 is processed by lithography and wet etching using a hydrofluoric acid-based solution, and the insulating film 20 is left at the position where the anode electrode is to be formed on the compound semiconductor multilayer structure 2. Thus, the mask 20a made of SiO ₂ is formed on the compound semiconductor multilayer structure 2. The mask 20a functions as an etching mask and a selective growth mask in the following steps.

Subsequently, as shown in FIG. 7 (a), to form a second region 11 _2.
Specifically, the InAlN layer 2A is removed by dry etching using the mask 20a until the surface of the spacer layer 2d is exposed. For dry etching, for example, a chlorine-based etching gas is used. The InAlN layer 2A remains only in the region under the mask 20a. Thus, the second region 11 ₂ is formed comprised of the remaining InAlN layer 2A.

Subsequently, as shown in FIG. 7 (b), to form a first region 11 _1.
Specifically, again using the mask 20a, by MOVPE, it is regrown InAlN on the spacer layer 2d exposed in the second region 11 ₂ on both sides. Thus, ₁ is formed first region 11. The first region 11 ₁ has an In composition ratio lower than that of the second region 11 ₂ , and is 0% or more and 17% or less, for example, 10%. Here, when x = 0, the first region 11 ₁ becomes AlN. Here, the first region 11 _1, In composition ratio is formed so as to be slightly lower than the other said surface at its surface (the site of the depth direction).
Thus, the second region 11 _2, the second region 11 ₂ of the electron supply layer 11 from both sides in the second region 11 having low In composition ratio than ₂ first region 11 ₁ Metropolitan constructed.

Subsequently, as shown in FIG. 7C, a cathode electrode 3 which is an ohmic electrode is formed.
First, a resist mask for forming the cathode electrode is formed. A resist is applied on the compound semiconductor multilayer structure 2 to form an opening that exposes the electrode formation region of the electron supply layer 11. Thus, a resist mask having the opening is formed.

Using this resist mask, for example, Ti / Al is deposited as an electrode material on the resist mask including the inside of the opening, for example, by vapor deposition. The thickness of Ti is about 10 nm, and the thickness of Al is about 300 nm. The resist mask and Ti / Al deposited thereon are removed by a lift-off method. Thereafter, the Si substrate 1 is heat-treated (Rapid Thermal Anneal: RTA) at a temperature of about 400 ° C. to 1000 ° C., for example, about 700 ° C., for example, in a nitrogen atmosphere with the mask 20a formed. Thereby, the remaining Ti / Al is in ohmic contact with the electron supply layer 11 (the first region 11 ₁ thereof). By performing heat treatment with the mask 20a formed, thermal desorption of InN in the _first region 111 due to the heat treatment is suppressed. If an ohmic contact with the Ti / Al electron supply layer 11 is obtained, heat treatment may be unnecessary. Thus, the cathode electrode 3 is formed on the electron supply layer 11 (the first region 11 ₁ thereof).
Thereafter, the mask 20a is removed by wet etching using a hydrofluoric acid-based solution.

Subsequently, as shown in FIG. 8A, a passivation film 4 is formed.
Specifically, an insulator such as SiN is deposited on the entire surface of the compound semiconductor multilayer structure 2 by a plasma CVD method or a sputtering method to a thickness of about 30 nm to 500 nm, for example, about 500 nm. Thereby, the passivation film 4 is formed. As an insulator for the passivation film, SiO ₂ , AlN, Al ₂ O ₃ or the like may be deposited instead of SiN.

Subsequently, as shown in FIG. 8B, an electrode recess 4 a is formed in the passivation film 4.
Specifically, a resist is applied to the surface of the passivation film 4. The resist is processed by lithography, and an opening that exposes the surface of the passivation film 4 corresponding to the region where the anode electrode is to be formed is formed in the resist. Thus, a resist mask having the opening is formed.

Using this resist mask, the electrode formation scheduled region of the passivation film 4 is removed by dry etching until the surface of the electron supply layer 11 is exposed. As described above, the electrode recess 4 a is formed in the passivation film 4 to expose the electrode formation scheduled region on the surface of the electron supply layer 11. Electrode recesses 4a, of the surface of the electron supply layer 11 to expose a second region 11 ₂ of the surface, a portion of the first region 11 ₁ of the surface in the second region 11 ₂ on both sides. For dry etching, for example, a fluorine-based etching gas is used. In this dry etching, etching damage to the electron supply layer 11 is required to be as small as possible. However, dry etching using a fluorine-based gas has little etching damage to the electron supply layer 11. The electrode recess may be formed by wet etching using a fluorine-based solution instead of dry etching.
Thereafter, the resist mask is removed by an ashing process using oxygen plasma or a wet process using a chemical solution.

Subsequently, as shown in FIG. 8C, an anode electrode 5 which is a Schottky electrode is formed.
Specifically, a resist mask for forming the anode electrode is formed. A resist is applied on the compound semiconductor multilayer structure 2 to form an opening exposing the electrode recess 4a. Thus, a resist mask having the opening is formed.

Using this resist mask, for example, Ni / Au is deposited as an electrode material on the resist mask including the inside of the opening exposing the electrode recess 4a, for example, by vapor deposition. As the electrode material, Pt or the like may be used instead of Ni / Au. The thickness of Ni is about 50 nm, and the thickness of Au is about 300 nm. The resist mask and Ni / Au deposited thereon are removed by a lift-off method. Thus, the anode electrode 5 having a shape that fills the electrode recess 4a and rides on the passivation film 4 (a cross section along the longitudinal direction is a so-called overhang shape) is formed. The anode electrode 5 is in Schottky junction with the compound semiconductor multilayer structure 2 (electron supply layer 11) in the electrode recess 4a. In the present embodiment, the anode electrode 5, the bottom surface of the electrode recesses 4a, both ends first region 11 ₁ of the surface and the first Schottky junction with portion SK1 is formed, the second region at the central portion 11 ₂ surface and a second Schottky junction SK2 is formed.

  Thereafter, the InAlN / GaN SBD according to the present embodiment is formed through various processes such as formation of each wiring connected to the cathode electrode 3 and the anode electrode 5.

  In the InAlN / GaN · SBD according to the present embodiment, when a forward bias voltage is applied, first, current is passed through the second Schottky junction on the inner side having a low Schottky barrier height. Therefore, the rising voltage in the forward direction becomes faster. On the other hand, when a reverse bias voltage is applied, a depletion layer spreads from the outer first Schottky junction having a high Schottky barrier height to the compound semiconductor multilayer structure immediately below, and is pinched off. In the InAlN / GaN SBD according to the present embodiment, it is possible to reliably achieve both a low on-voltage and a high off-voltage with a simple configuration without causing deterioration of Schottky characteristics and a reduction in device yield.

  As described above, according to the present embodiment, a low on-voltage and a high off-withstand voltage can be reliably achieved with a simple configuration without degrading the Schottky characteristics and reducing the yield of the device, and the device characteristics can be improved. Improved and highly reliable InAlN / GaN SBD is realized.

(Third embodiment)
In the present embodiment, a PFC (Power Factor Correction) circuit including the InAlN / GaN SBD according to the first or second embodiment is disclosed.
FIG. 9 is a connection diagram showing a PFC circuit according to the third embodiment.

  The PFC circuit 30 includes a switching element (transistor) 31, a diode 32, a choke coil 33, capacitors 34 and 35, a diode bridge 36, and an AC power supply (AC) 37. The InAlN / GaN SBD according to the first or second embodiment is applied to one or both of the diodes constituting the diode 32 and the diode bridge 36.

  In the PFC circuit 30, the drain electrode of the switch element 31 is connected to the anode terminal of the diode 32 and one terminal of the choke coil 33. The source electrode of the switch element 31 is connected to one terminal of the capacitor 34 and one terminal of the capacitor 35. The other terminal of the capacitor 34 and the other terminal of the choke coil 33 are connected. The other terminal of the capacitor 35 and the cathode terminal of the diode 32 are connected. An AC 37 is connected between both terminals of the capacitor 34 via a diode bridge 36. A direct current power supply (DC) is connected between both terminals of the capacitor 35. Note that a PFC controller (not shown) is connected to the switch element 31.

  In the present embodiment, the InAlN / GaN SBD according to the first or second embodiment is applied to the PFC circuit 30. Thereby, a highly reliable PFC circuit 30 is realized.

(Fourth embodiment)
In the present embodiment, a power supply device including InAlN / GaN SBD according to the first or second embodiment is disclosed.
FIG. 10 is a connection diagram illustrating a schematic configuration of the power supply device according to the fourth embodiment.

The power supply device according to this embodiment includes a high-voltage primary circuit 41 and a low-voltage secondary circuit 42, and a transformer 43 disposed between the primary circuit 41 and the secondary circuit 42. The
The primary side circuit 41 includes the PFC circuit 30 according to the third embodiment and an inverter circuit connected between both terminals of the capacitor 35 of the PFC circuit 30, for example, a full bridge inverter circuit 40. The full-bridge inverter circuit 40 includes a plurality (here, four) of switch elements 44a, 44b, 44c, and 44d.
The secondary circuit 42 includes a plurality (three in this case) of switch elements 45a, 45b, and 45c.

  In this embodiment, the PFC circuit 30 according to the third embodiment is applied to a primary circuit 41 that is a high-voltage circuit. As a result, a highly reliable high-power power supply device is realized.

  Hereinafter, various aspects of the compound semiconductor device, the manufacturing method thereof, the power supply device, and the high-frequency amplifier will be collectively described as appendices.

(Appendix 1) an electronic travel layer;
A compound semiconductor multilayer structure comprising: an InAlN electron supply layer formed above the electron transit layer and having a first region and a second region;
An electrode formed on the electron supply layer,
The first region has a lower In composition ratio than the second region,
The electrode forms a first Schottky junction with the first region at an end thereof, and forms a Schottky junction with the second region and the second electron supply 2 at a portion other than the end portion. A compound semiconductor device characterized by the above.

  (Supplementary note 2) The compound semiconductor device according to supplementary note 1, wherein the electron supply layer has a lower In composition ratio in a surface of the first region than in the surface other than the surface.

  (Appendix 3) The compound semiconductor device according to appendix 1 or 2, wherein the compound semiconductor multilayer structure further includes an AlN spacer layer between the electron transit layer and the electron supply layer.

(Appendix 4) Forming a compound semiconductor multilayer structure including an electron transit layer and an InAlN electron supply layer having a first region and a second region above the electron transit layer;
Forming an electrode on the electron supply layer,
The first region has a lower In composition ratio than the second region,
The electrode forms a first Schottky junction with the first region at an end portion thereof, and forms a second Schottky junction with the second region at a portion other than the end portion. A method of manufacturing a compound semiconductor device.

  (Supplementary note 5) The method of manufacturing a compound semiconductor device according to supplementary note 4, wherein the electron supply layer has a lower In composition ratio in a surface of the first region than in the surface other than the surface.

  (Additional remark 6) The said compound semiconductor laminated structure is further equipped with the spacer layer of AlN between the said electron transit layer and the said electron supply layer, The manufacturing method of the compound semiconductor device of Additional remark 4 or 5 characterized by the above-mentioned.

  (Supplementary note 7) Any one of Supplementary notes 4 to 6, wherein when the electron supply layer is formed, InN in InAlN is locally desorbed by heat treatment to form the first region. A method for manufacturing the compound semiconductor device according to the item.

(Supplementary Note 8) The heat treatment method of a compound semiconductor device according to Appendix 7, which comprises carrying out in an atmosphere of N ₂ gas or H ₂ gas.

  (Additional remark 9) The said heat processing is performed at the temperature within the range of 700 to 1000 degreeC, The manufacturing method of the compound semiconductor device of Additional remark 7 or 8 characterized by the above-mentioned.

  (Supplementary note 10) The compound semiconductor device according to supplementary note 7, wherein when forming the electron supply layer, the second region is formed by etching, and the first region is formed by regrowth. Method.

(Supplementary note 11) A power supply circuit comprising a transformer and a high-voltage circuit and a low-voltage circuit across the transformer,
The high-voltage circuit has a diode;
The diode is
An electronic travel layer,
A compound semiconductor multilayer structure comprising: an InAlN electron supply layer formed above the electron transit layer and having a first region and a second region;
An electrode formed on the electron supply layer,
The first region has a lower In composition ratio than the second region,
The electrode forms a first Schottky junction with the first region at an end portion thereof, and forms a second Schottky junction with the second region at a portion other than the end portion. Power supply circuit.

DESCRIPTION OF SYMBOLS 1 Si substrate 2 Compound semiconductor laminated structure 2a Initial layer 2b Buffer layer 2c Electron travel layer 2d Spacer layer 2e, 11 Electron supply layers 2e ₁ and 11 ₁ First region 2e ₂ and 11 ₂ Second region 2A InAlN layer 3 Cathode Electrode 4 Passivation film 4a Electrode recess 5 Anode electrode 10, 20 Insulating film 10a, 20a Mask SK1 First Schottky junction SK2 Second Schottky junction 30 PFC circuits 31, 44a, 44b, 44c, 44d, 45a, 45b , 45c Switch element 32 Diode 33 Choke coil 34, 35 Capacitor 36 Diode bridge 40 Full bridge inverter circuit 41 Primary side circuit 42 Secondary side circuit 43 Transformer

Claims (12)

A GaN electron transit layer;
A compound semiconductor multilayer structure comprising: an InAlN electron supply layer formed above the electron transit layer and having a first region and a second region;
An electrode formed on the electron supply layer,
The first region has a lower In composition ratio than the second region,
The electrode forms a first Schottky junction with the first region at an end thereof, and forms a second Schottky junction with the second region at a portion other than the end , The compound semiconductor device according to claim 1, wherein the first Schottky junction portion and the second Schottky junction portion are made of the same material . 2. The compound semiconductor device according to claim 1, wherein the second region is formed over the entire region in the thickness direction of the electron supply layer. The electron supply layer, a compound semiconductor device according to claim 1 or 2 surfaces of the first region is characterized by a low In composition ratio than the other said surface. The compound semiconductor laminated structure, a compound semiconductor device according to any one of claims 1 to 3, characterized by further comprising a spacer layer of AlN between the electron transit layer and the electron supply layer. Forming GaN and the electron transit layer, a compound semiconductor multilayer structure including an electron supply layer of InAlN having a first region and a second region above said electron transit layer,
Forming an electrode on the electron supply layer,
The first region has a lower In composition ratio than the second region,
The electrode forms a first Schottky junction with the first region at an end thereof, and forms a second Schottky junction with the second region at a portion other than the end , The method of manufacturing a compound semiconductor device , wherein the first Schottky junction portion and the second Schottky junction portion are made of the same material . 6. The method of manufacturing a compound semiconductor device according to claim 5, wherein the second region is formed over the entire region in the thickness direction of the electron supply layer. 7. The method of manufacturing a compound semiconductor device according to claim 5 , wherein the electron supply layer has a lower In composition ratio in a surface of the first region than in the surface other than the surface. The said compound semiconductor laminated structure is further equipped with the spacer layer of AlN between the said electron transit layer and the said electron supply layer, The manufacturing of the compound semiconductor device of any one of Claims 5-7 characterized by the above-mentioned. Method. When forming the electron supply layer, the InN of a portion corresponding to below the electrode in the InAlN by heat treatment by locally desorbed claims 5-6, characterized in that forming said first region 9. A method for producing a compound semiconductor device according to any one of 8 above. The method of manufacturing a compound semiconductor device according to claim 9 , wherein the heat treatment is performed in an atmosphere of NH ₃ gas or H ₂ gas. The method of manufacturing a compound semiconductor device according to claim 9 or 10 , wherein the heat treatment is performed at a temperature within a range of 700 ° C to 1000 ° C. 6. The method for manufacturing a compound semiconductor device according to claim 5 , wherein when forming the electron supply layer, the second region is formed by etching and the first region is formed by regrowth.

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