JP6015800B1 - DC / AC system interconnection device - Google Patents

Abstract

[PROBLEMS] To perform direct and mutual power conversion between DC power and AC power with a simple configuration. Two phases are selected from the three-phase AC power at a predetermined switching period in accordance with a bidirectional switch circuit and a plurality of modes divided according to the magnitude relationship of the voltage of each phase in the three-phase AC power. A virtual AC / DC conversion process for obtaining a plurality of line voltage generation sections to be performed, and from the second carrier waveform pattern CW2 corresponding to the plurality of modes and the P-phase signal level G1 corresponding to the phase on the output side, A control unit 20 that generates a switching pattern of the bidirectional switch circuit 10 so as to perform virtual DC / AC conversion processing corresponding to a plurality of line voltage generation sections, a current direction and a current amount of a current flowing through the power line LU, and Current setting unit 50, current detection unit 51 for detecting the current direction and current amount of power line LU, and signal level G1 is increased or decreased so that the current direction and current amount are input. It comprises a flow adjustment unit 52, a. [Selection] Figure 1

Description

  The present invention relates to a DC / AC system interconnection device that can directly and directly perform power conversion between DC power and AC power with a simple configuration.

  In general, a three-phase full bridge using a switching element such as an IGBT is used as a DC / AC converter that mutually converts DC power and AC power. This three-phase full bridge is used as a PWM converter.

  On the other hand, as what converts AC power and DC power using a matrix converter, for example, Patent Document 1 discloses a technique in which a three-phase to three-phase matrix converter is applied to drive a DC motor. Specifically, two outputs of a general three-phase / three-phase matrix converter are supplied to the armature of the DC motor, and a third output of the three-phase / three-phase matrix converter is connected to the field circuit of the DC motor. In addition, the phase is connected to each phase of the input power line via a corresponding diode.

JP 2003-88174 A

  On the other hand, the PWM converter as the DC / AC converter needs to make the DC voltage higher than the system voltage. Therefore, when the DC voltage, for example, the storage battery voltage is higher than the system voltage, the DC voltage can be converted into the system voltage, but when the storage battery voltage is lower than the system voltage, the storage battery voltage is boosted and PWM It is necessary to connect a bidirectional DC / DC chopper for use with a high direct current of the converter. For this reason, in the conventional DC / AC converter, when bidirectional power conversion is performed, it is necessary to provide a bidirectional DC / DC chopper or the like, which increases the number of parts and increases the cost.

  Although it is desired that the battery power and the three-phase power can be directly and mutually converted using a matrix converter, this is not realized at the present time. That is, there is no one that can directly perform grid interconnection between DC power and AC power using a matrix converter.

  The present invention has been made in view of the above, and provides a DC / AC system interconnection device capable of mutually and directly performing power conversion between DC power and AC power with a simple configuration. The purpose is to provide.

In order to solve the above-described problems and achieve the object, the DC / AC system interconnection apparatus according to the present invention can perform power conversion between three-phase AC power and DC power directly and directly. A DC / AC system interconnection device capable of being provided between a three-phase AC power source and a DC power source, and a bidirectional switch circuit for turning ON / OFF between the three-phase AC power source and the DC power source, A first carrier waveform pattern having a different pattern for each mode is generated at a predetermined switching period according to a plurality of modes divided according to the magnitude relationship of the voltages of each phase in the three-phase AC power, and the predetermined switching period and a first control signal generated based on the voltage of the first carrier waveform pattern and the three-phase AC power each phase of the inner, among a plurality of lines for selecting two phases among the three-phase AC power Voltage generation area A virtual AC / DC conversion process is performed to generate a second carrier waveform pattern that differs depending on the plurality of modes corresponding to the plurality of line voltage generation sections obtained by the virtual AC / DC conversion process. Then, for the two-phase line voltage selected in the plurality of line voltage generation sections, the generated second carrier waveform pattern and the second control signal corresponding to the DC power phase, A controller that generates a switching pattern of the bidirectional switch circuit, and a current flowing between the DC power source and the bidirectional switch circuit so as to perform different virtual DC / DC conversion processing according to the plurality of modes; A current setting unit for inputting a current setting value indicating a current direction and a current amount; and a current for detecting a current direction and a current amount of a current flowing between the DC power supply and the bidirectional switch circuit And a current adjustment unit that generates the second control signal in which the signal level is increased or decreased so that the current direction and current amount detected by the current detection unit become the current set value. Characteristic DC / AC system interconnection device.

Further, in the DC / AC system interconnection device according to the present invention, in the above invention, when the current adjusting unit converts the three-phase AC power into the DC power, the DC / AC system interconnection device is compared with an interphase voltage of the DC power. The amount of current is increased according to the magnitude of the difference voltage between the interphase voltage of the DC power and the average DC voltage while increasing the average DC voltage in the predetermined switching period generated by the virtual DC / DC conversion processing in the control unit. When generating the second control signal for adjusting the DC power and converting the DC power into the three-phase AC power, the average DC voltage is made smaller than the phase voltage of the DC power and the phase of the DC power The second control signal that adjusts the amount of current according to the magnitude of the voltage difference between the voltage and the average DC voltage is generated.

  In the DC / AC system interconnection device according to the present invention, the second control signal is a positive second control signal, and the negative second control signal is inverted by inverting the positive second control signal. And the magnitude of the average DC voltage corresponds to the difference between the signal level of the positive second control signal and the signal level of the negative second control signal. It is characterized by that.

  In the DC / AC system interconnection device according to the present invention, in the above invention, the control unit recognizes the maximum voltage phase, the minimum voltage phase, and the intermediate voltage phase in the three-phase AC power, and The line voltage generation interval includes a first interval corresponding to the intermediate voltage phase and the minimum voltage phase, a second interval corresponding to the maximum voltage phase and the minimum voltage phase, and a second interval corresponding to the maximum voltage phase and the intermediate voltage phase. It is obtained by dividing into three sections.

  In the DC / AC system interconnection device according to the present invention, the second carrier waveform pattern may have a mountain shape across two consecutive sections of the plurality of line voltage generation sections. It has a pattern in which the level changes.

  Further, in the DC / AC system interconnection device according to the present invention, in the above invention, the second carrier waveform pattern has a large voltage value among two voltage phases in each of the plurality of line voltage generation sections. When the voltage phase is the + side phase and the voltage phase having a small voltage value is the-side phase, when the line voltage generation section is switched, the phase is switched if there is a phase common to the + side phase or the-side phase. When there is a pattern in which the level continues in a mountain shape across the two line voltage generation sections, and there is a phase that reverses between the + side phase and the − side phase when the line voltage generation section switches , And having a pattern in which the level changes in a sawtooth shape at the boundary between the two line voltage generation sections to be switched.

According to the present invention, there is provided a DC / AC system interconnection device capable of directly and directly performing power conversion between three-phase AC power and DC power. A bidirectional switch circuit that is provided between the three-phase AC power source and the DC power source, and a plurality of modes that are classified according to the magnitude relationship of the voltage of each phase in the three-phase AC power the first carrier waveform pattern generated at a predetermined switching cycle, the predetermined switching period within said first voltage in each phase of a carrier wave pattern the 3-phase AC power having a different pattern for each mode depending on the A virtual AC / DC conversion process for obtaining a plurality of line voltage generation sections for selecting two phases of the three-phase AC power from the first control signal generated based on the first control signal; By A second carrier waveform pattern that differs according to the plurality of modes is generated corresponding to the plurality of line voltage generation intervals obtained in the above, and two-phase lines selected in the plurality of line voltage generation intervals Different virtual DC / DC conversion processes corresponding to the plurality of modes are performed on the inter-voltage from the generated second carrier waveform pattern and the second control signal corresponding to the phase of the DC power. A control unit that generates a switching pattern of the bidirectional switch circuit; and a current setting unit that inputs a current setting value indicating a current direction and a current amount of a current flowing between the DC power supply and the bidirectional switch circuit; A current detection unit that detects a current direction and a current amount of a current flowing between the DC power supply and the bidirectional switch circuit; and a current direction and a current amount detected by the current detection unit are the current setting value. So that comprises a current controller, the generating the second control signal to increase or decrease the signal level to become. As a result, there is no need to provide a bidirectional booster or the like, and power conversion between DC power and AC power can be performed directly and directly with a simple configuration.

FIG. 1 is a block diagram showing a configuration including a DC / AC system interconnection apparatus according to an embodiment of the present invention. FIG. 2 is a diagram showing an example of the configuration of the bidirectional switch shown in FIG. FIG. 3 is a diagram showing the relationship between the direction of current flowing through the P phase and the amount of current, depending on the magnitude relationship between the PN phase voltage and the average DC voltage obtained by the virtual DC / DC conversion process. FIG. 4 is a diagram showing a plurality of modes recognized by the control unit shown in FIG. FIG. 5 is a time chart showing virtual AC / DC conversion processing and virtual DC / DC conversion processing in mode m1 by the control unit shown in FIG. FIG. 6 is a time chart showing virtual AC / DC conversion processing and virtual DC / DC conversion processing in mode m2 by the control unit shown in FIG. FIG. 7 is a time chart showing virtual AC / DC conversion processing and virtual DC / DC conversion processing in mode m3 by the control unit shown in FIG. FIG. 8 is a time chart showing virtual AC / DC conversion processing and virtual DC / DC conversion processing in mode m4 by the control unit shown in FIG. FIG. 9 is a time chart showing virtual AC / DC conversion processing and virtual DC / DC conversion processing in mode m5 by the control unit shown in FIG. FIG. 10 is a time chart showing virtual AC / DC conversion processing and virtual DC / DC conversion processing in mode m6 by the control unit shown in FIG. FIG. 11 is a timing chart showing changes in current and voltage of each part when power is supplied from the three-phase AC power supply side to the storage battery side. FIG. 12 is a timing chart showing changes in current and voltage of each part when power is supplied from the storage battery side to the three-phase AC power supply side.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described with reference to the accompanying drawings.

(overall structure)
FIG. 1 is a block diagram showing a configuration including a DC / AC system interconnection device 1 according to an embodiment of the present invention. As shown in FIG. 1, the DC / AC system interconnection device 1 is a three-phase AC power of R phase, S phase, and T phase from a three-phase AC power source PS (AC device) via power lines LR, LS, and LT, respectively. The three-phase AC power that has been input is directly converted into DC power without being converted into DC power, and the storage battery LD (DC device) is connected via the power lines LU (P phase) and LV (N phase). Output to. Conversely, the DC power from the storage battery LD is directly output to the three-phase AC power supply PS side. That is, the DC / AC system interconnection device 1 performs power conversion between the three-phase AC power and the battery power directly and directly.

  The DC / AC system interconnection device 1 includes an input capacitor 40, a reactor 30, a bidirectional switch circuit 10, a control unit 20, a current detection unit 51, a current adjustment unit 52, and a current setting unit 50.

  The input capacitor 40 includes capacitors 41 to 43. One end of each of the capacitors 41 to 43 is connected to the R phase, the S phase, and the T phase, and the other end is commonly connected. The input capacitor 40 reduces current / voltage ripple of each phase.

  Reactor 30 is arranged on power line LU to reduce ripples.

  The bidirectional switch circuit 10 turns ON / OFF the supply of the input three-phase AC power to the storage battery LD so as to convert the input three-phase AC power into DC power. Further, the bidirectional switch circuit 10 turns ON / OFF the supply of the input DC power to the three-phase AC power source PS so as to convert the input DC power into three-phase AC power. The bidirectional switch circuit 10 includes a bidirectional switch group SW. The bidirectional switch group SW includes six bidirectional switches SRP, SSP, STP, SRN, SSN, and STN. The bidirectional switch circuit 10 is controlled by the control unit 20 so that the six bidirectional switches SRP, SSP, STP, SRN, SSN, and STN are turned on / off at predetermined timings, respectively, Convert AC power into single-phase AC power.

  The bidirectional switch SRP turns ON / OFF the connection between the R phase and the P phase. The bidirectional switch SSP turns on / off the connection between the S phase and the P phase. The bidirectional switch STP turns on / off the connection between the T phase and the P phase. The bidirectional switch SRN turns ON / OFF the connection between the R phase and the N phase. The bidirectional switch SSN turns on / off the connection between the S phase and the N phase. The bidirectional switch STN turns on / off the connection between the T phase and the N phase.

  Each bidirectional switch SRP, SSP, STP, SRN, SSN, STN is equivalent to, for example, the switch S shown in FIG. The switch S shown in FIG. 2A receives a switching signal from the control unit 20 via the control terminal CT, and turns on to connect the terminal T1 and the terminal T2, and turns off to cut off the terminal T1 and the terminal T2. . In the switch S, a current can flow in both directions between the terminal T1 and the terminal T2.

  The switch S shown in FIG. 2A is an ideal switch. Since the elements that actually constitute the switch have a switching time, they are connected as shown in FIG. 2B or FIG. 2C in consideration of the open mode and the short-circuit mode when commutating. And may be configured. The configuration shown in FIG. 2B is, for example, a configuration realized by connecting elements EL1 and EL2 having a reverse blocking function in parallel. The elements EL1 and EL2 having the reverse blocking function may be, for example, insulated gate bipolar transistors (IGBT). The terminals T1 ′ and T2 ′ correspond to the terminals T1 and T2 shown in FIG. 2A, respectively, and the control terminals CT1 ′ and CT2 ′ correspond to the control terminal CT shown in FIG. Yes.

  Alternatively, the configuration illustrated in FIG. 2C is a configuration realized by connecting elements EL11 and EL12 having no reverse blocking function in series, for example. The elements EL11 and EL12 having no reverse blocking function may be, for example, insulated gate bipolar transistors (IGBTs) in which free-wheeling diodes are connected at both ends, or field effect transistors (FETs). The terminal T1 ″ corresponds to the terminal T1 shown in FIG. 2A. The terminal T2 ″ corresponds to the terminal T2 shown in FIG. The control terminals CT1 ″ and CT2 ″ correspond to the control terminal CT shown in FIG.

  The current setting unit 50 inputs a current setting value indicating the current direction F / B of the current flowing through the power line LU and the current amount A to the current adjustment unit 52. The current detection unit 51 detects the current direction F / B of the current flowing through the power line LU and the current amount A1, and inputs the detection result to the current adjustment unit 52. The current adjustment unit 52 sets the signal level G1 that is the second control signal so that the current direction F / B detected by the current detection unit 51 and the current amount A1 become the current setting value input from the current setting unit 50. Output to the control unit 20.

(Processing overview of the control unit)
The control unit 20 generates a switching pattern of the bidirectional switch group SW in the bidirectional switch circuit 10. The control unit 20 performs virtual AC / DC conversion processing on the three-phase AC power input to the bidirectional switch circuit 10 and performs virtual DC / DC conversion processing on the power on which the virtual AC / DC conversion processing has been performed. Thus, the switching pattern of the bidirectional switch circuit 10 (that is, the pattern of the switching signal) is generated. In the following, “performing virtual AC / DC conversion processing” means performing virtual AC / DC conversion processing virtually, and “performing virtual DC / DC conversion processing” means virtual DC / DC conversion. It means that the process is virtually performed.

  The control unit 20 has a plurality of modes (for example, the modes m1 to m1 shown in FIG. 4) that are classified according to the magnitude relationship of the voltage of each phase in the input three-phase AC power with respect to the input three-phase AC power. The switching pattern of the bidirectional switch circuit 10 is generated so as to perform different virtual AC / DC conversion processes for m6). Here, the mode m1 is a phase interval of 0 ° to 60 ° with the start point (0 °) when the R-phase voltage is the maximum value (or when the S-phase voltage and the T-phase voltage intersect). Similarly, modes m2 to m6 are phase sections of 60 ° to 120 °, 120 ° to 180 °, 180 ° to 240 °, 240 ° to 300 °, and 300 ° to 360 °, respectively.

  The control unit 20 includes a synchronization signal detection unit 21. The synchronization signal detection unit 21 detects an intersection where the voltage difference between the S phase and the T phase is 0, and sets the intersection phase as 0 °. The AC voltage of each phase (R phase, S phase, T phase) on the input side Is recognized as the first control signal, and the mode at that time is recognized as a mode among the plurality of modes m1 to m6 according to the estimated magnitude relationship of the AC voltage of each phase.

  The control unit 20 includes a first carrier waveform pattern generation unit 22. The first carrier waveform pattern generation unit 22 has different first carrier waveform patterns for the plurality of modes m1 to m6, for example, the first carrier waveform pattern shown in FIGS. Carrier waveform patterns CW11 to CW13 are repeatedly generated every switching period T. That is, the first carrier waveform pattern generation unit 22 switches the first carrier waveform patterns CW11 to CW13 to be used for the virtual AC / DC conversion processing according to the modes m1 to m6 recognized by the synchronization signal detection unit 21. It is determined every period T. The switching period T is, for example, about 100 μs.

  The control unit 20 includes a phase information generation unit 23. As shown in FIG. 5A, the phase information generation unit 23 performs the first control corresponding to the first carrier waveform patterns CW11 to CW13 determined by the first carrier waveform pattern generation unit 22 and the phase on the input side. A plurality of virtual switching signals (R-phase pulse, S-phase pulse, T-phase pulse) in which each bidirectional switch SRP to STN virtually generates DC power in accordance with the comparison result. Is generated. At the same time, the phase information generation unit 23 generates a plurality of line voltage generation intervals φTS corresponding to combinations of levels (High, Low) of virtual switching signals (R-phase pulse, S-phase pulse, T-phase pulse). (For example, sections TS11, TS12, TS13 in the mode m1 shown in FIG. 5D) are obtained. Further, the phase information generation unit 23 obtains the selected + side phase and − side phase in the line voltage generation section φTS. The phase information generation unit 23 obtains a plurality of line voltage generation intervals φTS so that the average of the voltages between the selected two phases within the switching period T obtained in each mode m1 to m6 is equal. In other words, as will be described later, the phase information generation unit 23 virtually controls each bidirectional switch SRP to STN so that each bidirectional switch SRP to STN performs a virtual switching operation that generates DC power. AC / DC conversion processing (virtual AC / DC conversion processing) is performed.

The virtual switching operation is a switching operation different from that actually performed by each of the bidirectional switches SRP to STN, but the virtual direct current in the middle of virtual AC / DC conversion → virtual DC / DC conversion. This is a switching operation that each bidirectional switch SRP to STN considers as performing virtually in order to consider generating electric power. The process for generating virtual DC power in the middle stage is only virtual, and the process itself is not actually performed.

In addition, the control unit 20 switches the switching pattern of the bidirectional switch circuit 10 so as to perform different virtual DC / DC conversion processes for the plurality of modes m1 to m6 on the power subjected to the virtual AC / DC conversion process. (Ie, the pattern of the switching signal) is controlled.

Specifically, the control unit 20 includes a second carrier waveform pattern generation unit 24. The second carrier waveform pattern generation unit 24 is different from the second carrier waveform pattern (for example, the second carrier waveform shown in FIGS. 5 to 10) according to the plurality of modes m1 to m6 recognized by the synchronization signal detection unit 21. Patterns CW21 to CW26) are generated. The control unit 20 controls the bidirectional switch circuit 10 to perform virtual DC / DC conversion processing using the second carrier waveform patterns CW21 to CW26. That is, the control unit 20 generates the second carrier waveform patterns CW21 to CW26 corresponding to the plurality of line voltage generation sections φTS used for the virtual DC / DC conversion process according to the recognized modes m1 to m6. The second carrier waveform patterns CW21 to CW26 are also repeatedly generated at the switching period T if they are in the same mode. At this time, the plurality of line voltage generation intervals φTS correspond to combinations of virtual switching signal levels. That is, the control unit 20 determines the second carrier waveform pattern according to the recognized mode and the combination of the levels of a plurality of switching signals in which each bidirectional switch SRP to STN virtually generates DC power. CW21 to CW26 are generated.

  Here, the control unit 20 inputs the input P-phase signal level G1 to the negative side of the P-phase comparator CP. The inverter 27 inverts the P-phase signal level G1 and inputs the inverted N-phase signal level G2 to the negative side of the N-phase comparator CN. The second carrier waveform pattern CW2 (CW21 to CW26) generated by the second carrier waveform pattern generation unit 24 is input to each + side of the P-phase comparator CP and the N-phase comparator CN.

  The P-phase comparator CP compares the P-phase signal level G1 with the second carrier waveform pattern CW2, and outputs the comparison result to the switch control unit 28. On the other hand, the N-phase comparator CN compares the N-phase signal level G2 with the second carrier waveform pattern CW2, and outputs the comparison result to the switch control unit 28. Based on the comparison result of the P-phase comparator CP, the switch control unit 28 performs PWM control on the selected two-phase voltage obtained by the R-phase pulse, the S-phase pulse, and the T-phase pulse in the line voltage generation period φTS. The switching signals φSRP, φSSP, φSTP for switching the bidirectional switches SRP, SSP, STP connected to are generated. Further, the switch control unit 28 performs PWM control on the voltage between the two selected phases in the line voltage generation section φTS based on the comparison result of the N-phase comparator CN, and the bidirectional switches SRN, SSN, STN connected to the N-phase. Switching signals φSRN, φSSN, and φSTN are generated. The PN line voltage is a voltage between PN lines generated in the control unit 20 for each switching period T.

As shown in FIG. 3, the current adjustment unit 52 has a current direction (F) from the three-phase AC power supply PS side to the storage battery LD side, as compared to the PN phase voltage Vb (see FIG. 1) of the storage battery LD. , The average DC voltage Vave of the voltages P1, P2, and P3 in the switching period T generated by the virtual DC / DC conversion process in the control unit 20 (for example, the average of the PN line voltage in FIG. 5H) is increased. At the same time, a signal level G1 (second control signal) having an amount proportional to the difference voltage between the PN phase voltage Vb on the storage battery LD side and the average DC voltage Vave of the PN line voltage is generated, and the storage battery LD side Current direction (B) from the AC to the three-phase AC power source PS side, the average DC voltage Vave of the PN line voltage is made smaller than the PN phase voltage Vb on the storage battery LD side and the PN phase voltage on the storage battery LD side The voltage between Vb and PN line A signal level G1 (second control signal) is generated in which an amount proportional to the voltage difference from the uniform DC voltage Vave is a current amount.

  That is, the current adjustment unit 52 changes the current direction (F / B) depending on whether the average DC voltage Vave is increased or decreased as compared with the PN phase voltage Vb, and the current adjustment unit 52 depends on the magnitude (absolute value) of the difference voltage. The amount of current A is adjusted.

(Description of mode)
Here, a plurality of modes m1 to m6 recognized by the synchronization signal detection unit 21 will be described with reference to FIG.

  The synchronization signal detection unit 21 recognizes six modes m1 to m6 as shown in FIG. 4 according to the magnitude relationship of the detected AC voltage of each phase (R phase, S phase, T phase).

  In mode m1, the R phase is the maximum voltage phase, the T phase is the minimum voltage phase, and the S phase is the intermediate voltage phase. For example, when the synchronization signal detection unit 21 recognizes that the R phase is the maximum voltage phase, the T phase is the minimum voltage phase, and the S phase is the intermediate voltage phase, the current mode is the mode m1. recognize.

  In mode m2, the S phase is the maximum voltage phase, the T phase is the minimum voltage phase, and the R phase is the intermediate voltage phase. For example, when the synchronization signal detection unit 21 recognizes that the S phase is the maximum voltage phase, the T phase is the minimum voltage phase, and the R phase is the intermediate voltage phase, the current mode is the mode m2. recognize.

  In mode m3, the S phase is the maximum voltage phase, the R phase is the minimum voltage phase, and the T phase is the intermediate voltage phase. For example, when the synchronization signal detection unit 21 recognizes that the S phase is the maximum voltage phase, the R phase is the minimum voltage phase, and the T phase is the intermediate voltage phase, the current mode is the mode m3. recognize.

  In mode m4, the T phase is the maximum voltage phase, the R phase is the minimum voltage phase, and the S phase is the intermediate voltage phase. For example, when the synchronization signal detection unit 21 recognizes that the T phase is the maximum voltage phase, the R phase is the minimum voltage phase, and the S phase is the intermediate voltage phase, the current mode is the mode m4. recognize.

  In mode m5, the T phase is the maximum voltage phase, the S phase is the minimum voltage phase, and the R phase is the intermediate voltage phase. For example, when the synchronization signal detection unit 21 recognizes that the T phase is the maximum voltage phase, the S phase is the minimum voltage phase, and the R phase is the intermediate voltage phase, the current mode is the mode m5. recognize.

  In mode m6, the R phase is the maximum voltage phase, the S phase is the minimum voltage phase, and the T phase is the intermediate voltage phase. For example, when the synchronization signal detection unit 21 recognizes that the R phase is the maximum voltage phase, the S phase is the minimum voltage phase, and the T phase is the intermediate voltage phase, the current mode is the mode m6. recognize.

  The synchronization signal detection unit 21 may recognize each of the modes m1 to m6 on the basis of the start point of the mode m1, which is the point at which the R-phase detection voltage is maximized.

(Specific virtual AC / DC conversion processing)
Next, the virtual AC / DC conversion processing in each of the plurality of modes m1 to m6 will be described with reference to FIGS. 5 to 10 show two switching periods T that are continuous in each of the modes m1 to m6. In the following, for the sake of simplicity of explanation, a case where the DC voltage setting gain determined according to the signal level G1 is 1 will be described as an example.

[Mode m1]
In mode m1, as shown in FIG. 5A, the first carrier waveform pattern generation unit 22 uses a falling sawtooth wave W11 as the first carrier waveform pattern CW1 to be used for the virtual AC / DC conversion processing. And a first carrier waveform pattern CW11 having a rising sawtooth wave W12. The “falling sawtooth wave” refers to a sawtooth wave having a negative slope in which the amplitude decreases linearly with the passage of time, and the “rising sawtooth wave” A sawtooth wave having a positive slope whose amplitude increases linearly with the passage of time is assumed.

  On the other hand, the R-phase voltage a, the S-phase voltage b, and the T-phase voltage c directly detected by the synchronization signal detection unit 21 are input to the phase information generation unit 23. Alternatively, the phase information generation unit 23 estimates the R-phase voltage a, the S-phase voltage b, and the T-phase voltage c with reference to the start point of the mode m1, which is the point at which the R-phase detection voltage is maximized. The R-phase voltage a, the S-phase voltage b, and the T-phase voltage c are obtained for each switching period T and change as the switching period T elapses. FIG. 5 shows a case where the R phase voltage a, the S phase voltage b, and the T phase voltage c are in the adjacent switching period T. Here, the input or estimated R-phase voltage a, S-phase voltage b, and T-phase voltage c are obtained by standardizing the phase voltage between “−1” and “1”, respectively. At this time, the DC voltages in the sections (line voltage generation sections) TS11, TS12, and TS13 shown in FIG. 5D are respectively the ST voltage = bc, the RT voltage = ac, and the RS voltage = a-b.

  The pulses of each phase in the mode m1 will be described with reference to FIGS. 5 (a) and 5 (b). In the mode m1, the R phase is the maximum voltage phase, the T phase is the minimum voltage phase, and the S phase is the intermediate voltage phase. In the maximum voltage phase and the minimum voltage phase, the pulse is turned on for a time proportional to each potential. Therefore, the R-phase pulse width x = T | a | and the T-phase pulse width z = T | c |. Here, the timing when the R-phase pulse is turned on (timing when the section TS11 ends) is obtained from the intersection of the R-phase voltage | a | and the sawtooth wave W11. The R-phase pulse is turned on when the R-phase voltage | a | is equal to or greater than the value of the sawtooth wave W11. Thereby, an R-phase pulse is obtained. The timing at which the T-phase pulse is turned off (the timing at which the section TS12 after the section TS11 ends) is obtained from the intersection of the T-phase voltage | c | and the sawtooth wave W12. The T-phase pulse is turned ON when the T-phase voltage | c | is equal to or greater than the value of the sawtooth wave W12. Thereby, a T-phase pulse is obtained. The intermediate phase pulse is turned ON when either the maximum voltage phase pulse or the minimum voltage phase pulse is OFF. Therefore, the S-phase pulse is obtained from the intersection between the R-phase voltage | a | and the sawtooth wave W11, and the intersection between the T-phase voltage | c | and the sawtooth wave W12.

  Here, the widths of the line voltage generation sections TS11, TS12, and TS13 are T × (1− | a |), T × (| a | + | c | −1), and T × (1− | c), respectively. |). That is, a plurality of virtual switching signals (R-phase pulses, R width pulses, respectively) having widths corresponding to the line voltage generation sections TS11, TS12, TS13 for generating a virtual DC voltage by the virtual AC / DC conversion processing. S-phase pulse and T-phase pulse) are generated.

  In addition, the DC voltages (voltages between the selected two phases shown in FIG. 5C) in the line voltage generation sections TS11, TS12, and TS13 in the virtual AC / DC conversion process are the ST voltage = b−c and RT, respectively. Voltage = ac and RS voltage = ab. Of the two voltage phases in the selected two-phase voltage, if the voltage phase having a large level is defined as a + side phase and the voltage phase having a small level is defined as a − side phase, then in the line voltage generation section TS11, TS12, TS13, the S phase , R phase and R phase are + side phases, and T phase, T phase and S phase are-side phases. The phase information generation unit 23 outputs the line voltage generation period φTS (TS11, TS12, TS13) to the second carrier waveform pattern generation unit 24 and the switch control unit 28, and the + side phase and the − side from time to time. The phase is output to the switch control unit 28.

  By the way, the average of the DC voltage in the switching period T is obtained by integrating the DC voltage for each line voltage generation section TS11, TS12, TS13, adding them, and dividing by the switching period T. Can be expressed as:

Average of DC voltage of switching period T = {(b−c) × T × (1−a) + (a−c) × T × (ac−1) + (a−b) × T × (1 + c) )} / T
= A ² + c ² -b (a + c) (1)
Here, when a + b + c = 0 (three-phase condition) is considered, the equation (1) can be transformed into the following equation (2).
Average of DC voltage of switching period T = a ² + b ² + c ² (2)
Furthermore, from AC theory, from a ² + b ² + c ² = 3/2, equation (2) can be transformed into the following equation (3).
Average of DC voltage of switching period T = 3/2 (3)
As shown in Expression (3), the average of the virtual DC voltage in the switching period T can be a constant voltage.

  The input current in mode m1 will be described. As the R-phase input current, a positive current proportional to the time of the R-phase voltage a flows. As the T-phase input current, a negative current proportional to the magnitude of the T-phase voltage | c | flows. In the S-phase input current, a positive current flows in the line voltage generation section TS11, and a negative current flows in the line voltage generation section TS13. Therefore, the flowing current is T × (1−a) −T × (1 + c) = T (−a−c) = Tb, and when it is divided by the switching period T, it becomes the S phase voltage b. Therefore, currents proportional to the R-phase voltage a, S-phase voltage b, and T-phase voltage c flow in the R-phase, S-phase, and T-phase, respectively, and each phase of the input AC current is a sine wave. be able to.

[Mode m2]
In mode m2, as shown in FIG. 6A, the first carrier waveform pattern generator 22 generates a rising sawtooth wave W12 as the first carrier waveform pattern CW1 to be used for the virtual AC / DC conversion processing. A first carrier waveform pattern CW12 is determined. The phase information generation unit 23 acquires or estimates the R phase voltage a, the S phase voltage b, and the T phase voltage c according to the detection result of the synchronization signal detection unit 21. At this time, the DC voltages in the line voltage generation sections TS21, TS22, and TS23 shown in FIG. 6D are respectively the ST voltage = b−c, the RT voltage = ac, and the RS voltage = b−a. It becomes.

  The pulses of each phase in mode m2 will be described with reference to FIGS. 6 (a) and 6 (b). In mode m2, the S phase is the maximum voltage phase, the T phase is the minimum voltage phase, and the R phase is the intermediate voltage phase. The phase information generator 23 turns on the time proportional to each potential in the maximum voltage phase and the minimum voltage phase without changing the ON / OFF order of the R, S, and T phase pulses. Using the T-phase voltage | c |, the voltage (| b | + | c | −1), and the sawtooth wave W12, the ON / OFF timing of each phase pulse shown in FIG. 6B is generated.

  Here, the widths of the line voltage generation sections TS21, TS22, and TS23 are T × (| b | + | c | −1), T × (1− | b |), and T × (1− | c), respectively. |). That is, a plurality of virtual switching signals (R-phase pulses, R width pulses, respectively) having widths corresponding to the line voltage generation sections TS21, TS22, and TS23 for generating a virtual DC voltage by virtual AC / DC conversion processing. S-phase pulse and T-phase pulse) are generated.

  Here, the direct-current voltages (voltages between the selected two phases shown in FIG. 6C) in the line voltage generation sections TS21, TS22, and TS23 in the virtual AC / DC conversion process are respectively the ST voltage = b−c, RT Inter-voltage = ac, SR voltage = ba Of the two voltage phases in the selected two-phase voltage, if the voltage phase having a large level is defined as a + side phase and the voltage phase having a small level is defined as a − side phase, then in the line voltage generation sections TS21, TS22, TS23, the S phase , R phase and S phase are + side phases, and T phase, T phase and R phase are-side phases. The phase information generation unit 23 outputs the line voltage generation period φTS (TS21, TS22, TS23) to the second carrier waveform pattern generation unit 24 and the switch control unit 28, and the + side phase and − side The phase is output to the switch control unit 28.

By the way, the average of the DC voltage of the switching period T in the mode m2 can be expressed as the following equation (4).
Average of DC voltage of switching period T = {(b−c) × T × (−c + b−1) + (ac) × T × (−b + 1) + (b−a) × T × (1 + c)} / T
= B ² + c ² −a (b + c) (4)
Here, considering a + b + c = 0 (three-phase condition), the equation (4) can be transformed into the following equation (5).
Average of DC voltage of switching period T = a ² + b ² + c ² (5)
Furthermore, from AC theory, from a ² + b ² + c ² = 3/2, equation (5) can be transformed into the following equation (6).
Average of DC voltage of switching period T = 3/2 (6)
As shown in Expression (6), the average of the virtual DC voltage in the switching period T can be a constant voltage.

  The input current in mode m2 will be described. In mode m2, since the S phase is the maximum voltage phase and the T phase is the minimum voltage phase, a positive current proportional to the time of the S phase voltage b flows in the S phase, and the T phase is proportional to the time of the T phase voltage c. Negative current flows. In the R phase, a negative current flows in the line voltage generation section TS22, and a positive current flows in the line voltage generation section TS23. For this reason, the flowing current becomes T × (1−b) −T × (1 + c) = Ta, and when it is divided by the switching period T, it becomes the R phase voltage a. Therefore, a current proportional to the voltage flows in each phase, and each phase of the input AC current can be a sine wave.

[Mode m3]
In mode m3, as shown in FIG. 7A, the first carrier waveform pattern generator 22 uses a falling sawtooth wave W11 as the first carrier waveform pattern to be used for the virtual AC / DC conversion processing. A first carrier waveform pattern CW13 is determined. The phase information generation unit 23 acquires or estimates the R phase voltage a, the S phase voltage b, and the T phase voltage c according to the detection result of the synchronization signal detection unit 21. At this time, the DC voltages in the line voltage generation sections TS31, TS32, and TS33 shown in FIG. 7D are respectively the ST voltage = c−b, the RT voltage = ac, and the RS voltage = a−b. It becomes.

  The pulses of each phase in mode m3 will be described with reference to FIGS. 7 (a) and 7 (b). In mode m3, the S phase is the maximum voltage phase, the R phase is the minimum voltage phase, and the T phase is the intermediate voltage phase. In order to set the time ON proportional to the respective potentials in the maximum voltage phase and the minimum voltage phase without changing the ON / OFF order of the R, S, T phase pulses, in mode m3, the R phase voltage | a | By using (| a | + | b | -1) and the sawtooth wave W11, the ON / OFF timing of each pulse shown in FIG. 7B is generated.

  Here, the widths of the line voltage generation sections TS31, TS32, and TS33 are T × (1− | a |), T (1− | b |), and T × (| a | + | b | −1, respectively. ) That is, a plurality of virtual switching signals (R-phase pulse, R-phase pulse, each having a width corresponding to the line voltage generation section TS31, TS32, TS33 for generating a virtual DC voltage by the virtual AC / DC conversion processing. S-phase pulse and T-phase pulse) are generated.

  Here, the direct-current voltages (voltages between the selected two phases shown in FIG. 7C) in the line voltage generation sections TS31, TS32, and TS33 in the virtual AC / DC conversion processing are the ST voltage = b−c, TR, respectively. Inter-voltage = ca, SR voltage = ba Of the two voltage phases in the selected two-phase voltage, if the voltage phase having a large level is defined as a + side phase and the voltage phase having a small level is defined as a − side phase, in the line voltage generation sections TS31, TS32, and TS33, , T phase and S phase are + side phases, and T phase, R phase and R phase are-side phases. The phase information generation unit 23 outputs the line voltage generation period φTS (TS31, TS32, TS33) to the second carrier waveform pattern generation unit 24 and the switch control unit 28, and the + side phase and the − side from time to time. The phase is output to the switch control unit 28.

By the way, the average of the DC voltage of the switching period T in the mode m3 can be expressed as the following equation (7).
Average of DC voltage of switching period T = {(b−c) × T × (1 + a) + (− a + c) × T × (1−b) + (− a + b) × T × (−a + b−1)} / T
= A ² + b ² −c (a + b) (7)
Here, considering a + b + c = 0 (three-phase condition), the equation (7) can be transformed into the following equation (8).
Average of DC voltage of switching period T = a ² + b ² + c ² (8)
Furthermore, from AC theory, from a ² + b ² + c ² = 3/2, Equation (8) can be transformed into the following Equation (9).
Average of DC voltage of switching period T = 3/2 (9)
As shown in Expression (9), the average of the virtual DC voltage in the switching period T can be a constant voltage.

  The input current in mode m3 will be described. A positive current proportional to the time of the S phase voltage b flows through the S phase of the maximum voltage phase. A negative current proportional to the time of the R phase voltage a flows in the R phase of the minimum voltage phase. In the T phase, a negative current flows in the line voltage generation section TS31, and a positive current flows in the line voltage generation section TS32. For this reason, the flowing current is T × (1−b) −T × (1 + a) = Tc, and when it is divided by the switching period T, it becomes the T phase voltage c. Therefore, a current proportional to the voltage flows in each phase, and each phase of the input AC current can be a sine wave.

[Modes m4 to m6]
The virtual AC / DC conversion process in mode m4 is the same as the virtual AC / DC conversion process (see FIG. 5) in mode m1, as shown in FIG. The line voltage generation sections TS41, TS42, TS43 are also obtained in the same manner as in the mode m1. In the line voltage generation sections TS41, TS42, and TS43, the T phase, the T phase, and the S phase are positive side phases, and the S phase, the R phase, and the R phase are negative side phases, respectively.

  The virtual AC / DC conversion process in mode m5 is the same as the virtual AC / DC conversion process (see FIG. 6) in mode m2, as shown in FIG. The line voltage generation sections TS51, TS52, TS53 are also obtained in the same manner as in the mode m2. In the line voltage generation sections TS51, TS52, and TS53, the T phase, the T phase, and the R phase are the + side phases, and the S phase, the R phase, and the S phase are the − side phases, respectively.

  The virtual AC / DC conversion process in mode m6 is the same as the virtual AC / DC conversion process (see FIG. 7) in mode m3, as shown in FIG. The line voltage generation sections TS61, TS62, and TS63 are also obtained in the same manner as in the mode m3. In the line voltage generation sections TS61, TS62, and TS63, the T phase, the R phase, and the R phase are positive side phases, and the S phase, the T phase, and the S phase are negative side phases, respectively.

(Specific virtual DC / DC conversion processing)
Next, virtual DC / DC conversion processing in each of the plurality of modes m1 to m6 will be described with reference to FIGS. First, as shown in FIGS. 5E and 5F to FIGS. 10E and 10F, the second carrier waveform pattern generation unit 24 corresponds to the modes m1 to m6 and outputs the second carrier. A waveform pattern CW2 (CW21 to CW26) is generated. Second carrier waveform pattern CW2 is determined so as to have a pattern in which the level changes in a mountain shape across two continuous line voltage generation sections among a plurality of line voltage generation sections φTS. In addition, the second carrier waveform pattern CW2 extends over two line voltage generation sections to be switched when there are phases common to the + side phase or the − side phase when the plurality of line voltage generation sections φTS are switched. When the line voltage generation section φTS is switched and there is a phase that reverses between the + side phase and the − side phase when the line voltage generation section φTS switches, two line voltage generations that switch It is determined so as to have a pattern in which the level changes in a sawtooth shape at the boundary of the section φTS.

[Mode m1]
As shown in FIGS. 5 (e) and 5 (f), in the mode m1, the second carrier waveform pattern generation unit 24 uses the second carrier waveform pattern CW 2 to be used for the virtual DC / DC conversion process as a line-to-line A second carrier waveform pattern CW21 having a rising sawtooth wave, a falling sawtooth wave, and a rising sawtooth wave in the order of the voltage generation sections TS11, TS12, and TS13 is determined.

[Switching of bidirectional switches SRP, SSP, STP]
The P-phase comparator CP compares the second carrier waveform pattern CW21 with the P-phase signal level G1. The switch control unit 28 controls switching of the bidirectional switches SRP, SSP, and STP connected to the P phase based on the comparison result of the P phase comparator CP. The switching of the bidirectional switches SRP, SSP, and STP is equivalent to PWM control of the R-phase pulse, S-phase pulse, and T-phase pulse with respect to the P-phase voltage. As shown in FIG. 5E, the switch control unit 28, when the comparison result of the P-phase comparator CP is higher than the second carrier waveform pattern CW21 in the line voltage generation period TS11. During the period from t1 to t12, the + side phase, that is, the S phase is selected, the switching signal φSSP is set to the ON level, and the other switching signals φSRP and φSTP connected to the P phase are set to the OFF level. On the other hand, in the line voltage generation section TS11, the switch control unit 28 determines that the comparison result of the P-phase comparator CP is between the time points t12 and t13 when the P-phase signal level G1 is lower than the second carrier waveform pattern CW21. The phase, that is, the T phase is selected, the switching signal φSTP is turned on, and the other switching signals φSRP and φSSP connected to the P phase are turned off.

  Similarly, in the line voltage generation section TS12, the switch control unit 28, when the comparison result of the P-phase comparator CP shows that the P-phase signal level G1 is higher than the second carrier waveform pattern CW21, the + side phase, that is, R The phase is selected, the switching signal φSRP is turned on, and the other switching signals φSSP and φSTP connected to the P phase are turned off. On the other hand, when the comparison result of the P-phase comparator CP is lower than the second carrier waveform pattern CW21 in the line voltage generation section TS12, the switch control unit 28 sets the negative side phase, that is, the T phase. Then, the switching signal φSTP is set to the ON level and the other switching signals φSRP and φSSP connected to the P phase are set to the OFF level.

  Further, in the line voltage generation section TS13, the switch control unit 28 sets the + side phase, that is, the R phase, when the comparison result of the P phase comparator CP is higher than the second carrier waveform pattern CW21 in the P phase signal level G1. The switching signal φSRP is set to ON level, and the other switching signals φSSP and φSTP connected to the P phase are set to OFF level. On the other hand, when the comparison result of the P-phase comparator CP is lower than the second carrier waveform pattern CW21 in the line voltage generation section TS13, the switch control unit 28 sets the negative side phase, that is, the S phase. Then, the switching signal φSSP is turned on and the other switching signals φSRP and φSTP connected to the P phase are turned off.

[Switching of bidirectional switches SRN, SSN, STN]
On the other hand, the N-phase comparator CN compares the second carrier waveform pattern CW21 with the N-phase signal level G2. The switch control unit 28 controls switching of the bidirectional switches SRN, SSN, and STN connected to the N phase based on the comparison result of the N phase comparator CN. The switching of the bidirectional switches SRN, SSN, and STN is equivalent to PWM control of the R-phase pulse, the S-phase pulse, and the T-phase pulse with respect to the N-phase voltage, respectively. As shown in FIG. 5 (f), the switch control unit 28, when the comparison result of the N-phase comparator CN is higher than the second carrier waveform pattern CW21 in the line voltage generation section TS11. During the period from t1 to t11, the + side phase, that is, the S phase is selected, the switching signal φSSN is set to the ON level, and the other switching signals φSRN and φSTN connected to the N phase are set to the OFF level. On the other hand, in the line voltage generation section TS11, the switch control unit 28 indicates that the comparison result of the N-phase comparator CN is between the time points t11 to t13 when the N-phase signal level G2 is lower than the second carrier waveform pattern CW21. The phase, that is, the T phase is selected, the switching signal φSTN is turned on, and the other switching signals φSRN and φSSN connected to the N phase are turned off.

  Similarly, in the line voltage generation section TS12, the switch control unit 28 determines that the comparison result of the N-phase comparator CN is greater than the second carrier waveform pattern CW21 and the N-phase signal level G2 is + side phase, that is, R The phase is selected, the switching signal φSRN is turned on, and the other switching signals φSSN and φSTN connected to the N phase are turned off. On the other hand, when the comparison result of the N-phase comparator CN is lower than the second carrier waveform pattern CW21 in the line voltage generation section TS12, the switch control unit 28 sets the negative side phase, that is, the T phase. The switching signal φSTN is set to ON level, and other switching signals φSRN and φSSN connected to the N phase are set to OFF level.

  Further, in the line voltage generation section TS13, the switch control unit 28 sets the + side phase, that is, the R phase, when the comparison result of the N phase comparator CN indicates that the N phase signal level G2 is higher than the second carrier waveform pattern CW21. The switching signal φSRN is turned on and the other switching signals φSSN and φSTN connected to the N phase are turned off. On the other hand, when the comparison result of the N-phase comparator CN is lower than the second carrier waveform pattern CW21 in the line voltage generation section TS13, the switch control unit 28 sets the negative side phase, that is, the S phase. The switching signal φSSN is set to ON level, and other switching signals φSRN and φSTN connected to the N phase are set to OFF level.

  Note that the switching of the bidirectional switches SRP, SSP, STP, SRN, SSN, and STN by the switch control unit 28 described above is actual switching control.

[Average DC voltage of PN line voltage]
Here, the pulse width of the switching signal φSRP is hx obtained by reducing the pulse width x of the R-phase pulse (see FIG. 5B) in proportion to the P-phase signal level G1 (signal level h). Further, the pulse width of the switching signal φSSP is hy obtained by reducing the pulse width y of the S-phase pulse (see FIG. 5B) in proportion to the P-phase signal level G1 (signal level h). The pulse width of the switching signal φSTP is hz obtained by reducing the pulse width z of the T-phase pulse (see FIG. 5B) in proportion to the P-phase signal level G1 (signal level h).

In addition, since the switching signals φSRP, φSSP, and φSTP are alternatively turned on, the R phase voltage a, the S phase voltage b, and T are respectively applied during the period of the pulse width of each switching signal φSRP, φSSP, and φSTP. A phase voltage c is generated. The average DC voltage Vave of the switching period T can be expressed as the following expression (10) by accumulating the voltages for each period, adding them, and dividing by the switching period T.
Average of P-phase output voltage in switching period T = {a (hx) + b (hy) + c (hz)} / T
= H (ax + by + cz) / T (10)
From the above, since the R-phase pulse width x = T | a |, the S-phase pulse width y = T | b |, and the T-phase pulse width z = T | c | 11).
Average P-phase output voltage in switching period T = h (a ² + b ² + c ² ) (11)
Furthermore, from AC theory, from a ² + b ² + c ² = 3/2, equation (11) can be transformed into the following equation (12).
Average P-phase output voltage of switching period T = h × 3/2 (12)

  Similarly, the pulse width of the switching signal φSRN is the absolute value of −hx obtained by reducing the pulse width x of the R-phase pulse (see FIG. 5B) in proportion to the signal level −h of the N-phase control signal RWb. It becomes. The pulse width of the switching signal φSSN is an absolute value of −hy obtained by reducing the pulse width y of the S-phase pulse (see FIG. 5B) in proportion to the signal level −h of the N-phase control signal RWb. . Further, the pulse width of the switching signal φSTN is an absolute value of −hz obtained by reducing the pulse width z of the T-phase pulse (see FIG. 5B) in proportion to the signal level −h of the N-phase control signal RWb. .

Therefore, the average of the N-phase output voltage in the switching period T can be expressed by the following equation (13).
Average of N-phase output voltage of switching period T = {a (−hx) + b (−hy) + c (−hz)} / T
= -H (ax + by + cz) / T (13)
From the above, since the R-phase pulse width x = T | a |, the S-phase pulse width y = T | b |, and the T-phase pulse width z = T | c | ).
Average N-phase output voltage of switching period T = −h (a ² + b ² + c ² ) (14)
Furthermore, from AC theory, from a ² + b ² + c ² = 3/2, equation (14) can be transformed into the following equation (15).
Average of N-phase output voltage of switching period T = −h × 3/2 (15)

  As a result, the average of the P-phase output voltage and the average of the N-phase output voltage in the switching period T are both proportional to the signal levels h and -h. Note that the PN line voltage in the switching period T (t1 to t2) has a signal pattern obtained by subtracting the switching signals φSRN, φSSN, and φSTN from the switching signals φSRP, φSSP, and φSTP, as shown in FIG.

The average of the PN line voltage between the P phase and the N phase can be expressed by the following equation (16) by subtracting the value of equation (15) from the value of equation (12).
Average DC voltage of PN line voltage Vave = h × 3/2 − (− h × 3/2)
= H x 3 (16)
Therefore, the average DC voltage Vave of the PN line voltage is proportional to the signal level h.

  As shown in FIG. 5, in the switching cycle T described above, the P-phase signal level G1 is + h and the N-phase signal level G2 is -h. It may be set to 0.

[Modes m2 to m6]
In the mode m2, as shown in FIGS. 6 (e) and 6 (f), the second carrier waveform pattern generation unit 24 uses the line voltage as the second carrier waveform pattern CW2 to be used for the virtual DC / DC conversion processing. A second carrier waveform pattern CW22 having a rising sawtooth wave, a falling sawtooth wave, and a falling sawtooth wave is determined in the order of the generation sections TS21, TS22, and TS23.

  In the mode m2, as in the mode m1, the P-phase comparator CP compares the second carrier waveform pattern CW22 with the P-phase signal level G1, as shown in FIG. 6 (e). Then, as shown in FIG. 6G, the switch control unit 28 controls switching of the bidirectional switches SRP, SSP, and STP connected to the P phase based on the comparison result of the P phase comparator CP. Further, as shown in FIG. 6F, the N-phase comparator CN compares the second carrier waveform pattern CW22 with the N-phase signal level G2. Then, as shown in FIG. 6G, the switch control unit 28 controls switching of the bidirectional switches SRN, SSN, and STN connected to the N phase based on the comparison result of the N phase comparator CN. As a result, as shown in FIG. 6H, a PN line voltage in the mode m2 is generated. In addition, the average DC voltage Vave of the PN line voltage in each switching period T is proportional to the signal levels h and -h. Furthermore, as described above, the current direction and the current value of the P phase are determined based on the magnitude relationship between the average DC voltage Vave and the PN phase voltage Vb. For example, when the average DC voltage Vave when the signal level G1 is 0.5 and the signal level G2 is −0.5 is the same value as the PN phase voltage Vb, the signal level G1 is set larger than 0.5, and the signal level By making G2 smaller than −0.5, the average DC voltage Vave exceeds the PN phase voltage Vb. At this time, a current flows from the three-phase AC power supply PS side to the storage battery LD side.

In the mode m3, as shown in FIGS. 7E and 7F, the second carrier waveform pattern generation unit 24 uses the line voltage as the second carrier waveform pattern CW2 to be used for the virtual DC / DC conversion processing. A second carrier waveform pattern CW23 having a rising sawtooth wave, a rising sawtooth wave, and a falling sawtooth wave is sequentially determined in the generation sections TS31, TS32, and TS33.

  In the mode m3, as in the mode m1, the P-phase comparator CP compares the second carrier waveform pattern CW23 with the P-phase signal level G1, as shown in FIG. 7 (e). Then, as shown in FIG. 7G, the switch control unit 28 controls switching of the bidirectional switches SRP, SSP, and STP connected to the P phase based on the comparison result of the P phase comparator CP. Further, as shown in FIG. 7F, the N-phase comparator CN compares the second carrier waveform pattern CW23 and the N-phase signal level G2. Then, as illustrated in FIG. 7G, the switch control unit 28 controls switching of the bidirectional switches SRN, SSN, and STN connected to the N phase based on the comparison result of the N phase comparator CN. As a result, as shown in FIG. 7H, a PN line voltage in the mode m3 is generated. In addition, the average DC voltage Vave of the PN line voltage in each switching period T is proportional to the signal levels h and -h. Furthermore, as described above, the current direction and the current value of the P phase are determined based on the magnitude relationship between the average DC voltage Vave and the PN phase voltage Vb.

In the mode m4, as shown in FIGS. 8E and 8F, the second carrier waveform pattern generation unit 24 uses the line voltage as the second carrier waveform pattern CW2 to be used for the virtual DC / DC conversion processing. A second carrier waveform pattern CW24 having a falling sawtooth wave, a rising sawtooth wave, and a falling sawtooth wave is sequentially determined in the generation sections TS41, TS42, and TS43.

  In the mode m4, as in the mode m1, the P-phase comparator CP compares the second carrier waveform pattern CW24 with the P-phase signal level G1, as shown in FIG. 8 (e). Then, as shown in FIG. 8G, the switch control unit 28 controls switching of the bidirectional switches SRP, SSP, and STP connected to the P phase based on the comparison result of the P phase comparator CP. Further, the N-phase comparator CN compares the second carrier waveform pattern CW24 with the N-phase signal level G2 as shown in FIG. Then, as shown in FIG. 8G, the switch control unit 28 controls switching of the bidirectional switches SRN, SSN, and STN connected to the N phase based on the comparison result of the N phase comparator CN. As a result, as shown in FIG. 8H, a PN line voltage in the mode m4 is generated. In addition, the average DC voltage Vave of the PN line voltage in each switching period T is proportional to the signal levels h and -h. Furthermore, as described above, the current direction and the current value of the P phase are determined based on the magnitude relationship between the average DC voltage Vave and the PN phase voltage Vb.

In the mode m5, as shown in FIGS. 9E and 9F, the second carrier waveform pattern generation unit 24 uses the line voltage as the second carrier waveform pattern CW2 to be used for the virtual DC / DC conversion processing. A second carrier waveform pattern CW25 having a falling sawtooth wave, a rising sawtooth wave, and a rising sawtooth wave is sequentially determined in the generation sections TS51, TS52, and TS53.

  In the mode m5, as in the mode m1, the P-phase comparator CP compares the second carrier waveform pattern CW25 with the P-phase signal level G1, as shown in FIG. 9 (e). Then, as shown in FIG. 9G, the switch control unit 28 controls switching of the bidirectional switches SRP, SSP, and STP connected to the P phase based on the comparison result of the P phase comparator CP. The N-phase comparator CN compares the second carrier waveform pattern CW25 with the N-phase signal level G as shown in FIG. Then, as shown in FIG. 9G, the switch control unit 28 controls switching of the bidirectional switches SRN, SSN, and STN connected to the N phase based on the comparison result of the N phase comparator CN. As a result, as shown in FIG. 9H, the PN line voltage in the mode m5 is generated. In addition, the average DC voltage Vave of the PN line voltage in each switching period T is proportional to the signal levels h and -h. Furthermore, as described above, the current direction and the current value of the P phase are determined based on the magnitude relationship between the average DC voltage Vave and the PN phase voltage Vb.

In the mode m6, as shown in FIGS. 10E and 10F, the second carrier waveform pattern generation unit 24 uses the line voltage as the second carrier waveform pattern CW2 to be used for the virtual DC / DC conversion processing. A second carrier waveform pattern CW26 having a falling sawtooth wave, a falling sawtooth wave, and a rising sawtooth wave is sequentially determined in the generation sections TS61, TS62, and TS63.

  In the mode m6, as in the mode m1, the P-phase comparator CP compares the second carrier waveform pattern CW26 with the P-phase signal level G1, as shown in FIG. Then, as shown in FIG. 10G, the switch control unit 28 controls switching of the bidirectional switches SRP, SSP, and STP connected to the P phase based on the comparison result of the P phase comparator CP. Further, as shown in FIG. 10F, the N-phase comparator CN compares the second carrier waveform pattern CW26 with the N-phase signal level G2. Then, as shown in FIG. 10G, the switch control unit 28 controls switching of the bidirectional switches SRN, SSN, and STN connected to the N phase based on the comparison result of the N phase comparator CN. As a result, as shown in FIG. 10H, the PN line voltage in the mode m6 is generated. In addition, the average DC voltage Vave of the PN line voltage in each switching period T is proportional to the signal levels h and -h. Furthermore, as described above, the current direction and the current value of the P phase are determined based on the magnitude relationship between the average DC voltage Vave and the PN phase voltage Vb.

  As a result, as shown in FIG. 3, the DC / AC grid interconnection device 1 has the signal levels G1, G1 so that the current setting values (current direction F / B and current value A) indicated by the current setting unit 50 are obtained. The value of G2 is adjusted, and the current direction and current value of the P phase are controlled based on the magnitude relationship between the average DC voltage Vave and the PN phase voltage Vb. That is, when the current direction is F, three-phase AC power is supplied to the storage battery LD side with the power amount A, and when the current direction B is, the DC power of the storage battery LD is three-phase with the power amount A. Supplied to the AC power supply PS side.

  1 inputs only the current direction into the switch control unit 28. This is because the control unit 20 needs to have a switching order corresponding to the current direction.

  In the above-described embodiment, the switching signals φSRP, φSSP, and φSTP are modulated by the second carrier waveform pattern CW2. By this modulation, switching for the R phase, the S phase, and the T phase is sequentially performed in the R phase. → S phase → T phase → R phase, etc. Since the modulation is performed so as to be connected in an orderly manner without overlapping in a predetermined order, the commutation failure can be suppressed. In addition, switching of the switching signals φSRN, φSSN, and φSTN is similarly modulated in an orderly manner, so that commutation failures can be suppressed.

  The pulse widths of the switching signals φSRP, φSSP, φSTP, φSRN, φSSN, and φSTN are preferably larger than the cycle of the switching frequency limit of the bidirectional switch group SW. Thereby, since the pulse width is ensured longer than the switching time limit of the bidirectional switch group SW, the commutation failure can be suppressed.

(Suppression of switching frequency)
Here, suppression of the switching frequency of the bidirectional switch group SW within the switching period T will be described. In the virtual DC / DC conversion processing, three types of input-side pulses (R-phase pulse, S-phase pulse, and T-phase pulse) are divided into three types of line voltage generation intervals between one carrier waveform pattern (switching period T). Each φTS modulates to each phase (P phase, N phase) on the output side.

  If one carrier waveform pattern is configured with the same triangular wave for each of the three types of line voltage generation sections φTS, three switching times are required for each switching period T for the bidirectional switches SRP to STN.

  On the other hand, in the present embodiment, as shown in FIGS. 5 to 10, when the selection of each input voltage phase (+ side phase, − side phase) is viewed, the R phase, S phase, and T phase are 1 Two carrier waveform patterns appear overlapping. That is, each of the plurality of second carrier waveform patterns CW21 to CW26 shown in (e) and (f) of FIG. 5 to FIG. 10 is a mountain spanning two consecutive sections among the plurality of line voltage generation sections. The pattern has a pattern whose level changes. Each mode m1 to m6 includes a plurality of switching periods T.

  For example, as shown in FIGS. 5E and 5F, the second carrier waveform pattern CW21 has a pattern in which the level changes in a mountain shape on the upper side across the line voltage generation sections TS11 and TS12. It has a pattern in which the level changes in a mountain shape on the lower side across the line voltage generation sections TS12 and TS13.

  Further, as shown in FIGS. 6E and 6F, the second carrier waveform pattern CW22 has a pattern in which the level changes in a mountain shape on the upper side across the line voltage generation sections TS21 and TS22. It has a pattern in which the level changes in a mountain shape on the lower side across the line voltage generation sections TS23 and TS21.

  Further, as shown in FIGS. 7E and 7F, the second carrier waveform pattern CW23 has a pattern in which the level changes in a mountain shape on the upper side across the line voltage generation sections TS32 and TS33, It has a pattern in which the level changes in a mountain shape on the lower side across the line voltage generation sections TS33 and TS31.

  Further, as shown in FIGS. 8E and 8F, the second carrier waveform pattern CW24 has a pattern in which the level changes in a mountain shape on the upper side across the line voltage generation sections TS42 and TS43, It has a pattern in which the level changes in a mountain shape on the lower side across the line voltage generation section TS41 and section TS42.

  Further, as shown in FIGS. 9E and 9F, the second carrier waveform pattern CW25 has a pattern in which the level changes in a mountain shape on the upper side across the line voltage generation sections TS53 and TS51. It has a pattern in which the level changes in a mountain shape on the lower side across the line voltage generation sections TS51 and TS52.

  As shown in FIGS. 10E and 10F, the second carrier waveform pattern CW26 has a pattern in which the level changes in a mountain shape on the upper side across the line voltage generation sections TS63 and TS61. It has a pattern in which the level changes in a mountain shape on the lower side across the line voltage generation sections TS62 and TS63.

  More specifically, each of the second carrier waveform patterns CW21 to CW26 is a voltage having a small voltage value with a voltage phase having a large voltage value as a + side phase of two voltage phases in each of the plurality of line voltage generation sections. When the phase is set to the-side phase, if there is a phase common to the + side phase or the-side phase when the line voltage generation section is switched, the level is mountain-shaped across the two line voltage generation sections to be switched Has a continuous pattern, and when there is a phase that reverses between the + side phase and the − side phase when the line voltage generation section switches, it is serrated at the boundary between the two line voltage generation sections that switch Have a pattern whose level changes.

  For example, since the second carrier waveform pattern CW21 has a T phase common to the -side phase for the line voltage generation sections TS11 and TS12, the level is mountain-shaped on the upper side across the line voltage generation sections TS11 and TS12. It has a changing pattern. Since the second carrier waveform pattern CW21 has an R phase common to the + side phase for the line voltage generation sections TS12 and TS13, the level changes in a mountain shape on the lower side across the line voltage generation sections TS12 and TS13. Pattern. Since the second carrier waveform pattern CW21 has an S phase that is inverted between the + side phase and the − side phase for the line voltage generation sections TS13 and TS11, the second carrier waveform pattern CW21 has a sawtooth shape at the boundary between the line voltage generation sections TS13 and TS11. Have a pattern whose level changes.

  In addition, since the second carrier waveform pattern CW22 has a T-phase common to the -side phase with respect to the line voltage generation sections TS21 and TS22, the level is mountain-shaped on the upper side across the line voltage generation sections TS21 and TS22. It has a changing pattern. Since the second carrier waveform pattern CW22 has an R phase that is inverted between the + side phase and the − side phase with respect to the line voltage generation sections TS22 and TS23, the second carrier waveform pattern CW22 is serrated at the boundary between the line voltage generation sections TS22 and TS23. Have a pattern whose level changes. Since the second carrier waveform pattern CW22 has an S phase common to the + side phase for the line voltage generation sections TS23 and TS21, the level changes in a mountain shape on the lower side across the line voltage generation sections TS23 and TS21. Pattern.

  Further, since the second carrier waveform pattern CW23 has a T phase that is inverted between the + side phase and the − side phase for the line voltage generation sections TS31 and TS32, at the boundary between the line voltage generation sections TS31 and TS32. It has a pattern whose level changes like a sawtooth. Since the second carrier waveform pattern CW23 has an R phase common to the -side phase with respect to the line voltage generation sections TS32 and TS33, the level changes in a mountain shape on the upper side across the line voltage generation sections TS32 and TS33. Has a pattern. Since the second carrier waveform pattern CW23 has an S phase common to the + side phase for the line voltage generation sections TS33 and TS31, the level changes in a mountain shape on the lower side across the line voltage generation sections TS33 and TS31. Pattern.

  In addition, since the second carrier waveform pattern CW24 has a T phase common to the + side phase for the line voltage generation sections TS41 and TS42, the second carrier waveform pattern CW24 has a mountain-shaped level on the lower side across the line voltage generation sections TS41 and TS42. Has a changing pattern. Since the second carrier waveform pattern CW24 has an R phase common to the -side phase for the line voltage generation sections TS42 and TS43, the level changes in a mountain shape on the upper side across the line voltage generation sections TS42 and TS43. Has a pattern. Since the second carrier waveform pattern CW24 has an S phase that is inverted between the + side phase and the − side phase for the line voltage generation sections TS43 and TS41, the second carrier waveform pattern CW24 has a sawtooth shape at the boundary between the line voltage generation sections TS43 and TS41. Have a pattern whose level changes.

  In addition, since the second carrier waveform pattern CW25 has a T phase common to the + side phase for the line voltage generation sections TS51 and TS52, the second carrier waveform pattern CW25 has a mountain-shaped level on the lower side across the line voltage generation sections TS51 and TS52. Has a changing pattern. Since the second carrier waveform pattern CW25 has an R phase that is inverted between the + side phase and the − side phase for the line voltage generation sections TS52 and TS53, the second carrier waveform pattern CW25 has a sawtooth shape at the boundary between the line voltage generation sections TS52 and TS53. Have a pattern whose level changes. In the second carrier waveform pattern CW25, there is an S phase common to the -side phase with respect to the line voltage generation sections TS53 and TS51. Therefore, the level changes in a mountain shape on the upper side across the line voltage generation sections TS53 and TS51. Has a pattern.

  In addition, since the second carrier waveform pattern CW26 has a T phase that is inverted between the + side phase and the − side phase for the line voltage generation sections TS61 and TS62, at the boundary between the line voltage generation sections TS61 and TS62. It has a pattern whose level changes like a sawtooth. Since the second carrier waveform pattern CW26 has an R phase common to the + side phase for the line voltage generation sections TS62 and TS63, the level changes in a mountain shape on the lower side across the line voltage generation sections TS62 and TS63. Pattern. Since the second carrier waveform pattern CW26 has the S phase common to the -side phase for the line voltage generation sections TS63 and TS61, the level changes in a mountain shape on the upper side across the line voltage generation sections TS63 and TS61. Has a pattern.

  Further, each of the second carrier waveform patterns CW21 to CW26 includes a voltage phase having a high level as a + side phase and a voltage phase having a low level as a − side phase among two voltage phases in each of the plurality of line voltage generation sections. When there is a phase that is common to the + side phase or the − side phase when the mode is switched, it has a pattern in which the levels are continuous in a mountain shape across the two modes that are switched, and when the mode is switched When there is a phase that is inverted between the + side phase and the − side phase, it has a pattern in which the level changes in a sawtooth shape at the boundary between the two modes to be switched.

  For example, when the mode m1 is switched to the mode m2, there is an S phase that is inverted between the + side phase and the − side phase for the line voltage generation sections TS13 and TS21, and therefore the line voltage generation sections TS13 and TS21 It has a pattern whose level changes in a sawtooth shape at the boundary.

  Further, when the mode m2 is switched to the mode m3, since there is an S phase common to the + side phase for the line voltage generation sections TS23 and TS31, a mountain shape is formed on the lower side across the line voltage generation sections TS23 and TS31. Have a pattern whose level changes.

  Further, when the mode m3 is switched to the mode m4, there is an S phase that is inverted between the + side phase and the − side phase for the line voltage generation sections TS33 and TS41, so that the line voltage generation sections TS33 and TS41 It has a pattern whose level changes in a sawtooth shape at the boundary.

  Further, when the mode m4 is switched to the mode m5, there is an S phase that is inverted between the + side phase and the − side phase for the line voltage generation sections TS43 and TS51, so that the line voltage generation sections TS43 and TS51 It has a pattern whose level changes in a sawtooth shape at the boundary.

  In addition, when switching from mode m5 to mode m6, there is an S phase common to the -side phase for the line voltage generation sections TS53 and TS61, so that a mountain shape is formed on the upper side across the line voltage generation sections TS53 and TS61. It has a pattern whose level changes.

  In this way, by combining the rising and falling sawtooth waves to form one carrier waveform pattern (second carrier waveform pattern CW2), each phase is selected once in each switching period T. Can be. That is, the maximum voltage phase is always the + side phase, and the minimum voltage phase is always the-side phase. The intermediate voltage phase is a negative side phase for the maximum voltage phase and a positive side phase for the minimum voltage phase. The + side phase selects a period during which the second control signal (eg, P phase control signal RWa) is larger than the second carrier waveform pattern CW2, and the − side phase is the second control signal (eg, P phase). A period in which the control signal RWa) is smaller than the second carrier waveform pattern CW2 is selected. In this case, if the falling sawtooth wave and the rising sawtooth wave are made continuous so as to form a mountain shape on the lower side, the maximum voltage phase can be selected only once. Further, if the rising sawtooth wave and the falling sawtooth wave are made continuous so as to form a mountain shape on the upper side, the minimum voltage phase can be selected only once. Thereby, in each mode, it is possible to realize one switching frequency for each switching period T for each bidirectional switch SRP to STN. Further, even when the mode is switched, substantially one switching frequency can be realized for each switching period T for each of the bidirectional switches SRP to STN. In other words, the same control can be realized by switching within each mode and switching between modes, so that fluctuations in output voltage (fluctuation due to dead time, etc.) caused by intermittent switching can be reduced, and the shock at the time of switching Can be reduced.

  Further, since the switching signals φSRP to φSTP of the bidirectional switches SRP to STP can be maintained at the ON level across a plurality of line voltage generation sections, as shown in FIG. A wide pulse width of the switching signals φSRP to φSTP of SRP to STP can be secured. The same applies to the switching signals φSRN to φSTN of the bidirectional switches SRN to STN. That is, since the pulse width can be ensured larger than the dead time even at low load, the distortion rate of the waveform at low load can be suppressed to the same level as at high load.

  In the virtual AC / DC conversion processing in the above-described embodiment, the average of the output voltage in each switching period T is always constant. Further, the direct current is distributed to the input current in a ratio of the input voltage. Further, when the output power is constant, this input current becomes a three-phase AC waveform (for example, a sine wave).

That is,
1) The input current in the virtual AC / DC conversion process can be a three-phase AC waveform (for example, a sine wave) when the output power by the virtual DC / DC conversion process is constant. Usually, the power is constant for a short time (about 0.1 second).
2) The output voltage obtained by the virtual DC / DC conversion process can be obtained as a signal similar to the modulation signal (second control signal).

(Experimental result)
FIG. 11 is a timing chart showing changes in current and voltage of each part in the current direction F, that is, when power is supplied from the three-phase AC power supply PS side to the storage battery LD side. FIG. 11A shows the R-phase voltage VR. The system phase voltage is 115V in effective value. The current IR indicates the R-phase current IR. As described above, the average DC voltage Vave shown in FIG. 11C is an average voltage of the switching period T shown in FIG. 5H, for example. This average DC voltage Vave substantially corresponds to a DC voltage of 85 V, and is larger than the PN phase voltage Vb (= 80 V) on the storage battery LD side shown in FIG. And as shown in FIG.11 (d), the electric current Ib which flows into the storage battery LD side is 25A.

  On the other hand, FIG. 12 is a timing chart showing changes in the current and voltage of each part in the current direction B, that is, when power is supplied from the storage battery LD side to the three-phase AC power supply PS side. FIG. 12A shows the R-phase voltage VR. The system phase voltage is 115V. The current IR indicates the R-phase current IR. As described above, the average DC voltage Vave shown in FIG. 12C is, for example, the average voltage of the switching period T shown in FIG. This average DC voltage Vave substantially corresponds to a DC voltage of 75 V, and is smaller than the PN phase voltage Vb (= 80 V) on the storage battery LD side shown in FIG. And as shown in FIG.12 (d), the electric current Ib which flows into the three-phase alternating current power supply PS side from the storage battery LD side is -25A in consideration of an electric current direction. The current IR is out of phase with respect to the voltage VR and is negative power.

  In this embodiment, the DC / AC conversion can be performed without increasing the DC voltage on the storage battery LD side above the system voltage, so that a boost chopper is not required. In the above-described embodiment, three reactors are conventionally provided for each phase on the three-phase AC power side. However, since the input / output three-phase AC is a sine wave, these three reactors are not required, and the storage battery It is only necessary to provide one reactor 30 arranged on the LD side. Further, in the above-described embodiment, charging / discharging of the storage battery LD can be easily performed only by setting and controlling the magnitudes of the PN interphase voltage Vb and the average DC voltage Vave.

Further, in the above-described embodiment, the control unit 20 has a plurality of modes m1 divided according to the magnitude relationship of the voltage of each phase in the input three-phase AC power with respect to the input three-phase AC power. Different virtual AC / DC conversion processes are performed according to ~ m6, and different virtual DC / DC conversion processes are performed according to a plurality of modes m1 to m6 with respect to the power subjected to the virtual AC / DC conversion process. The switching pattern of the bidirectional switch circuit 10 is generated. Specifically, the control unit 20 performs a virtual AC / DC conversion process on the input three-phase AC power using the first carrier waveform patterns CW11 to CW13 that differ depending on the plurality of modes m1 to m6. The virtual DC / DC conversion processing is performed using the second carrier waveform patterns CW21 to CW26 that differ depending on the plurality of modes m1 to m6, for the power that has been subjected to the virtual AC / DC conversion processing. A switching pattern of the bidirectional switch circuit 10 is generated. Thereby, the power conversion between the three-phase AC power and the DC power can be directly and directly performed by a simple process without performing a complicated calculation such as a matrix calculation.

In the above-described embodiment, the control unit 20 corresponds to the first carrier waveform patterns CW11 to CW13 and the input-side phases (R phase, S phase, T phase) in each of the plurality of modes m1 to m6. First control signals (for example, voltage | a |, voltage | c |, voltage (| b | + | c | -1), voltage (| a | + shown in FIG. | B | -1)) to obtain a plurality of line voltage generation sections TS11 to TS63. Then, the control unit 20 generates the second carrier waveform patterns CW21 to CW26 corresponding to the plurality of line voltage generation sections TS11 to TS63, and the generated second carrier waveform patterns CW21 to CW26 and the phase on the output side Second control signals corresponding to (P-phase, N-phase) (for example, P-phase signal level G1 and N-phase signal level G2 shown in FIGS. 5 to 10 (e) and (f)). In comparison, the switching pattern of the bidirectional switch circuit 10 is generated. Thereby, the virtual AC / DC conversion process and the virtual DC / DC conversion process can be easily performed without performing a complicated matrix operation.

  Furthermore, in the above-described embodiment, the control unit 20 recognizes the maximum voltage phase, the minimum voltage phase, and the intermediate voltage phase in the input three-phase AC power. The control unit 20 includes a plurality of line voltage generation sections in one switching cycle T, a first section corresponding to the intermediate voltage phase and the minimum voltage phase, and a second section corresponding to the maximum voltage phase and the minimum voltage phase. And the third section corresponding to the maximum voltage phase and the intermediate voltage phase. The first section includes, for example, line voltage generation sections TS11, TS22, TS32, TS43, TS53, and TS61 shown in FIGS. The second section includes, for example, line voltage generation sections TS12, TS21, TS33, TS42, TS51, and TS63 shown in FIGS. The third section includes, for example, line voltage generation sections TS13, TS23, TS31, TS41, TS52, and TS62 shown in FIGS. Therefore, three kinds of line voltages of maximum-minimum, maximum-intermediate, and intermediate-minimum can be virtually generated in one switching period T, and the virtual line-to-line voltage can be generated using physical phenomena such as current subtraction The virtual DC voltage can be made substantially constant by the voltage, and the second carrier waveform pattern created in each voltage section and the second control signal are compared from the substantially constant virtual DC voltage. Switching signal can be generated. Thus, the first control signal is a sine wave and the second control signal is a direct current, so that the input current of the DC / AC system interconnection device 1 can be easily made a sine wave and the output voltage is a direct current. Can do.

  In the above-described embodiment, the second carrier waveform patterns CW21 to CW26 (see (e) and (f) of FIG. 5 to FIG. 10) are two continuous intervals among a plurality of line voltage generation intervals. It has a pattern in which the level changes in a mountain shape across. Thereby, since the frequency | count of switching in each switching period T can be reduced, the switching loss of each bidirectional | two-way switch SRP-STN in the bidirectional | two-way switch circuit 10 can be reduced.

  Furthermore, in the above-described embodiment, the second carrier waveform patterns CW21 to CW26 (see FIGS. 5 to 10 (e) and (f)) are in two consecutive sections among the plurality of line voltage generation sections. Since it has a pattern in which the level changes across the mountain, the pulse widths of the switching signals φSRP to φSTN of the bidirectional switches SRP to STN in the bidirectional switch circuit 10 can be easily secured. Thereby, the failure of commutation can be reduced. In addition, the power conversion efficiency can be improved.

  In the above-described embodiment, the control unit 20 recognizes the maximum voltage phase, the minimum voltage phase, and the intermediate voltage phase in the input three-phase AC power. The second carrier waveform patterns CW21 to CW26 generated by the control unit 20 include a voltage phase having a high level as a positive side phase of two voltage phases in each of a plurality of line voltage generation sections, and a voltage phase having a low level. -When the mode is switched, when there is a phase common to the + side phase or the-side phase when the mode is switched, it has a pattern in which the level is continuous in a mountain shape across the two modes to be switched, and the mode is When there is a phase that is inverted between the + side phase and the − side phase at the time of switching, it has a pattern in which the level changes in a sawtooth shape at the boundary between the two modes to be switched. Thereby, even when the mode is switched, substantially one switching can be realized for each switching period T for each of the bidirectional switches SRP to STN. In other words, since the same control can be realized by switching between modes and switching between modes, the shock at the time of switching can also be reduced.

  Furthermore, in the above-described embodiment, the zero-cross point of the difference voltage can be obtained from the two-phase intersection of the input AC voltage, and the input AC voltage of each phase can be estimated using this zero-cross point as a synchronization signal. In this case, the DC / AC system interconnection device can be configured more simply than in the case where the input AC voltage of each phase is detected.

DESCRIPTION OF SYMBOLS 1 DC / AC system interconnection apparatus 10 Bidirectional switch circuit 20 Control part 21 Synchronization signal detection part 22 1st carrier waveform pattern generation part 23 Phase information generation part 24 2nd carrier waveform pattern generation part 27 Inverter 28 Switch control Section 30 Reactor 40 Input capacitor 41 to 43 Capacitor 50 Current setting section 51 Current detection section 52 Current adjustment section CP P-phase comparator CN N-phase comparator LD Storage battery PS Three-phase AC power supply G1, G2 Signal level SW Bidirectional switch group SRP, SSP , STP, SRN, SSN, STN bidirectional switch

Claims (6)

A DC / AC system interconnection device capable of directly and directly performing power conversion between three-phase AC power and DC power,
A bidirectional switch circuit provided between a three-phase AC power source and a DC power source, and configured to turn ON / OFF between the three-phase AC power source and the DC power source;
A first carrier waveform pattern having a different pattern for each mode is generated at a predetermined switching period according to a plurality of modes divided according to the magnitude relationship of the voltage of each phase in the three-phase AC power, and the predetermined switching in the first control signal generated based on the voltage of the first carrier waveform pattern and the three-phase AC power each phase in the cycle, a plurality of lines for selecting two phases among the three-phase AC power A second carrier that performs a virtual AC / DC conversion process for obtaining an inter-voltage generation section and is different depending on the plurality of modes corresponding to the plurality of line voltage generation sections obtained by the virtual AC / DC conversion process. A waveform pattern is generated, and for the two-phase line voltage selected in the plurality of line voltage generation intervals, the generated second carrier waveform pattern and the phase of the DC power are paired. And a second control signal, to perform different corresponding to the plurality of mode virtual DC / DC conversion, and a control unit for generating a switching pattern of the bidirectional switch circuit,
A current setting unit for inputting a current setting value indicating a current direction and a current amount of a current flowing between the DC power supply and the bidirectional switch circuit;
A current detection unit that detects a current direction and a current amount of a current flowing between the DC power supply and the bidirectional switch circuit;
A current adjusting unit that generates the second control signal in which the signal level is increased or decreased so that the current direction and the current amount detected by the current detecting unit become the current set value;
A DC / AC system interconnection device comprising: The current adjustment unit is generated by the virtual DC / DC conversion process in the control unit as compared with the interphase voltage of the DC power when the current adjustment unit converts the three-phase AC power into the DC power. Generating the second control signal for increasing the average DC voltage in the predetermined switching period and adjusting the amount of current according to the magnitude of the difference voltage between the interphase voltage of the DC power and the average DC voltage, When converting DC power to the three-phase AC power, the average DC voltage is made smaller than the phase voltage of the DC power, and the difference voltage between the phase voltage of the DC power and the average DC voltage is used. 2. The DC / AC system interconnection apparatus according to claim 1, wherein the second control signal for adjusting a current amount is generated. An inverting unit configured to generate a negative second control signal obtained by inverting the positive second control signal, using the second control signal as a positive second control signal;
The average magnitude of the DC voltage, the DC of claim 2, characterized in that corresponding to the difference between the positive second control signal signal level and the negative signal level of the second control signal / AC system interconnection device.   The control unit recognizes a maximum voltage phase, a minimum voltage phase, and an intermediate voltage phase in the three-phase AC power, and sets the plurality of line voltage generation sections to a first voltage phase corresponding to the intermediate voltage phase and the minimum voltage phase. 4. The method according to any one of claims 1 to 3, characterized in that it is obtained by dividing into a section, a second section corresponding to the maximum voltage phase and the minimum voltage phase, and a third section corresponding to the maximum voltage phase and the intermediate voltage phase. The DC / AC system interconnection device according to any one of the above.   The said 2nd carrier waveform pattern has a pattern from which a level changes like a mountain shape over two continuous areas among these line voltage generation | occurrence | production areas. The DC / AC system interconnection device according to one.   The second carrier waveform pattern is obtained when a voltage phase having a large voltage value is set as a + side phase and a voltage phase having a small voltage value is set as a − side phase among two voltage phases in each of the plurality of line voltage generation sections. When there is a phase common to the + side phase or the − side phase when the line voltage generation interval is switched, a pattern in which the level is continuous in a mountain shape across the two line voltage generation intervals to be switched is provided. When there is a phase that is inverted between the + side phase and the − side phase when the line voltage generation section switches, the level changes in a sawtooth shape at the boundary between the two line voltage generation sections that switch. The direct current / alternating-current system interconnection device according to claim 1, wherein the direct-current / alternating-current system interconnection device has a pattern to perform.