JP6015431B2 - Sampling rate conversion device and program - Google Patents

Description

  The present invention relates to a sampling rate conversion apparatus and program.

  Digital signal processing is widely used in electronic devices such as portable music players and tablet terminals, and some of these electronic devices use a plurality of sampling rates. In this case, it is necessary to convert a signal sampled at a certain sampling rate for other processing that operates at a different sampling rate. For example, when there is processing using a signal at a certain sampling rate and the original sampling rate is higher than that, it is necessary to perform downsampling to reduce the original sampling rate.

  In digital signal processing such as down-sampling or up-sampling, an FIR (finite impulse response) filter is often used as a digital filter.

  In the FIR filter, the input samples pass through a sequence of registers corresponding to the Z-transform representation of the delay element. The operation of the filter is to multiply the newest N sample data by a constant array (tap coefficient) and add all the elements of the obtained array. By changing the weight of the coefficient and the number of taps of the filter, the FIR filter can realize an arbitrary frequency response characteristic. However, the circuit scale and power consumption increase as the number of taps increases.

  Therefore, a polyphase filter has been proposed that realizes necessary filter processing by dividing the FIR filter into several small elements and combining the results obtained from these elements.

  In addition, when processing a digital signal by FIR filtering, the input digital signal is partitioned in the time domain, the FIR filtering unit is partitioned in the time domain, and each of the partitions of the input digital signal is Fourier-transformed, and the filtering unit A technique has also been proposed in which a spectral partition is obtained by performing Fourier transform on each of the partitions and performing convolution in the frequency domain, and by combining the obtained spectral partitions, the entire spectrum is obtained.

JP 2009-141445 A Japanese Patent No. 3636361 US Pat. No. 5,502,747 U.S. Pat. No. 4,992,967 JP 2008-20913 A

  The convolution of the input digital signal and the filter that is partitioned in the frequency domain can be processed more efficiently than the convolution in the time domain, but the processing efficiency decreases as the number of taps still increases. Is inherent.

  FIG. 4 shows a basic configuration of the convolution processing of the partitioned signal in the frequency domain. The input digital signal (number of samples N) is FFT processed by the FFT calculator 10 and supplied to the multiplier 12. The FFT-processed signal is delayed by the delay element 14 and supplied to the multiplier 16, and further delayed by the delay element 18 and supplied to the multiplier 20.

  The filter coefficient 22 is digitized and divided into several partitions in the time domain. In the figure, corresponding to the fact that the input digital signal is divided into three partitions in the time domain, it is similarly divided into three partitions. Each partition of the filter coefficient 22 is subjected to FFT processing by FFT calculators 24, 26, and 28 and supplied to multipliers 12, 16, and 20, respectively.

  The input digital signal computed by the FFT computing unit 10 and the FFT coefficient unit FFT processed by the FFT computing unit 24 are multiplied by the multiplier 12 and supplied to the adder 30. Further, the input digital signal that has been processed by the FFT calculator 10 and delayed by the delay element 14 and the filter coefficient partition that has been FFT processed by the FFT calculator 26 are multiplied by the multiplier 16 and supplied to the adder 30. The Further, the input digital signal that is processed by the FFT calculator 10 and delayed by the delay element 14 and the delay element 18 and the filter coefficient partition that is FFT processed by the FFT calculator 28 are multiplied by the multiplier 20 and added. 30. The adder 30 adds these multiplication results to each other and supplies the result to an inverse FFT calculator (IFFT) 32. The inverse FFT calculator 32 restores the frequency domain signal from the adder 30 to a time domain signal and outputs an output signal (number of samples N).

In normal time-domain convolution, when the filter length is M taps, the calculation amount per sample is O (M) in proportion to the filter length, whereas in the frequency-domain convolution, the calculation amount per sample is Becomes O (2 * log ₂ (M)), and the calculation time can be reduced. Here, O is Landau's O-notation, and O (M) indicates that the processing time of the algorithm is on the order of M. For example, when M = 1024, since 2 * log ₂ (1024) = 20, the calculation time is 1/50.

  FIG. 5 shows a basic configuration of downsampling based on such a convolution process in the frequency domain. In addition to the configuration of FIG. 4, a decimation circuit 34 is added to the preceding stage of the inverse FFT calculator 32. The frequency domain signal from the adder 30 is supplied to the thinning circuit 34, thinned out to a desired number of samples by the thinning circuit 34, and supplied to the inverse FFT calculator 32.

  However, although the convolution process in the frequency domain is faster than the convolution process in the time domain, a method for further shortening the processing time is desired. In particular, the performance when an FFT computing unit is implemented greatly depends on the number of taps of the filter. When the number of taps is at a predetermined value or in the vicinity thereof, the processing speed or performance is highest. It is known that the number of taps decreases, especially when the number of taps increases beyond a predetermined value. When implementing FFT, it is necessary to determine the number of taps considering its performance. However, in the past, there was a problem that this point was not fully considered. Such processing time delay also affects subsequent processing, which may be a cause of lowering user satisfaction with electronic devices such as portable music players and tablet terminals.

  An object of the present invention is to provide a sampling rate conversion apparatus and program capable of converting the sampling rate by reducing the processing time more than before.

  The present invention includes a first signal dividing unit that divides an input digital signal into a plurality of partitions, a signal FFT unit that performs fast Fourier transform on each of the plurality of signal partitions generated by the first signal dividing unit, and the signal FFT. Generated by the first filter dividing unit, a second signal dividing unit that further divides each signal generated by the unit into a plurality of signal partitions, a first filter dividing unit that divides the digital filter into a plurality of partitions, and the first filter dividing unit. A second filter dividing unit that further divides the plurality of filter partitions into a plurality of filter partitions; a filter FFT unit that performs fast Fourier transform on each of the plurality of filter partitions generated by the second filter demarcation unit; and the second signal The signal partition generated by the dividing unit and the filter FFT unit A convolution unit that performs a convolution operation of the generated filter partition; and an inverse FFT unit that performs inverse fast Fourier transform on the signal generated by the convolution unit, and the division of the first signal division unit and the first filter division unit The number D1 is the same, the number of divisions D2 of the second signal dividing unit and the second filter dividing unit are the same, and the number of divisions D1 and D2 are determined by the sampling rate of the input digital signal. It is characterized by being set accordingly.

  In one embodiment of the present invention, the division number D1 is set according to a conversion ratio between a sampling rate of the input digital signal and a desired sampling rate to be output, and the division number D2 is the FFT unit. It is set according to a predetermined number of taps.

  In another embodiment of the present invention, a table that predefines a relationship between a detection unit that detects a sampling rate of the input digital signal, a sampling rate of the input digital signal, and the division number D1 and the division number D2. And a setting unit that sets the division number D1 and the division number D2 according to the sampling rate detected by the detection unit by referring to the table stored in the storage unit It is characterized by that.

  In still another embodiment of the present invention, the first signal dividing unit divides at least the input digital signal into an odd component and an even component, and the first filter dividing unit converts at least the digital filter into an odd component. The second signal dividing unit divides a plurality of signal partitions in the time domain, and the second filter dividing unit divides the plurality of filter partitions in the time domain.

  The present invention also provides a program for causing a computer to execute a process of converting a sampling rate of an input digital signal into a desired sampling rate and outputting the same, and the program causes a processor of the computer to input the input digital signal into a plurality of partitions. A first signal division step for dividing the signal partition, a signal FFT step for fast Fourier transforming each of the plurality of signal partitions generated in the first signal division step, and a plurality of signal partitions generated in the signal FFT step A second signal dividing step for dividing the plurality of signal partitions; a first filter dividing step for dividing the digital filter into a plurality of partitions; and a plurality of filter partitions generated in the first filter dividing step. A second filter dividing step for dividing into filter partitions, a filter FFT step for fast Fourier transforming each of the plurality of filter partitions generated in the second filter demarcation step, and a signal partition generated in the second signal dividing step A convolution step for performing a convolution operation of the filter component generated in the filter FFT step, an inverse FFT step for performing an inverse fast Fourier transform on the signal generated in the convolution step, and the first signal dividing step; The division numbers D1 of the first filter division step are the same, the division numbers D2 of the second signal division step and the second filter division step are the same, and the division numbers D1 and D2 are: The input digital signal Characterized in that characterized in that it is set in accordance with the purine Great.

  According to the present invention, when the input digital signal is filtered to generate the output digital signal, each of the input digital signal and the digital filter is divided into the first and second partitions, and the signal partition and the filter partition are divided. Since FFT processing is performed to convert to the frequency domain and convolution is performed in the frequency domain, the processing can be speeded up as compared with convolution in the time domain. Also, each of the input digital signal and the digital filter can be divided into the first sampling rate, and can be converted to a desired sampling rate by performing polyphase filtering with the number of divisions of the first division. Furthermore, by dividing the partition obtained by the first division into the second, the number of taps of the FFT can be adjusted, and the FFT operation can be speeded up or made efficient.

It is a block diagram of the sampling converter in embodiment. It is a graph which shows the relationship between the tap number of FFT processing, and processing speed. It is a block diagram of the generalized sampling converter. It is a basic block diagram of the convolution process in a frequency domain. It is a block diagram of the downsampling using the convolution process in a frequency domain.

  Hereinafter, the embodiment of the present invention will be described with reference to the drawings, taking as an example the case of being incorporated in an electronic device such as a portable music player or a tablet terminal, and the case of downsampling that converts the sampling rate of the input digital signal to ½. An example will be described. However, the sampling rate converter of the present invention is not limited to this.

  FIG. 1 shows a configuration diagram of a sampling rate conversion apparatus according to the present embodiment. The basic configuration is a configuration in which convolution processing is performed in the frequency domain shown in FIG. 4, but when performing downsampling, a polyphase filter configuration is used without providing a thinning circuit 34 as shown in FIG. Downsampling is realized.

  In FIG. 1, the input digital signal (number of samples N) is divided into two, odd-numbered samples (Odd) and even-numbered samples (Even). The odd-numbered samples are FFT processed by the FFT calculator 100 and supplied to the multiplier 112. The FFT-processed signal is delayed by the delay element 114 and supplied to the multiplier 116, and the signal delayed by the delay element 114 is delayed by the delay element 118 and supplied to the multiplier 120. That is, the signal subjected to the FFT processing by the FFT calculator 100 is further divided into three partitions in the time domain.

  The even-numbered sample of the input digital signal is subjected to FFT processing by the FFT calculator 200 and supplied to the multiplier 212. The FFT-processed signal is delayed by the delay element 214 and supplied to the multiplier 216, and the signal delayed by the delay element 214 is delayed by the delay element 218 and supplied to the multiplier 220. That is, the signal subjected to the FFT processing by the FFT computing unit 200 is further divided into three partitions in the time domain.

  Although not shown, a change-over switch is provided at a branch point P where the odd-numbered sample and the even-numbered sample branch out of the input digital signal, and the odd-numbered sample is switched by switching the contact of this change-over switch. Are supplied to the FFT calculator 100, and even-numbered samples are supplied to the FFT calculator 200.

  On the other hand, the filter 22 (shown as an analog waveform in the figure, but actually a digital filter) is an odd-numbered filter component (Hodd) 150 and an even-numbered filter component (Heven), similar to the input digital signal. ) Is divided into 250. Similarly, the odd-numbered sample and the even-numbered sample of the input digital signal are divided into three partitions in the same manner, corresponding to the fact that the delay elements 114, 118, 214, and 218 are divided into three partitions, respectively. It is done. That is, the odd-numbered filter Hodd150 is divided into Hodd1 (154), Hodd2 (156), and Hodd3 (158) in the time domain. (258).

  The filters that are divided into odd-numbered and even-numbered and further divided into three in the time domain are subjected to FFT processing by FFT calculators 124-228, respectively. That is, the filter partition Hodd 1 (154) is subjected to FFT processing by the FFT calculator 124 and supplied to the multiplier 112. The filter partition Hood2 (156) is subjected to FFT processing by the FFT calculator 126 and supplied to the multiplier 116. The filter partition Hodd3 (158) is subjected to FFT processing by the FFT calculator 128 and supplied to the multiplier 120. Similarly, the filter partition Heven 1 (254) is FFT processed by the FFT calculator 224 and supplied to the multiplier 212. The filter partition Heven2 (256) is subjected to FFT processing by the FFT calculator 226 and supplied to the multiplier 216. The filter partition Heven3 (258) is subjected to FFT processing by the FFT calculator 228 and supplied to the multiplier 220.

  The odd numbered signal of the input digital signal subjected to the FFT processing by the FFT computing unit 100 and the FFT processing performed by the FFT computing unit 124 are multiplied by the multiplier 112 and supplied to the adder 130. Also, the odd-numbered signal of the input digital signal that has been subjected to FFT processing by the FFT arithmetic unit 100 and subjected to delay processing by the delay element 114 and the filter partition that has been FFT processed by the FFT arithmetic unit 126 are multiplied by the multiplier 116 and added. 130. Further, the odd-numbered signal of the input digital signal that is arithmetically processed by the FFT arithmetic unit 100 and subjected to the delay processing by the delay element 114 and the delay element 118 and the filter partition that has been FFT processed by the FFT arithmetic unit 128 are multiplied by the multiplier 120. And supplied to the adder 130. The adder 130 adds these multiplication results to each other and supplies the result to the adder 260. Similarly, the even-numbered signal of the input digital signal subjected to the FFT processing by the FFT calculator 200 and the FFT partition by the FFT calculator 224 are multiplied by the multiplier 212 and supplied to the adder 230. The even-numbered signal of the input digital signal that has been subjected to FFT processing by the FFT arithmetic unit 200 and subjected to delay processing by the delay element 214 and the filter partition that has been subjected to FFT processing by the FFT arithmetic unit 226 are multiplied by the multiplier 216 and added. 230. Further, the even-numbered signal of the input digital signal that has been processed by the FFT calculator 200 and delayed by the delay element 214 and the delay element 218 and the filter partition that has been FFT processed by the FFT calculator 228 are multiplied by the multiplier 220. And supplied to the adder 230. The adder 230 adds these multiplication results to each other and supplies the result to the adder 260.

  The adder 260 adds and combines the processing result for the odd-numbered signal from the adder 130 and the processing result for the even-numbered signal from the adder 230, and supplies the result to the inverse FFT calculator (IFFT) 270. To do. The inverse FFT calculator 270 restores the frequency domain signal from the adder 260 to a time domain signal and outputs an output signal (number of samples N / 2).

  In this embodiment, when the natural number i is an index and the input digital signal is xi (n), odd-numbered samples x1 (n), x3 (n), x5 (n),. FFT processing is performed to convert the signal into a frequency domain signal Xi (ω) (hereinafter referred to as an odd component as appropriate). Further, the even-numbered samples x2 (n), x4 (n), x6 (n),... Are subjected to FFT processing by the FFT computing unit 200, and the frequency domain signal Xi (ω) (hereinafter referred to as the even component). (Referred to as appropriate).

  On the other hand, the odd-numbered filter Hodd and the even-numbered filter Heven are each further divided into three parts in the time domain, and are subjected to FFT processing by an FFT calculator and converted to Hi (ω). The number of signal partitions Xi (ω) of the input digital signal and the number of filter partitions Hi (ω) are both six and the same.

In this embodiment, the FFT-processed signal partition Xi (ω) and the FFT-processed filter partition Hi (ω) corresponding thereto are subjected to a convolution operation using the multipliers 112 to 220 and the adders 130 and 230. As a result, the convolution result Yi (ω) of the odd and even components is obtained. An output signal is obtained by combining these signals with an adder 260 and further restoring the signal into a time domain signal with an inverse FFT calculator 270. That is, if the output signal is y (m),
y (m) = IFFT (Y (ω))
Y (ω) = ΣYi (ω) = Σ {Xi (ω) * Hi (ω)}
It is. Here, IFFT represents inverse FFT, and * represents convolution.

Since the input digital signal and the filter have a polyphase filter configuration that is processed by being divided into two odd and even partitions, the number of samples of the output signal y (m) is 1 of the number of samples of the input digital signal. / 2. That is, normal convolution results in convolution of odd and even components of Xi (ω) and odd and even components of Hi (ω).
(Odd component of Xi (ω)) × (Odd component of Hi (ω))
+ (Odd component of Xi (ω)) × (Even component of Hi (ω))
+ (Even component of Xi (ω)) × (odd component of Hi (ω))
+ (Even component of Xi (ω)) × (even component of Hi (ω))
In the configuration of FIG.
(Odd component of Xi (ω)) × (Odd component of Hi (ω))
+ (Even component of Xi (ω)) × (even component of Hi (ω))
Only
(Odd component of Xi (ω)) × (even component of Hi (ω))
And (even component of Xi (ω)) × (odd component of Hi (ω))
This is because the number of samples obtained as a result of the calculation is halved.

  In the present embodiment, the odd-numbered and even-numbered samples of the input digital signal are each divided into three partitions in the time domain, and accordingly, the odd-numbered and even-numbered samples of the filter are divided into three in the time domain. Since it is divided into partitions, the number of taps in the FFT calculators 124 to 228 can be reduced to an appropriate length, thereby improving the FFT performance.

  FIG. 2 shows the relationship between the number of taps and the processing speed (abbreviated as speed in the figure) when performing an FFT operation with a general-purpose microprocessor. As the number of taps increases, the processing speed increases, the processing speed becomes maximum at or near the predetermined number of taps Nth, and the processing speed tends to decrease sharply as the number of taps further increases. Of course, depending on the type of microprocessor, the number of taps Nth that maximizes the processing speed may vary.

  Therefore, according to the microprocessors used as the FFT calculators 124 to 228, efficient FFT processing can be performed while downsampling by setting the taps to be the same as or close to the tap number Nth that maximizes the processing speed. It becomes. In the present embodiment, assuming that Nth is 4096, for example, the filter is first divided into even and odd numbers, and then divided into three in the time domain and divided into a total of six filter partitions. Assuming that the total number of taps of the filter is 24576, the number of taps in the FFT calculators 124 to 228 is 24576/6 = 4096, and the calculation speed in each of the FFT calculators 124 to 228 can be maximized. Become.

  In this embodiment, each of the input digital signal and the filter is first divided into odd and even numbers, and then divided into three in the time domain. The former division is the first division and the latter division. Is the second division, the number of divisions of the first division is determined according to the thinning coefficient k at the time of downsampling, and the number of divisions of the second division is the maximum of the processing speed in the thinning coefficient k and the FFT calculator. Will be determined according to the number of taps. Note that the number of divisions of the first division and the second division is equal to each other in the input digital signal and the filter.

  In the present embodiment, in order to perform downsampling with the number of samples being 1/2, the number of divisions of the first division is 2, and the number of divisions of the second division is 3, but for example, the number of samples is 1/8. When downsampling is performed, it is as follows.

  That is, since the thinning coefficient k is k = 8, the division number of the first division is set to 8. That is, the input digital signal is first divided into 8 partitions. The method of dividing into 8 partitions is arbitrary. For example, it may be divided first into an odd number and an even number, and each may be further divided into 4 partitions. Next, the division number of the second division is set to 3. That is, eight input digital signal partitions are subjected to FFT processing and then divided into three in the time domain. Similarly, the filter is also divided into eight filter partitions as the first division number, and each is further divided into three in the time domain. Thereby, for example, when the total number of taps of the filter is 98304, the number of taps in the FFT calculator becomes 98304/24 = 4096, and the processing speed in each FFT calculator can be maximized.

Hereinafter, the frequency of the input digital signal, the output frequency, the number of divisions of the first division, the number of divisions of the second division, the total number of taps of the filter, and the number of taps of the FFT calculator will be exemplified.
<Example 1>
Input digital signal frequency: 88200kHz
Output digital signal frequency: 44100 kHz
Number of divisions in the first division: 2
Number of divisions in the second division: 3
Total number of filter taps: 24576
Number of FFT taps: 4096
<Example 2>
Input digital signal frequency: 352800 kHz
Output digital signal frequency: 44100 kHz
Number of divisions in the first division: 8
Number of divisions in the second division: 3
Total number of filter taps: 98304
Number of FFT taps: 4096

  Note that in Examples 1 and 2 above, the output digital signal frequency is 44100 kHz, even though the input digital signal frequency is different. It should also be noted that the number of FFT taps is 4096 even when the input digital signal frequency is different. That is, even if the frequency of the input digital signal is different, a desired output digital signal frequency can be obtained by adaptively setting the number of divisions of the first division and the second division according to the frequency of the input digital signal. In addition, the FFT processing can be speeded up and processed efficiently. In addition, when the applicant of the present invention downsamples the sampling rate to 1/8 as shown in Example 2, the configuration of the present embodiment shown in FIG. 1 is about 1.5 compared to the conventional configuration shown in FIG. It has been confirmed that the processing speed can be doubled.

  FIG. 3 shows a generalized configuration of the configuration of FIG. The input digital signal is divided into the division number D1 (D1 is a natural number of 2 or more) in the first division, and after being subjected to FFT processing by the FFT calculator, the division number D2 (D2 is a natural number of 2 or more) in the second division. Is divided into D1 × D2 input signal partitions and supplied to the convolution calculator 300. Similarly, the digital filter (FIR filter) is also divided into the division number D1 in the first division, further divided into the division number D2 in the second division, and divided into D1 × D2 filter partitions. FFT processing is performed. The frequency domain signal subjected to the FFT processing is supplied to the convolution calculator 300. The convolution operator 300 includes a multiplier and an adder, performs a convolution operation on the input signal partition and the filter partition, and supplies the result to the IFFT operator 320. The IFFT calculator 320 performs inverse FFT processing on the signal obtained by the convolution calculation, and restores the signal in the time domain to obtain an output digital signal.

In the FFT computing unit, Mo is the number of taps (this is the predetermined number of taps) that provides the maximum processing speed (or maximum performance), k is the decimation factor for obtaining the sampling rate of the desired output digital signal, and the filter If the total number of taps is S, the division number D1 and the division number D2 satisfy the following expressions.
D1 = k
S / (D1 × D2) to Mo
Here, ~ Mo represents a predetermined number of taps Mo or its vicinity. The dividers (configured by switches and delay elements), the FFT calculator, the IFFT calculator, and the convolution calculator that perform the first division and the second division are configured by a DSP or a microprocessor. The DSP or the microprocessor detects the sampling rate (frequency) of the input digital signal, determines the thinning coefficient k in order to convert it to the sampling rate of the desired output digital signal, and efficiently performs the thinning coefficient k and the FFT calculation processing. The division numbers D1 and D2 are adaptively set according to a predetermined number of taps Mo that can be executed. The DSP or the microprocessor may detect the sampling rate of the input digital signal and calculate the division numbers D1 and D2 by calculation. However, the optimum sampling rate of the input digital signal and the division numbers D1 and D2 may be calculated in advance. A table defining the relationship is stored in the memory in advance, and when the sampling rate of the input digital signal is determined, the memory is accessed and the division numbers D1 and D2 are adaptively used using the relationship defined in the table. It may be set. The divider, FFT calculator, convolution calculator 300, and IFFT calculator 320 are configured by a DSP, and a separately provided microprocessor detects the sampling rate of the input digital signal and refers to a table stored in the memory. The division numbers D1 and D2 may be adaptively determined according to the sampling rate of the input digital signal, a control signal may be output to the DSP, and the division numbers D1 and D2 may be adjusted. Further, the first division, the second division, the FFT processing, the convolution operation, and the inverse FFT processing can be executed by the DSP, but the microprocessor sequentially reads out the program stored in the program memory and samples the input digital signal according to the program. Each process that detects the rate, supplies the control signal to the DSP, divides the input digital signal and filter into the first and second parts, performs FFT processing, convolution processing, and inverse FFT processing to output the output digital signal Execute. The DSP and the microprocessor are incorporated in an electronic device such as a portable music player or a tablet terminal, and the program is stored in a memory such as a tablet terminal. The program may be incorporated from the beginning in a memory such as a tablet terminal as firmware, or may be downloaded from a predetermined server via a communication line such as the Internet and stored in the memory. The input digital signal may be downloaded from the Internet as well as input from the source sound source.

  100, 124, 126, 128, 200, 224, 226, 228, 200 FFT (Fast Fourier Transform) calculator, 112, 116, 120, 212, 216, 220 multiplier, 130, 260 adder, 270, 320 IFFT (Inverse Fast Fourier Transform) computing unit, 300 convolution computing unit.

Claims (5)

A first signal divider for dividing an input digital signal into a plurality of partitions;
A signal FFT unit for fast Fourier transforming each of the plurality of signal partitions generated by the first signal dividing unit;
A second signal dividing unit that further divides each signal generated by the signal FFT unit into a plurality of signal partitions;
A first filter dividing unit for dividing the digital filter into a plurality of partitions;
A second filter divider that further divides the plurality of filter partitions generated by the first filter divider into a plurality of filter partitions;
A filter FFT unit that fast Fourier transforms each of the plurality of filter partitions generated in the second filter demarcation unit;
A signal partition generated by the second signal dividing unit, and a convolution unit that performs a convolution operation of the filter partition generated by the filter FFT unit;
An inverse FFT unit that performs an inverse fast Fourier transform on the signal generated by the convolution unit;
With
The division number D1 of the first signal division unit and the first filter division unit are the same, the division number D2 of the second signal division unit and the second filter division unit are the same, and the division number D1 and the number of divisions D2 are set according to the sampling rate of the input digital signal.   The division number D1 is set according to a conversion ratio between a sampling rate of the input digital signal and a desired sampling rate to be output, and the division number D2 is set according to a predetermined number of taps in the FFT unit. The sampling rate conversion apparatus according to claim 1, wherein A detection unit for detecting a sampling rate of the input digital signal;
A storage unit that stores a table that preliminarily defines a relationship between the sampling rate of the input digital signal and the number of divisions D1 and the number of divisions D2.
The setting part which sets the division number D1 and division number D2 according to the sampling rate detected by the detection part by referring to the table memorized by the storage part is further provided. The sampling rate conversion device according to any one of 1 and 2. The first signal dividing unit divides at least the input digital signal into an odd component and an even component,
The first filter dividing unit divides at least the digital filter into an odd component and an even component,
The second signal dividing unit divides a plurality of signal partitions in a time domain,
The sampling rate conversion apparatus according to claim 1, wherein the second filter dividing unit divides a plurality of filter partitions in a time domain. A program for causing a computer to execute a process of converting a sampling rate of an input digital signal to a desired sampling rate and outputting the same, wherein the program is executed by a processor of the computer.
A first signal dividing step for dividing an input digital signal into a plurality of partitions;
A signal FFT step of fast Fourier transforming each of the plurality of signal partitions generated in the first signal division step;
A second signal dividing step of further dividing the plurality of signal partitions generated in the signal FFT step into a plurality of signal partitions;
A first filter dividing step for dividing the digital filter into a plurality of partitions;
A second filter dividing step for further dividing the plurality of filter partitions generated in the first filter dividing step into a plurality of filter partitions;
A filter FFT step for performing a fast Fourier transform on each of the plurality of filter partitions generated in the second filter demarcation step;
A convolution step for performing a convolution operation of the signal partition generated in the second signal division step and the filter component generated in the filter FFT step;
Performing an inverse FFT step of performing an inverse fast Fourier transform on the signal generated in the convolution step,
The number of divisions D1 of the first signal division step and the first filter division step are the same, the number of divisions D2 of the second signal division step and the second filter division step are the same, and the number of divisions D1 and division number D2 are set according to the sampling rate of the input digital signal.