JP6011389B2 - Power supply control circuit and power supply device - Google Patents

Description

  The present invention relates to a control circuit for a power supply device, and more particularly to a power supply control circuit that employs non-linear control and a power supply device including the power supply control circuit.

  There are various types of circuits as power supply control circuits adopting nonlinear control. As one of the power supply control circuits, a DC power supply control device disclosed in Patent Document 1 below is known. This DC power supply control device includes a drive circuit that drives two switch elements (main switch elements) of a power converter (DCDC converter), a hysteresis voltage, and a command voltage phase described later on a non-inverting input terminal and an inverting input terminal. Comparator to which the outputs of the compensation means and the integration means are respectively input, a voltage source that outputs a command voltage, an integration circuit composed of a capacitor and a resistor, and a command voltage that is output with the command voltage having phase characteristics Phase compensation means, DC cut means composed of a capacitor and cuts and outputs a DC component contained in an output (voltage pulse) of a flip-flop circuit to be described later, an output terminal of the power converter, and an inverting input terminal of the comparator Between the output terminal of the resistor connected between the capacitor and the capacitor connected in parallel with the resistor and the DC cut means and the inverting input terminal of the comparator Integrating means composed of connected resistors for integrating the output of the DC cut means and superimposing it on the output of the power converter, and a flip-flop circuit set / reset based on the output of the comparator and the external synchronization signal The hysteresis PWM control for each switch element of the power conversion unit can be executed in synchronization with the external synchronization signal.

  In this DC power supply control device, the drive circuit generates drive signals for the two switch elements based on the output of the flip-flop circuit. One of the two drive signals is high when the output of the flip-flop circuit is high, and the other is high when the output of the flip-flop is low. During the period when the output of the flip-flop circuit is high level, the voltage input to the inverting input terminal of the comparator rises, and when this voltage reaches the high level threshold value of the comparator, the output of the comparator is Transition from high level to low level. When the output of the comparator becomes low level, the output of the flip-flop circuit is reset (becomes low level). When the output of the flip-flop circuit becomes low level, one drive signal output from the drive circuit shifts from high level to low level, and the other drive signal shifts from low level to high level. During the period when the output of the flip-flop circuit is low, the voltage input to the inverting input terminal of the comparator drops, and when this voltage reaches the low level threshold of the comparator, or the external synchronization signal is low. When shifting from the level to the high level, the output of the flip-flop circuit is set (becomes high level). When the output of the flip-flop circuit becomes high level, one drive signal output from the drive circuit shifts from low level to high level, and the other drive signal shifts from high level to low level. By repeating this operation, the DC power supply controller self-oscillates and outputs a drive signal when an external synchronization signal is not input, and inputs an external synchronization signal having a frequency higher than the frequency at the time of this self-oscillation. When it is, the drive signal is output in a state synchronized with the external synchronization signal.

  The DC power supply control device employs hysteresis PWM control as described above. In the hysteresis PWM control in this DC power supply control device, the steady-state deviation of the output voltage of the power supply device is suppressed by the integral compensation circuit, and the transient voltage of the power supply device is suppressed by the differential compensation circuit. Moreover, the response to the command voltage is improved by command voltage phase compensation means for performing integral compensation of the command voltage.

JP 2008-283802 A (page 6, FIG. 5)

  In this DC power supply control device, the command voltage is input to the comparator via the command voltage phase compensation means as described above. Since the command voltage phase compensation means is an integration circuit that performs integral compensation, a delay occurring in the integration circuit is inevitable. Therefore, in order to further improve the responsiveness when the command voltage is changed, it is conceivable to improve the response to the command voltage by deleting the command voltage phase compensation means and employing another means. However, in a DC power supply control device using a comparator (comparator) having this hysteresis characteristic, the command voltage phase compensation means also has an effect of ensuring stable control by performing integral compensation. If the phase compensation means is deleted, there is a risk of disturbing stable control.

  For this reason, the inventors of the present application examined a power supply control circuit that performs non-linear control with a configuration in which a command voltage is directly input to a high-speed comparator that does not have hysteresis characteristics that can be selected in a wider range with a small number of parts. In the control circuit, the phase margin of the feedback loop is reduced, which causes a new problem that the control operation for the power supply apparatus becomes unstable.

  The present invention has been made to solve such a problem, and provides a power supply control circuit capable of sufficiently ensuring a phase margin while further improving the responsiveness to a command voltage, and a power supply device including the power supply control circuit. The main purpose is to provide.

  In order to achieve the above object, a power supply control circuit according to the present invention is a power supply control circuit that controls a switching operation of a DCDC converter in synchronization with a clock pulse, and that is synchronized with a rising edge or a falling edge of the clock pulse. A pulse generation circuit that generates a control pulse that shifts from one voltage value to a second voltage value and that shifts from the second voltage value to the first voltage value in synchronization with a rising or falling edge of a trigger pulse; A first series circuit comprising a first capacitor connected to the output terminal of the DCDC converter, a first resistor having one end connected to the other end of the first capacitor and the other end connected to the pulse input end; A second series circuit comprising a resistor and a switch element that is turned on when the voltage value of the control pulse is the first voltage value; the first capacitor; and the first resistor. A voltage superimposing circuit that generates a comparison voltage in which an AC component of a voltage generated at a connection point with the output voltage is output from an output terminal of the DCDC converter or a divided voltage obtained by dividing the output voltage, and the comparison And a comparator that outputs a pulse that rises or falls when the comparison voltage reaches the command voltage as the trigger pulse, and the second series circuit has one end that is the first voltage. The other end is connected to a reference potential at a connection point between the capacitor and the first resistor, and a reference potential is applied to the pulse input end when the voltage value of the control pulse is the first voltage value. A voltage higher than the reference potential is applied when the voltage value of the control pulse is the second voltage value.

  In the power supply control circuit according to the present invention, the DCDC converter is a step-down type, and a pulse voltage generated by a switching operation of the DCDC converter is applied to the pulse input terminal.

  A power supply device according to the present invention includes the power supply control circuit described above.

  According to the power supply control circuit and the power supply device of the present invention, a comparator that does not have hysteresis characteristics is used, and a configuration in which the command voltage is directly input to the comparator without interposing an integration circuit is provided. Responsiveness can be improved.

  In addition, according to the power supply control circuit and the power supply device, the time constant at the time of charging the first capacitor is smaller than the time constant at the time of discharging the first capacitor in each cycle of switching to the main switch element. In addition, by switching the time constant dynamically, it is possible to sufficiently secure a phase margin in the feedback loop (negative feedback circuit) of the DCDC converter while using a comparator having no hysteresis characteristic.

2 is a configuration diagram illustrating a configuration of a power supply device PS1 including a power supply control circuit 2. FIG. It is a block diagram which shows the structure of power supply device PS2 provided with 2 A of power supply control circuits. It is a wave form diagram of each part for demonstrating operation | movement of the power supply control circuits 2 and 2A.

  Hereinafter, embodiments of a power supply control circuit will be described with reference to the accompanying drawings.

  First, a configuration of a power supply device including a power supply control circuit will be described with reference to the drawings. The power supply device PS1 shown in FIG. 1 includes a DCDC converter 1 and a power supply control circuit 2 as an example.

  The DCDC converter 1 is configured as a non-insulated step-down converter that is an example of a voltage conversion circuit. The DCDC converter 1 includes a pair of input terminals 11a and 11b (hereinafter also referred to as “input terminal 11” unless otherwise specified), main switch elements 12 and 13, an inductor 14, an output capacitor 15, and a pair of output terminals 16a and 16b. (Hereinafter, also referred to as “output terminal 16” unless otherwise specified).

  Specifically, the input voltage (DC voltage) Vin is input between the pair of input terminals 11a and 11b with the input terminal 11b connected to the reference potential (ground G in this example) as the low potential side. The main switch elements 12 and 13 are each configured using a semiconductor switch element such as a MOS type FET or a bipolar type transistor. One end of the main switch elements 12 and 13 is connected to one end of the inductor 14. The other end of the main switch element 12 is connected to the input terminal 11a, and the other end of the main switch element 13 is connected to the ground G. The other end of the inductor 14 is connected to one end of the output capacitor 15. Both ends of the output capacitor 15 are connected to a pair of output terminals 16a and 16b, respectively.

  The main switch element 12 is turned on / off by a drive pulse Sd1 described later, and shifts to an on state when the drive pulse Sd1 is at an H level, and shifts to an off state when the drive pulse Sd1 is at an L level. On the other hand, the main switch element 13 is driven on / off by a drive pulse Sd2 described later having a phase opposite to that of the drive pulse Sd1, and when the drive pulse Sd2 is at the H level (that is, when the drive pulse Sd1 is at the L level). Shifts to the on state, and shifts to the off state when the drive pulse Sd2 is at the L level (that is, when the drive pulse Sd1 is at the H level).

  As described above, the main switch elements 12 and 13 are controlled to be alternately turned on (switching operation) by the drive pulses Sd1 and Sd2. That is, the main switch element 13 is turned off when the main switch element 12 is on, and the main switch element 13 is turned on when the main switch element 12 is off. The inductor current flowing through the inductor 14 flows through the main switch element 12 when the main switch element 12 is on, and flows through the main switch element 13 when the main switch element 13 is on. This inductor current increases when the main switch element 12 is in the on state, and decreases when the main switch element 13 is in the on state. A voltage generated between both terminals of the output capacitor 15 due to the inductor current is output from the output terminal 16 as an output voltage (DC voltage) Vout.

  With the above configuration, the DCDC converter 1 steps down the input voltage (DC voltage) Vin input to the input terminal 11 to the output voltage (DC voltage) Vout by the switching operation of the main switch elements 12 and 13 described above. The output voltage Vout is output from the output terminal 16 with the output terminal 16b at the low potential side (specifically, output to a load (not shown) connected to the output terminal 16).

  The power supply control circuit 2 includes a first capacitor 21, a first resistor 22, a second resistor 23, a switch element 24, a third resistor 25, a second capacitor 26, a comparator 27, a pulse generation circuit 28, and a drive signal generation circuit 29. The switching operation of the DCDC converter 1 is controlled. In the power supply control circuit 2, the drive signal generation circuit 29 generates drive pulses Sd 1 and Sd 2 for driving the main switch elements 12 and 13 based on the control pulse Sp 1 output from the pulse generation circuit 28. The pulse generation circuit 28 is a circuit configured using a flip-flop circuit or the like. The output of the pulse generation circuit 28 is set in synchronization with the rising or falling edge of the clock pulse Sclk (in this example, in synchronization with the rising edge), and the output of the comparator 27 (trigger pulse Sp3 to be described later) is rising. Alternatively, it is set in synchronization with the falling edge (in this example, in synchronization with the rising edge as an example). The comparator 27 receives the comparison voltage Vcmp, which is a voltage obtained by superimposing the AC component (voltage Vtr1) of the voltage Vtr that changes due to charging / discharging of the first capacitor 21 on the output voltage Vout, and the command voltage Vor. The output of the pulse generation circuit 28 is reset by a pulse output from the comparator 27 when the comparison voltage Vcmp reaches the command voltage Vor. Hereinafter, this operation will be described in detail.

  First, a circuit for generating a voltage Vtr that repeats rising and falling at a constant cycle based on charging and discharging of the first capacitor 21 will be described. One end of the first capacitor 21 is connected to the output terminal 16 a, and the other end (connection point A) is connected to one end of the first resistor 22 and one end of the second resistor 23. The other end of the second resistor 23 is connected to the ground G, which is a reference potential, via a switch element 24 that forms a second series circuit together with the second resistor 23. The switch element 24 is turned on / off by a control pulse Sp2 output from the inverting output terminal (output terminal Q bar) of the pulse generation circuit 28. In this example, as an example, the other end of the first resistor 22 as the pulse input terminal 31 is connected to a non-inverting output terminal (output terminal Q) of the pulse generation circuit 28. The capacitance value of the first capacitor 21 is defined as C1, the resistance value of the first resistor 22 that constitutes the first series circuit together with the first capacitor 21 is defined as R1, and the resistance value of the second resistor 23 is Stipulated in R2. Note that the connection order of the second resistor 23 and the switch element 24 may be reversed. That is, one end of the switch element 24 may be connected to the connection point A, and the other end of the switch element 24 may be connected to the ground G via the second resistor 23. At that time, if the switch cannot be driven, it is necessary to insert a drive circuit.

  The control pulse Sp1 output from the non-inverting output terminal (output terminal Q) of the pulse generation circuit 28 is a pulse having two voltage values (first voltage value and second voltage value). One of the voltage values (first voltage value or second voltage value) is a voltage value substantially equal to the reference potential (ground G), and the other (second voltage value or first voltage value) is the reference potential. The voltage value is higher than (Ground G). Hereinafter, a voltage value substantially equal to the reference potential (ground G) is referred to as L level, and a voltage value higher than the reference potential (ground G) is referred to as H level. The control pulse Sp2 output from the inverting output terminal (output terminal Q bar) of the pulse generation circuit 28 is a pulse obtained by inverting the voltage value of the control pulse Sp1 output from the non-inverting output terminal (output terminal Q). That is, when the control pulse Sp1 is at the H level, the control pulse Sp2 is at the L level, and when the control pulse Sp1 is at the L level, the control pulse Sp2 is at the H level.

  The output voltage Vout of the DCDC converter 1 controlled by the power supply control circuit 2 is set in a range lower than the voltage value (second voltage value or first voltage value) when the control pulse Sp1 is at the H level. That is, when the control pulse Sp1 output from the non-inverting output terminal of the pulse generation circuit 28 is at the H level, the voltage at the output terminal 16a (output voltage Vout) is lower than the voltage at the non-inverting output terminal (H level). . The switch element 24 is turned on when the control pulse Sp2 output from the inverting output terminal of the pulse generation circuit 28 is at the H level, and turned off when the control pulse Sp2 is at the L level.

  In the steady state, the first capacitor 21 is charged so that the terminal on the output terminal 16a side has a high potential. Since the voltage Vtr at the connection point A becomes a voltage (Vout−Vc1) obtained by subtracting the charging voltage Vc1 of the first capacitor 21 from the output voltage Vout, the voltage Vtr decreases when the charging voltage Vc1 increases, and the charging voltage Vc1 decreases. Sometimes rise. The charging voltage Vc1 of the first capacitor 21 changes as follows. When the control pulse Sp1 is at the H level, a current flows from the non-inverting output terminal of the pulse generation circuit 28 toward the output terminal 16a, and the charging voltage Vc1 drops. When the control pulse Sp1 is at the L level, the control pulse Sp2 is at the H level and the switch element 24 is turned on, so that a current flows from the output terminal 16a toward the non-inverting output terminal of the pulse generation circuit 28, and the output terminal Since a current flows also from 16a toward the switch element 24, the charging voltage Vc1 rises.

  When the charging voltage Vc1 of the first capacitor 21 decreases, that is, when the voltage Vtr at the connection point A increases, the charging voltage Vc1 and the voltage Vtr change based on the current flowing through the first resistor 22. On the other hand, when the charging voltage Vc1 of the first capacitor 21 increases, that is, when the voltage Vtr at the connection point A decreases, the charging voltage Vc1 and the voltage based on the respective currents flowing through the first resistor 22 and the second resistor 23 Vtr changes. In this example, the resistance value R2 of the second resistor 23 is set to a value (R2 << R1) sufficiently smaller than the resistance value R1 of the first resistor 22. By setting in this way, the time constant when the charging voltage Vc1 rises, that is, the time when the voltage Vtr falls, is larger than the time constant when the charging voltage Vc1 falls, that is, when the voltage Vtr rises. I try to make it smaller.

  The switch element 24 basically employs an analog switch. It is also possible to use a semiconductor switching element such as a MOS type FET or a bipolar type transistor. In that case, a driving circuit for driving the semiconductor switching element is required.

  Next, a circuit (voltage superimposing circuit) for inputting the comparison voltage Vcmp to the non-inverting input terminal of the comparator 27 will be described. The non-inverting input terminal of the comparator 27 receives the comparison voltage Vcmp in which the AC component (voltage Vtr1) of the voltage Vtr at the connection point A is superimposed on the output voltage Vout or the DC voltage component obtained by dividing the output voltage Vout. The In this example, the voltage obtained by superimposing the AC component (voltage Vtr1) of the voltage Vtr on the output voltage Vout is used as the comparison voltage Vcmp. In order to input the comparison voltage Vcmp to the non-inverting input terminal of the comparator 27, the non-inverting input terminal is connected to the output terminal 16a via the third resistor 25 constituting the voltage superimposing circuit, and the voltage superimposing circuit is It is connected to the connection point A through the second capacitor 26 that constitutes it. By connecting in this way, the output voltage Vout (DC component of the output voltage Vout) is supplied to the non-inverting input terminal of the comparator 27 via the third resistor 25, and the AC component (voltage Vtr1) of the voltage Vtr at the connection point A. ) Is supplied to the non-inverting input terminal of the comparator 27 via the second capacitor 26. Further, the fluctuation component in the high frequency region generated in the output voltage Vout is supplied to the non-inverting input terminal of the comparator 27 via the first capacitor 21 and the second capacitor 26.

  When the AC component (voltage Vtr1) of the voltage Vtr at the connection point A is to be superimposed on the DC voltage obtained by dividing the output voltage Vout, for example, the third resistor 25 and the non-inverting input terminal of the comparator 27 Is connected to the ground G through a fourth resistor (not shown). In this case, the output voltage Vout is divided by the third resistor 25 and the fourth resistor, and the divided voltage is supplied to the non-inverting input terminal of the comparator 27. As described above, when the output voltage Vout is desired to be divided, a plurality of resistors may be connected between the output terminal 16a and the ground G. At this time, the ratio when the output voltage Vout is divided may be fixed or adjustable. For example, if an element capable of changing the resistance value is used, the voltage dividing ratio of the output voltage Vout can be adjusted. When the voltage dividing ratio of the output voltage Vout can be adjusted, the output voltage Vout can be changed by changing the voltage dividing ratio even if a command voltage Vor described later input to the comparator 27 is constant.

  The second capacitor 26, together with the first capacitor 21, forms a high-speed loop of a feedback loop that controls the duty ratio for the drive pulses Sd1, Sd2 for the main switch elements 12, 13. That is, since this high-speed loop transmits the fluctuation component in the high frequency region generated in the DC output voltage Vout to the non-inverting input terminal of the comparator 27 via the first capacitor 21 and the second capacitor 26, the third resistor 25 Fluctuation components in the high frequency region can be transmitted (feedback can be performed) at a higher speed than the loop through the.

  A series circuit composed of the second capacitor 26 and the third resistor 25 is connected in parallel to the first capacitor 21. The combined impedance of the series circuit is set to be sufficiently larger than the impedance of the first capacitor 21 at the switching frequency of the main switch elements 12 and 13. That is, the capacitance value of the second capacitor 26, the resistance value of the third resistor 25, and the first capacitor 21 are set so that the impedance of the first capacitor 21 is sufficiently smaller than the combined impedance of the series circuit. A capacitance value C1 is determined.

  Next, an operation in which the comparator 27 resets the output of the non-inverting output terminal of the pulse generation circuit 28 will be described. The comparator 27 resets the output of the non-inverting output terminal of the pulse generation circuit 28 when the comparison voltage Vcmp, which is a voltage obtained by superimposing the AC component (voltage Vtr1) of the voltage Vtr on the output voltage Vout, reaches the command voltage Vor. . The comparator 27 is composed of a comparator having no hysteresis characteristic. The comparison voltage Vcmp is input to the non-inverting input terminal of the comparator 27, and the command voltage Vor is input to the inverting input terminal of the comparator 27. Therefore, when the comparison voltage Vcmp reaches the command voltage Vor, the output of the comparator 27 shifts from the L level to the H level. In synchronization with this rise, the output of the non-inverting output terminal of the pulse generation circuit 28 is reset. When the output of the non-inverting output terminal of the pulse generation circuit 28 is reset, the control pulse Sp1 becomes L level and the switch element 24 is turned on, so that the voltage Vtr that is the voltage at the connection point A drops. As the voltage Vtr drops, the comparison voltage Vcmp also drops, so that the output of the comparator 27 shifts from the H level to the L level. In this way, the comparator 27 generates the trigger pulse Sp3 for resetting the output of the non-inverting output terminal of the pulse generation circuit 28.

  Next, an operation in which the pulse generation circuit 28 generates the control pulse Sp1 will be described. A clock pulse Sclk and a trigger pulse Sp3 having a predetermined frequency (switching frequency f0 of the main switch elements 12 and 13) and a trigger pulse Sp3 are input to the pulse generation circuit 28 (the clock pulse Sclk is input to a set input terminal (input terminal S)). The trigger pulse Sp3 is input to the reset input terminal (input terminal R)). The output of the pulse generation circuit 28 (the output of the non-inverting output terminal (output terminal Q)) is set in synchronization with the rising edge of the clock pulse Sclk. That is, the control pulse Sp1 output from the non-inverted output terminal (output terminal Q) of the pulse generation circuit 28 shifts to the H level in synchronization with the rising edge of the clock pulse Sclk, and L in synchronization with the rising edge of the trigger pulse Sp3. Move to level. The pulse generation circuit 28 generates a control pulse Sp2, which is a pulse obtained by inverting the control pulse Sp1, and outputs the control pulse Sp2 from the inverting output terminal (output terminal Q bar).

  The relationship between the voltage when the control pulse Sp1 is at the H level and the output voltage Vout is set as follows. In this example, as an example, the comparator 27, the pulse generation circuit 28, and the drive signal generation circuit 29 are operated by the auxiliary power supply voltage Vcc slightly lower than the input voltage Vin. Therefore, the voltage when the control pulse Sp1 output from the pulse generation circuit 28 is at the H level is substantially equal to the auxiliary power supply voltage Vcc. The auxiliary power supply voltage Vcc is set to a voltage higher than the output voltage Vout generated by stepping down the input voltage Vin in a steady state. When the output voltage Vout is set to a voltage higher than the auxiliary power supply voltage Vcc, a state in which the voltage Vtr at the connection point A and the output voltage Vout are substantially equal occurs in the process in which the output voltage Vout increases during startup. The change in the charging voltage Vc1 of the first capacitor 21 becomes minute. In order to avoid such a problem, the auxiliary power supply voltage Vcc is set to a voltage higher than the output voltage Vout.

  In this example, the pulse generation circuit 28 includes, for example, a flip-flop circuit or a latch circuit having an edge trigger function, (RS-flip-flop (latch), and JK-flip-flop (latch). ) And a flip-flop circuit or a latch circuit having a set / reset function such as a D-flip-flop (latch) having a set terminal and a reset terminal), and the output is set by the clock pulse Sclk, and the trigger pulse Sp3 Is configured to reset the output.

  With this configuration, the pulse generation circuit 28 shifts to the set state in synchronization with the rising edge of the clock pulse Sclk, and shifts to the reset state in synchronization with the rising edge of the trigger pulse Sp3. When shifting to the set state, the control pulse Sp1 output from the output terminal Q shifts to the H level, and the control pulse Sp2 output from the output terminal Q bar shifts to the L level. When shifting to the reset state, the control pulse Sp1 shifts to the L level, and the control pulse Sp2 shifts to the H level.

  Next, the relationship between the drive pulses Sd1 and Sd2 generated by the drive signal generation circuit 29 and the control pulse Sp1 generated by the pulse generation circuit 28 will be described. The drive signal generation circuit 29 generates drive pulses Sd1 and Sd2 having voltage values necessary for driving the main switch elements 12 and 13 based on the control pulse Sp1. The drive pulse Sd1 is a pulse for turning on the main switch element 12 while the control pulse Sp1 is at the H level, and the drive pulse Sd2 is for turning on the main switch element 13 when the control pulse Sp1 is at the L level. It is a pulse. In this example, the main switch elements 12 and 13 are set to turn on when the drive pulses Sd1 and Sd2 are at the H level and to turn off when the drive pulses are at the L level. Therefore, the drive pulse Sd1 is at the H level when the control pulse Sp1 is at the H level, and is at the L level when the control pulse Sp1 is at the L level. On the other hand, the drive pulse Sd2 becomes L level when the control pulse Sp1 is H level, and becomes H level when the control pulse Sp1 is L level.

  In this example, as an example, the drive signal generation circuit 29 employs a configuration in which the drive pulses Sd1 and Sd2 are generated based on the control pulse Sp1, but the drive pulse Sd2 is generated based on the control pulse Sp2. It may be configured. Further, it is possible to adopt a configuration in which the drive pulses Sd1 and Sd2 are generated based on the control pulse Sp2. Furthermore, when the main switch elements 12 and 13 are switch elements that can be sufficiently driven by the voltage values of the control pulses Sp1 and Sp2, the drive signal generation circuit 29 is omitted and the pulse generation circuit 28 is replaced by the main switch elements 12 and 13. It is also possible to adopt a configuration in which the is directly driven.

  Next, the operation of the power supply device PS1 will be described with reference to FIGS.

  First, the basic operation of the power supply control circuit 2 in a steady state will be described. As shown in FIG. 3, the clock pulse Sclk is input at a predetermined constant period T0 (predetermined constant frequency f0 = 1 / T0).

  First, an operation in the period P1 is described. This period corresponds to the period from the rising edge of the clock pulse Sclk to the rising edge of the trigger pulse Sp3. The pulse generation circuit 28 is set in synchronization with the rising edge of the clock pulse Sclk. Therefore, the control pulse Sp1 shifts to the H level, and the control pulse Sp2 shifts to the L level. At this time, the drive signal generation circuit 29 shifts the drive pulse Sd1 to the H level and shifts the drive pulse Sd2 to the L level based on the control pulse Sp1. In the DCDC converter 1, since the main switch element 12 is turned on and the main switch element 13 is turned off, the voltage Vp applied to the input side terminal of the inductor 14 is substantially equal to the input voltage Vin. The current flowing from the inductor 14 to the output side increases.

In the power supply control circuit 2, the control pulse Sp <b> 1 becomes H level and the control pulse Sp <b> 2 becomes L level, so that the H level control pulse Sp <b> 1 is applied to the other end of the first resistor 22 as the pulse input terminal 31. The switch element 24 shifts to the off state. When the H level control pulse Sp1 is applied to the pulse input terminal 31, a current flowing into the first capacitor 21 flows through the first resistor 22, and the charging voltage Vc1 of the first capacitor 21 decreases. . As the charging voltage Vc1 drops, the voltage Vtr, which is the voltage at the connection point A, rises. At this time, the voltage Vtr rises with a slope determined by the resistance value R1 of the first resistor 22 and the capacitance value C1 of the first capacitor 21, that is, a slope determined by the time constant (R1 × C1). Since this time constant is set to be sufficiently larger than the period T0 of the clock pulse Sclk, the voltage Vtr rises almost linearly in the period P1. The slope of the voltage Vtr is approximately expressed by the following equation.
(Vcc-Vout) / (R1 × C1)

  Note that at the start of the period P1, the charging voltage Vc1 of the first capacitor 21 has a voltage value close to the output voltage Vout (a voltage value slightly lower than the output voltage Vout). Therefore, the lower limit voltage Vmin (= Vout−Vc1), which is the voltage of the voltage Vtr at the start of the period P1, is close to the reference potential (ground G) (a voltage value slightly higher than the reference potential (ground G)). It has become. In the period P1, a current flows from the connection point A toward the output terminal 16a, and the charging voltage Vc1 of the first capacitor 21 drops almost linearly. As a result, the voltage Vtr rises almost linearly from the lower limit voltage Vmin.

  The comparator 27 compares the reference voltage Vcmp (Vout + Vtr1) obtained by superimposing the voltage Vtr1, which is an AC component of the voltage Vtr, on the output voltage Vout with the command voltage Vor, and when the comparison voltage Vcmp reaches the command voltage Vor, the output voltage L Shift from level to H level. That is, the trigger pulse Sp3 output from the comparator 27 shifts from the L level to the H level when the comparison voltage Vcmp reaches the command voltage Vor. The period P1 ends when the trigger pulse Sp3 shifts from the L level to the H level.

  Next, an operation in the period P2 is described. This period corresponds to the period from the rising edge of the trigger pulse Sp3 to the rising edge of the clock pulse Sclk. Since the pulse generation circuit 28 is reset in synchronization with the rising edge of the trigger pulse Sp3, the pulse Sp1 shifts to the L level and the control pulse Sp2 shifts to the H level. At this time, the drive signal generation circuit 29 shifts the drive pulse Sd1 to L level and shifts the drive pulse Sd2 to H level based on the control pulse Sp1. In the DCDC converter 1, since the main switch element 12 is turned off and the main switch element 13 is turned on, the voltage Vp applied to the input terminal of the inductor 14 is equal to the reference potential (ground G). It becomes substantially equal, and the current flowing from the inductor 14 to the output side decreases.

  In the power supply control circuit 2, the control pulse Sp <b> 1 becomes L level and the control pulse Sp <b> 2 becomes H level, so that the L level control pulse Sp <b> 1 is applied to the other end of the first resistor 22 as the pulse input terminal 31. The switch element 24 is turned on. For this reason, the terminal on the connection point A side of the first capacitor 21 is connected to the ground G via the first resistor 22 and the second resistor 23 connected in parallel to each other, and the first resistor 22 and the second resistor A current from the first capacitor 21 toward the ground G flows through the resistor 23, and the charging voltage Vc1 of the first capacitor 21 increases.

That is, in the period P2, the first capacitor 21 is charged from the output terminal 16a side by the DC output voltage Vout. The charging of the first capacitor 21 is continued until the clock pulse Sclk shifts from the L level to the H level (that is, the charging of the first capacitor 21 ends in synchronization with the rising of the clock pulse Sclk). At this time, the charging voltage Vc1 of the first capacitor 21 increases to a voltage value close to the output voltage Vout (a voltage value slightly lower than the output voltage Vout). Therefore, as shown in FIG. 3, the voltage Vtr (= Vout−Vc1) drops along a curve represented by an exponential function with the zero volt axis as an asymptote. The shape of this curve is determined by the parallel combined resistance value (R1 // R2) of the first resistor 22 and the second resistor 23 and the capacitance value C1 of the first capacitor 21. That is, the shape of this curve is determined by the time constant ((R1 // R2) × C1). Since this time constant ((R1 // R2) × C1) is smaller than the time constant (R1 × C1) when only the first resistor 22 is used, the voltage Vtr is limited only by the first resistor 22 to the first capacitor. Compared with the configuration connected to 21 (the configuration without the series circuit of the second resistor 23 and the switch element 24), the voltage drops faster. Note that the waveform of the voltage Vtr in the period P2 is expressed by the following equation.
Vmax × e ^{−t / ((R1 // R2) × C1)}

  In this way, in the power supply control circuit 2, the first resistor 22 discharges the first capacitor 21 when the control pulse Sp1 is at the H level within each switching period T0 for the main switch elements 12 and 13 (the first capacitor 21). When the control pulse Sp1 is at the L level, the first resistor 22 and the second resistor 23 charge the first capacitor 21 (increase the charge voltage Vc1 of the first capacitor 21). Thus, a voltage Vtr that repeatedly rises and falls is generated at the connection point A. In the operation of the power supply control circuit 2, the time constant for the waveform of the voltage Vtr when the first capacitor 21 is charged, as opposed to the time constant (R1 × C1) for the waveform of the voltage Vtr when the first capacitor 21 is discharged. The time constant is dynamically switched between charging and discharging so that ((R1 // R2) × C1) becomes smaller. For this reason, a sufficient phase margin in the feedback loop (negative feedback circuit) of the DCDC converter 1 is ensured.

  In this example, before the charging voltage Vc1 of the first capacitor 21 becomes the same voltage as the output voltage Vout, that is, before the triangular wave voltage Vtr reaches the reference potential (ground G), the pulse generation circuit 28 Set by Sclk. Further, it is reset by a trigger pulse Sp3 that rises when the comparison voltage Vcmp (Vout + Vtr1) reaches the command voltage Vor. When the comparison voltage Vcmp (Vout + Vtr1) reaches the command voltage Vor, the trigger pulse Sp3 shifts from the L level to the H level. However, since the voltage Vtr starts dropping in synchronization with the rising edge of the trigger pulse Sp3, the trigger pulse Sp3 is triggered. The pulse Sp3 shifts from the H level to the L level immediately after shifting from the L level to the H level.

  For the operation after the period P3, the same operation as the period P1 or the period P2 is repeated. In other words, the operation in the period P3 and the period P5 is the same as that in the period P1, and the operation in the period P4 and the period P6 is similar to that in the period P2.

  In the power supply control circuit 2, the output voltage Vout in the steady state is substantially equal to the command voltage Vor. However, in practice, the output voltage Vout is slightly lower than the command voltage Vor. Strictly speaking, the output voltage Vout is related to the amplitude of the charging voltage Vc1 of the first capacitor 21. That is, first, the control pulse Sp1 output from the non-inverted output terminal (output terminal Q) of the pulse generation circuit 28 in synchronization with the rising edge of the clock pulse Sclk shifts to the H level, and the inverted output terminal (output terminal Q bar). The control pulse Sp2 output from is shifted to the L level. Accordingly, the first resistor 22 discharges the first capacitor 21, the voltage at the connection point A increases, and the comparison voltage Vcmp (Vout + Vtr1) also increases. When the comparison voltage Vcmp reaches the command voltage Vor, the control pulse Sp1 of the pulse generation circuit 28 shifts to the L level, and the control pulse Sp2 shifts to the H level. Accordingly, the first capacitor 21 is charged by the parallel resistance of the first resistor 22 and the second resistor 23, the voltage at the connection point A drops, and the comparison voltage Vcmp (Vout + Vtr1) also drops. The charging time continues until the rising signal of the next clock pulse Sclk is received. The amplitude of the charging voltage Vc1 of the first capacitor 21 is automatically adjusted so that the charge amount and the discharge amount with respect to the first capacitor 21 become equal in one period T0 of the clock pulse, and accordingly, the AC component of the voltage Vtr The amplitude of (voltage Vtr1) is also automatically adjusted. The average value of the comparison voltage Vcmp is maintained in a state that matches the output voltage Vout. Thus, the output voltage Vout follows the command voltage Vor and is a voltage that is slightly lower than the command voltage Vor (a voltage that is ½ of the amplitude of the charging voltage Vc1 (the amplitude of the voltage Vtr1) than the command voltage Vor). ) Is controlled stably.

  Next, the operation of the power supply control circuit 2 when the DC output voltage Vout and the command voltage Vor change will be described.

  In the state in which the above-described PWM control for the DCDC converter 1 is executed, for example, an overshoot occurs in the DC output voltage Vout due to a sudden change in the load, and this occurrence is the main switch element as in the operation in the period P1. When 12 is maintained in the ON state, the time for the comparison voltage Vcmp to reach the command voltage Vor is advanced. Therefore, in the power supply control circuit 2, the period during which the control pulse Sp1 output from the pulse generation circuit 28 is maintained at the H level is shortened, and the period during which the main switch element 12 is maintained in the on state is also shortened. The Therefore, in the DCDC converter 1, the energy supplied from the input terminal 11 side to the inductor 14 side decreases, and the output voltage Vout drops. By such an operation, the delay time of the response to the overshoot of the output voltage Vout is shortened.

  Further, when this overshoot occurs during the period in which the main switch element 12 is maintained in the OFF state as in the operation in the period P2, the voltage Vtr (lower limit voltage Vmin) at the end of this period is the overshoot. It becomes higher than the case where does not occur. Therefore, this period ends, and the voltage at which the comparison voltage Vcmp starts to rise in the next period (or period P3 if this period is the period P2) becomes higher. As a result, the comparison voltage Vcmp becomes the command voltage Vor. The time to reach will be faster. Therefore, the period during which the control pulse Sp1 output from the pulse generation circuit 28 is maintained at the H level is shortened, and the period during which the main switch element 12 is maintained in the ON state is also shortened. Therefore, the energy supplied from the input terminal 11 side to the inductor 14 side decreases, and the output voltage Vout drops. By such an operation, the delay time of the response to the overshoot of the output voltage Vout is shortened.

  Although not described in detail, the operation of the power supply control circuit 2 when an undershoot occurs in the DC output voltage Vout is the reverse of the operation when an overshoot occurs. That is, the period during which the control pulse Sp1 output from the pulse generation circuit 28 is maintained at the H level is increased, and the period during which the main switch element 12 is maintained in the ON state is also increased. Therefore, the energy supplied from the input terminal 11 side to the inductor 14 side increases, and the output voltage Vout increases. By this operation, the delay time of the response to the undershoot of the DC output voltage Vout is shortened as in the case of occurrence of overshoot.

  Further, in the power supply control circuit 2, when the command voltage Vor is changed to a lower voltage and this change is performed during the period in which the main switch element 12 is maintained in the ON state as in the operation in the period P1, the comparison is made. The time for the voltage Vcmp to reach the command voltage Vor is advanced. Therefore, in the power supply control circuit 2, the period during which the control pulse Sp1 output from the pulse generation circuit 28 is maintained at the H level is shortened, and the period during which the main switch element 12 is maintained in the on state is also shortened. The Therefore, the energy supplied from the input terminal 11 side to the inductor 14 side in the DCDC converter 1 decreases, and the output voltage Vout drops. By such an operation, the output voltage Vout drops following a change in the command voltage Vor with a short delay time.

  Further, when this change in the command voltage Vor is performed during a period in which the main switch element 12 is maintained in the off state as in the operation in the period P2, the main switch element 12 is maintained in the on state after this period. The period during which the comparison voltage Vcmp reaches the command voltage Vor is advanced in the period during which the comparison voltage Vcmp is reached (if the period is the period P2, the period P3). Therefore, the period during which the control pulse Sp1 output from the pulse generation circuit 28 is maintained at the H level is shortened, and the period during which the main switch element 12 is maintained in the ON state is also shortened. With such an operation, the output voltage Vout drops following the command voltage Vor with a short delay time.

  Although not described in detail, the operation of the power supply control circuit 2 when the command voltage Vor is changed to a higher voltage is the reverse of the operation when the command voltage Vor is changed to a lower voltage. become. That is, the period during which the control pulse Sp1 output from the pulse generation circuit 28 is maintained at the H level is increased, and the period during which the main switch element 12 is maintained in the ON state is also increased. Therefore, the energy supplied from the input terminal 11 side to the inductor 14 side increases, and the output voltage Vout increases. By such an operation, the output voltage Vout rises following the command voltage Vor with a short delay time.

  As described above, according to the power supply control circuit 2, a comparator having no hysteresis characteristic is used as the comparator 27, and a configuration in which the command voltage Vor is directly input to the comparator 27 without interposing an integrating circuit is adopted. Thus, the response to the command voltage Vor can be improved.

  Further, according to the power supply control circuit 2, the time constant (R 1 × C 1) at the time of discharging with respect to the first capacitor 21 within each switching period T 0 with respect to the main switch elements 12, 13, with respect to the first capacitor 21. The feedback loop of the DCDC converter 1 while using a comparator having no hysteresis characteristic as the comparator 27 by dynamically switching the time constant so that the time constant ((R1 // R2) × C1) during charging is small. A sufficient phase margin at the switching frequency f0 in the power supply control circuit 2 constituting the (negative feedback circuit) can be secured.

  In the power supply control circuit 2, the pulse applied to the other end of the first resistor 22 as the pulse input terminal 31 shifts from the L level to the H level in synchronization with the rising edge of the clock pulse Sclk, and the trigger pulse Sp3 As long as the pulse shifts from the H level to the L level in synchronism with the above, a pulse other than the control pulse Sp1 may be used. That is, in the power supply control circuit 2, a pulse that becomes H level when the control pulse Sp1 is H level and becomes L level when the control pulse Sp1 is L level may be used instead of the control pulse Sp1. The voltage value when the pulse used instead of the control pulse Sp1 is at the H level is different from the voltage value when the control pulse Sp1 is at the H level if the voltage value is higher than the output voltage Vout in the steady state. It may be a voltage value.

  When the pulse generation circuit 28 is configured to be set in synchronization with the falling edge of the pulse input to the set input terminal, a pulse obtained by inverting the clock pulse Sclk is set as the set input terminal of the pulse generation circuit 28. You should just make it input to. Further, when the pulse generation circuit 28 is configured to be reset in synchronization with the falling edge of the pulse input to the reset input terminal, the command voltage Vor is input to the non-inverting input terminal of the comparator 27 and is inverted. The comparison voltage Vcmp may be input to the input terminal.

  FIG. 2 shows a power supply control circuit 2A in which the voltage Vp generated at the connection point between the main switch element 12 and the inductor 14 is used instead of the control pulse Sp1. The voltage Vp is a voltage generated by the switching operation of the DCDC converter 1 and is substantially equal to the input voltage Vin when the main switch element 12 is in the on state. When the main switch element 13 is in the on state, the reference potential ( The pulse voltage is equal to the ground G) (hereinafter also referred to as pulse voltage Vp). The main switch element 12 is turned on when the control pulse Sp1 is at the H level, and the main switch element 13 is turned on when the control pulse Sp1 is at the L level. Therefore, the pulse voltage Vp is alternately switched between the H level and the L level at the same timing as the control pulse Sp1. Thus, since the level of the pulse voltage Vp changes at the same timing as the control pulse Sp1, the pulse voltage Vp is used instead of the control pulse Sp1, and is input to the other end of the first resistor 22 as the pulse input terminal 31. The power control circuit 2A thus configured operates in the same manner as the power control circuit 2 in FIG.

  In the power supply control circuit 2A, since the voltage when the pulse voltage Vp is at the H level changes based on the input voltage Vin, the response to fluctuations in the input voltage is improved. For example, when the input voltage Vin decreases, the gradient when the voltage Vtr increases increases, so that the period during which the main switch element 12 is maintained in the on state becomes longer. On the other hand, when the input voltage Vin rises, the slope when the voltage Vtr rises increases, so the period during which the main switch element 12 is maintained in the on state is shortened.

  Although the step-down converter has been described as an example, it can be used as a power supply control circuit that performs PWM control on the step-up converter.

DESCRIPTION OF SYMBOLS 1 DCDC converter 2,2A Power supply control circuit 12,13 Main switch element 21 1st capacitor | condenser 22 1st resistor 23 2nd resistor 24 Switch element 25 Detection circuit 26 2nd capacitor 27 Comparator 28 Pulse generation circuit 31 Pulse input terminal Sclk Clock pulse Sp1, Sp2 Control pulse Sp3 Trigger pulse Vcmp Comparison voltage Vor Command voltage Vout DC output voltage

Claims (3)

A power supply control circuit for controlling a switching operation of a DCDC converter in synchronization with a clock pulse,
The first voltage value shifts from the first voltage value in synchronization with the rising or falling edge of the clock pulse, and the second voltage value shifts from the second voltage value to the first voltage value in synchronization with the rising or falling edge of the trigger pulse. A pulse generation circuit for generating a control pulse;
A first series circuit comprising a first capacitor having one end connected to the output terminal of the DCDC converter and a first resistor having one end connected to the other end of the first capacitor and the other end connected to the pulse input end; ,
A second series circuit comprising a second resistor and a switch element that is turned on when the voltage value of the control pulse is the first voltage value;
A comparison voltage in which an alternating current component of a voltage generated at a connection point between the first capacitor and the first resistor is superimposed on an output voltage output from an output terminal of the DCDC converter or a divided voltage obtained by dividing the output voltage. A voltage superposition circuit to be generated;
A comparator that inputs the comparison voltage and the command voltage, and outputs a pulse that rises or falls as the trigger pulse when the comparison voltage reaches the command voltage;
The second series circuit has one end connected to a connection point between the first capacitor and the first resistor and the other end connected to a reference potential.
A reference potential is applied to the pulse input terminal when the voltage value of the control pulse is the first voltage value, and a voltage higher than the reference potential is applied when the voltage value of the control pulse is the second voltage value. A power supply control circuit configured to be applied. The DCDC converter is a step-down type;
The power supply control circuit according to claim 1, wherein a pulse voltage generated by a switching operation of the DCDC converter is applied to the pulse input terminal.   A power supply apparatus comprising the power supply control circuit according to claim 1.

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