JP5980377B2 - ANALOG / DIGITAL CONVERSION CIRCUIT, ANALOG / DIGITAL CONVERSION INSPECTION METHOD, IMAGING DEVICE, IMAGING SYSTEM HAVING IMAGING DEVICE, IMAGING DEVICE INSPECTION METHOD - Google Patents

Description

  The present invention relates to an analog-to-digital conversion circuit having a plurality of circuit units each including a comparator and a memory, an inspection method for the analog-to-digital conversion circuit, an imaging device equipped with the analog-digital conversion circuit, an imaging system equipped with the imaging device, and imaging The present invention relates to an apparatus inspection method.

  Conventionally, a column parallel type analog-to-digital conversion has a plurality of columns of comparators and a column memory of a plurality of columns electrically connected to the comparators, and converts an analog signal into a digital signal in each column. A circuit (hereinafter, an analog-digital conversion circuit is referred to as an ADC, and a column parallel type ADC is referred to as a column ADC) is known. Patent Document 1 discloses a CMOS image sensor having a test mode in which a diagnostic logic unit writes test data into a column memory in order to test whether or not a column memory included in the column ADC has a failure.

Japanese Patent Laid-Open No. 11-331883

  However, in the above-described inspection mode of the CMOS image sensor, common inspection data is written in each column memory of the column ADC. Therefore, even if there is a short failure between the column memories, the signal output in the inspection mode is the same signal as when there is no short failure. Therefore, there is a problem that a short fault in the column memory cannot be found by inspection.

  An object of the present invention is to provide, for example, an ADC having a configuration capable of inspecting the presence or absence of a short fault between a plurality of memories, an inspection method thereof, an imaging device having an ADC, and an imaging system having the imaging device.

The present invention has been made in view of the above problems, and one aspect thereof is a comparator that outputs a comparison result signal indicating a comparison result between an analog signal and a reference signal, and a digital signal based on the comparison result signal. have a plurality of circuit units each comprising a memory and to hold a signal, the analog signal an analog-digital converter into a digital signal, each of the plurality of circuit portions first as the memory A plurality of first memories and a plurality of second memories, and each of the plurality of first memories includes a first digital signal. supplies the first test signal for holding the, in each of the plurality of second memory, for holding the second digital signals of different signal values from said first digital signal Comprising a test signal supply unit for supply supplying the second test signal, and an output comparator unit for storing an expected value, and the transfer portion, the transfer unit, a digital to the first and second memory are respectively held First and second transfer circuits for transferring a signal to the output comparison unit; each of the plurality of first memories transfers a digital signal to the first transfer circuit; Each of the memories transfers a digital signal to the second transfer circuit, the test signal supply unit supplies the first test signal to the plurality of first memories, and the plurality of second memories. After the second test signal is supplied to the first transfer circuit, the first transfer circuit continuously transfers the digital signal held in each of the plurality of first memories to the output comparison unit, and the second transfer The circuit is a digital signal held in the plurality of second memories. It was continuously transferred to the output comparator unit,
The output comparison unit compares the expected value with each of the first digital signal transferred from the first transfer circuit and the second digital signal transferred from the second transfer circuit. The analog-digital conversion circuit is characterized in that:

Another embodiment is a comparator for outputting a comparison result signal indicating a comparison result between the analog signal and the reference signal, a memory for holding the digital signal based on the comparison result signal, a plurality of circuit units each comprising Yes, and the analog signal an analog-digital converter into a digital signal, with each of said plurality of circuit sections includes a first memory or the second memory as the memory, the plurality of circuit portions comprising a plurality of said first memory and a plurality of the second memory, to each of the plurality of first memory supplies the first test signal for holding the first digital signal, said to each of the plurality of second memory, and a test signal supply unit for supplying subjected to a second test signal for holding the second digital signals of different signal values from said first digital signal, Comprising a force comparing unit, and a transfer unit, the transfer unit includes a first and a second transfer circuit for transferring digital signals the first and second memory are respectively held in the output comparator unit, The plurality of first memories include the first memory for transferring a digital signal to the first transfer circuit, and the first memory for transferring a digital signal to the second transfer circuit, The plurality of second memories include the second memory that transfers a digital signal to the first transfer circuit, and the second memory that transfers a digital signal to the second transfer circuit, and the test After the signal supply unit supplies the first test signal to the plurality of first memories and supplies the second test signal to the plurality of second memories, the first transfer circuit includes the first test signal. 1 outputs the digital signal held in the memory The digital signal held in the second memory after being transferred to the comparison unit is transferred to the output comparison unit, and the second transfer circuit transfers the digital signal held in the first memory to the output comparison unit. Later, the digital signal held in the second memory is transferred to the output comparison unit, and the output comparison unit receives the first digital signal transferred from the first transfer circuit and the second transfer circuit. The first digital signal transferred is compared, and the second digital signal transferred from the first transfer circuit is compared with the second digital signal transferred from the second transfer circuit. The analog-digital conversion circuit is characterized in that:

  According to the present invention, for example, the presence or absence of a short circuit failure between memories can be inspected.

Schematic diagram illustrating an example of the configuration of an imaging apparatus according to the first embodiment Schematic diagram showing an example of the configuration and operation of a pixel related to Example 1 Schematic diagram illustrating an example of the operation of the comparator and the selection circuit in the normal mode according to the first embodiment. Schematic diagram showing an example of the operation of the comparator and the selection circuit in the inspection mode according to the first embodiment. Timing chart of an example of operations of the column memory, the horizontal transfer unit, and the horizontal scanning unit in each of the normal mode and the inspection mode according to the first embodiment Schematic diagram illustrating an example of the configuration of an imaging apparatus according to the second embodiment FIG. 9 is a timing chart illustrating an example of operations of the column memory, the horizontal transfer unit, and the horizontal scanning unit in the normal mode according to the second embodiment. FIG. 5 is a timing diagram illustrating an example of operations of the comparator and the selection circuit in the inspection mode 1 and the inspection mode 2 according to the second embodiment. FIG. 6 is a timing chart illustrating an example of operations of the column memory, the horizontal transfer unit, and the horizontal scanning unit in the inspection mode 1 and the inspection mode 2 according to the second embodiment. Schematic diagram showing an example of the configuration of the memory unit related to Example 3 and Example 4 Schematic diagram illustrating an example of the configuration of an imaging system according to the fifth embodiment

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  This embodiment relates to an imaging apparatus having a column ADC. Hereinafter, the configuration of the imaging apparatus of the present embodiment will be described with reference to FIG.

  The present embodiment includes a pixel unit 200 and a vertical scanning unit 202 as an imaging unit. In the pixel portion 200, a plurality of columns 201 and a plurality of rows of pixels 201 that convert light incident on the imaging device into an electrical signal that is an analog signal are arranged. The pixel 201 includes a photoelectric conversion unit that performs photoelectric conversion that converts incident light into electric charges. The vertical scanning unit 202 selects a row obtained by dividing the pixel unit 200 in the horizontal direction by sequentially setting the signal levels of the vertical selection signal lines 203 and 204 to a high level (hereinafter referred to as an H level). That is, the pixels 11 to 18 are selected when the signal level of the vertical selection signal line 203 becomes H level. Similarly, when the signal level of the vertical selection signal line 204 becomes H level, the pixels 21 to 28 are selected. The electrical signal accumulated in the pixels constituting the row selected by the vertical scanning unit 202 is output from each of the pixels 11 to 18 to each of the signal lines 101 to 108 in units of rows. An electric signal output to the signal line is called a pixel signal.

  The pixel illustrated in FIG. 2A will be described as an example of a pixel that outputs a pixel signal. 2A partially shows the pixels 11 to 18, 21 to 28 of 2 rows and 8 columns of the pixel unit 200, the vertical scanning unit 202, and the signal lines 101 to 108 shown in FIG. is there. A specific configuration of the pixel 201 included in the pixel portion 200 is shown in the pixel 11. The pixel 201 includes a photoelectric conversion unit 501, a transfer MOS transistor 502, a reset MOS transistor 503, a floating diffusion unit (hereinafter referred to as an FD unit) 504, an amplification MOS transistor 505, and a selection MOS transistor 506. The photoelectric conversion unit 501 converts incident light into electric charges. Here, a photodiode is shown as an example. The transfer MOS transistor 502 transfers the charge of the photodiode 501 to the FD unit 504. The gate of the transfer MOS transistor 502 and the vertical scanning unit 202 that scans the pixels 201 row by row are connected via a transfer signal line 508.

  The FD portion 504 is electrically connected to the gate of the amplification MOS transistor 505. The amplification MOS transistor 505 amplifies and outputs a signal based on the charge of the FD unit 504. The power supply voltage Vdd is supplied to the drain of the amplification MOS transistor 505, and the source is electrically connected to the source of the selection MOS transistor 506. The selection MOS transistor 506 is provided in an electrical path between the amplification MOS transistor 505 and the signal line 101, and the gate is electrically connected to the vertical scanning unit 202 via the vertical selection signal line 203.

  The reset MOS transistor 503 has a source electrically connected to the FD unit 504 and a drain supplied with the power supply voltage Vdd. That is, the drain voltages of the amplification MOS transistor 505 and the reset MOS transistor 503 are set to a common power supply voltage Vdd. The gate of the reset MOS transistor 503 is electrically connected to the vertical scanning unit 202 via the reset signal line 507. The reset MOS transistor 503 resets the potential of the FD unit 504 when a reset pulse is applied from the vertical scanning unit 202. The pixel signal output from the amplification MOS transistor 505 is output to the signal line 101 via the selection MOS transistor 506.

  The signal lines 101 to 108 are connected to the column ADC. The column ADC of this embodiment includes a comparison unit 210 including a plurality of columns of comparators 301 to 308, a selection unit including selection circuits 121 to 128, and a memory unit 230 including a plurality of column memories 401 to 408. Each of the comparators 301 to 308 is electrically connected to signal lines 101 to 108 for transmitting an analog signal and a lamp voltage supply unit 212. The ramp voltage supply unit 212 generates a ramp voltage rmp and supplies it to the comparators 301 to 308 via the ramp signal line 213. The ramp voltage rmp is a reference signal that is compared with an analog signal transmitted through the signal lines 101 to 108. The comparators 301 to 308 output comparison result signals indicating the comparison results of the analog signal and the ramp voltage rmp to the selection circuits 121 to 128 via the comparator output lines 111 to 118, respectively. The selection circuits 121 to 128 are further electrically connected to the column memories 401 to 408 and the test signal supply unit 221 via the test signal supply lines 214 and 215, respectively. The circuit unit includes a column memory and a comparator. For example, the circuit section in the first column as counted from the left in FIG. 1 includes a column memory 401 and a comparator 301. The column ADC of the present embodiment is provided with eight columns of circuit portions arranged side by side. That is, the column memories 401 to 408 are provided side by side, and similarly, the comparators 301 to 308 are also provided side by side. The test signal supply unit 221 supplies the first test signal Ctr1, the second test signal Ctr2, and the mode selection signal SEL to the selection circuits 121 to 128. The selection circuits 121 to 128 select one of the comparators 301 to 308 and the first and second test signals Ctr1 and Ctr2 according to the signal of the mode selection signal SEL and select the selection circuit output line 131. Are output to the column memories 401 to 408 via .about.138. A horizontal transfer unit 240 is further electrically connected to the column memories 401 to 408 via column memory output lines 141 to 148. A horizontal selection signal from the horizontal scanning unit 250 is supplied to the horizontal transfer unit 240 via horizontal selection signal lines 151 to 158. Based on the horizontal selection signal supplied from the horizontal scanning unit 250, the digital signals stored in the column memories 401 to 408 are output to the horizontal transfer unit 240. The digital signals stored in the column memories 401 to 408 are output to the output signal line 290 by the horizontal transfer unit 240. The determination unit 300 reads the signal output to the output signal line 290. The determination unit 300 is an example of an output comparison unit. A memory (not shown) included in the determination unit 300 stores a digital signal based on a test signal supplied from the test signal supply unit 221 to the determination unit 300 via the determination unit supply line 216, and is used as a reference for determining whether there is a failure. Is expected value. The determination unit 300 compares this expected value with the signal output to the output signal line 290 to determine a failure.

  Next, the operation of the pixels included in the pixel portion 200 will be described with reference to the timing chart illustrated in FIG.

  PSEL shown in FIG. 2B is a pulse applied to the gate of the selection MOS transistor 506 via the vertical selection signal line 203. PRES is a reset pulse applied to the gate of the reset MOS transistor 503 via the reset signal line 507. PTX is a pulse applied to the gate of the transfer MOS transistor 502 via the transfer signal line 508. Vfd represents the potential of the FD portion 504, and Vline represents the potential of the signal line 101.

  At time t_a, PRES is at a high level (hereinafter referred to as H level), and PTX is at a low level (hereinafter referred to as L level). The pixel signal amplified by the amplification MOS transistor 505 is output to the signal line 101 by turning on the selection MOS transistor 506 by setting the PSEL in the selected pixel row to the H level.

  At time t_a, PRES is in the H level state, so the FD unit 504 is reset. A pixel signal based on the reset potential of the FD unit 504 is amplified by the amplification MOS transistor 505 and output to the signal line 101 via the selection MOS transistor 506.

  By resetting PRES to L level at time t_b, the reset of the FD unit 504 is released.

  By setting PTX to H level at time t_c and PTX to L level at time t_d, the charge accumulated in the photodiode 501 is transferred to the FD portion 504.

  A signal based on the potential of the FD unit 504 at this time is amplified and output by the amplification MOS transistor 505, and a pixel signal is output to the signal line 101.

  By setting PRES to H level again at time t_e, the potential of the FD portion 504 is reset. The vertical scanning unit 202 selects the pixels 11 to 18 in the first row and outputs pixel signals, and then selects the pixels 21 to 28 in the second row. Then, the same operation as the pixels 11 to 18 in the first row is performed, and pixel signals are output to the pixels 21 to 28 in the second row.

  Next, the operation of the column ADC included in the imaging apparatus illustrated in FIG. 1 will be described with reference to FIG. FIG. 3 illustrates the operation of the first to fourth columns, that is, the columns including the comparators 301 to 304 among the column ADCs included in the imaging apparatus illustrated in FIG.

  The image pickup apparatus of the present embodiment is characterized in that it can operate in two modes, a normal mode and an inspection mode, in which signals input to the column memories 401 to 408 are different. The normal mode here refers to a mode in which digital signals obtained by AD converting pixel signals are written in the column memories 401 to 408. On the other hand, the inspection mode refers to a mode in which the test signals Ctr1 and Ctr2 are written in the column memories 401 to 408 without depending on the light incident on the imaging device. In the inspection mode, the column memories 401 to 408, the horizontal transfer unit 240, and the horizontal scanning unit 250 are inspected. That is, this is an example of a memory inspection mode in which at least the column memory is inspected.

  First, the normal mode will be described.

  In response to the mode selection signal SEL supplied by the test signal supply unit 221, the selection circuits 121 to 124 output the signals of the comparator output lines 111 to 114 and the signals of the test signals Ctr 1 and Ctr 2 to the selection circuit output lines 131 to 134. That is, for example, the selection circuit 121 outputs the signal of the comparator output line 111 and one of the first and second test signals Ctr1 and Ctr2 to the selection circuit output line 131.

  In the normal mode, the selection circuits 121 to 124 output the signals of the comparator output lines 111 to 114 to the selection circuit output lines 131 to 134, respectively.

  The ramp voltage supply unit 212 increases the ramp voltage rmp for comparison with the signal levels of the signal lines 101 to 108 corresponding to the analog signals during the period from time t0 to time t5. That is, the lamp voltage rmp changes depending on time. Focusing on the comparator 301 in the first column, the analog signal transmitted through the signal line 101 is compared with the magnitude of the ramp voltage rmp input through the ramp signal line 213. When the ramp voltage rmp becomes larger than the analog signal transmitted by the signal line 101 at time t1, the signal level of the comparator output line 111 changes. Note that the signal level of the comparator output line 111 is a comparison result signal indicating the comparison result between the analog signal and the ramp signal output from the comparator 301.

  In the timing diagram illustrated in FIG. 3, the signal levels of the analog signals transmitted through the signal lines 101 to 104 are different from each other. Therefore, the comparator outputs of the comparators 302 to 304 do not change at time t1, and the time at which each comparator output changes differs depending on the signal level of the supplied analog signal.

  The column including the comparators 301 to 304 has been described above as an example, but the other comparators 305 to 308 are also operated in the same manner as the comparators 301 to 304. Therefore, in the normal mode, the comparator outputs of the comparators 301 to 308 are input to the memory unit 230 via the comparator output lines 111 to 118.

  The periods T1 to T4 illustrated in FIG. 3 represent periods from the time t0 when the ramp voltage rmp starts to rise until the comparator outputs of the comparators 301 to 304 change. The memory unit 230 counts the period from the time t0 until the comparator output changes with the clock signal. A count value (count signal), which is a count result obtained by counting the time from the start of counting with the clock signal until the change of the signal of the comparator output with the clock signal, is stored. This count value is written in each of the column memories 401 to 404 as a digital signal corresponding to the signal level of the analog signal transmitted by each of the signal lines 101 to 104. Hereinafter, for simplification of description, digital signals corresponding to the signal levels of the analog signals transmitted by the signal lines 101 to 104 are represented by D1 to D4, respectively.

  FIG. 5A is a timing diagram illustrating operations of the memory unit 230, the horizontal transfer unit 240, and the horizontal scanning unit 250 in the normal mode.

  Assuming that the signal level of the horizontal selection signal line 151 supplied by the horizontal scanning unit 250 is High level (hereinafter referred to as H level), horizontal transfer is performed from the column memory 401 to the horizontal transfer unit 240 via the column memory output line 141. A signal is output to the unit 240. Since the column memory 401 stores the digital signal D 1, the digital signal D 1 is output from the horizontal transfer unit 240 to the output signal line 290. Similarly, the digital signals D1 to D4 stored in the column memories 401 to 404 are sequentially output to the output signal line 290 by setting the signal levels of the horizontal selection signal lines 152 to 154 to the H level.

  Next, the inspection mode will be described.

  FIG. 4 is a timing chart illustrating operations of the selection circuits 121 to 124 and the test signal supply unit 221 in the inspection mode.

  In the inspection mode, the selection circuits 121 to 124 output any one of the test signals Ctr1 and Ctr2 to the column memories 401 to 404 via the selection circuit output lines 131 to 134 in response to the mode selection signal SEL. In the inspection mode, the mode selection signal SEL is output so that different test signals are applied to adjacent column memories. Therefore, in FIG. 1, when the first test signal Ctr1 is output to the selection circuit output lines 131 and 133 in the odd columns counted from the left, the second circuit is applied to the selection circuit output lines 132 and 134 in the even columns. A test signal Ctr2 is output. That is, the first test signal Ctr1 and the second test signal Ctr2 are alternately input to the column memories of a plurality of columns. Therefore, regardless of the signal levels of the comparator output lines 111 to 114, the first test signal Ctr1 is stored in the odd column memory 401, 403, and the second test signal is stored in the even column memory 402, 404. Ctr2 is input. That is, the second test signal Ctr2 is input to the column memory located next to the column memory to which the first test signal Ctr1 is input. In this case, the odd-numbered column memory 401, 403 is the first memory, and the even-numbered column memory 402, 404 is the second memory. Each of the first memories 401 and 403 is included in a first circuit part that is a part of the circuit part, and each of the second memories 402 and 404 is a second part that includes at least a part other than the first circuit part. Is included in the circuit section.

  The periods T1 ′ and T2 ′ illustrated in FIG. 4 represent periods from the time t0 when the clock signal counting starts to the time when the signal values of the test signals Ctr1 and Ctr2 change. The memory unit 230 counts this period with a clock signal, and stores a count value as a counting result, so that digital signals corresponding to the periods T1 ′ and T2 ′ represented by the test signals Ctr1 and Ctr2 are written. Hereinafter, for simplification of description, digital signals corresponding to the test signals Ctr1 and Ctr2 are represented by D1 ′ and D2 ′, respectively. The digital signal D1 ′ and the digital signal D2 ′ are digital signals having different signal values.

  The operation described above is similarly performed for the column memories 405 to 408. Therefore, the digital signal D1 ′ is written in the column memories 401, 403, 405, and 407 of the odd columns, and the digital signal D2 ′ is written in the column memories 402, 404, 406, and 408 of the even columns.

  FIG. 5B is a timing diagram illustrating operations of the memory unit 230, the horizontal transfer unit 240, and the horizontal scanning unit 250 in the inspection mode.

  The signal level of the horizontal selection signal line 151 supplied by the horizontal scanning unit 250 is set to H level, the digital signal D1 ′ stored in the column memory 401 is transferred to the horizontal transfer unit 240, and the digital signal D1 ′ is transferred to the output signal line 290. Is output.

  Similarly, when the signal level of the horizontal selection signal line 152 is H level, the digital signal D2 ′ stored in the column memory 402 is output to the output signal line 290. Similarly, by setting the signal levels of the horizontal selection signal lines 152 to 154 to the H level, the digital signals D1 ′, D2 ′, D1 ′, and D2 ′ stored in the column memories 401 to 404 are output to the output signal line 290. Is done.

  The determination unit 300 illustrated in FIG. 1 performs determination processing using the digital signals D1 ′ and D2 ′ corresponding to the test signals Ctr1 and Ctr2 as expected values for the digital signal output to the output signal line 290. If the digital signal output to the output signal line 290 is different from the expected value, it can be determined that there is a failure. Therefore, by writing different digital signals to the adjacent column memories, it is possible to inspect whether there is a short failure between the adjacent column memories.

  In addition, in the column ADC included in the imaging apparatus of the present embodiment, it is possible to inspect whether there is a stuck-at fault. For example, the data width stored in each of the column memories 401 to 408 is 8 bits. As an example, two inspection modes are implemented: a step in which digital signals represented by D1 ′ and D2 ′ are set to 10101010 and 01010101, and a step in which 01010101 and 10101010 are set, respectively. As a result, the determination unit 300 can determine whether or not a stuck-at fault has occurred by checking that each memory bit configuring the memory unit 230 transitions from 0 → 1, 1 → 0.

  Further, by setting the digital signal transferred by the horizontal transfer unit 240 to a different value in the adjacent column memory, it is possible to inspect the delay failure of the horizontal transfer unit 240.

  Further, when the horizontal scanning unit 250 sequentially selects and outputs the column memories 401 to 408, if the horizontal scanning unit 250 has no failure, the digital signals D1 ′ and D2 ′ are alternately output to the output signal line 290. . If a failure occurs in the horizontal scanning unit 250, D1 ′ and D2 ′ are not alternately output to the output signal line 290. Therefore, the determination unit 300 according to the present embodiment can also check for a failure in the horizontal scanning unit 250 based on whether the digital signals D1 ′ and D2 ′ are alternately output.

  In the present embodiment, the test signal is supplied from the test signal supply unit 221 to the memory unit 230 via the selection circuits 121 to 128. The present embodiment is not limited to this mode, and the comparison unit 210 operates as the test signal supply unit 221 and the selection circuits 121 to 128 can be omitted. That is, the analog signals transmitted by the signal lines 101 to 108 are set as follows. When different digital signals are written between adjacent column memories, the analog signals transmitted by the signal lines 101, 103, 105, and 107 change the comparison outputs of the comparators 301, 303, 305, and 307 at time t1 ′. A level signal may be used. Similarly, the pixel signals transmitted by the signal lines 102, 104, 106, and 108 may be signals having a level at which the comparison outputs of the comparators 302, 304, 306, and 308 change at time t2 ′. That is, the first comparator is the comparators 301, 303, 305, and 307, and the second comparator is the comparators 302, 304, 306, and 308. In order to output such an analog signal as a pixel signal from a pixel, the potential of the FD portion 504 may be set to a different potential between adjacent pixels. To do this, for example, an inspection image including a striped test pattern that captures a black region of the pixel 11 and a white region of the pixel 12 is captured. When the inspection image is captured and the pixel is output, a pixel signal that is an inspection signal is output to the signal lines 101 to 108. Similarly to the normal mode, the pixel signal that is the inspection signal is AD-converted, the memory unit 230 stores the digital signal based on the pixel signal that is the inspection signal, and the digital signal held by the memory unit 230 is read to the output signal line 290. The determination unit 300 compares the digital signal transmitted to the output signal line 290 with the digital signal obtained when the black image is captured or the digital signal obtained when the white image is captured. Can be inspected.

  In the present embodiment, the mode of writing different digital signals between adjacent column memories has been described. In this embodiment, writing different digital signals is not limited to adjacent column memories. That is, the first test signal may be supplied to a part of the plurality of column memories and the test signal different from the first test signal may be supplied to another part of the plurality of column memories. Also in this embodiment, by comparing the digital signal input to the column memory with the digital signal stored in the determination unit 300, the presence or absence of a short fault in the column memory can be inspected.

  In the present embodiment, the mode in which two digital signals are written in the column memory has been described. The present embodiment is not limited to this, and a plurality of different digital signals may be written in a plurality of columns of memory using three or more test signals.

  The column ADC described in the present embodiment has been described as a mode in which the ramp voltage rmp changes depending on time and is compared with an analog signal. The column ADC of the present embodiment is not limited to this form, and may be a column ADC of another scheme such as a successive approximation type, a cyclic type, a delta-sigma type, and a sub-ranging type. That is, any comparator may be used as long as it outputs a comparison result signal indicating a comparison result obtained by comparing the analog signal with the reference signal.

  Further, in this embodiment, a configuration in which a plurality of comparators are provided is shown. However, for example, a plurality of comparators are provided so that the column ADC illustrated in FIG. 1 is rotated 90 ° clockwise or counterclockwise. It may be a different form. That is, an ADC having a plurality of comparators may be used.

  Further, in this embodiment, the column memory for transferring the stored signal is selected by setting the signal level of the horizontal selection signal lines 151 to 158 to the H level, and is set to the non-selection by setting the signal level to the L level. explained. However, conversely, a column memory for transferring a signal stored at the L level may be selected and non-selected at the H level.

  The test signal supply unit 221 may be provided on the same substrate as the substrate on which the selection circuits 121 to 128 are provided. Further, the test signal supply unit 221 may be provided outside the substrate on which the selection circuits 121 to 128 are provided. More specifically, a switch terminal is provided in each wiring for supplying the mode selection signal SEL and the test signals Ctr1 and Ctr2, and the test signal supply unit 221 and the memory unit 230 are electrically connected via the switch terminals. It may be. At this time, the mode selection signal SEL is L level when the electrical connection between the test signal supply unit 221 and the memory unit 230 is cut off, and the test signal supply unit 221 and the memory unit 230 are electrically connected. When it is, the H level may be set.

  Similarly, the determination unit 300 may be provided on the same substrate as the substrate on which the memory unit 230 is provided. The determination unit 300 may be provided outside the substrate on which the memory unit 230 is provided. In other words, the output signal line 290 may be provided with a switch terminal, and the determination unit 300 and the output signal line 290 may be electrically connected via the switch terminal. In the case of this form, the electrical connection between the determination unit 300 and the output signal line 290 can be switched. Therefore, the determination unit 300 can be electrically connected to the output signal line 290 when performing the inspection mode, and the electrical connection between the determination unit 300 and the output signal line 290 can be interrupted when performing the normal mode.

  Further, the test mode may be performed by electrically connecting a tester having the test signal supply unit 221 and the determination unit 300 to terminals provided in the memory unit 230 and the output signal line 290, respectively. .

  In the present embodiment, a configuration in which the determination unit 300 is used as an example of the output comparison unit is shown. The output comparison unit does not need to determine whether or not there is a failure, and may be any unit that compares the test signal stored in the output comparison unit with the signal output to the output signal line 290.

  In the present embodiment, the imaging unit having the pixel unit 200 and the vertical scanning unit 202 has been described as an example of the configuration for outputting an analog signal. This embodiment is not limited to an image pickup apparatus having an image pickup section, and can be suitably implemented as long as the apparatus has a configuration for supplying an analog signal to the comparison section 210 of a column ADC having a plurality of column memories. it can.

  The present embodiment will be described with a focus on differences from the first embodiment.

  The present embodiment is configured to perform horizontal two-channel output that simultaneously outputs two columns of digital signals written in the memory unit 230, and the first embodiment is mainly inspected for a delay fault in the horizontal transfer unit 240. Different. Hereinafter, with reference to FIG. 6, the difference between the present embodiment and the first embodiment will be described.

  FIG. 6 is a block diagram of an example of the imaging apparatus according to the present embodiment. In the selection circuits 121 to 128, any one of the four test signal supply lines 214 to 217 is electrically connected in order one by one for each column. Signals from the selection circuits 121 to 128 are output to the selection circuit output lines 131 to 138.

  The horizontal transfer unit 240 includes a first transfer circuit 241 and a second transfer circuit 242. The first transfer circuit 241 outputs a digital signal to the first output signal line 290, and the second transfer circuit 242 outputs a digital signal to the second output signal line 291.

  In the imaging apparatus of the present embodiment, in addition to the normal mode for converting an analog signal into a digital signal, the inspection mode 1 is a mode for inspecting the memory unit 230, and the inspection mode 2 is a mode for mainly inspecting the horizontal transfer unit 240. These two modes can be operated in a time-sharing manner.

  First, the normal mode will be described.

  Since the operations of the comparison unit 210, the lamp voltage supply unit 212, and the memory control unit 220 in the normal mode are the same as those in the first embodiment, the timing diagram is omitted.

  FIG. 7 is a timing diagram illustrating operations of the memory unit 230, the horizontal transfer unit 240, and the horizontal scanning unit 250 in the normal mode.

  The horizontal transfer unit 240 includes a first transfer circuit 241 and a second transfer circuit 242. When the signal level of the horizontal selection signal line 151 output from the horizontal scanning unit 250 is H level, the digital signal D1 stored in the column memory 401 is transferred to the first transfer circuit 241, and the second transfer circuit 242 is transferred. Is transferred with the digital signal D2 stored in the column memory 402. As a result, the digital signal D1 is output to the first output signal line 290. Similarly, the digital signal D2 is output to the second output signal line 291. Next, by setting the signal level of the horizontal selection signal line 152 to the H level, digital signals stored in the column memories 403 and 404 are similarly applied to the first output signal line 290 and the second output signal line 291. D3 and D4 are output.

  Next, an inspection mode 1 that is a memory inspection mode for inspecting the memory unit 230 will be described.

  FIG. 8A shows a timing diagram illustrating the operation of the test signal supply unit 221 and the selection circuits 121 to 128 in the inspection mode 1.

  Hereinafter, the operation of the selection circuits 121 to 124 in the first to fourth columns will be described as an example. The selection circuit 121 in the first column outputs the signal level of the comparator output line 111 to the column memory 401 when the mode selection signal tst is at the L level, and the test signal Ctr1 when the mode selection signal tst is at the H level. The selection circuit 122 in the second column outputs the signal level of the comparator output line 112 to the column memory 402 when the mode selection signal tst is at the L level, and the test signal Ctr2 when the mode selection signal tst is at the H level. The selection circuit 123 in the third column outputs the signal level of the comparator output line 113 to the column memory 403 when the mode selection signal tst is at the L level, and the test signal Ctr3 when the mode selection signal tst is at the H level. The selection circuit 124 in the fourth column outputs the signal level of the comparator output line 114 to the column memory 404 when the mode selection signal tst is at the L level, and the test signal Ctr4 when the mode selection signal tst is at the H level. The operations of the selection circuits 125 to 128 in the fifth to eighth columns are the same as the operations of the selection circuits 121 to 124, respectively.

  The operations from when the pixel unit 200 outputs an analog signal to the signal lines 101 to 104 until the comparators 301 to 304 output the comparison result signals to the comparator output lines 111 to 114 are the same as in the first embodiment. Description is omitted.

  In the inspection mode 1, since the mode selection signal tst is at the H level, the selection circuit 121 in the first column outputs the test signal Ctr1 to the column memory 401 via the selection circuit output line 131. Similarly, the selection circuits 122 to 124 in the second to fourth columns output the test signals Ctr2 to Ctr4 to the column memories 402 to 404 via the selection circuit output lines 132 to 134, respectively.

  In the inspection mode 1, the test signals Ctr1 and Ctr3 can be the same test signal. Similarly, the test signals Ctr2 and Ctr4 can be the same test signal. A period T1 ′ illustrated in FIG. 8A represents a period from the time t0 when the ramp voltage rmp starts to rise until the test signals Ctr1 and Ctr3 change. A period T2 ′ represents a period from when the ramp voltage rmp starts to rise until the test signals Ctr2 and Ctr4 change.

  The memory unit 230 counts the clock signal input to the counter during the period from the time t0 to when the test signals Ctr1 to Ctr4 change, and stores the count value that is the count result of the clock signal. As a result, digital signals corresponding to the periods T1 ′ and T2 ′ represented by the test signals Ctr1 to Ctr4 are written. Hereinafter, digital signals corresponding to the test signals Ctr1 and Ctr3 are represented as D1 ′, and digital signals corresponding to the test signals Ctr2 and Ctr4 are represented as D2 ′. These digital signals D1 ′ and D2 ′ are stored in advance in a memory (not shown) in the determination unit 300, and are set as expected values for determining a failure as will be described later.

  Through the operation described above, the digital signal D1 ′ is written in the odd-numbered column memories 401, 403, 405, and 407 from the left in FIG. 6, and the even-numbered column memories 402, 404, 406, and 408 are written. Is written with a digital signal D2 ′. The first memories in the inspection mode 1 are column memories 401, 403, 405, and 407, and the second memories are column memories 402, 4094, 406, and 408.

  FIG. 9A is a timing diagram illustrating operations of the memory unit 230, the horizontal transfer unit 240, and the horizontal scanning unit 250 in the inspection mode 1.

  When the signal level of the horizontal selection signal line 151 output from the horizontal scanning unit 250 is set to H level, the digital signal D 1 ′ stored in the column memory 401 is transferred to the first transfer circuit 241. The digital signal D <b> 2 ′ stored in the column memory 402 is transferred to the second transfer circuit 242. Thus, the digital signal D1 ′ is output to the first output signal line 290, and the digital signal D2 ′ is output to the second output signal line 291. Similarly, the digital signals D1 ′ stored in the column memories 403, 405, and 407 are output to the first output signal line 290 by sequentially setting the signal levels of the horizontal selection signal lines 152 to 154 to the H level. The Further, the digital signal D2 ′ stored in the column memories 404, 406, and 408 is output to the second output signal line 291.

  In the inspection mode 1, the signal output to the first output signal line 290 is always the digital signal D1 ′, and the signal output to the second output signal line 291 is always the digital signal D2 ′. Accordingly, different digital signals D1 ′ and D2 ′ can be written in adjacent memories. Signals output by the horizontal transfer unit 240 to the output signal lines 290 and 291 are fixed to digital signals D1 ′ and D2 ′, respectively.

  In the determination unit 300 illustrated in FIG. 6, the digital signals D1 ′ and D2 ′ stored in a memory (not illustrated) included in the determination unit 300 are compared as expected values with respect to the signals output to the output signal lines 290 and 291. Determine if there is a failure. When the signals output to the output signal lines 290 and 291 are different from the expected values, it can be determined as a failure. Therefore, by writing different digital signals to adjacent memories, it is possible to check for a short circuit failure in adjacent memories.

  In addition, in the column ADC included in the imaging apparatus of the present embodiment, it is possible to inspect whether there is a stuck-at fault. For example, the data width stored in the column memories 401 to 408 is 8 bits. As an example, two inspection modes, a step of setting signal values of digital signals represented by D1 ′ and D2 ′ to 10101010 and 01010101 and a step of setting 01010101 and 10101010, respectively, are performed. Thereby, the transition from 0 → 1, 1 → 0 of each memory bit constituting the memory unit 230 can be inspected, and the presence or absence of a stuck-at fault in the memory unit 230 can be inspected.

  Next, inspection mode 2 that is a transfer unit inspection mode for mainly inspecting the horizontal transfer unit 240 will be described.

  FIG. 8B is a timing diagram illustrating operations of the comparison unit 210, the lamp voltage supply unit 212, the test signal supply unit 221, and the selection circuits 121 to 128 in the inspection mode 2.

  Although the mode selection signal tst is at the H level in the inspection mode 1, the mode selection signal is also set to the H level in the inspection mode 2. The difference between the inspection mode 2 and the inspection mode 1 will be described. In the inspection mode 1, the digital signal D1 ′ corresponding to the test signals Ctr1 and Ctr3 is stored in the column memories 401, 403, 405, and 407 of the odd columns. Similarly, the digital signals D2 ′ corresponding to the test signals Ctr2 and Ctr4 are stored in the column memories 402, 404, 406, and 408 of even-numbered columns. On the other hand, in the inspection mode 2, as shown in FIG. 8B, it is preferable that the test signals Ctr1 and Ctr2 are the same test signal. Similarly, the test signals Ctr3 and Ctr4 are preferably the same test signal. The operation in which the column memories 401 to 408 store the digital signal D1 ′ corresponding to the test signals Ctr1 and Ctr2 and the digital signal D2 ′ corresponding to the test signals Ctr3 and Ctr4 is common to the inspection mode 1 and the inspection mode 2. Therefore, the column signals 401, 402, 405, and 406 store the digital signal D1 ′, and the column memories 403, 404, 407, and 408 store the digital signal D2 ′. That is, the first memory in the inspection mode 2 is the column memories 401, 402, 405, and 406, and the second memory is the column memories 403, 404, 407, and 408.

  FIG. 9B is a timing diagram illustrating operations of the memory unit 230, the horizontal transfer unit 240, and the horizontal scanning unit 250 in the inspection mode 2.

  When the signal level of the horizontal selection signal line 151 output from the horizontal scanning unit 250 is set to H level, digital signals stored in the column memories 401 and 402 are respectively stored in the first transfer circuit 241 and the second transfer circuit 242. D1 'is output. Subsequently, when the signal level of the horizontal selection signal line 152 is set to H level, the digital signal D2 ′ stored in the column memories 403 and 404 is output. Similarly, by sequentially setting the signal levels of the horizontal selection signal lines 153 to 154 to the H level, the digital signals D1 ′ and D2 ′ are repeatedly output to the output signal lines 290 and 291.

  In the determination unit 300 illustrated in FIG. 6, the digital signals D1 ′ and D2 ′ stored in a memory (not illustrated) included in the determination unit 300 are compared as expected values with respect to the signals output to the output signal lines 290 and 291. Determine if there is a failure. That is, it is inspected whether the digital signals D1 ′ and D2 ′ are alternately output for the signals output to the output signal lines 290 and 291, respectively. In the inspection mode 1, since the first transfer circuit 241 and the second transfer circuit 242 output only one of the digital signals D1 ′ and D2 ′, respectively, even if a stuck-at failure occurs in the horizontal transfer unit 240, the inspection is performed. In mode 1, it is difficult to find stuck-at faults. On the other hand, in this inspection mode 2, when the horizontal transfer unit 240 has a stuck-at fault, the digital signals D1 ′ and D2 ′ are not alternately output to the output signal line. Therefore, the stuck-at fault of the horizontal transfer unit 240 can be inspected.

  In addition, since digital signals having the same value are synchronously output to the output signal lines 290 and 291 in the inspection mode 2, the digital signals output from the output signal lines 290 and 291 are compared and output time is compared. If there is a deviation, it can be determined that the horizontal transfer unit 240 has a delay fault.

  Even in the case where a stuck-at failure has occurred in the horizontal scanning unit 250, the imaging apparatus of the present embodiment can be inspected. In the configuration in which the first transfer circuit 241 and the second transfer circuit 242 transfer digital signals in synchronization as in the present embodiment, the horizontal scanning unit 250 is degenerated in both the inspection mode 1 and the inspection mode 2. In the case of failure, a digital signal having a value different from that of the digital signal to be originally transferred is simultaneously transferred to both of the output signal lines 290 and 291. Alternatively, a blank period in which no digital signal is transferred occurs simultaneously on both output signal lines 290 and 291. For example, when the signal level of the horizontal selection signal line 151 should be H level, when the horizontal scanning unit 250 is at L level due to a failure, the digital signals stored in the column memories 401 and 402 are both output signal lines 290 and 291. Not output. Therefore, when there is a period during which the digital signal is not transferred when both of the output signal lines 290 and 291 are present simultaneously when the digital signal is to be transferred, it can be determined that the horizontal scanning unit 250 has failed. Therefore, it is possible to inspect the stuck-at fault of the horizontal scanning unit 250.

  In the present embodiment, the inspection of the memory unit 230 and the horizontal transfer unit 240 can be performed by combining the inspection mode 1 for mainly inspecting the memory unit and the inspection mode 2 for mainly inspecting the horizontal transfer unit 240. . Further, in the configuration in which the first transfer circuit 241 and the second transfer circuit 242 transfer digital signals in synchronization, the horizontal scanning unit 250 can also be inspected. For example, when a failure of the memory unit 230 is not found in the inspection mode 1 and different digital signals are detected in the first output signal line 290 and the second output signal line 291 in the inspection mode 2, horizontal transfer is performed. It can be determined that a failure has occurred in one or both of the unit 240 and the horizontal scanning unit 250. Further, in the inspection mode 1 or the inspection mode 2, when there are simultaneously periods during which digital signals that should be originally transferred to both the output signal lines 290 and 291 are present, it can be determined that the horizontal scanning unit 250 has failed.

  Also in the inspection mode 2, if a short circuit failure occurs between the column memories 402 and 403, the column memories 404 and 405, or the column memories 406 and 407, the digital signal that each column memory should originally output Since a digital signal with a signal value different from that is output, a failure can be detected. Therefore, in inspection mode 2, it is possible to detect a short circuit failure between column memories supplied with different test signals. Therefore, inspection mode 2 may be used as column memory inspection instead of inspection mode 1.

  In the present embodiment, a mode has been described in which different digital signals are written to the memory unit 230 for each column or every two columns by the four test signals Ctr1 to Ctr4. However, a configuration in which five or more test signals are supplied and different digital signals are written in a plurality of columns may be employed. In addition, regardless of which order the inspection mode 1 and the inspection mode 2 are performed, it is possible to inspect for a short circuit failure in the column memories 401 to 408, a failure in the horizontal transfer unit 240, and the horizontal scanning unit 250.

  Further, for example, the test signals Ctr1 and 3 in the inspection mode 1 are described as the same signals as the test signals Ctr1 and Ctr2 in the inspection mode 2. The present embodiment is not limited to this form, and the inspection mode 1 may be the same signal in each pair of the test signals Ctr1 and Ctr3 and the pair Ctr2 and Ctr4. The inspection mode 2 may be the same signal in each of the pair of test signals Ctr1 and Ctr2 and the pair of Ctr3 and Ctr4. That is, the test signals used in the inspection modes 1 and 2 may not be common between the inspection modes 1 and 2, and the test signals corresponding to the digital signals D1 ′ and D2 ′ are used in the inspection mode 1. In such a case, test signals corresponding to the digital signals D3 ′ and D4 ′ may be used in the inspection mode 2.

  In the present embodiment, in the inspection mode 1, a mode in which different digital signals are written between adjacent column memories has been described. In this embodiment, writing different digital signals is not limited to adjacent column memories. That is, any form may be used as long as a plurality of different digital signals are written to a plurality of column memories. Also in this embodiment, the presence or absence of a short failure in the column memory can be inspected by comparing the digital signal input to the column memory with the digital signal stored in the column memory.

  In the inspection mode 1 of the present embodiment, the determination unit 300 compares the digital signals transmitted by the output signal lines 290 and 291 with the digital signals D1 ′ and D2 ′. However, the inspection mode 1 of the present embodiment may be configured such that the determination unit 300 compares the digital signal transmitted by one of the output signal lines 290 and 291. For example, when the determination unit 300 compares only the digital signal transmitted by the output signal line 290, if the digital signal to be transmitted by the output signal line 290 is D1 ′, the digital signal D1 ′ and the output signal line 290 are transmitted. The determination unit 300 compares the digital signal to be processed. At this time, for example, when a short circuit failure occurs in the column memory 401 and the column memory 402, the signal held in the column memory 401 is influenced by the digital signal held in the column memory 402 and is different from the digital signal D1 ′. It may become. Therefore, a period in which the digital signal transmitted by the output signal line 290 is different from the digital signal D1 ′ occurs, so that the determination unit 300 can determine a short circuit failure in the memory unit.

  In the present embodiment, the configuration in which the first transfer circuit 241 and the second transfer circuit 242 perform the transfer in synchronization has been described as an example. The present embodiment is not limited to the configuration in which one horizontal selection signal line is commonly connected to the first transfer circuit 241 and the second transfer circuit 242, but the first transfer circuit 241, Different horizontal selection signal lines are electrically connected to the second transfer circuits 242, and the transfer operations of the first transfer circuit 241 and the second transfer circuit 242 do not have to be synchronized. Even in this configuration, the inspection of the memory unit 230 and the horizontal transfer unit 240 can be performed by performing the inspection mode 1 and the inspection mode 2.

  The present embodiment will be described focusing on differences from the first embodiment.

  FIG. 10A shows an example of the configuration of the memory unit of the imaging apparatus according to the present invention.

  In this embodiment, column memories 1-401 to 1-408 having a counter function for counting clock signals for each column are arranged. Further, in order to overlap the AD conversion period and the horizontal transfer period, second stage column memories 2-401 to 2-408 for buffering digital signals stored in the column memories 1-401 to 1-408 are arranged. Yes. The second stage column memories 2-401 to 2-408 are third and fourth memories.

  The memory unit 230 includes a first memory area 232 and a second memory area 233. The clock signal supply unit 235 is electrically connected to the column memories 1-401 to 1-408 included in the first memory area 232 and supplies clock signals to the column memories 1-401 to 1-408. The transfer signal supply unit 234 is electrically connected to the column memories 2-401 to 2-408 included in the second memory area 233, and supplies transfer signals to the column memories 2-401 to 2-408.

  Hereinafter, the normal mode will be described.

  The selection circuits 121 to 128 output the signal levels of the comparator output lines 111 to 114 to the column memories 1-401 to 1-408 via the selection circuit output lines 131 to 138, respectively. The clock signal clk generated by the clock signal supply unit 235 is input to the column memories 1-401 to 1-408. In the column memories 1-401 to 1-408, a period defined by T 1 and T 2, which is a time from the time t 0 when the ramp voltage rmp starts to rise to the time when the signal level of the selection circuit output lines 131 to 138 changes ( Hereinafter, it is counted by the clock signal clk. The column memories 1-401 to 1-408 store count values that are the count results of the clock signals.

  Outputs of the column memories 1-401 to 1-408 are electrically connected to inputs of the column memories 2-401 to 2-408 via data lines 161 to 168, respectively. The column memories 2-401 to 2-408 receive the digital signals stored in the column memories 1-401 to 1-408 when the transfer signal mtx generated by the transfer signal supply unit 234 is at the H level. Transfer to ~ 2-408. The data lines 161 to 168 and the transfer signal supply unit 234 are inter-memory transfer units. After the digital signals are transferred to the column memories 2-401 to 2-408, the column memories 1-401 to 1-408 can again count the comparison period with the clock signal clk. The column memory output lines 141 to 148 electrically connected to the outputs of the column memories 2-401 to 2-408 are electrically connected to a horizontal transfer unit (not shown). By adopting the configuration exemplified in this embodiment, the AD conversion period represented by the comparison period and the horizontal transfer period represented by the period for outputting the digital signals stored in the column memories 2-401 to 2-408 are provided. Can be stacked. Thereby, the present embodiment can shorten the total period of the AD conversion period and the horizontal transfer period required for converting the pixel signals of a plurality of rows into a digital signal, as compared with the first embodiment.

  The inspection of the memory unit 230 can be performed in the same manner as in the first embodiment.

  In the inspection mode, the selection circuits 121 to 128 have the test signals Ctr1 and Ctr2 supplied from the test signal supply unit 221 inputted to the column memories 1-401 to 1-408, respectively. In the column memories 1-401 to 1-408, clocks T1 ′ and T2 ′, which are times from when the mode selection signal tst becomes H level to when the signal levels of the test signals Ctr1 and Ctr2 change, are clocked. Count with signal clk. The column memories 1-401 to 1-408 store count values that are the count results of the clock signals.

  By performing the inspection mode, the first memory area 232 and the second memory area 233 can be inspected for a stuck-at fault or a short-circuit fault between adjacent column memories in each memory area.

  The clock signal supply unit 235 and the transfer signal supply unit 234 may be provided on the same substrate as the substrate on which the memory unit 230 is provided. Further, the clock signal supply unit 235 and the transfer signal supply unit 234 may be provided outside the substrate on which the memory unit 230 is provided.

  The present embodiment will be described focusing on differences from the first embodiment.

  FIG. 10B shows an example of the memory unit of the imaging apparatus of the present embodiment.

  In the present embodiment, column memories 1-401 to 1-408 for storing count signals cnt are arranged, and further, column memory 1-401 to 1-408 includes second-stage column memories 2-401 to 2-408. Electrically connected. The column memories 1-401 to 1-408 constitute a first memory area 232, and the column memories 2-401 to 2-408 constitute a second memory area.

  The memory unit 230 includes a first memory area 232 and a second memory area 233. The count signal supply unit 236 counts clock signals from a clock signal supply unit (not shown), and generates a count signal cnt that is a count result. The count signal supply unit 236 is electrically connected to the column memories 1-401 to 1-408 included in the first memory area 232. The transfer signal supply unit 234 is electrically connected to the column memories 2-401 to 2-408 included in the second memory area 233, and supplies transfer signals to the column memories 2-401 to 2-408.

  Hereinafter, the normal mode will be described.

  The selection circuit output lines 131 to 138 are electrically connected to the column memories 1-401 to 1-408, respectively. The count signal cnt generated by the count signal supply unit 236 is input to the column memories 1-401 to 1-408. The count signal supply unit 236 starts counting from a time t0 when a ramp voltage rmp (not shown) starts increasing, and generates a count signal cnt. The column memories 1-401 to 1-408 take in the value of the count signal cnt at the time when the signal level of the selection circuit output lines 131 to 138 changes. The period represented by the time when the signal levels of all the selection circuit output lines change from time t0 is the comparison period in this embodiment.

  The outputs of the column memories 1-401 to 1-408 are electrically connected to the inputs of the column memories 2-401 to 2-408 via data lines 161 to 168, respectively. The column memories 2-401 to 2-408 receive the digital signals stored in the column memories 1-401 to 1-408 when the transfer signal mtx generated by the transfer signal supply unit 234 is at the H level. Transfer to ~ 2-408. The data lines 161 to 168 and the transfer signal supply unit 234 are inter-memory transfer units. After the digital signals are transferred to the column memories 2-401 to 2-408, the column memories 1-401 to 1-408 can capture the value of the count signal cnt again. Therefore, the AD conversion period and the horizontal transfer period can be overlapped. The column memory output lines 141 to 148 that are electrically connected to the outputs of the column memories 2-401 to 2-408 are output to the horizontal transfer unit that is electrically connected to the second memory area 233.

  The digital signals stored in the column memories 2-401 to 2-408 are output signals via the horizontal transfer unit 240 when the horizontal scanning unit 250 sequentially sets the signal levels of the horizontal selection signal lines 151 to 158 to the H level. Output on line 290.

  By adopting the configuration exemplified in this embodiment, the AD conversion period represented by the comparison period and the horizontal transfer period represented by the period for outputting the digital signals stored in the column memories 2-401 to 2-408 are provided. Can be stacked. Thereby, the output speed of the digital signal can be increased.

  The inspection mode for inspecting the memory unit can be performed in the same manner as in the first embodiment.

  Hereinafter, the inspection mode will be described.

  In the inspection mode, the count signal supply unit 236 starts counting when the mode selection signal tst becomes H level, and generates the count signal cnt. In the selection circuits 121 to 128, the test signals Ctr1 and Ctr2 supplied from the test signal supply unit 221 are input to the column memories 1-401 to 1-408, respectively. The column memories 1-401 to 1-408 take in the count signal cnt and store the count value at the time when the signal levels of the test signals Ctr1 and Ctr2 change. The stored count values are T1 ′ and T2 ′.

  The signals stored in the column memories 1-401 to 1-408 are output to the column memories 2-401 to 2-408, and then output by the horizontal scanning unit 250 via the horizontal transfer unit 240, as in the normal mode. The signal is output to the signal line 290.

  By performing the inspection mode, the first memory area 232 and the second memory area 233 can be inspected for a stuck-at fault or a short-circuit fault between adjacent column memories in each memory area.

  The count signal supply unit 236 and the transfer signal supply unit 234 may be provided on the same substrate as the substrate on which the memory unit 230 is provided. Further, the count signal supply unit 236 and the transfer signal supply unit 234 may be provided outside the substrate on which the memory unit 230 is provided.

  In these embodiments, examples in which the present invention is applied to an imaging apparatus have been described, but the present invention can also be applied to other apparatuses. In this case, analog signals to be converted into digital signals in such a device are input to the signal lines 101 to 108.

  An embodiment when the imaging apparatus of the present invention is applied to an imaging system will be described in detail. Examples of the imaging system include a digital still camera, a digital camcorder, and a surveillance camera. FIG. 11 illustrates a block diagram when applied to a digital still camera as an example of an imaging system.

  In FIG. 11, reference numeral 1 denotes a barrier for protecting the lens, 2 denotes a lens for forming an optical image of a subject on the imaging device 4, and 3 denotes a diaphragm for changing the amount of light passing through the lens 2. Reference numeral 4 denotes the image pickup apparatus described in the first to fifth embodiments, which converts an optical image formed by the lens 2 as image data. Reference numeral 7 denotes a signal processing unit that compresses various corrections and data into the imaging data output from the imaging device 4. In FIG. 11, 8 is a timing generator for outputting various timing signals to the imaging device 4 and the signal processor 7, and 9 is an overall control / arithmetic unit for controlling various calculations and the entire digital still camera. 10 is a data holding unit for temporarily storing image data, 11 is an interface unit for recording or reading data on a recording medium, and 12 is a detachable semiconductor memory or the like for recording or reading image data. It is a recording medium. Reference numeral 13 denotes an interface unit for communicating with an external computer or the like. Here, the timing signal or the like may be input from the outside, and the imaging system only needs to include at least the imaging device 4 and the signal processing unit 7 that processes the imaging signal output from the imaging device. The error display unit 14 is a display unit that performs display based on a signal output from the determination unit 300 of the imaging device 4.

  The determination unit 300 provided in the imaging apparatus outputs an error signal to the error display unit 14 when it is determined that there is a failure. When an error signal is input, the error display unit 14 performs a display notifying that a failure has occurred in the imaging apparatus. This display can be performed, for example, by displaying a light-emitting operation of the warning lamp or a message indicating that a failure has occurred.

  Alternatively, an error signal may be output from the determination unit 300 to the overall control / calculation unit 9. In this embodiment, when an error signal is input to the overall control / calculation unit 9, the subsequent imaging operation can be controlled to stop. In the case of this form, the form which an error signal is input from the determination part 300 to the error display part 14 may be sufficient, and the form which outputs the signal which makes the error display part 14 perform an error display from the overall control / calculating part 9 It may be.

  As described above, the imaging apparatus of the present invention can be applied to an imaging system. By applying the imaging device of the present invention to an imaging system, a failure is notified to a photographer who performs an imaging operation when a short-circuit failure or a stuck-at failure occurs in the memory unit of the imaging device or a stuck-out failure occurs in the horizontal scanning unit. be able to. Therefore, it is possible to prevent the camera from continuing shooting without noticing the failure.

  In the present embodiment, the form in which the imaging system has the error display unit 14 has been described. The present embodiment is not limited to this form, and may be a form without the error display unit 14. As such a form, for example, there is a form in which imaging is not performed when the determination unit 300 determines a failure.

  In the present embodiment, the form in which the imaging device 4 included in the imaging system includes the determination unit 300 has been described. The present embodiment is not limited to this, and the determination unit 300 may be provided outside the imaging device 4 and the imaging system. In other words, in the manufacturing process of the imaging device 4 included in the imaging system, the determination unit 300 may be electrically connected to a terminal provided on the output signal line to determine whether or not the column memory has failed.

  In this manufacturing process, when a failure of the column memory is detected, the failed column memory is repaired or the manufacturing of the imaging system using the imaging device 4 determined to be failed is stopped. Can do. Also, the position of the column memory determined to be faulty is stored in an external look-up table, and the column memory determined to be faulty is replaced with a signal held in a normal column memory or corrected. It may be possible to operate normally.

  Therefore, an imaging system having the imaging device 4 capable of normal operation can be manufactured by inspecting whether or not the column memory is faulty.

101-108 signal line 111-118 comparator output line 121-128 selection circuit 131-138 selection circuit output line 141-148 column memory output line 151-158 horizontal selection signal line 212 lamp voltage supply unit 221 test signal supply unit 290 output Signal line 300 determination unit (an example of an output comparison unit)
301-308 Comparator 401-408 Column Memory

Claims (9)

A plurality of circuit units each including a comparator that outputs a comparison result signal indicating a comparison result between the analog signal and the reference signal, and a memory that holds a digital signal based on the comparison result signal;
An analog-digital conversion circuit for converting the analog signal into a digital signal,
Each of the plurality of circuit units includes a first memory or a second memory as the memory, and the plurality of circuit units include a plurality of the first memories and a plurality of the second memories,
A first test signal for holding the first digital signal is supplied to each of the plurality of first memories, and the first digital signal is supplied to each of the plurality of second memories. A test signal supply unit for supplying a second test signal for holding a second digital signal having a different signal value;
An output comparison unit for storing the expected value;
A transfer unit, and
The transfer unit includes first and second transfer circuits that transfer digital signals held by the first and second memories to the output comparison unit, respectively.
Each of the plurality of first memories transfers a digital signal to the first transfer circuit, and each of the plurality of second memories transfers a digital signal to the second transfer circuit,
After the test signal supply unit supplies the first test signal to the plurality of first memories and supplies the second test signal to the plurality of second memories, the first transfer circuit includes: The digital signal held in each of the plurality of first memories is continuously transferred to the output comparison unit, and the second transfer circuit transfers the digital signal held in the plurality of second memories to the output comparison unit. Transfer continuously to
The output comparison unit compares the expected value with each of the first digital signal transferred from the first transfer circuit and the second digital signal transferred from the second transfer circuit. An analog-digital conversion circuit characterized by:   2. The analog-digital conversion circuit according to claim 1, wherein one of the plurality of second memories is provided between each of the plurality of first memories. Signals supplied to the plurality of first memories and the plurality of second memories, the comparison result signal output from the comparator,
3. The analog-digital conversion circuit according to claim 1, further comprising a selection unit that switches between the first test signal and the second test signal supplied from the test signal supply unit. 4. A counter that supplies a count signal obtained by counting the clock signal to the plurality of first memories and the plurality of second memories in common;
Each of the plurality of first memories holds the count signal as a digital signal based on the first test signal, and each of the plurality of second memories stores the count signal based on the second test signal. 4. The analog-digital conversion circuit according to claim 1, wherein the signal is held as a digital signal. A clock signal supply unit for supplying a clock signal to the plurality of first memories and the plurality of second memories;
Each of the plurality of first memories and each of the plurality of second memories has a counter that generates a count signal obtained by counting the clock signals;
Each of the plurality of first memories holds the count signal as a digital signal based on the first test signal, and each of the plurality of second memories stores the count signal based on the second test signal. 4. The analog-digital conversion circuit according to claim 1, wherein the signal is held as a digital signal. Further, each of the plurality of circuit units includes third and fourth memories, and an inter-memory transfer unit,
The inter-memory transfer unit transfers the digital signal held in the first memory to the third memory, transfers the digital signal held in the second memory to the fourth memory, and The analog-to-digital conversion circuit according to claim 1, wherein the digital signal is transferred from the memory to the transfer unit, and the digital signal is transferred from the fourth memory. After the test signal supply unit supplies the first test signal to the plurality of first memories, and supplies the second test signal to the plurality of second memories,
The first transfer circuit transfers the digital signal held in the first memory to the output comparison unit, and then transfers the digital signal held in the second memory to the output comparison unit, and the second transfer. The circuit transfers the digital signal held by the first memory to the output comparison unit, and then transfers the digital signal held by the second memory to the output comparison unit.
The output comparison unit includes the first and second digital signals transferred alternately from the first transfer circuit, and the first and second digital signals transferred alternately from the second transfer circuit. The analog-to-digital conversion circuit according to claim 1, wherein the expected value is compared with each of the analog-to-digital conversion circuit. The analog-digital conversion circuit according to any one of claims 1 to 7 ,
A plurality of pixels each including a photoelectric conversion unit, and a pixel unit arranged in a plurality of columns,
An image pickup apparatus configured to input an analog signal output from each column of the pixel portion to the comparator of each circuit portion of the analog-to-digital conversion circuit. An imaging device according to claim 8 ;
A signal processing unit for processing a digital signal output from the imaging device;
An imaging system comprising:

Images