JP5979447B2 - Wireless communication device - Google Patents

Description

  The present invention relates to a wireless communication apparatus that performs intermittent communication and synchronizes with a communication partner.

  In recent years, there has been a widespread use of a monitor system that includes a slave unit equipped with an image sensor that captures an image and a monitor master unit in a room that displays image data from the slave unit on a monitor (for example, Patent Document 1). reference). For example, the monitor system disclosed in Patent Document 1 includes a camera unit for capturing an image of a visitor, an entrance cordless handset provided with a microphone and a speaker for talking with the visitor, and an LCD panel for displaying an image of the visitor at the entrance cordless handset. And an additional master device capable of TDMA (time division multiplex communication) wireless communication between the home master device and the home master device. The image of the entrance child machine is sent to the extension parent machine via the living room parent machine. The image from the entrance cordless handset is also displayed on the LCD panel of the extension base phone carried by the user in the room. Then, the user can talk while moving with the extension base unit.

  The monitor system of patent document 1 connects the subunit | mobile_unit which has a camera, and the main | base station in a living room by wire. Moreover, in the monitor system of patent document 1, the electric power for operating a subunit | mobile_unit is supplied by wire from a living room main | base station. Therefore, in the monitor system of Patent Document 1, it is necessary to install a communication line between the slave unit and the master unit. A system in which a slave unit having a camera is driven by a battery and an image or sound from the slave unit is directly transmitted to an indoor parent unit by radio is becoming widespread. However, if the power consumption of the slave unit is not suppressed, the battery is frequently used. It needs to be replaced.

  Hereinafter, an example of a configuration in which a camera slave unit and a monitor master unit perform TDMA (time division multiplexing communication) wireless communication and transmit and receive images or sounds in a conventional monitor system will be described with reference to FIG. FIG. 1A is a diagram showing the communication slot configuration of the monitor master unit, and FIG. 1B is a diagram showing the operation of the camera slave unit. As shown in FIG. 1, the camera slave unit and the monitor master unit are synchronized at a predetermined cycle. Specifically, the monitor base unit transmits a control signal (control channel) using a slot (slot S1 in FIG. 1) having a predetermined frame period (for example, 10 msec period). On the other hand, the camera slave unit receives one control signal for every predetermined number of control signals (control channels) from the monitor master unit and maintains synchronization (synchronization cycle T in FIG. 1). For example, the synchronization period T is a predetermined number of times the frame period of the monitor base unit. Further, as shown in FIG. 1, the camera slave unit periodically turns on / off the power of the communication unit to realize intermittent communication operation while maintaining synchronization, and low power consumption ( For example, the power consumption of the battery is suppressed by performing a sleep operation of several μA).

  In addition, a camera slave unit that performs such intermittent communication operation is often composed of a high-speed drive unit and a low-speed drive unit that operate with a high-speed clock. Since the low-speed drive unit operates with a low-speed clock, it can be driven with ultra-low power consumption.

  Next, the operation of the camera slave unit that performs the conventional intermittent communication operation will be described with reference to FIG.

  The low-speed drive unit operates at low power consumption by starting the low-speed timer A during sleep. When the counting by the low speed timer A is completed, the low speed driving unit sends an activation signal from the low speed timer A to the power control unit and the low speed timer B of the high speed driving unit.

  The power control unit of the high-speed drive unit supplies power to each unit so as to activate the high-speed drive unit, and operates based on a program.

  The high-speed drive unit reads the reception timing timer value from the external memory, and sets the read reception timing timer value in the reception timing timer. Meanwhile, the low speed timer B continues counting with the low speed clock.

  The low-speed timer B sends an activation signal to the reception timing timer when the count ends. The reception timing timer receives this activation signal and counts the reception timing based on the reception timing timer value. The high-speed drive unit performs a reception operation when the count by the reception timing timer is completed.

  The high-speed drive unit calculates the next reception timing value after receiving the signal from the monitor base unit. The high speed drive unit sets the timer value of the low speed timer A and the timer value of the low speed timer B to each timer based on the calculated next reception timing value. The high-speed drive unit stops supplying power and shifts to a sleep state at a predetermined cycle. Therefore, the reception timing timer value is stored in a non-volatile external memory (such as an EEPROM) that retains memory even when the power is turned off. Note that the timer value of the low-speed timer B is a fixed value.

  In the above-mentioned camera slave unit, since the reception timing timer value is repeatedly stored in the external memory at a predetermined cycle, there is a problem that the write limit (component life) of the external memory is reached and the product life is shortened. In order to solve such a problem, conventionally, a camera slave unit is known in which reception timing timer values are distributed and stored in a plurality of external memories so as not to shorten the product life.

JP 2007-208608 A

  However, in a conventional wireless communication device such as a camera slave unit, the reception timing timer value is distributed and stored, so that the size of the external memory increases and the access time and startup time for the external memory become longer. There is a problem that the battery life is shortened.

  An object of the present invention is to store information related to reception timing in a low-speed timer so that the size of the external memory can be greatly reduced, and the access time and start-up time to the external memory can be shortened. It is an object of the present invention to provide a wireless communication device that can extend the lifetime.

  A wireless communication apparatus according to the present invention is a wireless communication apparatus that performs intermittent communication and synchronizes with a communication partner, and includes a low-speed timer that measures a predetermined time and a storage unit that stores information related to reception timing. A reception timing timer that starts counting according to information about the reception timing output from the low-speed drive unit and the low-speed drive unit, and starts when the low-speed timer reaches a predetermined expiration value; and the reception timing timer And a high-speed drive unit that starts communication with the communication partner when a predetermined expiration value is reached.

  According to the present invention, by storing information related to the reception timing in the low-speed timer, the size of the external memory can be significantly reduced, and the access time and start-up time to the external memory can be shortened. The lifetime can be extended.

Diagram explaining synchronization of camera slave unit and monitor base unit The figure which shows the timing of the count start and count end of each timer The block diagram which shows the structure of the monitor system in Embodiment 1 of this invention. 1 is a block diagram showing the configuration of a camera slave unit in Embodiment 1 of the present invention. 1 is a block diagram showing the configuration of a monitor base unit in Embodiment 1 of the present invention. The figure which shows the count start timing of each timer and the timing of starting of a high-speed drive part in Embodiment 1 of this invention. The flowchart which shows the operation | movement of the camera subunit in Embodiment 1 of this invention The flowchart which shows operation | movement of the camera subunit in Embodiment 2 of this invention Block diagram showing a configuration of a camera slave unit according to Embodiment 3 of the present invention. The figure which shows the register | resistor of the external memory and the 1st low speed timer in Embodiment 3 of this invention The flowchart which shows operation | movement of the camera subunit in Embodiment 3 of this invention

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
<Monitor system configuration>
The monitor system 10 in Embodiment 1 of this invention is demonstrated using FIG. The monitor system 10 in the present embodiment includes a monitoring device and a camera device. In particular, in the present embodiment, the camera device is described as the camera slave device 100, and the monitoring device is described as the monitor parent device 200.

  The camera slave unit 100 performs intermittent communication with the monitor master unit 200 to synchronize with the monitor master unit 200. The camera slave device 100 acquires image data of a visitor or the like and transmits the acquired image data to the monitor master device 200.

  The monitor master device 200 performs intermittent communication with the camera slave device 100 to synchronize with the camera slave device 100. The monitor master device 200 displays an image of the image data received from the camera slave device 100.

<Configuration of camera slave unit>
The configuration of camera slave unit 100 according to Embodiment 1 of the present invention will be described with reference to FIG. In the present embodiment, the reception timing timer value is stored as reception timing information in the register 122 of the second low-speed timer 117.

  The camera slave unit 100 includes an antenna 101, a wireless unit 102, an audio processing unit 103, a microphone 104, a speaker 105, an imaging unit 106, an image data processing unit 107, an internal memory 108, and a power control unit 109. A battery 110, a high-speed clock supply unit 111, a control unit 112, a program memory 113, an external memory 114, a reception timing timer 115, a first low-speed timer 116, a second low-speed timer 117, It is mainly composed of a low-speed clock supply unit 118. The camera slave unit 100 can be applied to a wireless communication device.

  The high-speed driving unit 130 includes a wireless unit 102, an audio processing unit 103, a microphone 104, a speaker 105, an imaging unit 106, an image data processing unit 107, an internal memory 108, a power control unit 109, and a control. A unit 112, a program memory 113, an external memory 114, and a reception timing timer 115 are included. The high-speed drive unit 130 is supplied with a high-speed clock from the high-speed clock supply unit 111, and is intermittently activated and operated by receiving power from the battery 110. The high-speed drive unit 130 is in a sleep state while not operating.

  The low speed drive unit 131 includes a first low speed timer 116 and a second low speed timer 117. The low-speed driving unit 131 receives a low-speed clock supplied from the low-speed clock supply unit 118 and receives power supplied from the battery 110 to operate. The low speed drive unit 131 operates even when the high speed drive unit 130 is in the sleep state.

  The antenna 101 receives a signal transmitted from the monitor base device 200 and outputs the signal to the wireless unit 102. The antenna 101 transmits the signal input from the wireless unit 102 to the monitor base device 200. Communication between the monitor base device 200 and the camera slave device 100 is performed by, for example, DECT (Digital Enhanced Cordless Telecommunications (registered trademark)) communication.

  When receiving an instruction to start communication from the control unit 112, the wireless unit 102 amplifies and frequency-converts the signal input from the control unit 112 and outputs the signal to the antenna 101. Further, when receiving an instruction to start communication from the control unit 112, the radio unit 102 amplifies and converts the frequency of the signal input from the antenna 101 and outputs the signal to the control unit 112. The signal input from the control unit 112 includes, for example, image data, audio data, a communication start response, a communication end response, or a cycle change response. The signal input from the antenna 101 includes, for example, audio data, a communication start request, a communication end request, a cycle change request, or the like.

  The audio processing unit 103 performs audio processing on the audio data input from the control unit 112 and transmitted from the monitor parent device 200 and outputs the audio data to the speaker 105. The sound processing unit 103 performs sound processing on the sound data input from the microphone 104 and outputs the sound data subjected to the sound processing to the control unit 112.

  The microphone 104 outputs voice data of a visitor or the like to the voice processing unit 103.

  The speaker 105 outputs the sound of the sound data input from the sound processing unit 103 to the outside.

  The imaging unit 106 acquires image data according to an instruction (not shown) of the control unit 112, and outputs the acquired image data to the image data processing unit 107.

  The image data processing unit 107 performs image data processing on the image data input from the imaging unit 106 and outputs the processed image data to the control unit 112.

  The internal memory 108 is a memory for executing information processing, and stores predetermined data necessary for information processing in advance.

  The power supply control unit 109 supplies the power supplied from the battery 110 to the control unit 112 and via the control unit 112 when the activation signal, which is a notification that the count has ended, is acquired from the first low-speed timer 116. Supply to each component. Thereby, the high-speed drive part 130 starts.

  The battery 110 is a power supply and supplies power to the power supply control unit 109 and the low-speed drive unit 131.

  The high-speed clock supply unit 111 supplies a high-speed clock to the control unit 112.

  The control unit 112 controls the entire camera slave unit 100 when activated by receiving power from the power supply control unit 109. When receiving power from the power supply control unit 109, the control unit 112 also supplies power to each component. The control unit 112 operates based on the clock output from the high-speed clock supply unit 111. The control unit 112 reads the reception timing timer value from the register 122 of the second low-speed timer 117 and outputs it to the reception timing timer 115 when the count (timing) in the first low-speed timer 116 is finished and started. Then, the control unit 112 stores the regular timer value of the second low speed timer 117 read from the program memory 113 in the register 122 of the second low speed timer 117.

  When the control unit 112 receives a notification of completion of counting from the reception timing timer 115, the control unit 112 instructs the wireless unit 102 to start communication. When the control unit 112 is activated, the control unit 112 calculates the next reception timing through communication with the monitor parent device 200. The control unit 112 calculates timer values of the first low-speed timer 116 and the reception timing timer 115 used at the next activation based on the calculated next timing. Then, the control unit 112 stores the next timer value of the first low-speed timer 116 in the register 121, stores the next timer value (regular timer value) of the second low-speed timer 117 in the program memory 113, and receives it. The next reception timing timer value of the timing timer 115 is stored in the register 122 of the second low-speed timer 117.

  When the control unit 112 receives a communication start request (or communication end request) from the monitor base unit 200 during activation, the control unit 112 outputs a response to the received communication start request (or communication end request) to the wireless unit 102. . The control unit 112 controls the exchange of audio data and image data between the monitor master device 200 and the camera slave device 100 during communication with the monitor master device 200. Here, the reception timing timer value indicates the end point of the count in the reception timing timer 115.

  The program memory 113 is a memory for storing programs, and stores a predetermined program in advance. The program memory 113 stores in advance a regular timer value of the second low speed timer 117. The regular timer value of the second low speed timer 117 is a fixed value.

  The external memory 114 stores predetermined information. The external memory 114 is, for example, an EEPROM.

  The reception timing timer 115 sets the reception timing timer value input from the control unit 112. The reception timing timer 115 starts timing when it receives a count end notification from the second low-speed timer 117 (third count). The reception timing timer 115 ends the count when the count value reaches the reception timing timer value, and notifies the control unit 112 that the count has ended. The reception timing timer value that determines the end point of the third count is read from the register 122 of the second low-speed timer 117 when the count in the first low-speed timer 116 ends and the high-speed drive unit 130 is activated. Value.

  The first low-speed timer 116 has a register 121 for storing a timer value indicating expiration. The first low-speed timer 116 counts according to the clock from the low-speed clock supply unit 118 when the high-speed drive unit 130 is in the sleep state (first count). The first low-speed timer 116 finishes counting when the count value reaches the timer value stored in the register 121, and notifies the power supply control unit 109 and the second low-speed timer 117 that the counting has ended. The notification signal to be notified is output.

  The second low-speed timer 117 has a register 122 for storing a regular timer value that means the count of itself is expired, and a reception timing timer value that means the count of the reception timing timer 115 is expired. Yes. The second low speed timer 117 starts counting according to the count end notification from the first low speed timer 116 (second count). The second low speed timer 117 counts up according to the clock from the low speed clock supply unit 118. The second low-speed timer 117 outputs the reception timing timer value stored in the register 122 to the control unit 112 when receiving a count end notification from the first low-speed timer 116. The second low-speed timer 117 is a regular timer value of the second low-speed timer 117 input from the control unit 112 while outputting the reception timing timer value to the control unit 112 and still counting. Is stored in the register 122. Then, the second low-speed timer 117 ends the count when the count value reaches the regular timer value stored in the register 122, and notifies the reception timing timer 115 that the count has ended.

  The low speed clock supply unit 118 supplies a low speed clock to the low speed drive unit 131.

<Configuration of monitor base unit>
The configuration of monitor master device 200 according to Embodiment 1 of the present invention will be described with reference to FIG.

  The monitor base unit 200 includes an antenna 201, a radio unit 202, an audio processing unit 203, a microphone 204, a speaker 205, a display unit 206, a memory 207, an operation unit 208, a power supply unit 209, and a control unit. 210, a system clock supply unit 211, and a battery 212.

  The antenna 201 receives a signal transmitted from the camera slave unit 100 and outputs the signal to the wireless unit 202. The antenna 201 transmits the signal input from the wireless unit 202 to the camera slave unit 100.

  The radio unit 202 amplifies and frequency-converts the signal input from the control unit 210 and outputs the signal to the antenna 201. The radio unit 202 amplifies and frequency converts the signal input from the antenna 201 and outputs the signal to the control unit 210. The signal input from the control unit 112 includes, for example, a signal for requesting the start of communication with the camera slave unit 100 (hereinafter referred to as “communication start request”) and a signal for requesting the end of the communication (hereinafter, “ A communication end request ”, audio data, or a signal for requesting a change in the synchronization period for intermittent communication between the camera slave unit 100 and the monitor master unit 200 (hereinafter referred to as a“ cycle change request ”). Included). Also, the signal input from the antenna 201 includes, for example, image data, audio data, or a response (for example, a communication start response, a communication end response, a cycle change response) to the request signal of the monitor base unit 200. ing.

  The audio processing unit 203 performs audio processing on the audio data input from the control unit 210 and transmitted from the camera slave unit 100, and outputs the audio data subjected to the audio processing to the speaker 205. The audio processing unit 203 performs audio processing on the audio data acquired by the microphone 204 and outputs the audio data subjected to the audio processing to the control unit 210.

  The microphone 204 outputs voice data of the voice of the person who responds to the visitor to the voice processing unit 203.

  The speaker 205 outputs the sound of the sound data input from the sound processing unit 203 to the outside.

  The display unit 206 displays the image data input from the control unit 210 and transmitted from the camera slave unit 100 on a display or the like.

  The memory 207 is used for storing a program or executing information processing by the control unit 210 that controls the entire monitor base unit 200.

  The operation unit 208 outputs the content of the user's operation input to the control unit 210. The user's operation input includes, for example, an operation for starting (or ending) communication with the camera slave unit 100 (for example, pressing a communication button (not shown)).

  The power supply unit 209 receives power from the battery 212 and supplies power to each component of the monitor base unit 200 according to the control of the control unit 210.

  The control unit 210 controls the monitor base unit 200 as a whole. For example, the control unit 210 receives a control signal (communication) for requesting the camera slave unit 100 to start communication (communication end) when a user inputs a communication start (communication end) operation in the operation unit 208. (Start request, communication end request) is generated, and the generated control signal is output to the wireless unit 202. Further, the control unit 210 controls the exchange of audio data and image data between the monitor parent device 200 and the camera slave device 100 during communication with the camera slave device 100. In addition, the control unit 210 controls the power supply of each component to the power supply unit 209. The control unit 210 operates based on the clock output from the system clock supply unit 211.

  The system clock supply unit 211 supplies a clock to the control unit 210.

  The battery 212 supplies power to the power supply unit 209.

<Timing of start and end of each timer and start timing of high-speed drive unit>
The timing at which each timer starts and ends and the timing at which the high-speed drive unit is activated in Embodiment 1 of the present invention will be described in detail with reference to FIG.

  The first low-speed timer 116 keeps counting while the high-speed driving unit 130 is in the sleep state. At this time, the first low-speed timer 116 counts the clock from the low-speed clock supply unit 118. When the count value of the first low-speed timer 116 reaches the timer value stored in the register 121, the count ends (time t2), and the start signal is sent to the power control unit 109 of the high-speed drive unit 130 and the second low-speed timer. It outputs to 117. The power control unit 109 turns on the switch according to the input activation signal and supplies power to each unit via the control unit 112. Thereby, the high-speed drive part 130 starts. The control unit 112 operates based on a program stored in the program memory 113.

  The second low-speed timer 117 starts counting using the low-speed clock from the low-speed clock supply unit 118 when the activation signal is input (time t2). Further, the control unit 112 that has started the operation in response to the activation signal acquires the reception timing timer value stored in the register 122 of the second low-speed timer 117 and sets the acquired reception timing timer value in the reception timing timer 115. . Then, the control unit 112 sets the regular timer value of the second low speed timer 117 stored in the program memory 113 in the register 122 of the second low speed timer 117. This regular timer value determines the end point of the count in the second low-speed timer 117.

  Next, the second low-speed timer 117 finishes counting when the count value reaches the regular timer value stored in the register 122 (time t3). As a result, the second low speed timer 117 outputs an activation signal to the reception timing timer 115. The reception timing timer 115 starts counting according to the input activation signal. At this time, the reception timing timer 115 counts the clock from the high-speed clock supply unit 111.

  Next, the reception timing timer 115 ends the count when the count value reaches the reception timing timer value (time t4). Thereby, the control unit 112 instructs the wireless unit 102 to start communication. When the wireless unit 102 receives an instruction to start communication from the control unit 112, the wireless unit 102 performs a reception operation.

  Next, the control unit 112 calculates the next reception timing in the intermittent reception after receiving the signal of the monitor base unit 200. Specifically, the control unit 112 calculates a timer value for causing the first low-speed timer 116 to expire and a reception timing timer value for causing the reception timing timer 115 to expire. The control unit 112 calculates and stores the timer value of the first low-speed timer 116 in the register 121 of the first low-speed timer 116, and stores the reception timing timer value in the register 122 of the second low-speed timer 117. Then, the high speed drive unit 130 shifts to a sleep operation. Note that the timer value of the second low-speed timer 117 is a fixed value and is stored in advance in a program stored in the program memory 113.

<Operation of camera slave unit>
The operation of the camera slave unit 100 according to Embodiment 1 of the present invention will be described with reference to FIG.

  First, the high speed drive unit 130 continues the sleep operation (step ST701).

  Next, power supply control section 109 and second low speed timer 117 determine whether or not counting by first low speed timer 116 has ended (step ST702). That is, the power control unit 109 and the second low speed timer 117 determine whether or not an activation signal is input from the first low speed timer 116.

  When power supply control section 109 determines that an activation signal has been input (step ST702: YES), power supply section 109 supplies power to each component of high speed driving section 130 to activate high speed driving section 130 (step ST703).

  Next, the activated control unit 112 reads the reception timing timer value from the register 122 of the second low-speed timer 117 (step ST704).

  Next, control section 112 sets the read reception timing timer value in reception timing timer 115 (step ST705).

  Next, the control unit 112 reads the regular timer value of the second low speed timer 117 from the program memory 113 (step ST706).

  Next, the control part 112 memorize | stores the read regular timer value in the register | resistor 122 of the 2nd low speed timer 117 (step ST707).

  On the other hand, the second low-speed timer 117 is started when it is determined that the start signal is input after the counting by the first low-speed timer 116 is finished (step ST702: YES) (step ST708), and the above-described step ST703 is performed. -Counting is performed in parallel with the operation of step ST707. At this time, the control unit 112 reads the regular timer value of the second low-speed timer 117 from the program memory 113 during the counting by the second low-speed timer 117, and sets the read regular timer value to the second Are stored in the register 122 of the low-speed timer 117.

  Reception timing timer 115 determines whether or not counting by second low-speed timer 117 has ended (step ST709). That is, the control unit 112 determines whether an activation signal is input from the second low-speed timer 117.

  If reception timing timer 115 determines that counting by second low-speed timer 117 has not ended (step ST709: NO), it repeats the process of step ST709.

  On the other hand, if reception timing timer 115 determines that counting by second low-speed timer 117 has ended (step ST709: YES), reception timing timer 115 starts counting based on the reception timing timer value (step ST710).

  Next, control section 112 determines whether or not counting by reception timing timer 115 has ended (step ST711).

  When it is determined that the counting by reception timing timer 115 has not ended (step ST711: NO), control unit 112 repeats the process of step ST711.

  On the other hand, when it is determined that the counting by the reception timing timer 115 has ended (step ST711: YES), the control unit 112 receives a signal from the monitor parent device 200 (step ST712). That is, the control unit 112 starts an operation of detecting a signal transmitted from the monitor base unit 200 from signals received via the antenna 101 and the radio unit 102, acquires necessary information, and monitors the base unit 200. Control to transmit necessary information to the monitor base unit 200 is performed at a timing synchronized with the signal.

  In addition, control unit 112 corrects the reception timing based on the signal received from monitor parent device 200 (step ST713).

  Based on the corrected reception timing, control unit 112 calculates the next timing of the start and end of counting in each timer (step ST714).

  Next, the control unit 112 stores the timer value of the first low speed timer 116 at the next timing in the register 121 of the first low speed timer 116 (step ST715), and the normal value of the second low speed timer 117 at the next timing. Are stored in the program memory 113.

  Next, control section 112 sets the reception timing timer value at the next timing in register 122 of second low-speed timer 117 (step ST716).

  Then, control unit 112 causes high-speed drive unit 130 to shift to a sleep operation (step ST717).

<Effect of Embodiment 1>
In the present embodiment, the next reception timing timer value is stored in the register 122 of the second low speed timer 117 of the low speed drive unit 131. Thereby, according to the present embodiment, since it is not necessary to store the reception timing timer value in the external memory, the size of the external memory can be greatly reduced, and the access time and start-up time for the external memory can be reduced. It is possible to shorten the battery life.

(Embodiment 2)
Since the configuration of the monitor system according to the second embodiment of the present invention is the same as that of the monitor system 10 of FIG. 3, the description thereof is omitted. Further, since the configuration of the camera slave unit in the first embodiment of the present invention is the same as that of the camera slave unit 100 of FIG. Further, the configuration of the monitor base unit according to Embodiment 2 of the present invention is the same as that of the monitor base unit 200 of FIG. In addition, the count start timing and count end timing of each timer in Embodiment 2 of the present invention are the same as those in FIG.

  In the present embodiment, description will be made using the reference numeral of the monitor system 10 in FIG. 3, the reference numeral of the camera slave unit 100 in FIG. 4, and the reference numeral of the monitor parent unit 200 in FIG.

<Outline of Embodiment 2>
As described in the first embodiment, the control unit 112 sets the reception timing timer value in the second low-speed timer 117. Then, the control unit 112 switches the reception timing timer value and the timer value of the second low speed timer 117 while the second low speed timer 117 is counting.

  However, when the reception timing timer value is small, there is a possibility that the counting by the second low-speed timer 117 is ended before the above timer value is replaced.

  Therefore, in the present embodiment, before the timer value is exchanged, a process for preventing the second low speed timer 117 from ending is performed. Specifically, the control unit 112 sets the reception timing timer value set in the second low speed timer 117 to be equal to or greater than the timer value of the second low speed timer 117 before shifting to the sleep operation. In the present embodiment, in the register 122 of the second low speed timer 117, a reception timing timer value that is equal to or greater than the timer value of the second low speed timer 117 is stored as reception timing information.

<Operation of camera slave unit>
The operation of the camera slave unit 100 according to Embodiment 2 of the present invention will be described with reference to FIG.

  In FIG. 8, parts that are the same as those in FIG. 7 are denoted by the same step symbols and description thereof is omitted.

  After reading the reception timing timer value in step ST704, control unit 112 returns the reception timing timer value to a normal value (step ST801). And the control part 112 performs the process of step ST705.

  Moreover, the control part 112 makes a reception timing timer value more than the timer value of the 2nd low speed timer 117 after the process of step ST715 (step ST802). And the control part 112 performs the process of step ST716.

<Method 1 for making the reception timing timer value equal to or greater than the timer value of the second low-speed timer>
For example, when the bit number of the timer value of the second low-speed timer 117 is 16 bits and the bit number of the reception timing timer value is 12 bits, the control unit 112 sets the reception timing timer to be set in the second low-speed timer 117. 4 bits of “1111” are added to the upper part of the value to make the number of bits of the reception timing timer value 16 bits.

  When the reception timing timer value is set in the reception timing timer 115, the control unit 112 extracts the lower 12 bits of the reception timing timer value and discards the remaining upper 4 bits of “1111”.

<Method 2 for making the reception timing timer value equal to or greater than the timer value of the second low-speed timer>
For example, the control unit 112 sets the reception timing timer value to be stored in the register 122 of the second low speed timer 117 as “reception timing timer value + timer value of the second low speed timer 117”. As a result, the reception timing timer value stored in the second low speed timer 117 becomes equal to or greater than the timer value of the second low speed timer 117.

  Then, when setting the reception timing timer value in the reception timing timer 115, the control unit 112 extracts only the reception timing timer value and discards the timer value portion of the second low-speed timer 117.

<Effect of Embodiment 2>
In the present embodiment, when storing the reception timing timer value, the reception timing timer value is set to be equal to or greater than the timer value of the second low-speed timer. Thus, according to the present embodiment, in addition to the effect of the first embodiment, before the reception timing timer value and the timer value of the second low-speed timer are switched, the second low-speed timer It is possible to prevent the count from ending.

(Embodiment 3)
Since the configuration of the monitor system according to the third embodiment of the present invention is the same as that of the monitor system 10 of FIG. 3, the description thereof is omitted. Further, the configuration of the monitor base unit according to Embodiment 3 of the present invention is the same as that of the monitor base unit 200 of FIG.

  In the present embodiment, the reference numerals of the monitor master unit 200 in FIG. 5 are used for the description using the monitor master unit.

<Outline of Embodiment 3>
Conventionally, since the reception timing timer value is written in the same location of the external memory every intermittent reception cycle T of several seconds, the location where the reception timing timer value is written will soon reach the component life. For example, when writing is performed every 2.5 seconds, the number of parts write limit is reached in less than one month, which affects the life of the parts.

  Conventionally, in order to increase the component life, the storage location of the reception timing timer value is changed and stored for each intermittent reception cycle (distributed and stored). At that time, conventionally, address information indicating a storage destination of the reception timing timer value is also stored together. Thus, conventionally, a reception timing timer value required at the time of activation can be read out.

  However, in the above, it is necessary to save the reception timing timer value and address information required at the time of activation, and the memory area required for saving becomes large.

  Therefore, in the present embodiment, as shown in FIG. 9, the address information is stored in the register 922 of the second low-speed timer 901, and the reception timing timer value is stored in the external memory 902. In the present embodiment, in the register 922 of the second low-speed timer 901, address information indicating the storage area of the reception timing timer value in the external memory 902 is stored as reception timing information.

<Configuration of camera slave unit>
The configuration of the camera slave unit 900 according to Embodiment 3 of the present invention will be described with reference to FIG.

  A camera slave device 900 shown in FIG. 9 has a second low speed timer 901 instead of the second low speed timer 117 as compared with the camera slave device 100 according to the first embodiment shown in FIG. 114 includes an external memory 902, a control unit 903 instead of the control unit 112, and a register 922 instead of the register 122. 9, parts having the same configuration as in FIG. 4 are denoted by the same reference numerals and description thereof is omitted.

  The camera slave unit 900 includes an antenna 101, a wireless unit 102, an audio processing unit 103, a microphone 104, a speaker 105, an imaging unit 106, an image data processing unit 107, an internal memory 108, and a power control unit 109. A battery 110, a high-speed clock supply unit 111, a program memory 113, a reception timing timer 115, a first low-speed timer 116, a low-speed clock supply unit 118, a second low-speed timer 901, and an external memory 902. And a control unit 903. The camera slave unit 900 can be applied to a wireless communication device.

  The high-speed drive unit 930 includes a wireless unit 102, an audio processing unit 103, a microphone 104, a speaker 105, an imaging unit 106, an image data processing unit 107, an internal memory 108, a power control unit 109, a program A memory 113, a reception timing timer 115, an external memory 902, and a control unit 903 are included. The high-speed driving unit 930 is supplied with a high-speed clock from the high-speed clock supply unit 111, and is intermittently activated and operated by receiving power from the battery 110. The high-speed drive unit 930 is in a sleep state while not operating.

  The low speed drive unit 931 includes a first low speed timer 116 and a second low speed timer 901. The low speed drive unit 931 operates even when the high speed drive unit 930 is in the sleep state.

  The second low-speed timer 901 has a register 922 for storing a timer value that means the count of itself has expired and address information indicating a storage area of the reception timing timer value in the external memory 902. The second low speed timer 901 starts counting according to the count end notification from the first low speed timer 116 (second count). The second low speed timer 901 counts up according to the clock from the low speed clock supply unit 118. When the count value reaches the timer value stored in the register 922 and the count ends, the second low-speed timer 901 notifies the reception timing timer 115 that the count has ended. The second low-speed timer 901 outputs the address information stored in the register 922 to the control unit 903 when receiving a count end notification from the first low-speed timer 116. The second low-speed timer 901 outputs the regular timer value of the second low-speed timer 117 input from the control unit 903 while the address information is output to the control unit 903 and is still being counted. Store in register 922. Therefore, the second low-speed timer 901 ends counting when the count value reaches the regular timer value stored in the register 922.

  The reception timing timer 115 sets the reception timing timer value input from the control unit 903. The reception timing timer 115 starts measuring time when receiving a count end notification from the second low-speed timer 901 (third count). The reception timing timer 115 ends the count when the count value reaches the reception timing timer value, and notifies the control unit 903 that the count has ended.

  The external memory 902 stores address information written from the control unit 903.

  The control unit 903 controls the entire camera slave unit 900 when activated by receiving power supply from the power supply control unit 109. The control unit 903 also supplies power to each component when receiving power supply from the power supply control unit 109. The control unit 903 operates based on the clock output from the high-speed clock supply unit 111. While the second low-speed timer 901 is counting, the control unit 903 reads the address information from the register 922 of the second low-speed timer 901, and the regular low-speed timer 901 read from the program memory 113 The timer value is stored in the register 922 of the second low speed timer 901. The control unit 903 reads the reception timing timer value from the storage area of the external memory 902 indicated by the read address information, and outputs the read reception timing timer value to the reception timing timer 115.

  When the control unit 903 receives a notification of completion of counting from the reception timing timer 115, the control unit 903 instructs the wireless unit 102 to start communication. When the control unit 903 is activated, the control unit 903 calculates the next reception timing through communication with the monitor parent device 200. The control unit 903 calculates the timer values of the first low-speed timer 116 and the reception timing timer 115 used at the next activation based on the calculated next reception timing. Then, the control unit 903 stores the next timer value of the first low speed timer 116 in the register 121. Also, the control unit 903 stores the next reception timing timer value of the reception timing timer 115 in the external memory 902. In addition, the control unit 903 stores address information indicating the storage area of the reception timing timer value in the external memory 902 to be used at the next activation in the register 922 of the second low-speed timer.

  When the control unit 903 receives a communication start request (or communication end request) from the monitor base unit 200 while it is activated, the control unit 903 outputs a response to the communication start request (or communication end request) to the wireless unit 102. The control unit 903 controls the exchange of audio data and image data between the monitor master 200 and the camera slave 900 when communicating with the monitor master 200.

<Register for external memory and second low-speed timer>
The external memory 902 and the register 922 of the second low-speed timer 901 in Embodiment 3 of the present invention will be described with reference to FIG.

  As shown in FIG. 10, the external memory 902 stores the reception timing timer value by changing the storage area.

  The register 922 of the second low-speed timer 901 stores address information indicating the storage area of the external memory 902 as shown in FIG.

<Operation of camera slave unit>
The operation of the camera slave unit 900 according to Embodiment 3 of the present invention will be described with reference to FIG.

  In FIG. 11, the same steps as those in FIG. 7 are denoted by the same step symbols, and the description thereof is omitted.

  After the high speed drive unit 930 is activated in step ST703, the control unit 903 reads address information from the register 922 of the second low speed timer 901 (step ST1101).

  Next, the control unit 903 reads the reception timing timer value stored in the storage area of the external memory 902 indicated by the read address information from the external memory 902 (step ST1102). And the control part 903 performs the process of step ST705.

  Further, after storing the timer value of the next timing in the register 121 of the first low-speed timer 116 in step ST715, the control unit 903 changes the storage timing timer value of the next timing calculated in step ST714 by changing the storage area. It is stored in the external memory 902 (step ST1103).

  Next, control section 903 stores address information indicating the storage area in which the reception timing timer value is stored in step ST1103 in register 922 of second low-speed timer 901 (step ST1104). And the high speed drive part 930 performs the process of step ST717.

<Effect of Embodiment 3>
In the present embodiment, the storage area is changed to store the reception timing timer value in the external memory, and the address information is stored in the register of the second low-speed timer. Thus, according to the present embodiment, the size of the external memory can be significantly reduced, the access time to the external memory and the startup time can be shortened, and the battery life can be increased.

<Modification of Embodiment 3>
In this embodiment, the address information is stored in the register of the second low-speed timer as it is. However, after the number of bits of the address information is set to be equal to or greater than the number of bits of the timer value of the second low-speed timer, It may be stored in a register. In this case, the value of the address information can be increased by a method similar to the method of increasing the reception timing timer value in the second embodiment.

  The wireless communication apparatus according to the present invention is suitable for performing intermittent communication and synchronizing with a communication partner.

DESCRIPTION OF SYMBOLS 100 Camera subunit | mobile_unit 101 Antenna 102 Radio | wireless part 103 Audio | voice processing part 104 Microphone 105 Speaker 106 Imaging part 107 Image data processing part 108 Internal memory 109 Power supply control part 110 Battery 111 High-speed clock supply part 112 Control part 113 Program memory 114 External memory 115 Reception Timing timer 116 First low-speed timer 117 Second low-speed timer 118 Low-speed clock supply unit 121, 122 Register 130 High-speed drive unit 131 Low-speed drive unit

Claims (3)

A wireless communication device that performs intermittent communication and synchronizes with a communication partner,
A low-speed drive unit having a low-speed timer that measures a predetermined time, and a storage unit that stores information about reception timing;
A reception timing timer that starts counting according to the information on the reception timing output from the low-speed drive unit, and starts when the low-speed timer reaches a predetermined expiration value; and the reception timing timer is a predetermined expiration value A high-speed drive unit that starts communication with the communication partner when reaching
A wireless communication device. Information on the reception timing is stored in the storage unit of the low-speed drive unit and used at the next start-up,
The wireless communication apparatus according to claim 1. The low-speed timer performs a first count for measuring a predetermined time and starts a second count when the first count ends, and the high-speed drive unit starts when the first count ends. to start,
The wireless communication apparatus according to claim 1.

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