JP5978600B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device using graphene.

  The CMOS technology using silicon is approaching the limit of miniaturization, and a channel alternative material for extending its lifetime is being sought. As the most promising candidates, nanocarbon materials such as carbon nanotubes and graphene are attracting attention, and various research and development are being conducted.

  As an example of a device using a nanocarbon material, a graphene transistor using graphene in a channel region of a field effect transistor can be given. Since graphene has higher carrier mobility than silicon, a high-speed transistor can be realized by forming a channel using graphene.

International Publication No. 2008/108383 Pamphlet

Y. Wang et al., "Scalable synthesis of graphene on patterned Ni and transfer", IEEE trans. Electron Devices, Vol. 57, No. 12, 2010

  In order to form a channel using graphene, it is required to form graphene over the insulating film. However, a catalyst is required for the synthesis of graphene, and a catalytic metal film exists on the base of the synthesized graphene. Therefore, a process for transferring graphene synthesized on another substrate onto an insulating film has been proposed, but the graphene may be bent or bent during the transfer, and damage such as resist residue may be introduced. It was difficult to stably obtain the device characteristics.

  An object of the present invention is to provide a method for manufacturing a semiconductor device capable of forming high-quality graphene on an insulating film.

  According to one aspect of the embodiment, the step of forming a first catalytic metal film on a first substrate, and the first catalytic metal film as a catalyst on the first catalytic metal film, A step of forming one graphene, a step of forming a first insulating film on the first graphene, a step of forming a first metal film on the first insulating film, and a second A step of forming a second metal film on the substrate, and a surface of the first metal film and a surface of the second metal film are opposed to each other, and the first metal film and the second metal A method for manufacturing a semiconductor device is provided, which includes a step of bonding a film and a step of removing the first substrate.

  Further, according to another aspect of the embodiment, a step of forming a catalytic metal film on the first substrate, a step of forming graphene on the catalytic metal film using the catalytic metal film as a catalyst, Forming a first metal film on the graphene; patterning the first metal film and the graphene to form a graphene wiring made of the graphene; and a second substrate on the second substrate. Forming the metal film, and making the surface of the first metal film and the surface of the second metal film face each other and bonding the first metal film and the second metal film, There is provided a method for manufacturing a semiconductor device, comprising: a step of removing the first substrate; and a step of removing the catalytic metal film.

  According to still another aspect of the embodiment, a step of forming a catalytic metal film on the first substrate, and a step of forming graphene on the catalytic metal film using the catalytic metal film as a catalyst, , A step of forming a first insulating film on the graphene, a step of forming a second insulating film on the second substrate, a surface of the first insulating film, and the second insulating film A method for manufacturing a semiconductor device is provided, which includes a step of facing the surface and bonding the first insulating film and the second insulating film, and a step of removing the first substrate.

  According to the disclosed method for manufacturing a semiconductor device, since the insulating film and the metal film are on the graphene, and the graphene is transferred onto another substrate on which the metal film is formed using thermocompression bonding between the metal films, It is possible to prevent wrinkling and bending of the graphene during transfer. In addition, a member for transfer such as a resist is not in direct contact with the graphene, and the introduction of damage to the graphene due to a resist residue or the like can be prevented.

1A and 1B are a plan view and a schematic sectional view showing the structure of the semiconductor device according to the first embodiment. FIG. 2 is a process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 3 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 4 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 5 is a process cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a plan view and a schematic sectional view showing the structure of the semiconductor device according to the second embodiment. FIG. 7 is a process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 8 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 9 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is a plan view (part 1) illustrating the structure of a semiconductor device according to a modification of the second embodiment. FIG. 11 is a plan view (part 2) illustrating the structure of a semiconductor device according to a modification of the second embodiment. 12A and 12B are a plan view and a schematic sectional view showing the structure of the semiconductor device according to the third embodiment. FIG. 13 is a process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the third embodiment. FIG. 14 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the third embodiment. FIG. 15 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the third embodiment. FIG. 16 is a process cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the third embodiment; FIG. 17 is a schematic cross-sectional view showing the structure of the semiconductor device according to the fourth embodiment. FIG. 18 is a process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the fourth embodiment. FIG. 19 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the fourth embodiment. FIG. 20 is a schematic cross-sectional view showing the structure of the semiconductor device according to the fifth embodiment. FIG. 21 is a process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the fifth embodiment. FIG. 22 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the fifth embodiment. FIG. 23 is a schematic sectional view showing the structure of the semiconductor device according to the sixth embodiment. FIG. 24 is a process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the sixth embodiment. FIG. 25 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the sixth embodiment. FIG. 26 is a schematic cross-sectional view showing the structure of the semiconductor device according to the seventh embodiment. FIG. 27 is a process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the seventh embodiment. FIG. 28 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the seventh embodiment; FIG. 29 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the seventh embodiment; FIG. 30 is a process cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the seventh embodiment; FIG. 31 is a process cross-sectional view (No. 5) showing the method for manufacturing the semiconductor device according to the seventh embodiment. FIG. 32 is a process cross-sectional view (No. 6) illustrating the method for manufacturing the semiconductor device according to the seventh embodiment.

[First Embodiment]
The semiconductor device and the manufacturing method thereof according to the first embodiment will be described with reference to FIGS.

  FIG. 1 is a plan view and a schematic sectional view showing the structure of the semiconductor device according to the present embodiment. 2 to 5 are process cross-sectional views illustrating the method for fabricating the semiconductor device according to the present embodiment.

  First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along line AA ′ of FIG.

  A metal film 36 is formed on the substrate 30. An insulating film 16 is formed on the metal film 36. A graphene channel 14 a is formed on the insulating film 16. A source electrode 38 and a drain electrode 40 are formed on the insulating film 16 so as to be connected to both ends of the graphene channel 14a. An insulating film 42 is formed on the graphene channel 14a. A gate electrode 44 is formed on the insulating film 42 on the graphene channel 14a.

  Thus, the semiconductor device according to the present embodiment is a graphene transistor having the graphene channel 14a as a channel. A metal film 36 is formed below the graphene channel 14a with the insulating film 16 therebetween. A gate electrode 44 is formed above the graphene channel 14a with an insulating film 42 interposed therebetween. Thereby, it is possible to operate as a double gate transistor using the metal film 36 as a back gate electrode and the gate electrode 44 as a top gate electrode. If the insulating film 16 is thickened to widen the gap between the graphene channel 14a and the metal film 36, it can operate as a single gate transistor.

  Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.

  First, the substrate 10 is prepared. The substrate 10 is used as a base for synthesizing graphene, and is formed on at least a surface of a material that can be selectively etched with respect to graphene and the graphene catalyst material (catalyst metal film 12). If it is, it will not specifically limit. For example, a silicon substrate in which a silicon oxide film having a thickness of 300 nm is formed on the surface can be used.

  Next, iron (Fe) with a film thickness of, for example, 500 nm is deposited on the substrate 10 by, for example, a sputtering method to form a catalytic metal film 12 made of iron (FIG. 2A). The catalyst metal film 12 is not particularly limited as long as it is a material that functions as a catalyst for growing graphene.

  Next, the graphene 14 is synthesized using the catalytic metal film 12 as a catalyst, for example, by thermal CVD (FIG. 2B). For example, the graphene 14 is synthesized under the conditions that the growth temperature is 590 ° C., a mixed gas of acetylene and argon is used as the raw material gas, and further diluted with argon, and the flow rate ratio of argon: acetylene is 1000: 0.1. The thickness of the graphene 14 may be a single layer or several layers (about 2 to 5 layers). By performing synthesis for 5 minutes under the above conditions, a single-layer graphene 14 can be synthesized.

Next, for example, an ALD (Atomic Layer Deposition) method is used to deposit, for example, an aluminum oxide film (AlO) having a thickness of 10 nm to form an insulating film 16 made of an aluminum oxide film (FIG. 2C). The insulating film 16 is a film serving as a gate insulating film that separates the graphene channel and the back gate electrode. In addition to the aluminum oxide film, a titanium oxide film, a hafnium oxide film, a zirconium oxide film, or the like can be used. In addition to the ALD method, for example, it is also possible to use silicon oxide films such as alumina (Al ₂ O ₃ ), silica (SiO ₂ ), aluminum (Al) deposited by the electron beam evaporation method, and TEOS deposited by the CVD method. It is.

  Next, for example, titanium (Ti) with a thickness of 10 nm and gold (Au) with a thickness of 200 nm are sequentially deposited on the insulating film 16 by, for example, an electron beam evaporation method to form a metal film 18 having an Au / Ti structure. (FIG. 3A).

  Next, the silicon oxide film on the surface of the substrate 10 is wet-etched using, for example, a hydrofluoric acid aqueous solution, and the stacked structure 22 of the catalytic metal film 12, the graphene 14, the insulating film 16, and the metal film 18 is peeled from the substrate 10 (FIG. 3 (b)). The substrate 10 may be removed after the step shown in FIG. 4A described later and before the step shown in FIG.

  In addition to the production of the laminated structure 22, another substrate 30 different from the substrate 10 is prepared. The substrate 30 is a base on which the graphene transistor is formed, and is not particularly limited. For example, a silicon substrate having an insulating film such as a silicon oxide film formed on the surface can be used. An insulating film may be formed on a silicon substrate on which an element such as a transistor and a wiring layer are formed.

  Next, titanium (Ti) with a thickness of 10 nm and gold (Au) with a thickness of 200 nm, for example, are sequentially deposited on the substrate 30 by, for example, an electron beam evaporation method to form a metal film 32 having an Au / Ti structure ( FIG. 3 (c)).

  Next, on the substrate 30 on which the metal film 32 is formed, the laminated structure 22 is overlaid so that the metal film 32 and the metal film 18 face each other while appropriately aligning, and the metal film 32 is bonded to the metal film 32 by a gold thermocompression bonding method. The metal film 18 is joined (FIG. 4A). The bonded metal film 18/32 is hereinafter referred to as a metal film 36.

For joining the metal film 32 and the metal film 18, for example, a flip chip bonder is used, and pressure is applied by applying a pressure of about 0.1 N to 1 N per unit area (mm ² ) at a temperature of 300 ° C., for example. Do. It is desirable that the temperature and pressure during thermocompression bonding are appropriately selected according to the substrate size and metal type.

  In the above example, the metal film 32 and the metal film 18 are bonded by gold thermocompression bonding, but the pressure bonding method is not limited to gold-gold pressure bonding. In addition to gold, for example, copper (Cu), silver (Ag), nickel (Ni), titanium silicide (TiSix), silicon (Si), platinum (Pt), or the like can be used. Further, after the film surface is activated by plasma treatment or the like, thermocompression bonding may be performed.

  In the present embodiment, the graphene 14 is transferred onto the substrate 30 while being sandwiched between the catalytic metal film 12, the insulating film 16, and the metal film 18, so that the graphene 14 is wrinkled or bent during the transfer. Can be prevented. In addition, a transfer member such as a resist is not directly in contact with the graphene 14, and the introduction of damage to the graphene 14 due to a resist residue or the like can be prevented.

  Next, the catalytic metal film 12 is selectively removed by wet etching using, for example, hydrochloric acid or an iron chloride solution (FIG. 4B).

  Next, the graphene 14 is patterned to form a graphene channel 14a (FIG. 4C). Photolithography or electron beam lithography can be used to form a resist film that serves as a mask for patterning. Etching of the graphene 14 can be performed by oxygen plasma treatment or heating in an oxygen atmosphere.

  In the etching of graphene 14 by oxygen plasma treatment, for example, a sample is placed in a plasma of about 300 W in an oxygen atmosphere at about atmospheric pressure, and the graphene other than the channel portion is removed by performing treatment for several minutes to several tens of minutes. can do.

  In the graphene etching by heating in an oxygen atmosphere, for example, the graphene other than the channel portion can be removed by performing an appropriate time treatment at a temperature of about 500 ° C. to 600 ° C. in an oxygen atmosphere of 1 kPa.

  The etching conditions of the graphene 14 are desirably set as appropriate according to the quality of graphene, the number of layers, and the like.

  The shape of the graphene channel 14a varies depending on the application and is not particularly limited. Typically, the channel length is in the range of about 0.5 nm to 500 nm and the channel width is in the range of about 0.5 nm to 1000 nm. In particular, a channel length of about 5 nm to 500 nm and a channel width of about 1 nm to 50 nm are particularly preferable.

  In this embodiment, the graphene 14 synthesized on the entire surface of the substrate 10 is transferred onto the substrate 30 and then the graphene 14 is patterned to form the graphene channel 14a, so that a complicated process such as catalyst embedding and polishing is unnecessary. It is. Moreover, since it synthesize | combines on the whole surface on the board | substrate 10, the quality graphene 14 excellent in the uniformity can be synthesize | combined.

  Next, if necessary, the lower insulating film 16 and the metal film 36 may be patterned to form an electrode pattern or a wiring pattern made of the metal film 36.

  Next, for example, titanium (Ti) with a thickness of 10 nm and gold (Au) with a thickness of 200 nm are sequentially deposited on the entire surface by, for example, an electron beam evaporation method to form a metal film having an Au / Ti structure.

  Next, the metal film is patterned by lithography and dry etching to form a source electrode 38 and a drain electrode 40 respectively in contact with both ends of the patterned graphene channel 14a (FIG. 5A). The formation method of the source electrode 38 and the drain electrode 40 is not specifically limited, You may form by the lift-off method etc.

  Next, for example, alumina having a film thickness of 10 nm is deposited by, eg, ALD, and an insulating film 42 made of alumina is formed (FIG. 5B). The insulating film 42 is a film serving as a gate insulating film that separates the graphene channel 14a from the top gate electrode.

  Next, on the insulating film 42, for example, an electron beam evaporation method is used to sequentially deposit, for example, titanium having a thickness of 10 nm and gold having a thickness of 200 nm to form a metal film having an Au / Ti structure.

  Next, the metal film is patterned by lithography and dry etching to form a gate electrode 44 (FIG. 5C). The formation method of the gate electrode 44 is not particularly limited, and may be formed by a lift-off method or the like.

  Thereafter, as required, predetermined elements, wiring layers, passivation films, and the like are formed, and the semiconductor device according to the present embodiment is completed.

  As described above, according to the present embodiment, graphene is transferred using thermocompression bonding between metal films on another substrate on which the metal film is formed in a state where the insulating film and the metal film are formed on the graphene. Therefore, it is possible to prevent the graphene from being wrinkled or bent during the transfer. In addition, a member for transfer such as a resist is not in direct contact with the graphene, and the introduction of damage to the graphene due to a resist residue or the like can be prevented.

[Second Embodiment]
The semiconductor device and the manufacturing method thereof according to the second embodiment will be described with reference to FIGS. Constituent elements similar to those of the semiconductor device and the manufacturing method thereof according to the first embodiment shown in FIGS.

  FIG. 6 is a plan view and a schematic sectional view showing the structure of the semiconductor device according to the present embodiment. 7 to 9 are process cross-sectional views illustrating the method for fabricating the semiconductor device according to the present embodiment.

  First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG. 6A is a plan view, and FIG. 6B is a cross-sectional view taken along line AA ′ of FIG. 6A.

  A metal film 36 is formed on the substrate 30. An insulating film 46 is formed on the substrate 30 on which the metal film 36 is formed. A graphene channel 14 a is formed on the insulating film 46. On the insulating film 46, a source electrode 38 and a drain electrode 40 are formed so as to be connected to both ends of the graphene channel 14a. An insulating film 42 is formed on the graphene channel 14a. A gate electrode 44 is formed on the insulating film 42 on the graphene channel 14a.

  Thus, the semiconductor device according to the present embodiment is a graphene transistor having the graphene channel 14a as a channel. A metal film 36 is formed below the graphene channel 14a via an insulating film 46. A gate electrode 44 is formed above the graphene channel 14a with an insulating film 42 interposed therebetween. Thereby, it is possible to operate as a double gate transistor using the metal film 36 as a back gate electrode and the gate electrode 44 as a top gate electrode. If the insulating film 16 is thickened to widen the gap between the graphene channel 14a and the metal film 36, it can operate as a single gate transistor.

  In the semiconductor device according to the present embodiment, unlike the semiconductor device according to the first embodiment shown in FIG. 1, the metal film 36 is patterned into a predetermined back gate electrode shape. In the example of FIG. 6, the back gate electrode pattern is formed so as to include the pattern of the graphene channel 14a, but the back gate electrode pattern is not limited thereto. Similar to the gate electrode 44, a back gate electrode pattern may be formed so as to overlap with a partial region of the graphene channel 14a.

  Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.

  First, the catalytic metal film 12, the graphene 14, the insulating film 16, and the metal film 18 are formed on the substrate 10 in the same manner as in the method of manufacturing the semiconductor device according to the first embodiment shown in FIGS. Is formed (FIG. 7A).

  Next, the metal film 18 is patterned into a predetermined shape (here, the pattern of the back gate electrode) by lithography and dry etching (FIG. 7B).

  Next, after alumina is deposited on the entire surface by, for example, ALD, this alumina is polished by, for example, CMP (Chemical Mechanical Polishing) until the metal film 18 is exposed. Thereby, the insulating film 20 made of alumina is formed on the insulating film 16 in the region where the metal film 18 is not formed (FIG. 7C).

  Next, the silicon oxide film on the surface of the substrate 10 is wet-etched using, for example, a hydrofluoric acid aqueous solution, and the stacked structure 22 of the catalytic metal film 12, the graphene 14, the insulating film 16, and the metal film 18 / insulating film 20 is removed from the substrate 10. Peel off.

  Further, a metal film 32 is formed on the substrate 30 in the same manner as in the semiconductor device manufacturing method according to the first embodiment shown in FIG. 3C (FIG. 8A).

  Next, the metal film 32 is patterned into a predetermined shape (here, the pattern of the back gate electrode) by lithography and dry etching (FIG. 8B).

  Next, after alumina is deposited on the entire surface by, for example, ALD, this alumina is polished by, for example, CMP, until the metal film 32 is exposed. Thus, an insulating film 34 made of alumina is formed on the substrate 30 in the region where the metal film 32 is not formed (FIG. 8C).

  Next, on the substrate 30 on which the metal film 32 is formed, the laminated structure 22 is overlaid so that the metal film 32 and the metal film 18 face each other while appropriately aligning, and the metal film 32 is bonded to the metal film 32 by a gold thermocompression bonding method. The metal film 18 is joined (FIG. 9A). The bonded metal film 18/32 is hereinafter referred to as a metal film 36. The insulating films 16, 20, and 34 are hereinafter referred to as an insulating film 46.

  Next, the catalytic metal film 12 is selectively removed by wet etching using, for example, hydrochloric acid or an iron chloride solution (FIG. 9B).

  Next, in the same manner as in the method of manufacturing the semiconductor device according to the first embodiment shown in FIGS. 4C to 5C, the graphene 14 is patterned to form the graphene channel 14a, and the source electrode 38 and the drain electrode 40 are formed. Then, the gate insulating film 42 and the gate electrode 44 are formed (FIG. 9C).

  In the above example, the back gate electrode patterned in a predetermined shape is formed by the metal film 36 obtained by bonding the metal film 18 and the metal film 32. However, if the bonding portion between the metal film 18 and the metal film 32 is only the electrode portion or the wiring portion, the ratio of the bonding area to the entire surface of the substrate becomes insufficient, and it may be difficult to reliably bond the substrates. In such a case, a dummy electrode pattern for bonding may be provided on the metal film 18 and the metal film 32 in addition to the electrode pattern and the wiring pattern used in the actual device.

  For example, as shown in FIG. 10, a back gate electrode 36A and a bonding dummy electrode pattern 36B arranged around the transistor may be provided by a metal film 36.

  Alternatively, for example, as shown in FIG. 11, a back gate electrode 36A, a bonding dummy electrode pattern 36B, a contact pad portion 36C for the source electrode 38, a contact pad portion 36D for the drain electrode 40, and the like are provided by the metal film 36. You may do it.

  Thereby, the ratio of the junction area with respect to the whole surface of a board | substrate can be increased, and the laminated structure 22 can be bonded together on the board | substrate 10 reliably.

  When the bonding dummy electrode pattern 36B is provided, the electrode pattern and the wiring pattern formed by the metal films 18 and 32 are not necessarily formed by the metal film 36 that is a laminate of these. For example, in the example of FIGS. 10 and 11, the whole or part of the back gate electrode 36 </ b> A may be formed only by the metal film 18 or the metal film 32. For example, the functional part of the back gate electrode 36A immediately below the graphene channel 14a can be formed only by the metal film 18, and the contact pad part connected thereto can be formed by the metal film 36.

  The electrode pattern, wiring pattern, and dummy electrode pattern for bonding formed by the metal film 36 are not limited to the above arrangement, and can be appropriately changed as necessary. Further, as described above, the electrode pattern and the wiring pattern may be formed of the metal film 36 or may be formed of only the metal film 18 or the metal film 32.

  As described above, according to the present embodiment, graphene is transferred using thermocompression bonding between metal films on another substrate on which the metal film is formed in a state where the insulating film and the metal film are formed on the graphene. Therefore, it is possible to prevent the graphene from being wrinkled or bent during the transfer. In addition, a member for transfer such as a resist is not in direct contact with the graphene, and the introduction of damage to the graphene due to a resist residue or the like can be prevented.

[Third Embodiment]
A semiconductor device and a manufacturing method thereof according to the third embodiment will be described with reference to FIGS. The same components as those in the semiconductor device and the manufacturing method thereof according to the first and second embodiments shown in FIGS. 1 to 11 are denoted by the same reference numerals, and description thereof will be omitted or simplified.

  FIG. 12 is a plan view and a schematic sectional view showing the structure of the semiconductor device according to the present embodiment. 13 to 16 are process cross-sectional views illustrating the semiconductor device manufacturing method according to the present embodiment.

  First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG. FIG. 12A is a plan view, and FIG. 12B is a cross-sectional view taken along the line AA ′ in FIG.

  A metal film 36 is formed on the substrate 30. An insulating film 16 is formed on the metal film 36. A graphene channel 14 a is formed on the insulating film 16. The metal film 36, the insulating film 16, and the graphene channel 16a are patterned in the same shape, and an insulating film 48 is formed on the side wall portion. A source electrode 38 and a drain electrode 40 are formed on the substrate 30 so as to be connected to both ends of the graphene channel 14a. An insulating film 42 is formed on the graphene channel 14a. A gate electrode 44 is formed on the insulating film 42 on the graphene channel 14a.

  Thus, the semiconductor device according to the present embodiment is a graphene transistor having the graphene channel 14a as a channel. A metal film 36 is formed below the graphene channel 14a with the insulating film 16 therebetween. A gate electrode 44 is formed above the graphene channel 14a with an insulating film 42 interposed therebetween. Thereby, it is possible to operate as a double gate transistor using the metal film 36 as a back gate electrode and the gate electrode 44 as a top gate electrode. If the insulating film 16 is thickened to widen the gap between the graphene channel 14a and the metal film 36, it can operate as a single gate transistor.

  In the semiconductor device according to the present embodiment, unlike the semiconductor device according to the first embodiment shown in FIG. 1, the metal film 36 is patterned into the shape of the back gate electrode having the same shape as the graphene channel 14a. In the example of FIG. 12, the lead line of the back gate electrode formed by the metal film 36 is formed by the metal film 32.

  Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.

  First, the catalytic metal film 12, the graphene 14, the insulating film 16, and the metal film 18 are formed on the substrate 10 in the same manner as in the method of manufacturing the semiconductor device according to the first embodiment shown in FIGS. Is formed (FIG. 13A).

  Next, the metal film 18, the insulating film 16, the graphene 14, and the catalyst metal film 12 are patterned into the shape of the graphene channel 14a to be formed by lithography and dry etching. By this patterning, a graphene channel 14a made of graphene 14 is formed (FIG. 13B). In this patterning step, it is not always necessary to pattern the catalytic metal film 12. At least the metal film 18, the insulating film 16, and the graphene 14 may be patterned into a predetermined shape.

  In the present embodiment, since the graphene 14 is patterned in a state where the insulating film 16 and the metal film 18 are covered, the graphene 14 is directly applied with a resist film, or the graphene 14 is exposed to an atmosphere for removing the resist film. There is nothing. Accordingly, damage introduced into the graphene 14 can be reduced as compared with the first and second embodiments.

  When the bonding dummy electrode pattern is arranged to increase the bonding area, the laminated structure of the metal film 18, the insulating film 16, the graphene 14, and the catalytic metal film 12 is also formed in the bonding dummy electrode pattern formation region. The patterning is performed so that.

  Further, a metal film 32 is formed on the substrate 30 in the same manner as in the semiconductor device manufacturing method according to the first embodiment shown in FIG. 3C (FIG. 14A).

  Next, the metal film 32 is patterned into a predetermined shape by lithography and dry etching (FIG. 8B). Here, the metal film 32 forms a back gate electrode pattern 32A, a contact pad portion pattern 32B for the source electrode 38, and a contact pad portion pattern 32C for the drain electrode 40. When the bonding dummy electrode pattern is arranged to increase the bonding area, patterning is performed so that the metal film 32 remains in the bonding dummy electrode pattern formation region.

  Next, on the substrate 30 on which the metal film 32 is formed, the laminated structure 22 is overlaid so that the metal film 32 and the metal film 18 face each other while appropriately aligning, and the metal film 32 is bonded to the metal film 32 by a gold thermocompression bonding method. The metal film 18 is joined (FIG. 15A). The joined metal film 18/32 is hereinafter referred to as a metal film 36.

  At this time, for example, if the alignment is performed using the orientation flat of the substrates 10 and 30, the patterns 10 and 30 can be easily aligned by arranging the patterns so that they can be crimped at desired locations. it can.

  In this embodiment, since the periphery of the metal films 18 and 32 is not flattened by the insulating film, if the pattern of the metal film 18 to be joined and the pattern of the metal film 32 are different, the metal film 18 or the metal A void is formed in a region where either one of the films 32 is not formed. From this point of view, it is desirable that the pattern of the metal film 18 and the pattern of the metal film 32 have a mirror image relationship with each other.

  Next, for example, using a hydrofluoric acid aqueous solution, the silicon oxide film on the surface of the substrate 10 is wet-etched, and the substrate 10 is peeled off from the catalyst metal film 12 (FIG. 15B).

  Next, the catalytic metal film 12 is selectively removed by wet etching using, for example, hydrochloric acid or an iron chloride solution (FIG. 15C).

  Next, an insulating film 48 is selectively formed on the side walls of the metal film 36, the insulating film 16, and the graphene channel 14a (FIG. 16A). For example, after depositing alumina on the entire surface by, for example, ALD, this alumina is patterned to selectively leave the insulating film 48 on the side walls of the metal film 36, the insulating film 16, and the graphene channel 14a. Alternatively, after alumina is deposited on the entire surface by, for example, ALD, the alumina is etched back, and the insulating film 48 is selectively left on the side walls of the metal film 36, the insulating film 16, and the graphene channel 14a.

  The insulating film 48 covers the side wall portion of the metal film 36 and separates the metal film 36 from the source electrode 38 and the drain electrode 40. The insulating film 48 may be formed by any method as long as this purpose can be achieved.

  The step of forming the insulating film 48 may be performed after the step of FIG. 15B and before the step of FIG. In this case, since the graphene channel 14a is covered with the catalytic metal film 12 when the insulating film 48 is etched back or patterned, damage introduced into the graphene channel 14a can be reduced.

Next, the source electrode 38 and the drain electrode 40 connected to the graphene channel 14a are formed in the same manner as the semiconductor device manufacturing method according to the first embodiment shown in FIG. 5A (FIG. 16B).
Next, the gate insulating film 42 and the gate electrode 44 are formed in the same manner as in the semiconductor device manufacturing method according to the first embodiment shown in FIGS. 5B to 5C (FIG. 16C).

  As described above, according to the present embodiment, graphene is transferred using thermocompression bonding between metal films on another substrate on which the metal film is formed in a state where the insulating film and the metal film are formed on the graphene. Therefore, it is possible to prevent the graphene from being wrinkled or bent during the transfer. In addition, a member for transfer such as a resist is not in direct contact with the graphene, and the introduction of damage to the graphene due to a resist residue or the like can be prevented.

[Fourth Embodiment]
The semiconductor device and the manufacturing method thereof according to the fourth embodiment will be described with reference to FIGS. The same components as those of the semiconductor device and the manufacturing method thereof according to the first to third embodiments shown in FIGS. 1 to 16 are denoted by the same reference numerals, and description thereof will be omitted or simplified.

  FIG. 17 is a schematic cross-sectional view showing the structure of the semiconductor device according to the present embodiment. 18 and 19 are process cross-sectional views illustrating the method for fabricating the semiconductor device according to the present embodiment.

  First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG.

  A metal film 36 is formed on the substrate 30. An insulating film 16 is formed on the metal film 36. A graphene channel 14 a is formed on the insulating film 16. The metal film 36, the insulating film 16, and the graphene channel 16a are patterned in the same shape, and an insulating film 48 is formed on the side wall portion. A source electrode 38 and a drain electrode 40 are formed on the substrate 30 so as to be connected to both ends of the graphene channel 14a. An insulating film 50 is formed on the graphene channel 14a. A gate electrode 44 is formed on the insulating film 50 on the graphene channel 14a.

  Thus, the semiconductor device according to the present embodiment is a graphene transistor having the graphene channel 14a as a channel. A metal film 36 is formed below the graphene channel 14a with the insulating film 16 therebetween. A gate electrode 44 is formed above the graphene channel 14a with an insulating film 50 interposed therebetween. Thereby, it is possible to operate as a double gate transistor using the metal film 36 as a back gate electrode and the gate electrode 44 as a top gate electrode. If the insulating film 16 is thickened to widen the gap between the graphene channel 14a and the metal film 36, it can operate as a single gate transistor.

  The semiconductor device according to the present embodiment is the same as the semiconductor device according to the third embodiment shown in FIG. 12 except that the insulating film 50 is formed of an insulating compound of a catalytic metal material used when synthesizing the graphene channel 14a. Basically the same.

  Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. Similar to the method of manufacturing the semiconductor device according to the third embodiment shown in FIGS. 13A to 15B, the metal film 18, the insulating film 16, and the graphene channel are formed on the substrate 30 on which the metal film 32 is formed. The laminated structure of 14a and the catalytic metal film 12 is transferred (FIG. 18A).

  Next, the catalytic metal film 12 is polished or dry-etched, for example, by dry etching, and thinned until the thickness of the catalytic metal film 12 becomes, for example, about 20 nm (FIG. 18B).

  Next, the thinned catalyst metal film 12 is oxidized to form an insulating film 50 made of an oxide of the catalyst metal material that forms the catalyst metal film 12 (FIG. 18C). For example, the insulating film 50 can be formed by exposing the catalytic metal film 12 to plasma of about 200 W in an oxygen atmosphere at a pressure of about 1 Pa for 10 minutes.

  At this time, the exposed portion is formed of gold or an insulating film having high oxidation resistance and is hardly affected by oxidation. Although the side wall portion of the graphene channel 14a may react, the influence is slight.

  In the step of thinning the catalytic metal film 12, the catalytic metal film 12 is formed so that the thickness of the insulating film 50 obtained by oxidizing the thinned catalytic metal film 12 becomes a desired film thickness as a gate insulating film. The remaining film thickness is set appropriately.

  The insulating film 50 may be formed by oxidizing or nitriding all of the catalytic metal film 12 to form the insulating film 50 and then reducing the insulating film 50 to a desired thickness. However, the damage caused by exposure to the oxidizing atmosphere is reduced by forming the insulating film 50 by oxidizing or nitriding after the catalyst metal film 12 is thinned.

  Examples of the catalytic metal material for forming an oxide or nitride applicable as a gate insulating film include aluminum (Al), hafnium (Hf), zirconium (Zr), molybdenum (Mo), titanium (Ti), and tantalum ( Ta), silicon (Si), iron (Fe), copper (Cu), cobalt (Co), or an alloy containing at least one of these.

  Next, an insulating film 48 is formed on the sidewalls of the metal film 36, the insulating film 16, and the graphene channel 14a in the same manner as the semiconductor device manufacturing method according to the third embodiment shown in FIG. a)).

  Next, the insulating film 50 is patterned by lithography and etching to expose both end portions of the graphene channel 14a (FIG. 19B).

  Next, the source electrode 38, the drain electrode 40, the gate insulating film 42, and the gate electrode 44 are formed in the same manner as in the method for fabricating the semiconductor device according to the third embodiment shown in FIGS. FIG. 19 (c)).

  In the method of this embodiment, the graphene channel 14a is not exposed to the substrate surface through a series of manufacturing processes, and the physical or chemical treatment is not performed on the graphene channel 14a. As a result, damage to the graphene channel 14a can be minimized.

  As described above, according to the present embodiment, graphene is transferred using thermocompression bonding between metal films on another substrate on which the metal film is formed in a state where the insulating film and the metal film are formed on the graphene. Therefore, it is possible to prevent the graphene from being wrinkled or bent during the transfer. In addition, a member for transfer such as a resist is not in direct contact with the graphene, and the introduction of damage to the graphene due to a resist residue or the like can be prevented.

[Fifth Embodiment]
The semiconductor device and the manufacturing method thereof according to the fifth embodiment will be described with reference to FIGS. The same components as those of the semiconductor device and the manufacturing method thereof according to the first to fourth embodiments shown in FIGS. 1 to 19 are denoted by the same reference numerals, and description thereof will be omitted or simplified.

  FIG. 20 is a schematic cross-sectional view showing the structure of the semiconductor device according to the present embodiment. 21 and 22 are process cross-sectional views illustrating the method for fabricating the semiconductor device according to the present embodiment.

  First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG.

  An insulating film 16 is formed on the substrate 30. A graphene channel 14 a is formed on the insulating film 16. A source electrode 38 and a drain electrode 40 are formed on the insulating film 16 so as to be connected to both ends of the graphene channel 14a. An insulating film 42 is formed on the graphene channel 14a. A gate electrode 44 is formed on the insulating film 42 on the graphene channel 14a.

  Thus, the semiconductor device according to the present embodiment is a graphene transistor having the graphene channel 14a as a channel.

  Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.

  First, the catalytic metal film 12, the graphene 14, and the insulating film 16 are formed on the substrate 10 in the same manner as in the method of manufacturing the semiconductor device according to the first embodiment shown in FIGS. FIG. 21 (a)). Here, it is assumed that the insulating film 16 is formed of a silicon oxide film.

  In addition to the substrate 10, a substrate 30 having a silicon oxide insulating film formed on the surface is prepared.

  Next, the substrate 10 is overlaid on the substrate 30 so that the insulating film 16 faces the substrate 30 while appropriately aligning.

  Next, heat treatment is performed for about 1 hour at a temperature of, for example, about 800 ° C. to 1000 ° C. in a nitrogen atmosphere while applying a pressure between the substrate 30 and the substrate 10. As a result, the silicon oxide film on the surface of the substrate 30 and the insulating film 16 are joined (FIG. 21B).

  Since the temperature and time when the silicon oxide films are bonded to each other vary depending on the bonding area, the warpage of the substrate, and the like, it is desirable to set appropriately. Here, a silicon oxide film is used as the insulating film to be pressure-bonded, but there is no particular limitation as long as it is an insulator or oxide such as a silicon nitride film or alumina.

  In the present embodiment, since the graphene 14 is transferred onto the substrate 30 while being sandwiched between the catalytic metal film 12 and the insulating film 16, it is possible to prevent the graphene 14 from being wrinkled or bent during the transfer. In addition, a transfer member such as a resist is not directly in contact with the graphene 14, and the introduction of damage to the graphene 14 due to a resist residue or the like can be prevented.

  As in the third embodiment, the substrate 10 and the substrate 30 may be bonded after the insulating film 16, the graphene 14, and the catalytic metal film 12 are patterned into a predetermined shape.

  Next, the silicon oxide film on the surface of the substrate 10 is wet etched using, for example, a hydrofluoric acid aqueous solution, and the substrate 10 is removed.

  Next, the catalytic metal film 12 is selectively removed by wet etching using, for example, hydrochloric acid or an iron chloride solution (FIG. 22A). Note that the substrate 10 may be removed at the same time by etching the catalytic metal film 12 without separately performing the step of removing the substrate 10.

  Next, the graphene 14 is patterned to form a graphene channel 14a (FIG. 22B).

  Next, the source electrode 38, the drain electrode 40, the insulating film 42, and the gate electrode 44 are formed in the same manner as in the semiconductor device manufacturing method according to the first embodiment shown in FIGS. 22 (c)).

  As described above, according to the present embodiment, in a state where the insulating film is formed on the graphene, the graphene is transferred onto another substrate on which the insulating film is formed using the pressure bonding of the insulating films. In this case, it is possible to prevent the graphene from being wrinkled or bent. In addition, a member for transfer such as a resist is not in direct contact with the graphene, and the introduction of damage to the graphene due to a resist residue or the like can be prevented.

[Sixth Embodiment]
A semiconductor device and a manufacturing method thereof according to the sixth embodiment will be described with reference to FIGS. The same components as those of the semiconductor device and the manufacturing method thereof according to the first to fifth embodiments shown in FIGS. 1 to 22 are denoted by the same reference numerals, and description thereof will be omitted or simplified.

  FIG. 23 is a schematic cross-sectional view showing the structure of the semiconductor device according to the present embodiment. 24 and 25 are process cross-sectional views illustrating the method for fabricating the semiconductor device according to the present embodiment.

  First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG.

  A metal film 36 is formed on the substrate 30. An insulating film 46 is formed on the substrate 30 on which the metal film 36 is formed. A graphene channel 14 a is formed on the insulating film 46. On the insulating film 46, a source electrode 38 and a drain electrode 40 are formed so as to be connected to both ends of the graphene channel 14a. An insulating film 42 is formed on the graphene channel 14a. A gate electrode 44 is formed on the insulating film 42 on the graphene channel 14a.

  Thus, the semiconductor device according to the present embodiment is a graphene transistor having the graphene channel 14a as a channel. A metal film 36 is formed below the graphene channel 14a via an insulating film 46. A gate electrode 44 is formed above the graphene channel 14a with an insulating film 42 interposed therebetween. Thereby, it is possible to operate as a double gate transistor using the metal film 36 as a back gate electrode and the gate electrode 44 as a top gate electrode. If the insulating film 16 is thickened to widen the gap between the graphene channel 14a and the metal film 36, it can operate as a single gate transistor.

  Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.

  First, the catalytic metal film 12, the graphene 14, the insulating film 16, and the metal film 18 are formed on the substrate 10 in the same manner as in the method of manufacturing the semiconductor device according to the second embodiment shown in FIGS. 7A to 7C. Then, the insulating film 20 is formed (FIG. 24A).

  Further, an insulating film 34 in which a metal film 32 is embedded in the surface portion is formed on the substrate 30 (FIG. 24B).

  Next, on the substrate 30 on which the metal film 32 is formed, while appropriately aligning the substrate, the metal film 32 and the metal film 18 face each other, and the insulating film 34 and the insulating film 20 face each other. 10 are overlapped.

Next, while applying a pressure of about 0.1 N to 1 N per unit area (mm ² ) between the substrate 30 and the substrate 10, heat treatment is performed in a nitrogen atmosphere at a temperature of about 200 ° C. to 800 ° C. for about 1 hour, for example. I do. Thereby, the metal film 32 and the metal film 18 are joined, and the insulating film 34 and the insulating film 20 are joined (FIG. 24C). The bonded metal film 18/32 is hereinafter referred to as a metal film 36. Further, the insulating films 16, 20, and 34 are represented as an insulating film 46.

  Next, the silicon oxide film on the surface of the substrate 10 is wet etched using, for example, a hydrofluoric acid aqueous solution, and the substrate 10 is removed.

  Next, the catalytic metal film 12 is selectively removed by wet etching using, for example, hydrochloric acid or iron chloride solution (FIG. 25A). Note that the substrate 10 may be removed at the same time by etching the catalytic metal film 12 without separately performing the step of removing the substrate 10.

  Next, the graphene 14 is patterned to form the graphene channel 14a (FIG. 25B).

  Next, a source electrode 38, a drain electrode 40, an insulating film 42, and a gate electrode 44 are formed in the same manner as in the semiconductor device manufacturing method according to the second embodiment shown in FIG. 9C (FIG. 25C).

  As described above, according to the present embodiment, the graphene is transferred using the pressure bonding between the metal films and between the insulating films in a state where the insulating film and the metal film are formed on the graphene. It is possible to prevent wrinkles and bending. In addition, a member for transfer such as a resist is not in direct contact with the graphene, and the introduction of damage to the graphene due to a resist residue or the like can be prevented.

[Seventh Embodiment]
A semiconductor device and a manufacturing method thereof according to the seventh embodiment will be described with reference to FIGS. The same components as those of the semiconductor device and the manufacturing method thereof according to the first to sixth embodiments shown in FIGS. 1 to 25 are denoted by the same reference numerals, and description thereof will be omitted or simplified.

  FIG. 26 is a schematic cross-sectional view showing the structure of the semiconductor device according to the present embodiment. 27 and 32 are process cross-sectional views illustrating the method for fabricating the semiconductor device according to the present embodiment.

  First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG.

  A metal film 36 is formed on the substrate 30. An insulating film 46 is formed on the substrate 30 on which the metal film 36 is formed. A graphene channel 14 a is formed on the insulating film 46. On the insulating film 46, a source electrode 38 and a drain electrode 40 are formed so as to be connected to both ends of the graphene channel 14a. An insulating film 42 is formed on the graphene channel 14a. A catalytic metal film 52 is formed on the source electrode 38 and the drain electrode 40. A catalytic metal film 52 also serving as a gate electrode is formed on the insulating film 42 on the graphene channel 14a. Thus, a double gate transistor is formed on the substrate 30 using the metal film 36 as a back gate electrode and the catalyst metal film 54 on the insulating film 42 as a top gate electrode.

  An interlayer insulating film 56 is formed on the substrate 30 on which the graphene transistor is formed. In the interlayer insulating film 56, a via wiring 54 made of a bundle of carbon nanotubes electrically connected to the gate electrode (catalytic metal film 52), the source electrode 38, and the drain electrode is embedded. A via wiring 54 is buried, and a graphene wiring 64 a sandwiched between the metal films 68 and 70 is formed on the interlayer insulating film 54 so as to be connected to the via wiring 54.

  An interlayer insulating film 74 is formed on the interlayer insulating film 56 on which the graphene wiring 64a is formed. A via wiring 72 made of a bundle of carbon nanotubes electrically connected to the graphene wiring 64 a is embedded in the interlayer insulating film 74. On the interlayer insulating film 74 in which the via wiring 72 is embedded, a graphene wiring 78 having a metal film 76 formed on the lower surface side is formed so as to be connected to the via wiring 72.

  As described above, in the semiconductor device according to the present embodiment, the wiring layer is formed by the graphene wirings 54 and 74. By forming the wiring layer from graphene, the resistance of the wiring layer can be easily reduced. As will be described later, the graphene wirings 54 and 74 can be formed using the same process as the graphene channel 14a.

  In the semiconductor device according to the present embodiment, the via wiring is formed by a bundle of carbon nanotubes. By forming the via wiring with a bundle of carbon nanotubes, the resistance of the via wiring can be easily reduced. Note that the via wiring does not necessarily need to be formed by a bundle of carbon nanotubes, and a normal via wiring forming process can be applied.

  Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.

  First, in the same manner as in the method of manufacturing the semiconductor device according to the second embodiment shown in FIGS. 7A to 9C, the metal film 36, the insulating film 46, the graphene channel 14 a, and the source electrode 38 are formed on the substrate 30. Then, the drain electrode 40 and the insulating film 42 are formed (FIG. 27A).

  In this embodiment, an example in which the structure of the second embodiment is applied as the underlying transistor structure is shown, but the underlying transistor structure is not limited to this. Instead of the structure of the second embodiment, the structure of any of the first, third to sixth embodiments may be applied, or another transistor structure may be applied. In addition, although the gate electrode 44 is not formed in FIG. 27A, the gate electrode 44 may be formed on the insulating film 42 as in FIG. 9C.

  Next, the insulating film 42 is patterned by lithography and etching to expose the surfaces of the source electrode 38 and the drain electrode 40 (FIG. 27B).

  Next, a catalytic metal film 52 is formed on the contact formation portion on the source electrode 38 and the drain electrode 40 and on the formation portion of the gate electrode on the insulating film 42 by, for example, a lift-off method (FIG. 27B). The catalytic metal film 52 on the insulating film 42 can be used as a gate electrode. When the gate electrode 44 is formed on the insulating film 42, the catalytic metal film 52 is formed on the contact formation portion on the gate electrode 44. The method for forming the catalytic metal film 52 is not limited to the lift-off method.

  As the catalytic metal film 52, for example, a tantalum (Ta) film having a thickness of 5 nm, a titanium nitride (TiN) film having a thickness of 5 nm, and a cobalt (Co) film having a thickness of 1 nm are sequentially deposited by sputtering. To form. Cobalt is a catalyst material, titanium nitride is a support material that promotes synthesis, and tantalum is a film that prevents diffusion of the underlying metal.

  As the catalyst material, in addition to cobalt, for example, iron (Fe), nickel (Ni), copper (Cu), gold (Au), platinum (Pt), or an alloy containing at least one of these, these A compound such as an oxide / nitride can be used.

  As the support material, in addition to titanium nitride, for example, aluminum (Al), hafnium (Hf), zirconium (Zr), molybdenum (Mo), titanium (Ti), tantalum (Ta), silicon (Si), titanium silicide ( TiSix), vanadium (V), niobium (Nb), ruthenium (Ru), or an alloy containing at least one of them, and compounds such as oxides and nitrides thereof can be applied.

  As the diffusion preventing film, in addition to tantalum, for example, titanium (Ti), ruthenium (Ru), an alloy containing at least one of them, or a compound such as oxide or nitride thereof can be applied. .

  Next, carbon nanotubes are synthesized using the catalytic metal film 52 as a catalyst, for example, by thermal CVD, and via wirings 54 made of bundles of carbon nanotubes are formed on the catalytic metal film 52 (FIG. 28A). For example, a carbon nanotube having a length of about 500 nm is grown under the conditions of using a mixed gas of acetylene and argon as a source gas (acetylene gas is 0.1% or less of argon), a pressure of 1 kPa, and a substrate temperature of 450 ° C.

Next, for example, a silicon oxide film is deposited by, eg, CVD, and an interlayer insulating film 56 of the silicon oxide film is formed (FIG. 28B).

  Next, the surface of the interlayer insulating film 56 is polished by, eg, CMP, and the upper end portion of the via wiring 54 is exposed on the surface of the interlayer insulating film 56 (FIG. 29A).

  Next, for example, titanium (Ti) with a thickness of 10 nm and gold (Au) with a thickness of 200 nm are sequentially deposited on the interlayer insulating film 56 by, for example, an electron beam evaporation method to form a metal film 58 having an Au / Ti structure. To do.

  Next, the metal film 58 is patterned by lithography and etching to form a predetermined wiring pattern connected to the via wiring 54 (FIG. 29B).

  Further, a substrate 60 is prepared separately from the substrates 10 and 30. The substrate 60 is used as a base for synthesizing graphene, and is formed on at least the surface of a material that can be selectively etched with respect to graphene and the graphene catalyst material (catalyst metal film 62). If it is, it will not specifically limit. For example, a silicon substrate in which a silicon oxide film having a thickness of 300 nm is formed on the surface can be used.

  Next, iron (Fe) having a film thickness of, for example, 500 nm is deposited on the substrate 60 by, for example, sputtering to form a catalytic metal film 62 made of iron.

  Next, in the same manner as the synthesis of the graphene 14, the graphene 64 is synthesized using the catalytic metal film 62 as a catalyst. The graphene 64 is used as a wiring, and the number of layers can be appropriately increased or decreased according to the requirement of wiring resistance.

  Next, on the graphene 64, for example, titanium (Ti) with a film thickness of 10 nm and gold (Au) with a film thickness of 200 nm are sequentially deposited by, for example, an electron beam evaporation method to form a metal film 66 having an Au / Ti structure ( FIG. 30 (a)).

  Next, the metal film 66, the graphene 64, and the catalyst metal film 62 are patterned into a predetermined shape corresponding to the wiring pattern of the metal film 58 by lithography and etching (FIG. 30B). By this patterning, a graphene wiring 64a made of graphene 64 is formed. In this patterning step, it is not always necessary to pattern the catalyst metal film 62. At least the metal film 66 and the graphene 64 may be patterned into a predetermined shape.

  Next, on the insulating film 56 on which the metal film 58 is formed, the substrate 60 is overlaid so that the metal film 58 and the metal film 66 face each other while appropriately aligning, and the metal film 32 and the metal are bonded by a gold thermocompression bonding method. The film 18 is joined (FIG. 31A). The bonded metal film 66/58 is hereinafter referred to as a metal film 68.

  Next, the silicon oxide film on the surface of the substrate 60 is wet-etched using, for example, a hydrofluoric acid aqueous solution, and the substrate 60 is removed.

  Next, the catalytic metal film 62 is selectively removed by wet etching using, for example, hydrochloric acid or an iron chloride solution (FIG. 31B).

  Thus, the graphene wiring 64a electrically connected to the gate electrode (catalyst metal film 52), the source electrode 38, and the drain electrode 40 of the graphene transistor through the via wiring 54 of the carbon nanotube bundle is formed.

  It is also conceivable that after the step of FIG. 29B, a catalytic metal film is deposited and the graphene wiring is directly formed using this as a catalyst. An advantage of this embodiment is that the metal film that is the base of the graphene wiring is not limited to the catalytic metal material.

  Next, if necessary, the catalytic metal film 70, the via wiring 72, the interlayer insulating film 74, the metal film 76, and the graphene are formed on the graphene wiring 64a in the same manner as in the steps of FIGS. 27C to 31B. The wiring 78 is repeatedly formed to form a multilayer wiring structure (FIG. 32).

  As described above, according to the present embodiment, in a state where the metal film is formed on the graphene, the graphene is transferred onto another substrate on which the metal film is formed using thermocompression bonding between the metal films. It is possible to prevent wrinkling and bending of the graphene during transfer. In addition, a member for transfer such as a resist is not in direct contact with the graphene, and the introduction of damage to the graphene due to a resist residue or the like can be prevented.

[Modified Embodiment]
The present invention is not limited to the above embodiment, and various modifications are possible.

  For example, although the method of synthesizing graphene by the thermal CVD method has been described in the above embodiment, the present invention is not limited to the thermal CVD method, and a remote plasma CVD method, a plasma CVD method, or the like may be used. The source gas is not limited to acetylene, and hydrocarbon gas such as ethylene gas and methane gas, alcohol such as ethanol, benzene, and the like may be used.

  Further, the catalyst used for the synthesis of graphene is not limited to iron, and other materials that function as a catalyst for the synthesis of graphene may be used. For example, a metal such as Co (cobalt), Ni (nickel), Cu (copper), Pt (platinum), Au (gold), an alloy containing at least one of these, a carbide, an oxide, a nitride, or the like may be used. .

  The method for forming the catalytic metal film 12 is not particularly limited, and is not limited to the sputtering method, and an electron beam evaporation method, a molecular beam epitaxy method, or the like may be used.

  As another synthesis method of graphene, for example, a method of synthesizing graphene by a thermal CVD method using a copper thin film having a thickness of 500 nm deposited on a silicon substrate with a thermal oxide film by a sputtering method as a catalyst can be given. In this case, for example, methane is used as the source gas, and the partial pressure of the gas is 100 sccm of hydrogen and 10 sccm of methane with respect to 900 sccm of argon gas for dilution, and graphene can be synthesized at a temperature of 900 ° C.

  In the seventh embodiment, the method of synthesizing the carbon nanotubes by the thermal CVD method is shown. However, the present invention is not limited to the thermal CVD method, and a remote plasma CVD method, a plasma CVD method, or the like may be used. The source gas is not limited to acetylene, and hydrocarbon gas such as ethylene gas and methane gas, alcohol such as ethanol, benzene, and the like may be used.

  In the first, second, third, fourth, sixth, and seventh embodiments, a double-gate transistor is shown. In the fifth embodiment, a top-gate transistor is shown. The structure is not limited to this.

  For example, in the first, second, third, fourth, sixth, and seventh embodiments, the gate electrode 44 is not necessarily required, and a back gate transistor having only a back gate electrode may be used. Alternatively, in the second and sixth embodiments, a back gate electrode is not necessarily formed, and a top gate transistor having only the gate electrode 44 may be used. Alternatively, the insulating films 16 and 46 separating the metal film 36 and the graphene channel 14a may be made thick so that the metal film 36 does not substantially function as a back gate electrode. Alternatively, the graphene channel 14a described in the first to sixth embodiments may be a graphene wiring.

  Moreover, the structure and the manufacturing method described in each embodiment can be arbitrarily combined. For example, the process of the fourth embodiment in which the catalytic metal film 12 is oxidized to form the gate insulating film may be applied to the first, second, third, fifth, or sixth embodiment. Further, the wiring structure of the seventh embodiment may be applied to the first to sixth embodiments.

  In addition, the structure, structural parameters, constituent materials, manufacturing conditions, and the like of the semiconductor device described in the above embodiment are merely examples, and can be appropriately modified or changed according to technical common sense of those skilled in the art. .

  Moreover, although the example applied to the graphene channel transistor and the graphene wiring was shown in the said embodiment, it is not limited to these, It can apply to the various device and structure which have a graphene.

10, 30, 60 ... substrate 12, 52, 62, 70 ... catalytic metal film 14, 64 ... graphene 14a ... graphene channel 16, 20, 34, 42, 46, 48, 50 ... insulating films 18, 32, 36, 58 , 66, 68, 76 ... metal film 22 ... laminated structure 38 ... source electrode 40 ... drain electrode 44 ... gate electrodes 54, 72 ... via wirings 56, 74 ... interlayer insulating films 64a, 78 ... graphene wiring

Claims (13)

Forming a first catalytic metal film on a first substrate;
Forming first graphene on the first catalytic metal film using the first catalytic metal film as a catalyst;
Forming a first insulating film on the first graphene;
Forming a first metal film on the first insulating film;
Forming a second metal film on the second substrate;
A step of causing the surface of the first metal film and the surface of the second metal film to face each other and bonding the first metal film and the second metal film;
And removing the first substrate. A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 1,
After the step of removing the first substrate, a step of removing the first catalytic metal film, and a step of patterning the first graphene to form a graphene channel made of the first graphene A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 1,
After the step of forming the first metal film, patterning the first metal film, the first insulating film, and the first graphene to form a graphene channel made of the first graphene Furthermore, it has a manufacturing method of the semiconductor device characterized by the above-mentioned. In the manufacturing method of the semiconductor device according to claim 3,
After the step of forming the graphene channel, the method further includes the step of removing the first catalytic metal film. In the manufacturing method of the semiconductor device according to claim 3,
After the step of removing the first substrate, the method further comprises the step of oxidizing the first catalytic metal film to form a third insulating film. In the manufacturing method of the semiconductor device according to any one of claims 2 to 5,
After the step of forming the graphene channel, the method further includes a step of forming a source electrode and a drain electrode connected to the graphene channel. The method of manufacturing a semiconductor device according to claim 6.
Forming a second catalytic metal film on the source electrode and the drain electrode;
On the second catalytic metal film, the second catalytic metal film grown carbon nanotubes as a catalyst, a method of manufacturing a semiconductor device characterized by further comprising the step of forming a via wiring of the carbon nanotube bundles . The method of manufacturing a semiconductor device according to claim 7 .
Forming a third catalytic metal film on a third substrate;
Forming second graphene on the third catalytic metal film using the third catalytic metal film as a catalyst;
Forming a third metal film on the second graphene;
Patterning the third metal film and the second graphene to form a graphene wiring made of the second graphene;
Forming a fourth metal film on the via wiring;
A step of causing the surface of the third metal film and the surface of the fourth metal film to face each other and bonding the third metal film and the fourth metal film;
Removing the third substrate;
Removing the second catalytic metal film. A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to any one of claims 1 to 8,
A step of forming a second insulating film on the second substrate;
In the step of forming the first metal film, the first metal film embedded in the surface portion of the first insulating film is formed,
In the step of forming the second metal film, the second metal film embedded in the surface portion of the second insulating film is formed,
In the step of joining the first metal film and the second metal film, the first metal film and the second metal film are joined, and the first insulating film and the second metal film are joined. A method for manufacturing a semiconductor device, comprising bonding an insulating film. In the manufacturing method of the semiconductor device according to any one of claims 1 to 9,
The method for manufacturing a semiconductor device, wherein the first metal film and the second metal film are bonded by thermocompression bonding. Forming a catalytic metal film on the first substrate;
Forming graphene on the catalytic metal film using the catalytic metal film as a catalyst;
Forming a first metal film on the graphene;
Patterning the first metal film and the graphene to form a graphene wiring made of the graphene;
Forming a second metal film on the second substrate;
A step of causing the surface of the first metal film and the surface of the second metal film to face each other and bonding the first metal film and the second metal film;
Removing the first substrate;
And a step of removing the catalytic metal film. Forming a catalytic metal film on the first substrate;
Forming graphene on the catalytic metal film using the catalytic metal film as a catalyst;
Forming a first insulating film on the graphene;
Forming a second insulating film on the second substrate;
A step of causing the surface of the first insulating film and the surface of the second insulating film to face each other and bonding the first insulating film and the second insulating film;
And removing the first substrate. A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 12,
The method of manufacturing a semiconductor device, further comprising a step of patterning the first insulating film and the graphene after the step of forming the first insulating film.

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